Semiconductor device

Abstract

To provide a semiconductor device with excellent electric characteristics.SOLUTION: A semiconductor device comprises: a first oxide; a first conductor and a second conductor on the first oxide; a first insulator on the first conductor; a second insulator on the second conductor; a second oxide provided on the first oxide and in contact with a side surface of the first conductor and a side surface of the second conductor; a third oxide provided on the second oxide and having a region in contact with the side surface of the first insulator and the side surface of the second insulator; a third insulator on the third oxide; and a third conductor on the third insulator.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention An embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device, or to a manufacturing method of a semiconductor device, or to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification etc. relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, semiconductor devices have been developed and are mainly used in LSIs, CPUs, memories, etc. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed on chips by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of the components in various electronic devices.

[0006] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0007] It is also known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0008] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits, and there is also a demand for improved productivity in the manufacture of semiconductor devices including integrated circuits.

[0009] Furthermore, with the development of communication technology, communication means capable of transmitting and receiving large volumes of data at high speeds are attracting attention. Among the many communication means proposed, communication means compliant with the fourth generation mobile communication system (4G) or communication means compliant with the fifth generation mobile communication system (5G) are attracting particular attention (Patent Document 3). Communication means compliant with 5G use frequency bands of 500 MHz or more and 52 GHz or less. High-speed communication of large volumes of data is expected to improve the real-time nature of communication and enable simultaneous control of multiple terminals. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A [Patent Document 3] U.S. Patent Publication No. 2019 / 0090218 Summary of the Invention [Problem to be solved by the invention]

[0011] A circuit used in such a communication means is required to have high-speed switching. Thus, an object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device having a large on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0013] One embodiment of the present invention is a semiconductor device having a first oxide, a first conductor and a second conductor on the first oxide, a first insulator on the first conductor, a second insulator on the second conductor, a second oxide provided on the first oxide and in contact with a side surface of the first conductor and a side surface of the second conductor, a third oxide provided on the second oxide and having a region in contact with a side surface of the first insulator and a side surface of the second insulator, a third insulator on the third oxide, and a third conductor on the third insulator.

[0014] In the above, at least one of the first oxide, the second oxide, and the third oxide preferably contains indium, an element M (wherein the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0015] In the above, at least one of the first oxide, the second oxide, and the third oxide preferably has crystallinity.

[0016] In the above, it is preferable that the third oxide is crystalline, and the c-axis of the third oxide has a region oriented perpendicular or approximately perpendicular to the top surface of the first oxide, a region oriented perpendicular or approximately perpendicular to the side surface of the first insulator, and a region oriented perpendicular or approximately perpendicular to the side surface of the second insulator.

[0017] In the above, it is preferable that the third oxide has a region in contact with a side surface of the first conductor and a side surface of the second conductor.

[0018] In the above, the electrical conductivity of the second oxide is preferably higher than that of the first oxide.

[0019] In the above, the resistivity of the third oxide is preferably higher than the resistivity of the first oxide.

[0020] In the above, it is preferable that the third insulator has a first layer and a second layer between the first layer and the third conductor, and the second layer contains hafnium oxide. Effect of the Invention

[0021] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device having a large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0023] [Figure 1] Fig. 1A is a top view of a semiconductor device according to one embodiment of the present invention, and Figs. 1B to 1D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Diagram 2] 2A and 2B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Diagram 3] 3A to 3C are diagrams for explaining the behavior of microwaves. [Figure 4] Figure 4A is a diagram explaining the classification of IGZO crystal structures, Figure 4B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 4C is a diagram explaining the ultrafine electron beam diffraction pattern of a CAAC-IGZO film. [Diagram 5] 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6]6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 18B to 18D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 19B to 19D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 20B to 20D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 21B to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] 22A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 22B to 22D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 23B to 23D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 24B to 24D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 25]25A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 25B to 25D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 26B to 26D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 27 is a top view illustrating a microwave processing device according to one embodiment of the present invention. [Figure 28] FIG. 28 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Diagram 30] Fig. 30A is a top view of a semiconductor device according to one embodiment of the present invention, and Fig. 30B to Fig. 30D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Diagram 31] Fig. 31A is a top view of a semiconductor device according to one embodiment of the present invention, and Figs. 31B to 31D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Diagram 32] 32A and 32B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 33] 33A and 33B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Diagram 34] FIG. 34 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Diagram 35] FIG. 35 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Diagram 36] 36A and 36B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 37] 37A and 37B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 38 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 39]FIG. 39 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 40] 40A and 40B are block diagrams illustrating a configuration example of a storage device according to one embodiment of the present invention, and a perspective view illustrating a configuration example of a storage device according to one embodiment of the present invention. [Diagram 41] 41A to 41H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Diagram 42] FIG. 42 is a diagram showing various storage devices by hierarchy. [Diagram 43] Fig. 43A is a block diagram of a semiconductor device according to one embodiment of the present invention, and Fig. 43B is a perspective view of the semiconductor device according to one embodiment of the present invention. [Diagram 44] 44A and 44B are diagrams illustrating an example of an electronic component according to one embodiment of the present invention. [Diagram 45] 45A to 45E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 46] 46A to 46G are diagrams showing electronic devices according to one embodiment of the present invention. [Figure 47] FIG. 47 is a diagram showing an example of an electronic device according to an embodiment of the present invention. [Figure 48] 48A to 48E are diagrams illustrating an example of an electronic device according to one embodiment of the present invention. [Figure 49] FIG. 49 is a diagram showing the hierarchical structure and required specification trends of an IoT network according to one embodiment of the present invention. [Figure 50] FIG. 50 is an image diagram of factory automation according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0025] In addition, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may be unintentionally thinned by etching or other processes, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

[0026] In order to facilitate understanding of the invention, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0027] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for explanation. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

[0028] In addition, in this specification, the terms "above" and "below" indicating the arrangement are used for convenience in order to explain the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0029] For example, when it is explicitly stated in this specification that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are considered to be disclosed in this specification. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and a connection relationship other than that shown in a figure or text is also considered to be disclosed in the figure or text. Here, X and Y are objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0030] In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter, also referred to as a channel formation region) is provided, and a current can flow between the source and the drain through the channel formation region. In this specification, a channel formation region refers to a region through which a current mainly flows.

[0031] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0032] The channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or a distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in a channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0033] The channel width refers to, for example, the length of a channel formation region in a vertical direction based on the channel length direction in a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or in a channel formation region. Note that the channel width does not necessarily have the same value in all regions in one transistor. In other words, the channel width of one transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0034] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers a side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence of this may not be negligible. For example, in a fine transistor in which a gate electrode covers a side surface of a semiconductor, the proportion of a channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

[0035] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not precisely known, it is difficult to accurately measure the effective channel width.

[0036] In this specification, when simply described as a channel width, it may refer to an apparent channel width. Alternatively, when simply described as a channel width, it may refer to an effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0037] Note that impurities in a semiconductor refer to, for example, anything other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the density of defect states in the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiencies (V O :oxygen vacancy) may be formed.

[0038] In this specification and the like, silicon oxynitride refers to a composition having a higher oxygen content than nitrogen. Silicon nitride oxide refers to a composition having a higher nitrogen content than oxygen. Similarly, aluminum oxynitride refers to a composition having a higher oxygen content than nitrogen. Aluminum nitride oxide refers to a composition having a higher nitrogen content than oxygen. Similarly, hafnium oxynitride refers to a composition having a higher oxygen content than nitrogen. Hafnium nitride oxide refers to a composition having a higher nitrogen content than oxygen.

[0039] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0040] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0041] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0042] In this specification and the like, normally-off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1×10 at 85℃ -18 A or less, or 1×10 at 125°C -16 This means that it is A or lower.

[0043] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 of one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS. 1A to 33B.

[0044] <Example of semiconductor device configuration> A configuration of a semiconductor device having a transistor 200 will be described with reference to FIGS. 1A to 1D. FIGS. 1A to 1D are a top view and a cross-sectional view of a semiconductor device having a transistor 200. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 1A. Note that some elements are omitted in the top view of FIG. 1A for clarity.

[0045] The semiconductor device of one embodiment of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 284 on the insulator 282, an insulator 283 on the insulator 284, and an insulator 274 on the insulator 283. The insulators 212, 214, 280, 282, 284, 283, and 274 function as interlayer films. The semiconductor device also includes a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with a side surface of the conductor 240 that functions as a plug. Moreover, a conductor 246 (conductor 246a and conductor 246b) that is electrically connected to the conductor 240 and functions as wiring is provided on the insulator 274 and on the conductor 240. Furthermore, an insulator 286 is provided on the conductor 246 and on the insulator 274.

[0046] Insulator 241a is provided in contact with the inner walls of the openings of insulators 280, 282, 284, 283, and 274, a first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inward. Insulator 241b is provided in contact with the inner walls of the openings of insulators 280, 282, 284, 283, and 274, a first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inward. Here, the height of the top surface of conductor 240 and the height of the top surface of insulator 274 in the region overlapping with conductor 246 can be made to be approximately the same. Note that, although the transistor 200 shows a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by giving ordinal numbers in the order of formation.

[0047] [Transistor 200] As shown in FIGS. 1A to 1D , the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a, conductor 205b, and conductor 205c) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxide 243a and oxide 243b) on the oxide 230b, a conductor 242a on the oxide 243a, an insulator 271a on the conductor 242a, a conductor 242b on the oxide 243b, and a conductor 242a on the oxide 243a. b, oxide 230c located between oxide 243a and oxide 243b and on oxide 230b, oxide 230d on oxide 230c, insulator 250 (insulator 250a and insulator 250b) on oxide 230d, conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping part of oxide 230b, insulator 273 arranged to cover insulator 224, oxide 230a, oxide 230b, oxide 243, conductor 242a, conductor 242b, insulator 271a, and insulator 271b, and insulator 275 arranged on insulator 273. In addition, the insulator 214 may have a recess or an opening so as to overlap with the opening of the insulator 216, and the conductor 205 may be disposed so as to be embedded in the opening of the insulator 216 and the recess or the opening of the insulator 214. Here, as shown in FIG. 1B and FIG. 1C, the upper surface of the conductor 260 is disposed so as to substantially coincide with the upper surface of the insulator 250, the upper surface of the oxide 230d, and the upper surface of the insulator 280. Also, the insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, the oxide 230d, and the insulator 280.

[0048] In the following, the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d may be referred to as the oxide 230. In this case, the oxide 230 may indicate one or more selected from the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d. For example, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. The oxide 230a, the oxide 230b, and the oxide 230c may be collectively referred to as the oxide 230. The oxide 230b and the oxide 230c may be collectively referred to as the oxide 230. The oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d may be collectively referred to as the oxide 230. The insulator 271a and the insulator 271b may be collectively referred to as the insulator 271. The conductor 242a and the conductor 242b may be collectively referred to as the conductor 242.

[0049] Between the conductor 240a and the conductor 240b, an opening is provided in the insulator 280, the insulator 275, and the insulator 273. In the opening, the insulator 271, the conductor 242, and the oxide 243 are removed, and the oxide 230b is exposed. In the opening, the oxide 230c is disposed, and the oxide 230d is disposed on the oxide 230c. At this time, the oxide 230c is preferably disposed on the bottom surface of the opening, and the oxide 230d is preferably disposed so as to contact the upper surface of the oxide 230c and the side surface of the opening. 1B and 1C show an example in which oxide 230c is provided in the opening on oxide 230b and on insulator 224, and is in contact with the side surface of oxide 243 and part of the side surface of conductor 242, and oxide 230d is in contact with the upper surface of oxide 230c, another part of the side surface of conductor 242, the side surface of insulator 271, the side surface of insulator 273, the side surface of insulator 275, and the side surface of insulator 280. However, the arrangement of oxide 230c and oxide 230d is not limited to this.

[0050] 1B, oxide 230c may be disposed in a recess formed in oxide 230b, and oxide 230d may be disposed so as to contact the upper surface of oxide 230c, the side of oxide 243, the side of conductor 242, the side of insulator 271, the side of insulator 273, the side of insulator 275, and the side of insulator 280. Also, oxide 230c may be disposed so as to contact the upper surface of oxide 230b and the side of oxide 243, and oxide 230d may be disposed so as to contact the upper surface of oxide 230c, the side of conductor 242, the side of insulator 271, the side of insulator 273, the side of insulator 275, and the side of insulator 280. In addition, oxide 230c may be arranged so as to contact the upper surface of oxide 230b, the side of oxide 243, and the side of conductor 242, and oxide 230d may be arranged so as to contact the upper surface of oxide 230c, the side of insulator 271, the side of insulator 273, the side of insulator 275, and the side of insulator 280.

[0051] The insulator 250 and the conductor 260 are disposed inside the oxide 230d. In addition, in the channel length direction of the transistor 200, the oxide 230c, the oxide 230d, the conductor 260, and the insulator 250 are provided between the insulator 271a, the conductor 242a, and the oxide 243a and the insulator 271b, the conductor 242b, and the oxide 243b. The oxide 230c has a region in contact with the upper surface of the oxide 230b. In addition, the side surface of the oxide 230c is preferably in contact with the conductor 242a and the conductor 242b. In addition, the upper surface of the oxide 230c is in contact with the oxide 230d. The insulator 250 has a region in contact with the side surface of the oxide 230d, a region in contact with the bottom surface of the oxide 230d, a region in contact with the side surface of the conductor 260, and a region in contact with the bottom surface of the conductor 260.

[0052] The oxide 230 preferably has an oxide 230a arranged on the insulator 224, an oxide 230b arranged on the oxide 230a, an oxide 230c arranged on the oxide 230b, and an oxide 230d arranged on the oxide 230c. By having the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b. In addition, by arranging the oxide 230c on the oxide 230b, it is possible to make the oxide 230c or the vicinity of the interface between the oxide 230b and the oxide 230c the main path of carriers.

[0053] For example, when carriers flow from the conductor 242a to the conductor 242b, the following carrier paths are possible. First, when the side of the oxide 230c contacts the conductor 242a and the conductor 242b, the oxide 230c can be the main path of the carriers. Also, when the side of the oxide 230d contacts the conductor 242a and the conductor 242b, the carriers flow from the conductor 242a through the oxide 230d or the oxide 243a to the oxide 230c. Then, the carriers flow from the oxide 230c through the oxide 230d or the oxide 243b to the conductor 242b. Here, it is preferable that the oxide 230d or the oxide 243b has a higher resistivity than the oxide 230b or the oxide 230c. In this case, the oxide 230d or the oxide 243b may function as a high resistance region. Here, the high resistance region refers to a region that has the same effect as a so-called LDD (Lightly Doped Drain). Alternatively, carriers flow from the conductor 242a through the oxide 243a to the oxide 230b. Then, the carriers move near the interface between the oxide 230b and the oxide 230c, and flow through the oxide 243b to the conductor 242b. At this time, the carriers may move within the oxide 230b or within the oxide 230c.

[0054] Moreover, by providing a metal oxide that suppresses the diffusion or permeation of oxygen as the oxide 230d on the side surface of the conductor 242, it is possible to suppress the oxidation of the side surface of the conductor 242 or the expansion of the oxidized region, and to suppress an increase in the resistance value on the side surface of the conductor 242. The film thickness of the oxide 230d is 0.3 nm to 3 nm, preferably 0.5 nm to 1.5 nm.

[0055] The material that can be used for the oxide 230d is not limited to metal oxide. As long as the effect of suppressing the diffusion or permeation of oxygen can be obtained as described above, metal nitride, silicon oxide, silicon nitride, etc. can be used. Even when the above-mentioned materials are used as the material for suppressing the diffusion or permeation of oxygen, these materials are referred to as the oxide 230d for convenience.

[0056] When the side of the conductor 242 is oxidized or the oxidized region expands and the resistance value increases, the region cannot function as the source or drain of the transistor 200, and the distance between the source and drain becomes larger than the distance between the conductor 242a and the conductor 242b. That is, the effective channel length of the transistor 200 becomes longer than the distance between the conductor 242a and the conductor 242b. Furthermore, the effective channel length varies depending on the degree of oxidation of the conductor 242, causing variations in the characteristics of the obtained transistor 200. On the other hand, by providing the oxide 230d on the side of the conductor 242, the oxidation of the side is suppressed, and it is possible to control the effective channel length of the transistor 200 and reduce the variation.

[0057] Note that, in the transistor 200, the oxide 230 includes the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d, but the present invention is not limited to this. For example, a structure not including the oxide 230a or a structure not including the oxide 230d may be used, or one or both of the oxide 230a and the oxide 230b may have a stacked structure.

[0058] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a bottom gate) electrode. The insulator 250 functions as a first gate insulator, and the insulators 222 and 224 function as second gate insulators. The conductor 242a functions as one of a source or a drain, and the conductor 242b functions as the other of the source or the drain. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0059] Here, an enlarged view of the vicinity of the channel formation region in FIG. 1B is shown in FIG. 2A, and an enlarged view of the vicinity of the channel formation region in FIG. 1C is shown in FIG. 2B. As shown in FIG. 2A, the oxide 230b and the oxide 230c have a region 230bc that functions as a channel formation region of the transistor 200. The oxide 230b is provided to sandwich the region 230bc and has regions 230ba and 230bb that function as source and drain regions. At least a portion of the region 230bc overlaps with the conductor 260. In other words, the region 230bc is provided in a region between the conductor 242a and the conductor 242b. The region 230ba has a region that overlaps with the conductor 242a, and the region 230bb has a region that overlaps with the conductor 242b. The region 260L indicates the gate length of the transistor 200. 2A shows an example in which the length of the region 230bc in the channel length direction is greater than the length of the region 260L in the channel length direction, but this embodiment is not limited to this. There are cases in which the length of the region 260L in the channel length direction is equal to the length of the region 230bc in the channel length direction, and cases in which the length of the region 260L in the channel length direction is greater than the length of the region 230bc in the channel length direction.

[0060] The region 230bc functioning as a channel formation region has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, and is therefore a high-resistance region with a low carrier concentration. The regions 230ba and 230bb functioning as a source region or drain region have many oxygen vacancies or a high concentration of impurities such as hydrogen, nitrogen, and metal elements, and therefore have an increased carrier concentration and low resistance. In other words, the regions 230ba and 230bb have a higher carrier concentration and lower resistance than the region 230bc.

[0061] Here, the carrier concentration of the region 230bc functioning as a channel forming region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but is, for example, 1×10 -9 cm -3 It can be said that:

[0062] The carrier concentration in the oxide can be measured using a phase shift method in electron holography analysis, scanning capacitance microscopy (SCM), scanning spreading resistance microscopy (SSRM), etc. In this specification, a material with a relatively high carrier concentration may be referred to as a material with high electrical conductivity or a material with low resistivity. On the other hand, a material with a relatively low carrier concentration may be referred to as a material with low electrical conductivity or a material with high resistivity.

[0063] A region may be formed between the region 230bc and the region 230ba or the region 230bb, the carrier concentration of which is equal to or lower than that of the region 230ba and the region 230bb, and equal to or higher than that of the region 230bc. That is, the region functions as a junction region between the region 230bc and the region 230ba or the region 230bb. The junction region may have a hydrogen concentration equal to or lower than that of the region 230ba and the region 230bb, and equal to or higher than that of the region 230bc. The junction region may have an oxygen vacancy equal to or less than that of the region 230ba and the region 230bb, and equal to or more than that of the region 230bc.

[0064] 2A shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxides 230b and 230c, but the present invention is not limited to this. For example, the above regions may be formed not only in the oxides 230b and 230c, but also in the oxides 230a. The region 230bc may be formed only in the oxide 230c. The region 230bc may be formed in the oxide 230d.

[0065] In addition, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentrations of metal elements, hydrogen, nitrogen, and other impurity elements detected in each region may not only vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements, hydrogen, nitrogen, and other impurity elements decrease in the region closer to the channel formation region.

[0066] In the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 including the channel formation region (the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d).

[0067] In addition, the metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a wide band gap in this way, the off-state current of a transistor can be reduced.

[0068] As the oxide 230, for example, a metal oxide such as an In-M-Zn oxide having indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. Alternatively, as the oxide 230, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0069] Here, it is preferable that the atomic ratio of In to element M in the metal oxides used for oxide 230b and oxide 230c is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0070] In this manner, by disposing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0071] In addition, since the oxide 230a and the oxide 230b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced. Since the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, the effect of interface scattering on carrier conduction can be reduced.

[0072] The oxide 230c may be made of the same material as the oxide 230b. The oxide 230c may be made of a material having an atomic ratio of In to element M that is greater than the atomic ratio of In to element M in the metal oxide used for the oxide 230b. The oxide 230c may be made of In-Zn oxide, indium oxide, or the like that does not contain element M as a main component. The above-mentioned material may be used as a material having a higher electrical conductivity than the oxide 230b. By providing the oxide 230c on the oxide 230b, the mobility of the transistor 200 is improved and a high on-current is obtained. In particular, it is preferable to provide the oxide 230c in contact with the conductor 242a and the conductor 242b, since the above-mentioned effect can be obtained more effectively.

[0073] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230c is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a or oxide 230d.

[0074] In addition, when the oxide 230c is used as the main path of the carriers, the atomic ratio of In to the main metal element in the oxide 230c is preferably greater than the atomic ratio of In to the main metal element in the oxide 230b. In addition, the atomic ratio of In to the element M in the oxide 230c is preferably greater than the atomic ratio of In to the element M in the oxide 230b. By using a metal oxide with a high In content in the channel formation region, the on-current of the transistor can be increased. Therefore, by making the atomic ratio of In to the main metal element in the oxide 230c greater than the atomic ratio of In to the main metal element in the oxide 230b, the oxide 230c can be used as the main path of the carriers. In addition, the conduction band minimum of the oxide 230c is preferably farther from the vacuum level than the conduction band minimums of the oxides 230a and 230b. In other words, it is preferable that the electron affinity of the oxide 230c is larger than those of the oxide 230a and the oxide 230b. At this time, the main path of carriers is the oxide 230c.

[0075] Specifically, the oxide 230a or the oxide 230d may be a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, M:Zn=2:1 [atomic ratio] or a composition close thereto, or M:Zn=2:5 [atomic ratio] or a composition close thereto, or an oxide of element M. The oxide 230a and the oxide 230d may be metal oxides having the same composition or different compositions. Specifically, the oxide 230b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, or a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, or a composition of In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto. Specifically, the oxide 230c may be a metal oxide having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, or a composition of In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto, or a composition of In:M:Zn=10:1:3 [atomic ratio] or a composition close thereto, an In-Zn oxide, an indium oxide, or the like. The oxide 230b and the oxide 230c may be metal oxides having the same composition or different compositions.

[0076] In addition, it is preferable that the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d each have crystallinity. In particular, it is preferable that the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d each use CAAC-OS (c-axis aligned crystalline oxide semiconductor).

[0077] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not become polycrystallized after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be increased, and the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0078] On the other hand, it is difficult to identify clear grain boundaries in CAAC-OS, so it is said that the decrease in electron mobility caused by grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and highly reliable.

[0079] The oxide 230d can be made of the same material as the oxide 230a. Alternatively, the oxide 230d can be made of a material having an atomic ratio of In to the element M smaller than the atomic ratio of In to the element M in the metal oxide used for the oxide 230b.

[0080] Moreover, the oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230c, and more preferably contains all of the metal elements. For example, the oxide 230c may be In-M-Zn oxide, In-Zn oxide, or indium oxide, and the oxide 230d may be In-M-Zn oxide, M-Zn oxide, or an oxide of element M. This can reduce the defect state density at the interface between the oxide 230c and the oxide 230d.

[0081] Specifically, the oxide 230c may be a metal oxide having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto, or In:M:Zn=10:1:3 [atomic ratio] or a composition close thereto, or an indium oxide. The oxide 230d may be a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, M:Zn=2:1 [atomic ratio] or a composition close thereto, or M:Zn=2:5 [atomic ratio] or a composition close thereto, or an oxide of element M. The term "nearby composition" includes a range of ±30% of the desired atomic ratio. As the element M, it is preferable to use gallium.

[0082] Moreover, the oxide 230d is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c. By providing the oxide 230d between the insulator 250 and the conductor 242, oxidation of the conductor 242 can be suppressed, and oxygen contained in the insulator 250 can be efficiently supplied to the oxide 230c and the oxide 230b.

[0083] Note that the oxide 230c and the oxide 230d may be provided for each transistor 200. That is, the oxide 230c and the oxide 230d of the transistor 200 may not be in contact with the oxide 230c and the oxide 230d of the transistor 200 adjacent to the transistor 200. The oxide 230c and the oxide 230d of the transistor 200 may be separated from the oxide 230c and the oxide 230d of the transistor 200 adjacent to the transistor 200. In other words, the oxide 230c and the oxide 230d may not be disposed between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0084] In a semiconductor device in which a plurality of transistors 200 are arranged in the channel width direction, the above configuration allows the oxide 230c and the oxide 230d to be provided independently in the transistor 200. This makes it possible to suppress the generation of a parasitic transistor between the transistor 200 and a transistor 200 adjacent to the transistor 200, thereby suppressing the generation of the leakage path. Thus, it is possible to provide a semiconductor device that has favorable electrical characteristics and can be miniaturized or highly integrated.

[0085] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region in which a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies is called a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) and generate electrons that serve as carriers. For this reason, if oxygen vacancies are present in a region in an oxide semiconductor in which a channel is formed, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region in an oxide semiconductor in which a channel is formed, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that a region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0086] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor and heat treatment is performed. In this way, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or drain region, this may cause a decrease in the on-current or a decrease in the field effect mobility of the transistor 200. Furthermore, if the oxygen supplied to the source region or drain region varies within the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0087] Therefore, in the oxide semiconductor, the region 230bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 230ba and 230bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 230ba and 230bb.

[0088] Therefore, in this embodiment, the oxide 230b is subjected to microwave processing in an atmosphere containing oxygen, and the oxygen vacancies in the region 230bc and the V O H is reduced. Here, the microwave treatment refers to a treatment using an apparatus having a power source that generates high density plasma using microwaves, for example. At this time, by performing the microwave treatment in a state where the conductor 242a and the conductor 242b are provided on the oxide 230b, the region 230bc of the oxide 230b can be effectively irradiated with microwaves. The microwave treatment may also be performed in a state where one or both of the insulator 250a and the insulator 250b are provided on the region 230bc. The microwave treatment may be performed immediately after the formation of the oxide 230, or may be performed during the manufacturing process of the transistor 200. The microwave treatment is preferably performed once or a plurality of times during the manufacturing process of the transistor 200.

[0089] 3A to 3C show the behavior of microwaves when they are incident on a metal or dielectric material.

[0090] 3A shows the behavior of microwaves when they are incident on metal 501. In FIG. 3A, the microwaves incident on metal 501 are referred to as incident microwaves 503, and the microwaves reflected by metal 501 are referred to as reflected microwaves 505. Incident microwaves 503 are reflected by free electrons on the surface of metal 501. Thus, incident microwaves 503 are reflected as reflected microwaves 505 without reaching the inside of metal 501 or the layer below metal 501. In other words, incident microwaves 503 are blocked by metal 501.

[0091] 3B shows the behavior of microwaves when they are incident on dielectric 511. In FIG. 3B, a microwave incident on dielectric 511 is referred to as incident microwave 513, a microwave reflected by dielectric 511 is referred to as reflected microwave 515, and a microwave transmitted through dielectric 511 is referred to as transmitted microwave 517. A part of incident microwave 513 is reflected at the surface of dielectric 511, inside dielectric 511, or at the interface with the lower layer of dielectric 511. Another part of incident microwave 513 transmits through dielectric 511. Thus, a part of incident microwave 513 is reflected by dielectric 511 as reflected microwave 515, and another part of incident microwave 513 transmits through dielectric 511 as transmitted microwave 517.

[0092] FIG. 3C shows the behavior of microwaves when the microwaves are incident on the dielectric 521. In FIG. 3C, the microwaves incident on the dielectric 521 are referred to as incident microwaves 523, the microwaves reflected by the dielectric 521 are referred to as reflected microwaves 525, and the microwaves transmitted through the dielectric 521 are referred to as transmitted microwaves 527. Here, the relative dielectric constant or loss factor of the dielectric 521 is greater than the relative dielectric constant or loss factor of the dielectric 511. A part of the incident microwaves 523 is reflected by the surface of the dielectric 521, the inside of the dielectric 521, or the interface with the lower layer of the dielectric 521. In addition, another part of the incident microwaves 523 transmits through the dielectric 521. Thus, a part of the incident microwaves 523 is reflected by the dielectric 521 as reflected microwaves 525, and another part of the incident microwaves 523 transmits through the dielectric 521 as transmitted microwaves 527.

[0093] FIG. 3B and FIG. 3C show examples of irradiating microwaves to dielectrics having relatively different dielectric constants or loss factors. The dielectric constant or loss factor of the dielectric 511 is smaller than that of the dielectric 521, and the dielectric constant or loss factor of the dielectric 521 is larger than that of the dielectric 511. A part of the microwave incident on the dielectric is absorbed by the dielectric and reflected by the dielectric as a reflected microwave. At this time, if the dielectric constant or loss factor of the dielectric is small, the microwave is hardly absorbed and passes through the dielectric. On the other hand, if the dielectric constant or loss factor of the dielectric is large, the microwave absorbed by the dielectric increases, and the reflected microwave increases accordingly. Absorption of microwaves occurs when the frequency that causes polarization of the dielectric and the microwave frequency resonate with each other. When polarization occurs in the dielectric, the dielectric heats up due to the vibration of atoms and electrons. From this, it can be understood that a dielectric with a large dielectric constant or loss factor is more likely to heat up when irradiated with microwaves.

[0094] Since dielectric 521 shown in FIG. 3C has a larger dielectric constant or loss factor than dielectric 511, region 529 irradiated with incident microwave 523 may generate heat. If there is a risk that dielectric 521 or a material in contact with it may be altered due to heat generation in region 529, the thickness of dielectric 521 may be reduced. For dielectrics having the same dielectric constant or loss factor, the smaller the thickness of the dielectric, the more the absorption of microwaves can be suppressed and the amount of heat generated by microwave irradiation can be reduced. Here, alteration refers to a change in the crystallinity, composition, etc. of dielectric 521 or a material in contact with it.

[0095] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be made to work. At this time, microwaves or high frequency waves such as RF can be irradiated onto the oxide 230, particularly the region 230bc. The V of the region 230bc can be increased by the action of the plasma, microwaves, etc. OH is split off, hydrogen H is removed from the region 230bc, and oxygen vacancy V O can be compensated for with oxygen. That is, in the region 230bc, "V O H→H+V O " and "V O +O→null” occurs, and the hydrogen concentration in the region 230bc can be reduced. O It is possible to reduce H and lower the carrier concentration. Note that this microwave treatment may be performed on the entire oxide 230, or may be performed on the oxide film that constitutes the oxide 230.

[0096] Here, the conductor 242a and the conductor 242b correspond to the metal 501 described above. Therefore, when microwave processing is performed in an atmosphere containing oxygen after the conductor 242a and the conductor 242b are formed on the oxide 230 and before the conductor 260 is formed, the action of microwaves, high frequency waves such as RF, oxygen plasma, etc. is shielded by the conductor 242a and the conductor 242b and does not reach the region 230ba and the region 230bb. Furthermore, the action of oxygen plasma can be reduced by the insulators 271, 273, 275, and 280 that are provided to cover the oxide 230b and the conductor 242. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, a decrease in the carrier concentration can be prevented.

[0097] In this manner, oxygen vacancies and V are selectively formed in the oxide semiconductor region 230bc. O By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be suppressed, and the n-type can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor 200, and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0098] By adopting the above-mentioned configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device having good electrical characteristics.

[0099] In FIG. 1 and other figures, the side of the opening in which the conductor 260 and the like are embedded is perpendicular or approximately perpendicular to the surface on which the oxide 230b is formed, including the groove of the oxide 230b, but this embodiment is not limited to this. For example, the bottom of the opening may be in a U-shape with a gentle curve. Also, for example, the side of the opening may be inclined with respect to the surface on which the oxide 230b is formed.

[0100] 1C, in a cross-sectional view in the channel width direction of the transistor 200, there may be curved surfaces between the side surface of the oxide 230b and the top surface of the oxide 230b, and between the side surface of the oxide 230c and the top surface of the oxide 230c. In other words, the ends of the side surfaces and the ends of the top surface may be curved (hereinafter also referred to as rounded).

[0101] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By forming the curved surface in this manner, the coverage of the oxide 230b by the insulator 250 and the conductor 260 can be improved.

[0102] The oxide 230a and the oxide 230b preferably have different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.

[0103] Moreover, the oxide 230b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies) and have a highly crystalline and dense structure. This can suppress the source electrode or drain electrode from extracting oxygen from the oxide 230b. As a result, even if heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable against heat applied in the manufacturing process.

[0104] Here, the conduction band minimum changes gradually at the junction between the oxide 230a and the oxide 230b. In other words, the conduction band minimum at the junction between the oxide 230a and the oxide 230b can be said to change continuously or to be a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b.

[0105] Specifically, the oxide 230a and the oxide 230b have a common element other than oxygen as a main component, so that a mixed layer with a low defect level density can be formed. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a can be an oxide containing at least one of In, element M, and Zn. For example, an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, or the like may be used. Also, when the oxide 230a is an In-M-Zn oxide, the oxide 230b can be an oxide containing at least one of In, element M, and Zn. For example, an In-M-Zn oxide, an In-Zn oxide, an indium oxide, or the like may be used.

[0106] Specifically, the oxide 230a may be a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto. The oxide 230b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. The composition close thereto includes a range of ±30% of the desired atomic ratio. The element M is preferably gallium.

[0107] The oxide 230c may be made of the same material as the oxide 230b. The oxide 230c may be made of a material having an atomic ratio of In to element M that is greater than the atomic ratio of In to element M in the metal oxide used for the oxide 230b. Specifically, the oxide 230c may be made of a metal oxide having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, or a composition of In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto. The oxide 230c may be made of an In-Zn oxide, an indium oxide, or the like that does not contain the element M as a main component. The above-mentioned materials may be used as materials having a higher electrical conductivity than the oxide 230b. By providing the oxide 230c on the oxide 230b, the mobility of the transistor 200 is improved, and a high on-current is obtained.

[0108] Also, as described in the description of oxide 230b, oxide 230c is preferably a crystalline oxide such as CAAC-OS.

[0109] The oxide 230d may be made of the same material as the oxide 230a. The oxide 230d may be made of a material having an atomic ratio of In to element M smaller than the atomic ratio of In to element M in the metal oxide used for the oxide 230b. Specifically, the oxide 230d may be made of a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or a composition of In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto. The oxide 230d preferably has a higher electrical resistivity than the oxide 230b. When the oxide 230d is provided between the conductor 242 and the oxide 230c, i.e., on the carrier path, the oxide 230d becomes a high resistance region and can have a function equivalent to a so-called LDD region.

[0110] In addition, the oxide 230d is preferably an oxide having crystallinity such as CAAC-OS. In this case, the c-axis of the crystal plane of the oxide 230d is oriented perpendicular or approximately perpendicular to the surface on which it is formed. That is, the c-axis of the crystal plane of the oxide 230d has a component oriented perpendicular or approximately perpendicular to the surface of the oxide 230c, and a component oriented perpendicular or approximately perpendicular to the side surface of the conductor 242. Here, when oxygen contained in the insulator 280 or the insulator 250a is supplied to the oxide 230d, the oxygen is more likely to move in the ab-plane direction than in the c-axis direction of the oxide 230d. That is, since the oxygen is less likely to move to the conductor 242, the oxidation of the side surface of the conductor 242 can be suppressed by providing the oxide 230d on the side surface of the conductor 242.

[0111] In addition, when a metal oxide film is formed by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0112] In addition, when a metal oxide film is formed by a chemical vapor deposition (CVD) method such as a metal organic chemical vapor deposition (MOCVD) method or an atomic layer deposition (ALD) method, the atomic ratio of the formed metal oxide film may be close to the above atomic ratio.

[0113] By configuring the oxide 230a and the oxide 230b as described above, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced. Therefore, the influence of the interface scattering on the carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics. Furthermore, by providing the oxide 230c on the oxide 230b, the transistor 200 can obtain a larger on-current and higher frequency characteristics. Furthermore, by providing the oxide 230d, the effective channel length of the transistor 200 can be controlled and its variation can be reduced, so that the transistor 200 with less variation and good characteristics can be realized.

[0114] At least one of the insulators 212, 214, 271, 273, 275, 282, 284, 283, and 286 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, at least one of the insulators 212, 214, 271, 273, 275, 282, 284, 283, and 286 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (through which the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (through which the above oxygen is difficult to permeate).

[0115] In this specification, a barrier insulating film refers to an insulating film having a barrier property. In this specification, the barrier property means a function of suppressing the diffusion of a corresponding substance (also called low permeability) or a function of capturing and fixing a corresponding substance (also called gettering).

[0116] For the insulators 212, 214, 271, 273, 275, 282, 284, 283, and 286, it is preferable to use insulators having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride or the like having a higher hydrogen barrier property as the insulators 212, 275, 283, and 286. Furthermore, for example, it is preferable to use aluminum oxide or magnesium oxide or the like having a high function of capturing and fixing hydrogen as the insulators 214, 271, 273, 282, and 284. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulator 286 to the transistor 200 side. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulator 212 and the insulator 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280 or the like to an upper side than the transistor 200 through the insulator 282 or the like. In this manner, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 273, 275, 282, 284, 283, and 286, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0117] Here, it is preferable to use an oxide having an amorphous structure as the insulator 214, the insulator 271, the insulator 273, the insulator 282, and the insulator 284. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as y (y is any number greater than 0). In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a transistor 200 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0118] Furthermore, the insulators 214, 271, 273, 282, and 284 preferably have an amorphous structure, but may have a polycrystalline region in a portion thereof. The insulators 214, 271, 273, 282, and 284 may have a multilayer structure in which a layer of an amorphous structure and a layer of a polycrystalline structure are stacked. For example, they may have a stacked structure in which a layer of a polycrystalline structure is formed on a layer of an amorphous structure.

[0119] The insulators 212, 214, 271, 273, 275, 282, 284, 283, and 286 may be formed by, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen as a film formation gas, the hydrogen concentration of the insulators 212, 214, 271, 273, 275, 282, 284, 283, and 286 can be reduced. Note that the film formation method is not limited to the sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like may be used as appropriate.

[0120] It may also be preferable to reduce the resistivity of the insulators 212, 283, and 286. For example, it may be preferable to reduce the resistivity of the insulators 212, 283, and 286 to approximately 1×10 13 By setting the resistivity at Ωcm, the insulator 212, the insulator 283, and the insulator 286 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, the conductor 240, or the conductor 246 during a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulator 212, the insulator 283, and the insulator 286 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0121] The insulators 216, 280, and 274 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like may be used as appropriate for the insulators 216, 280, and 274.

[0122] The conductor 205 has a region overlapping with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216.

[0123] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and side wall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. The conductor 205c is provided in contact with the upper surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the upper surface of the conductor 205c is approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216. In other words, the conductor 205b is configured to be wrapped in the conductor 205a and the conductor 205c.

[0124] Here, the conductor 205a and the conductor 205c are preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0125] By using a conductive material having a function of reducing hydrogen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224 and the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to suppress the conductor 205b from being oxidized and its conductivity from decreasing. As the conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive material. For example, the conductor 205a may be made of titanium nitride.

[0126] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0127] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 (gate potential of the transistor 200) is 0 V, compared to not applying a negative potential.

[0128] The electrical resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and therefore the diffusion of the impurities into the oxide 230 can be reduced.

[0129] As shown in FIG. 1A, the conductor 205 is preferably provided larger than the size of the region of the oxide 230 that does not overlap with the conductor 242a and the conductor 242b. In particular, as shown in FIG. 1C and FIG. 2B, the conductor 205 preferably extends to the region outside the end of the oxide 230a and the oxide 230b that intersects with the channel width direction. In other words, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator on the outside of the side surfaces of the oxide 230a and the oxide 230b in the channel width direction. With this configuration, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode can electrically surround the channel formation region of the oxide 230a, the oxide 230b, and the oxide 230c on the oxide 230b. In this specification, a transistor structure in which a channel formation region is electrically surrounded by the electric fields of a first gate and a second gate is called a surrounded channel (S-channel) structure.

[0130] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a fin type structure and a planar type structure. By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to make a transistor in which the short channel effect is unlikely to occur.

[0131] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0132] Note that, in the transistor 200, the conductor 205 has a stacked structure of the conductor 205a, the conductor 205b, and the conductor 205c, but the present invention is not limited to this. For example, the conductor 205 may have a single layer, a two-layer, or a four or more layer stacked structure.

[0133] Insulator 222 and insulator 224 function as gate insulators.

[0134] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0135] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Thus, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the insulator 224 and the oxygen contained in the oxide 230.

[0136] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. The insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0137] The insulator 222 may be a single layer or a multilayer of insulators containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0138] The thickness of the insulator 222 is preferably 1 nm to 30 nm, typically 5 nm, 10 nm, or 20 nm.

[0139] The insulator 224 in contact with the oxide 230 preferably contains excess oxygen (oxygen is released by heating). For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0140] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 224. An oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 More than 1.0×10 19 molecules / cm 3 More preferably, 2.0×10 19 molecules / cm 3 or more than 3.0×10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0141] In addition, in the manufacturing process of the transistor 200, it is preferable to perform heat treatment while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 600° C. or lower, more preferably 350° C. or higher and 550° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230 to reduce oxygen deficiencies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0142] In addition, by subjecting the oxide 230 to an oxygen addition treatment, the oxygen vacancies in the oxide 230 are repaired by the supplied oxygen. In other words, O In addition, the reaction of the hydrogen remaining in the oxide 230 with the oxygen supplied can be promoted, and the hydrogen can be removed as H2O (dehydrated). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0143] In addition to or instead of the above-mentioned heat treatment or oxygen addition treatment, the above-mentioned microwave treatment may be performed. O H is split off, hydrogen H is removed from the oxide 230, and oxygen vacancy V O can be compensated for with oxygen. O H→H+V O " and "V O+O→null” reaction occurs, and the hydrogen concentration in the oxide 230 can be reduced. Therefore, the oxygen vacancies in the oxide 230 and the V O H can be reduced, lowering the carrier concentration.

[0144] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, and may be made of different materials. The insulator 224 may be formed in an island shape by overlapping with the oxide 230a. In this case, the insulator 275 is configured to contact the side surface of the insulator 224 and the upper surface of the insulator 222.

[0145] An oxide 243a and an oxide 243b are provided on the oxide 230b. The oxide 243a and the oxide 243b are provided apart from each other with the conductor 260 therebetween.

[0146] The oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 243, which has a function of suppressing oxygen permeation, between the conductor 242 functioning as a source electrode or drain electrode and the oxide 230b, oxidation of the conductor 242 can be suppressed. This is also preferable because the electrical resistance between the conductor 242 and the oxide 230b is reduced. With this structure, the electrical characteristics and reliability of the transistor 200 can be improved. Note that if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.

[0147] A metal oxide having element M may be used as the oxide 243. In particular, the element M may be one or more selected from aluminum, gallium, yttrium, tin, and titanium. The oxide 243 preferably has a higher concentration of element M than the oxide 230b. Gallium oxide may be used as the oxide 243. A metal oxide such as an In-M-Zn oxide may be used as the oxide 243. Specifically, a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn=1:1:1 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn=1:3:2 [atomic ratio] or a composition in the vicinity thereof, M:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or M:Zn=2:5 [atomic ratio] or a composition in the vicinity thereof, or an oxide of element M may be used. The thickness of the oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and further preferably 1 nm to 2 nm. The oxide 243 is preferably crystalline. When the oxide 243 is crystalline, the release of oxygen in the oxide 230 can be suitably suppressed. For example, if the oxide 243 has a crystal structure such as a hexagonal crystal structure, the release of oxygen in the oxide 230 can be suppressed in some cases.

[0148] It is preferable that the conductor 242a be provided in contact with an upper surface of the oxide 243a, and the conductor 242b be provided in contact with an upper surface of the oxide 243b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0149] As the conductor 242 (conductor 242a and conductor 242b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.

[0150] Note that hydrogen contained in the oxide 230b etc. may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b etc. is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b etc. may be absorbed by the conductor 242a or the conductor 242b.

[0151] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. The insulator 271 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 271 preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 271 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280. For example, a nitride containing silicon such as silicon nitride may be used as the insulator 271. Also, the insulator 271 preferably has a function of capturing impurities such as hydrogen. In that case, the insulator 271 may be an insulator such as a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide. In particular, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 271 because hydrogen can be captured or fixed more effectively. This makes it possible to manufacture a transistor 200 and a semiconductor device having excellent characteristics and high reliability.

[0152] The insulator 273 is provided so as to cover the insulator 224, the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and the insulator 271, and is provided in contact with the upper surfaces of the insulator 224, the insulator 271a, and the insulator 271b. The insulator 273 is preferably in contact with the side surfaces of the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and the insulator 271. The insulator 275 is provided on the insulator 273. The insulator 273 preferably has a function of capturing impurities such as hydrogen. In that case, an insulator such as a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide, may be used as the insulator 273. In particular, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 273, since hydrogen may be more effectively captured or fixed. As a result, a transistor 200 and a semiconductor device having favorable characteristics and high reliability can be manufactured.

[0153] The insulator 275 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 275 preferably has a function of suppressing oxygen diffusion. For example, the insulator 275 preferably has a function of suppressing oxygen diffusion more than the insulator 280. As the insulator 275, for example, a nitride containing silicon, such as silicon nitride, may be used.

[0154] By providing the insulator 271 and the insulator 273 as described above, the conductor 242 can be wrapped in an insulator having a barrier property against oxygen. This makes it possible to suppress oxidation of the conductor 242, and to suppress an increase in the resistivity of the conductor 242 and a decrease in the on-current of the transistor 200.

[0155] Note that in the case where the insulator 275 has sufficient barrier properties against oxygen and the like, one or both of the insulators 271 and 273 may be omitted.

[0156] The insulator 275 is provided to cover the insulator 273, and an opening is formed in the region where the insulator 250 and the conductor 260 are provided. The insulator 275 is preferably provided in contact with the upper surface of the insulator 273. The insulator 275 preferably functions as a barrier insulating film that suppresses oxygen transmission. The insulator 275 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing from above to the insulator 224 or the insulator 273, and preferably has a function of capturing impurities such as hydrogen. In that case, the insulator 275 preferably includes an insulator such as a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide. For example, an insulator such as aluminum oxide or silicon nitride may be used as the insulator 275.

[0157] By providing insulator 271, insulator 273, or insulator 275, which has a function of capturing impurities such as hydrogen and is in contact with insulator 280, insulator 224, or insulator 273 in the region sandwiched between insulator 212 and insulator 283, impurities such as hydrogen contained in insulator 280, insulator 224, insulator 273, or the like can be captured, and the amount of hydrogen in the region can be kept constant. In this case, it is preferable to use aluminum oxide or the like as insulator 271, insulator 273, or insulator 275.

[0158] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. Also, hafnium oxide can be used as the insulator 250. Two or more materials selected from the above materials may be stacked. For example, silicon oxide or silicon oxynitride can be used as the insulator 250a, and hafnium oxide can be used as the insulator 250b on the insulator 250a.

[0159] Like the insulator 224, the insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less. When the insulator 250 has a layered structure of the insulator 250a and the insulator 250b, the thickness of the insulator 250b is preferably 0.5 nm or more and 2 nm or less, and more preferably 1 nm or more and 1.5 nm or less.

[0160] In addition, in FIG. 1B and FIG. 1C, the insulator 250 is illustrated as a two-layered structure of the insulator 250a and the insulator 250b, but it may be a single layer or a three-layered or more layered structure. When the insulator 250 is a two-layered structure, it is preferable that the insulator 250a is formed using an insulator that releases oxygen when heated, and the insulator 250b is formed using an insulator that has a function of suppressing the diffusion of oxygen. By adopting such a configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulator 250a is provided using an insulating material containing silicon, such as the above-mentioned silicon oxide or silicon oxynitride, and the insulator 250b can be provided using a material similar to the insulator 222 in addition to the above-mentioned hafnium oxide.

[0161] When silicon oxide or silicon oxynitride is used for the insulator 250a, the insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. The gate insulator can be made into a laminated structure of the insulators 250a and 250b, which is stable against heat and has a high dielectric constant. This makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0162] Specifically, the insulator 250b may be a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium. For example, the insulator 250 may be a laminated structure containing silicon oxide and hafnium oxide on the silicon oxide.

[0163] The thickness of the insulator 250b may be set to 0.5 nm or more and 5 nm or less, preferably 1 nm or more and 3 nm or less, and more preferably 1 nm or more and 2 nm or less. Typically, the thickness of the insulator 250b may be set to 1.5 nm. The thickness can be appropriately selected by the practitioner according to the performance required for the transistor 200.

[0164] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen from the insulator 250 can be suppressed.

[0165] The metal oxide may be configured to function as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 may be used as the metal oxide. In this case, the electric resistance value of the metal oxide can be reduced to make it a conductor by forming the conductor 260a by a sputtering method. This can be called an OC (Oxide Conductor) electrode.

[0166] By including the metal oxide, the on-current of the transistor 200 can be improved without weakening the effect of the electric field from the conductor 260. Furthermore, by maintaining a distance between the conductor 260 and the oxide 230 due to the physical thickness of the insulator 250 and the metal oxide, it is possible to suppress leakage current between the conductor 260 and the oxide 230. Furthermore, by providing a stacked structure of the insulator 250 and the metal oxide, it is possible to easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0167] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIG. 1B and FIG. 1C, the top surface of the conductor 260 is substantially flush with the top surface of the insulator 250. Note that, although the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b in FIG. 1B and FIG. 1C, the conductor 260 may be a single-layer structure or a stacked structure of three or more layers.

[0168] The conductor 260a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0169] Furthermore, since the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0170] In addition, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0171] Moreover, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242a and the conductor 242b without alignment.

[0172] 1C, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the interface between the top surface of the oxide 230b and the oxide 230c, when the bottom surface of the insulator 222 is taken as the reference. By configuring the conductor 260, which functions as a gate electrode, to cover the side and top surfaces of the channel formation regions of the oxide 230c and the oxide 230b via the insulator 250 or the like, the electric field of the conductor 260 can be easily applied to the entire channel formation regions of the oxide 230c and the oxide 230b. This increases the on-current of the transistor 200 and improves the frequency characteristics. When the bottom surface of insulator 222 is used as a reference, the difference between the height of the bottom surface of conductor 260 in the region where oxide 230a and oxide 230b do not overlap with conductor 260 and the height of the interface between the top surface of oxide 230b and oxide 230c is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0173] The insulator 280 is provided on the insulator 275, and an opening is formed in the region where the oxide 230c, the insulator 250, and the conductor 260 are provided. In addition, the oxide 230d is provided on the side surface of the opening. In addition, the upper surface of the insulator 280 may be planarized.

[0174] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.

[0175] Like the insulator 224, the insulator 280 preferably has an excess oxygen region or excess oxygen. The concentrations of impurities such as water and hydrogen in the insulator 280 are preferably reduced. For example, the insulator 280 may be an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate. By providing an insulator having excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0176] The insulator 282 preferably has a function of supplying oxygen to the insulator 280 during its formation. The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280, and preferably has a function of capturing impurities such as hydrogen. The insulator 282 preferably functions as a barrier insulating film that suppresses the transmission of oxygen. The insulator 282 may be an insulator such as a metal oxide having an amorphous structure, for example, aluminum oxide. By providing the insulator 282, which is in contact with the insulator 280 and has a function of capturing impurities such as hydrogen, in the region sandwiched between the insulator 212 and the insulator 283, the impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in the region can be made constant. In particular, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 282, because hydrogen can be more effectively captured or fixed. As a result, a transistor 200 and a semiconductor device having favorable characteristics and high reliability can be manufactured.

[0177] The insulator 283 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 283 is disposed on the insulator 282. It is preferable to use a nitride containing silicon, such as silicon nitride or silicon nitride oxide, as the insulator 283. For example, silicon nitride formed by a sputtering method may be used as the insulator 283. By forming the insulator 283 by a sputtering method, a silicon nitride film that is high in density and unlikely to form voids can be formed. Alternatively, the insulator 283 may be formed by stacking a silicon nitride film formed by a CVD method on a silicon nitride film formed by a sputtering method.

[0178] An insulator 284 may be provided between the insulator 282 and the insulator 283. The insulator 284 can be made of a material similar to that of the insulator 282. By providing the insulator 284, impurities such as hydrogen contained in the insulator 280 and the like can be captured more effectively, and the amount of hydrogen in the region sandwiched between the insulator 212 and the insulator 283 can be kept at a constant value.

[0179] The insulator 274 functions as an interlayer insulating film. The insulator 274 preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. The insulator 274 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.

[0180] The conductor 240a and the conductor 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a and the conductor 240b may have a layered structure.

[0181] In addition, when the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the insulators 274, 283, 284, 282, 280, 275, 273, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. In addition, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminated layer. In addition, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide 230 through the conductors 240a and 240b.

[0182] Further, the insulator 241 (insulator 241a and insulator 241b) may be provided on the side of the conductor 240. For example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used as the insulator 241. The insulator 241a and the insulator 241b are provided in contact with the insulator 283, the insulator 284, the insulator 282, the insulator 275, the insulator 273, and the insulator 271, and therefore impurities such as water and hydrogen contained in the insulator 274 and the insulator 280 can be prevented from being mixed into the oxide 230 through the conductor 240a and the conductor 240b. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. Also, it is possible to prevent the oxygen contained in the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.

[0183] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surface of conductor 240a and the upper surface of conductor 240b to function as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0184] The insulator 286 is provided over the conductor 246 and the insulator 274. The insulator 286 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 274. As the insulator 286, it is preferable to use a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 286 may be a silicon nitride film formed by a sputtering method. By forming the insulator 286 by a sputtering method, a silicon nitride film that has high density and is less likely to form voids can be formed. Alternatively, as the insulator 286, a silicon nitride film formed by a CVD method may be stacked on top of the silicon nitride film formed by the sputtering method.

[0185] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0186] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of substrates include a substrate having a metal nitride, a substrate having a metal oxide, and the like. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0187] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0188] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0189] Further, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0190] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0191] In addition, the transistor using metal oxide can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0192] The insulator that functions as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0193] <<Conductors>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0194] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0195] In addition, when an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0196] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0197] <<Metal oxides>> It is preferable to use a metal oxide that functions as a semiconductor (oxide semiconductor) as the oxide 230. Hereinafter, metal oxides that can be applied to the oxide 230 according to the present invention will be described.

[0198] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0199] Here, the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc is considered. The element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium. Other elements applicable to the element M include boron, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where the element M may be a combination of multiple of the above elements.

[0200] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0201] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 4A. Fig. 4A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0202] As shown in FIG. 4A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and poly crystal). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0203] The structure in the bold frame shown in Fig. 4A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" and "Crystal".

[0204] The crystal structure of the film or substrate can be evaluated using X-ray diffraction (XRD) spectrum. Figure 4B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 4B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 4B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 4B is 500 nm.

[0205] As shown in Figure 4B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 4B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0206] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 4C. Figure 4C shows a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 4C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0207] As shown in Figure 4C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0208] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 4A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0209] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0210] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which a plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0211] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0212] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0213] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0214] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0215] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0216] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0217] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the introduction of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against heat applied in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0218] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0219] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0220] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0221] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0222] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0223] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0224] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0225] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0226] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0227] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0228] Oxide semiconductors have a variety of structures and each structure has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0229] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0230] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0231] For the channel formation region of the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0232] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0233] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0234] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0235] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0236] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the vicinity of the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0237] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0238] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 To the following:

[0239] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0240] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0241] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the oxide 230. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material (also called an atomic layer material, a two-dimensional material, etc.) that functions as a semiconductor is preferably used for the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor for the semiconductor material.

[0242] Here, in this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0243] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0244] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0245] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device of one embodiment of the present invention shown in FIGS. 1A to 1D will be described with reference to FIGS. 5A to 26D.

[0246] In each of Figures 5A to 26D, A is a top view. Also, B in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. Also, C in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Also, D in each figure is a cross-sectional view of a portion indicated by a dashed line A5-A6 in A of each figure. Note that in the top view of A in each figure, some elements are omitted for clarity.

[0247] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0248] Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner, and RF-superimposed DC sputtering, which superimposes RF and DC. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when forming a film using a conductive target. In addition to forming a conductive film, DC sputtering can also form an insulating film by performing reactive sputtering. Pulsed DC sputtering is mainly used when forming a film of compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-superimposed DC sputtering allows control of ion energy during film formation and control of the target side potential. Therefore, damage caused by film formation is reduced compared to RF sputtering. Also, a high-quality film can be obtained.

[0249] CVD methods can be classified into plasma enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, photo CVD (Photo CVD), etc. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0250] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0251] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0252] In addition, the ALD method utilizes the self-regulating nature of atoms and can deposit atoms one layer at a time, which has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. In the PEALD (Plasma Enhanced ALD) method, the use of plasma can enable film formation at lower temperatures, which may be preferable. Note that some precursors used in the ALD method contain impurities such as carbon. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS).

[0253] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0254] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0255] First, a substrate (not shown) is prepared, and the insulator 212 is formed on the substrate (see FIGS. 5A to 5D). The insulator 212 is preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the method for forming the insulator 212 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.

[0256] In this embodiment, a silicon nitride film is formed by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas as the insulator 212. By using the pulsed DC sputtering method, a film can be formed stably even with a target having a lower conductivity than a metal target. In addition, the generation of particles due to arcing on the target surface can be suppressed, so the quality of the formed film is good.

[0257] By using an insulator such as silicon nitride through which impurities such as water and hydrogen do not easily permeate, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using an insulator such as silicon nitride through which copper does not easily permeate as the insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below the insulator 212, it is possible to suppress the diffusion of the metal upward through the insulator 212.

[0258] Next, the insulator 214 is deposited on the insulator 212 (see FIGS. 5A to 5D). The insulator 214 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of hydrogen or hydride in the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0259] In this embodiment, an aluminum oxide film is formed by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas as the insulator 214. By using the pulse DC sputtering method, an insulator with good film quality can be formed.

[0260] It is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high function of trapping and fixing hydrogen, as the insulator 214. This makes it possible to trap or fix hydrogen contained in the insulator 216 and the like and prevent the hydrogen from diffusing into the oxide 230. In particular, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 214, because hydrogen can be more effectively trapped or fixed. This makes it possible to manufacture a transistor 200 and a semiconductor device having excellent characteristics and high reliability.

[0261] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of hydrogen or hydride in a deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0262] In this embodiment, a silicon oxide film is formed by pulse DC sputtering using a silicon target in an atmosphere containing oxygen gas as the insulator 216. By using the pulse DC sputtering method, an insulator with good film quality can be formed.

[0263] It is preferable that the insulators 212, 214, and 216 are successively formed without exposure to the air. For example, a multi-chamber film formation apparatus can be used. This allows the insulators 212, 214, and 216 to be formed with reduced hydrogen in the films, and further reduces the incorporation of hydrogen into the films between each film formation process.

[0264] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The opening may refer to a region in which the opening is formed. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form a groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, it is preferable to use silicon nitride, aluminum oxide, or hafnium oxide for the insulator 214. Furthermore, a recess or opening may be formed in the insulator 214 by forming the opening. The recess or opening formed in the insulator 214 may be included in the opening.

[0265] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0266] After the openings are formed, the conductive film 205A is formed (see FIGS. 5A to 5D). The conductive film 205A desirably includes a conductor having a function of suppressing oxygen transmission. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film 205A may be a stacked film of a conductor having a function of suppressing oxygen transmission and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film 205A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0267] In this embodiment, titanium nitride is formed as the conductive film 205A. By using such a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0268] Next, a conductive film 205B is formed (see FIGS. 5A to 5D). As the conductive film 205B, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film 205B.

[0269] Next, a CMP process is performed to remove a portion of the conductive film 205A and the conductive film 205B, thereby exposing the insulator 216 (see FIGS. 6A to 6D). As a result, the conductor 205a and the conductor 205b remain only in the openings. Note that the CMP process may remove a portion of the insulator 216.

[0270] Next, etching is performed to remove the upper portion of the conductor 205b (see FIGS. 7A to 7D). As a result, the upper surface of the conductor 205b becomes lower than the upper surfaces of the conductor 205a and the insulator 216. The conductor 205b can be etched by dry etching or wet etching, but dry etching is preferable for controlling the amount of etching in the depth direction.

[0271] Next, the conductive film 205C is formed over the insulator 216, the conductor 205a, and the conductor 205b (see FIGS. 8A to 8D). The conductive film 205C preferably contains a conductor having a function of suppressing oxygen permeation, similar to the conductive film 205A.

[0272] In this embodiment, titanium nitride is formed as the conductive film 205C. By using such a metal nitride as the upper layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 222 or the like. Even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205c.

[0273] Next, a part of the conductive film 205C is removed by performing CMP processing to expose the insulator 216 (see FIG. 9A to FIG. 9D). As a result, the conductor 205a, the conductor 205b, and the conductor 205c remain only in the opening. This allows the conductor 205 to be formed with a flat upper surface. Furthermore, the conductor 205b is configured to be surrounded by the conductor 205a and the conductor 205c. This prevents impurities such as hydrogen from the conductor 205b from diffusing out of the conductor 205a and the conductor 205c, and prevents oxygen from entering from outside the conductor 205a and the conductor 205c and oxidizing the conductor 205b. Note that the CMP processing may remove a part of the insulator 216.

[0274] Next, the insulator 222 is formed on the insulator 216 and the conductor 205 (see FIGS. 10A to 10D). As the insulator 222, an insulator containing one or both of an oxide of aluminum and hafnium may be formed. Note that as the insulator containing one or both of an oxide of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. An insulator containing one or both of an oxide of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, the hydrogen and water contained in the structure provided around the transistor 200 are prevented from diffusing into the inside of the transistor 200 through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed.

[0275] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a hafnium oxide film is formed by a sputtering method as the insulator 222. By using a sputtering method in which hydrogen is not required as a deposition gas, the hydrogen concentration in the insulator 222 can be reduced.

[0276] It is preferable to carry out a heat treatment subsequently. The heat treatment may be carried out at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0277] In addition, it is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulator 222 as much as possible.

[0278] In this embodiment, after the insulator 222 is formed, heat treatment is performed at a flow rate ratio of nitrogen gas and oxygen gas of 4 slm:1 slm at a temperature of 400° C. for one hour. The heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may cause part of the insulator 222 to crystallize. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0279] Next, the insulator 224 is formed on the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 224 by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 224 can be reduced. Since the insulator 224 comes into contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0280] Here, in order to form an excess oxygen region in the insulator 224, a plasma treatment including oxygen may be performed under reduced pressure. For the plasma treatment including oxygen, it is preferable to use an apparatus having a power source that generates high density plasma using, for example, microwaves. Alternatively, the apparatus may have a power source that applies RF (Radio Frequency) to the substrate side. By using high density plasma, high density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment including an inert gas using this apparatus, a plasma treatment including oxygen may be performed to compensate for the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, heat treatment does not need to be performed.

[0281] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, a CMP process may be performed until the insulator 224 is reached. The CMP process can planarize and smooth the surface of the insulator 224. By disposing the aluminum oxide on the insulator 224 and performing the CMP process, it becomes easy to detect the end point of the CMP process. In addition, the CMP process may polish a part of the insulator 224, and the thickness of the insulator 224 may become thin, but the thickness may be adjusted when the insulator 224 is formed. By planarizing and smoothing the surface of the insulator 224, it may be possible to prevent a deterioration in the coverage rate of the oxide to be formed later and to prevent a decrease in the yield of the semiconductor device. In addition, it is preferable to form an aluminum oxide film on the insulator 224 by a sputtering method, since oxygen can be added to the insulator 224.

[0282] Next, oxide film 230A and oxide film 230B are sequentially formed on insulator 224 (see FIGS. 10A to 10D). Note that oxide film 230A and oxide film 230B are preferably formed successively without being exposed to the air environment. By forming the films without exposing them to the air, it is possible to prevent impurities or moisture from the air environment from adhering to oxide film 230A and oxide film 230B, and it is possible to keep the vicinity of the interface between oxide film 230A and oxide film 230B clean.

[0283] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0284] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed can be increased. In addition, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0285] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the ratio of oxygen contained in the sputtering gas may be set to 70% or more, preferably 80% or more, and more preferably 100%.

[0286] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than or equal to 1% and less than or equal to 30%, preferably 5% to 20%,. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. When the oxide film is formed while the substrate is heated, the crystallinity of the oxide film can be improved.

[0287] In this embodiment, the oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. The oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. The composition of the obtained oxide film 230A is In:Ga:Zn=1:3:4 or close to it. The composition of the obtained oxide film 230B is In:Ga:Zn=4:2:4.1 or close to it. For example, the composition of the obtained oxide film 230B is In:Ga:Zn=4:2:3 or close to it. It is preferable to form each oxide film according to the characteristics required for the oxide 230a and the oxide 230b by appropriately selecting the film formation conditions and the atomic ratio.

[0288] Next, the oxide film 243A is formed on the oxide film 230B (see FIGS. 10A to 10D). The oxide film 243A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 243A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. The composition of the obtained oxide film 243A is In:Ga:Zn=1:3:4 or close to that.

[0289] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A by a sputtering method without exposing them to the atmosphere. For example, a multi-chamber film forming apparatus may be used. This allows the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A to be formed with reduced hydrogen in the films, and further reduces the inclusion of hydrogen in the films between each film forming process.

[0290] Next, it is preferable to perform a heat treatment. The heat treatment may be performed in a temperature range where the oxide film 230A, the oxide film 230B, and the oxide film 243A are not polycrystallized, and may be performed at 250° C. to 650° C., preferably 400° C. to 600° C. For example, the heat treatment may be performed at 400° C. or 550° C., and the implementer may appropriately select the temperature according to the desired characteristics of the transistor 200 and the heat resistance of the semiconductor device. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0291] In addition, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and the like from being taken into the oxide film 230A, the oxide film 230B, and the oxide film 243A as much as possible.

[0292] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for 1 hour, followed by another heat treatment in an oxygen atmosphere at 400°C for 1 hour. This heat treatment can remove impurities such as water and hydrogen from the oxide film 230A, the oxide film 230B, and the oxide film 243A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser and more compact structure. This can reduce the diffusion of oxygen or impurities in the oxide film 230B.

[0293] In addition to or instead of the above heat treatment, a microwave treatment may be performed (see Figs. 10A to 10D). In addition, in the above heat treatment, instead of the heat treatment performed in a nitrogen atmosphere, a microwave treatment may be performed, and then a heat treatment may be performed in an oxygen atmosphere. Here, the dotted lines in Figs. 10B, 10C, and 10D indicate microwaves, high frequency such as RF, oxygen plasma, or oxygen radicals. For the microwave treatment, it is preferable to use a microwave treatment device having a power source that generates high density plasma using microwaves. In addition, the microwave treatment device may have a power source that applies RF to the substrate side. By using high density plasma, high density oxygen radicals can be generated. In addition, by applying RF to the substrate side, oxygen ions generated by high density plasma can be efficiently guided into the oxide film 230A, the oxide film 230B, and the oxide film 243A. In addition, the microwave treatment is preferably performed under reduced pressure, and the pressure may be 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. The oxygen flow rate ratio (O2 / O2+Ar) is preferably 50% or less, and more preferably 10% to 30%. The treatment temperature is 750° C. or less, and more preferably 500° C. or less, for example, about 400° C. After the oxygen plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air.

[0294] By performing microwave treatment, the V of the oxide film 230A, the oxide film 230B, and the oxide film 243A O H is split off, hydrogen H is removed from the oxide film 230A, the oxide film 230B, and the oxide film 243A, and oxygen vacancies V O In other words, in the oxide film 230A, the oxide film 230B, and the oxide film 243A, "V O H→H+V O " and "V O +O→null” occurs, and the hydrogen concentrations in the oxide films 230A, 230B, and 243A can be reduced. OH can be reduced, lowering the carrier concentration.

[0295] Next, the conductive film 242A is formed on the oxide film 243A (see FIGS. 11A to 11D). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, tantalum nitride may be formed as the conductive film 242A by sputtering. Note that heat treatment may be performed before the conductive film 242A is formed. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed continuously without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A and the like can be removed, and the moisture concentration and hydrogen concentration in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is set to 200° C.

[0296] Next, the insulating film 271A is formed on the conductive film 242A (see FIGS. 11A to 11D). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271A is preferably an insulating film having a function of suppressing oxygen permeation. For example, the insulating film 271A may be formed of aluminum oxide or silicon nitride by a sputtering method.

[0297] Note that the conductive film 242A and the insulating film 271A are preferably formed by a sputtering method without exposure to the air. For example, a multi-chamber film formation apparatus may be used. This allows the conductive film 242A and the insulating film 271A to be formed with reduced hydrogen in the films, and further reduces the inclusion of hydrogen in the films between film formation steps. In addition, when a hard mask is provided on the insulating film 271A, the film to be the hard mask may also be formed continuously without exposure to the air.

[0298] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, and the insulating film 271A are processed into an island shape by using a lithography method to form the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B (see FIGS. 12A to 12D). This processing can be performed by a dry etching method or a wet etching method. The dry etching method is suitable for fine processing. The oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, and the insulating film 271A may be processed under different conditions. In this process, the thickness of the region of the insulator 224 that does not overlap with the oxide 230a may become thin. In this process, the insulator 224 may be processed into an island shape by overlapping with the oxide 230a.

[0299] In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a wet etching process after a dry etching process, or a dry etching process after a wet etching process.

[0300] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film that will be the hard mask material is formed on the insulating film 271A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of a desired shape. Etching of the insulating film 271A and the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. After etching of the insulating film 271A and the like, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask. In this embodiment, the insulating layer 271B is used as a hard mask. It is preferable to appropriately adjust the film thickness of the insulating layer 271B to suppress disappearance of the insulating layer 271B during etching of the conductive film 242A and the like.

[0301] Here, since the insulating layer 271B functions as a mask for the conductive layer 242B, the conductive layer 242B does not have a curved surface between the side surface and the top surface, as shown in FIG. 12B to FIG. 12D. As a result, the conductor 242a and the conductor 242b shown in FIG. 1B and FIG. 1D have angular ends where the side surface and the top surface intersect. Since the end where the side surface and the top surface of the conductor 242 intersect is angular, the cross-sectional area of ​​the conductor 242 is larger than when the end has a curved surface. This reduces the resistance of the conductor 242, and therefore the on-current of the transistor 200 can be increased.

[0302] Moreover, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are formed so that at least a part of them overlaps with the conductor 205. Moreover, it is preferable that the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are perpendicular or approximately perpendicular to the upper surface of the insulator 222. When the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are perpendicular or approximately perpendicular to the upper surface of the insulator 222, it is possible to reduce the area and increase the density when providing a plurality of transistors 200. Alternatively, a configuration may be adopted in which the angle between the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B and the upper surface of the insulator 222 is small. In this case, the angles between the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B and the upper surface of the insulator 222 are preferably 60 degrees or more and less than 70 degrees. By making the shape like this, the coverage of the insulators 273, 275, and 280 can be improved in the subsequent steps, and defects such as voids can be reduced.

[0303] In addition, by-products generated in the above etching process may be formed in layers on the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B. In this case, the layered by-products are formed on the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and between the insulator 271 and the insulator 273. Similarly, layered by-products may be formed on the insulator 224. Even if the insulator 273 is formed in a state in which the layered by-products are formed on the insulator 224, the layered by-products will prevent oxygen from being added to the insulator 224. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of the insulator 224.

[0304] Next, the insulator 273 is formed over the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B (see FIGS. 13A to 13D). The insulator 273 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, aluminum oxide may be formed by a sputtering method as the insulator 273. Silicon nitride or silicon oxide may also be formed by a sputtering method as the insulator 273. Oxygen can be added to the insulator 224 by forming an oxide film by a sputtering method as the insulator 273.

[0305] Next, the insulator 275 is formed over the insulator 273. (See FIGS. 13A to 13D.) The insulator 275 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 275 is preferably an insulating film having a function of suppressing oxygen permeation. For example, aluminum oxide may be formed as the insulator 275 by a sputtering method.

[0306] In this manner, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B can be covered with the insulating layer 271B, the insulator 273, and the insulator 275, which have the function of suppressing the diffusion of hydrogen and oxygen. This makes it possible to suppress the diffusion of hydrogen into the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B, the release of oxygen from the oxide 230a, the oxide 230b, and the oxide layer 243B, and the oxidation of the conductive layer 242B, which may be caused by the formation of the insulator 280 in a later process.

[0307] Next, an insulating film to be the insulator 280 is formed on the insulator 275. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film may be formed by a sputtering method as the insulating film. The insulating film to be the insulator 280 can be formed by a sputtering method in an atmosphere containing oxygen, thereby forming the insulator 280 containing excess oxygen. In addition, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require hydrogen as a deposition gas. Note that a heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 and the like can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0308] Next, the insulating film that becomes the insulator 280 is subjected to CMP processing to form the insulator 280 with a flat upper surface (see FIGS. 13A to 13D). Note that a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed until the silicon nitride reaches the insulator 280.

[0309] Next, a part of the insulator 280, a part of the insulator 275, a part of the insulator 273, a part of the insulating layer 271B, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the oxide 230b are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the insulator 271a, the insulator 271b, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed (see FIGS. 14A to 14D).

[0310] When forming the opening, the upper part of the oxide 230b is removed. By removing a part of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening.

[0311] In addition, a part of the insulator 280, a part of the insulator 275, a part of the insulator 273, a part of the insulating layer 271B, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the oxide 230b can be processed by dry etching or wet etching. The dry etching method is suitable for fine processing. In addition, the processing may be performed under different conditions. For example, a part of the insulator 280 may be processed by dry etching, a part of the insulator 275, a part of the insulator 273, and a part of the insulating layer 271B may be processed by wet etching, and a part of the oxide layer 243B, a part of the conductive layer 242B, and a part of the oxide 230b may be processed by dry etching. In addition, the processing of a part of the oxide layer 243B and a part of the conductive layer 242B and the processing of a part of the oxide 230b may be performed under different conditions.

[0312] Here, it is preferable to remove impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused therein. It is also preferable to remove damaged areas formed on the surface of the oxide 230b by the dry etching. The impurities include those originating from components contained in the insulator 280, the insulator 275, a part of the insulator 273, a part of the insulating layer 271B, and the conductive layer 242B, components contained in the members used in the device used to form the opening, and components contained in the gas or liquid used in the etching. The impurities include, for example, aluminum, silicon, tantalum, fluorine, and chlorine.

[0313] In particular, impurities such as aluminum or silicon inhibit the oxide 230b from becoming a CAAC-OS. Therefore, it is preferable that impurity elements such as aluminum or silicon that inhibit the CAAC-OS formation are reduced or removed. For example, the concentration of aluminum atoms in the oxide 230b and its vicinity may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0314] In addition, the region of the metal oxide in which the CAAC-OS formation is inhibited by impurities such as aluminum or silicon and which becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, so the V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC region of the oxide 230b is reduced or removed.

[0315] In contrast, it is preferable that the oxide 230b has a CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the lower end of the drain. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. In other words, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed, and by having the CAAC structure, the fluctuation in the electrical characteristics of the transistor 200 can be further suppressed. In addition, the reliability of the transistor 200 can be improved.

[0316] In order to remove the above-mentioned impurities, a cleaning process is performed. The cleaning method includes wet cleaning using a cleaning solution, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning methods may be combined appropriately. Note that the above-mentioned grooves may become deeper due to the cleaning process.

[0317] For wet cleaning, a cleaning process may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0318] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be called diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be called diluted ammonia water. The concentration and temperature of the aqueous solution may be appropriately adjusted depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0319] In addition, it is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning. By using such a frequency, damage to the oxide 230b and the like can be reduced.

[0320] The above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0321] In the present embodiment, as the cleaning process, wet cleaning is performed using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.

[0322] In the past, processing such as dry etching or the above-mentioned cleaning process may result in the thickness of insulator 224 in the area that overlaps with the opening but does not overlap with oxide 230b being thinner than the thickness of insulator 224 in the area that overlaps with oxide 230b.

[0323] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed at a temperature of 100° C. to 450° C., preferably 350° C. to 400° C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230a and the oxide 230b, thereby reducing the oxygen vacancy V. O In addition, by performing such a heat treatment, the crystallinity of the oxide 230b can be improved. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0324] The side surfaces of the conductor 242a and the conductor 242b may be oxidized in the opening due to the processing such as the etching or the post-processing such as the cleaning after the processing. Therefore, it is preferable to perform the processing and the post-processing under conditions that do not easily cause oxidation of the conductor 242a and the conductor 242b. For example, when the processing or the post-processing is performed by a dry process, it is preferable to perform the processing under conditions that do not include oxygen. Also, when the processing or the post-processing is performed by a wet process, it is preferable to perform the processing under conditions that do not include an oxidizing agent.

[0325] Next, the oxide film 230C is formed (see FIG. 15A to FIG. 15D). The oxide film 230C can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. At this time, the oxide film 230C is preferably formed only on the bottom of the opening. Alternatively, it is preferable to form the oxide film 230C thicker on the bottom than on the side of the opening. When the oxide film 230C is formed by a sputtering method, it is preferable to form the oxide film 230C by applying a high frequency of 10 MHz or more, preferably 40 MHz or more, between the sputtering target and the substrate. Furthermore, it is preferable to use a so-called ionization sputtering method in which sputtering particles are ionized during film formation. Alternatively, it is preferable to use a so-called long-throw sputtering method in which the distance between the sputtering target and the substrate is 60 mm or more, preferably 100 mm or more. The oxide film 230C may be formed by an ALD method such as a PEALD method or a thermal ALD method, or an MOCVD method. At this time, by forming the film while applying a bias to the substrate, a thick oxide film 230C can be formed on the side surface and bottom of the opening.

[0326] The oxide film 230C is preferably made of the same material as the oxide film 230B, or a material having a higher electrical conductivity than the oxide film 230B. For example, the composition of the oxide film 230C may be In:Ga:Zn=4:2:3 [atomic ratio] or thereabouts, In:Ga:Zn=5:1:3 [atomic ratio] or thereabouts, or In:M:Zn=10:1:3 [atomic ratio] or thereabouts. In-Zn oxide, indium oxide, etc. may be used as the oxide film 230C.

[0327] Next, the oxide film 230C is isotropically etched to remove the oxide film 230C on the side of the opening, and an oxide 230c is formed on the bottom of the opening (see FIGS. 16A to 16D). At this time, as shown in FIGS. 16B to 16D, a part of the side of the oxide 230d is exposed in the opening. The oxide 230c may also be formed on the insulator 280. As shown in FIGS. 1C and 2B, the oxide 230c may also be formed on the insulator 224 located in a region not overlapping with the oxide 230a and the oxide 230b in the opening. The oxide 230c is preferably provided so as to contact the oxide 230b inside the opening. The oxide 230c is preferably provided so as to contact the conductor 242a and the conductor 242b inside the opening.

[0328] It is preferable to use a wet etching method for etching the oxide film 230C. When dry etching is used for etching the oxide film 230C, it is preferable not to apply a bias to the substrate side during etching. It is also possible to use a plasma etching method, a radical etching method, or a gas etching method. The above etching method, which does not have anisotropy in the etching proceeding direction, can etch the oxide film 230C formed on the bottom and side of the opening at the same speed in the film thickness direction, so that the oxide film 230C formed on the side of the opening, which is formed thinner than the bottom of the opening, can be removed first.

[0329] Next, the oxide film 230D is formed (see FIGS. 17A to 17D). The oxide film 230D can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In order to uniformly form the oxide film 230D on the bottom and side of the opening, it is preferable to form the oxide film 230D by an ALD method such as PEALD or thermal ALD. The oxide film 230D may also be formed by MOCVD. The thickness of the oxide film 230D is set to 0.3 nm or more and 3 nm or less, preferably 0.5 nm or more and 1.5 nm or less.

[0330] The oxide film 230D can be formed using the same material as the oxide film 230A. For example, the composition of the oxide film 230D may be In:Ga:Zn=1:3:4 [atomic ratio] or a similar value. By providing a metal oxide that suppresses the diffusion or permeation of oxygen on the side surface of the conductor 242 as the oxide film 230D, the oxidation of the side surface of the conductor 242 can be suppressed in the subsequent steps. Even if the side surface of the conductor 242 has an oxidized region, the expansion of the oxidized region can be suppressed in the subsequent steps. For example, the oxidation of the conductor 242 in the step of forming the insulating film 250A can be suppressed. Also, the diffusion of oxygen contained in the insulator 280 to the insulator 250, the diffusion of oxygen contained in the insulator 250 to the conductor 242, and the like can be suppressed. By providing the oxide film 230D, the increase in the resistance value on the side surface of the conductor 242 can be suppressed in the subsequent steps.

[0331] Next, the insulating film 250A is formed (see FIGS. 18A to 18D). A heat treatment may be performed before the formation of the insulating film 250A, and the heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the atmosphere. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230 can be removed, and the moisture concentration and hydrogen concentration in the oxide 230 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0332] The insulating film 250A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulating film 250A to be reduced. Since the insulating film 250A becomes the insulator 250 that contacts the oxide 230 in a later process, it is preferable that the hydrogen concentration is reduced in this manner.

[0333] In addition, it is preferable to form the insulating film 250A by using the ALD method. The thickness of the insulator 250 functioning as the gate insulating film of the miniaturized transistor 200 must be extremely thin (for example, about 5 nm to 30 nm) and have small variations. In contrast, the ALD method is a film formation method in which a precursor and a reactant (oxidizer) are alternately introduced, and the thickness can be adjusted by the number of times this cycle is repeated, so that precise film thickness adjustment is possible. Therefore, the precision of the gate insulating film required by the miniaturized transistor 200 can be achieved. In addition, as shown in FIG. 18B and FIG. 18C, the insulating film 250A must be formed with good coverage on the bottom and side of the opening formed by the insulator 280, etc. Since layers of atoms can be deposited one by one on the bottom and side of the opening, the insulating film 250A can be formed with good coverage on the opening.

[0334] In addition, for example, when the insulating film 250A is formed by using the PECVD method, the film formation gas containing hydrogen is decomposed in the plasma, and a large amount of hydrogen radicals is generated. The oxygen in the oxide 230 is extracted by the reduction reaction of the hydrogen radicals, and V O When H is formed, the hydrogen concentration in the oxide 230 increases. However, when the insulating film 250A is formed using the ALD method, the generation of hydrogen radicals can be suppressed both when the precursor and the reactant are introduced. Therefore, by forming the insulating film 250A using the ALD method, the hydrogen concentration in the oxide 230 can be prevented from increasing.

[0335] In addition, in FIG. 18B, FIG. 18C, and FIG. 18D, the insulating film 250A is illustrated as a single layer, but it may have a laminated structure of two or more layers. When the insulating film 250A has a laminated structure of two layers, it is preferable that the lower layer of the insulating film 250A is formed using an insulator that releases oxygen when heated, and the upper layer of the insulating film 250A is formed using an insulator that has a function of suppressing the diffusion of oxygen. With such a configuration, it is possible to suppress the diffusion of oxygen contained in the lower layer of the insulator 250 to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 due to the oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulating film 250A is provided using a material that can be used for the insulator 250 described above, and the upper layer of the insulating film 250A can be provided using a material similar to that of the insulator 222.

[0336] Specifically, the upper layer of the insulating film 250A may be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0337] In this embodiment, the insulating film 250A is formed by depositing silicon oxide using the PEALD method.

[0338] In addition, when the insulating film 250A has a two-layer laminated structure, it is preferable to continuously deposit the insulating film that is the lower layer of the insulating film 250A and the insulating film that is the upper layer of the insulating film 250A without exposing them to the air environment. By depositing the films without exposing them to the air, it is possible to prevent impurities such as hydrogen or moisture from the air environment from adhering to the insulating film that is the lower layer of the insulating film 250A and the insulating film that is the upper layer of the insulating film 250A, and it is possible to keep the vicinity of the interface between the insulating film that is the lower layer of the insulating film 250A and the insulating film that is the upper layer of the insulating film 250A clean.

[0339] Next, microwave processing is performed in an atmosphere containing oxygen (see Figs. 19A to 19D). Here, the dotted lines in Figs. 19B, 19C, and 19D indicate microwaves, high frequency such as RF, oxygen plasma, or oxygen radicals. For the microwave processing, it is preferable to use a microwave processing device having a power source that generates high density plasma using microwaves. The microwave processing device may also have a power source that applies RF to the substrate side. By using high density plasma, high density oxygen radicals can be generated. By applying RF to the substrate side, oxygen ions generated by high density plasma can be efficiently introduced into the oxide 230. The microwave processing is preferably performed under reduced pressure, with the pressure being 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. The oxygen flow rate ratio (O2 / O2+Ar) is preferably 50% or less, preferably 10% or more and 30% or less. The processing temperature may be 750°C or less, preferably 500°C or less, for example, about 400°C. Furthermore, after the oxygen plasma treatment, a heat treatment may be performed successively without exposure to the outside air.

[0340] As shown in Figures 19B, 19C, and 19D, by performing microwave processing in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between conductor 242a and conductor 242b of oxide 230. At this time, microwaves or high frequency waves such as RF can also be irradiated to region 230bc. In other words, microwaves, high frequency waves such as RF, oxygen plasma, etc. can be applied to region 230bc shown in Figure 2A. The action of plasma, microwaves, etc. increases the V of region 230bc. O H can be split off and hydrogen H can be removed from the region 230bc. O H→H+V O " and "V O +O→null” occurs, and the hydrogen concentration in the region 230bc can be reduced. OBy supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in the region 230bc, the oxygen vacancies in the region 230bc can be further reduced, and the carrier concentration can be reduced.

[0341] On the other hand, conductors 242a and 242b are provided on regions 230ba and 230bb shown in Fig. 2A. As shown in Figs. 19B, 19C, and 19D, conductors 242a and 242b block the effects of microwaves, high frequencies such as RF, oxygen plasma, and the like, so that these effects do not reach regions 230ba and 230bb. As a result, by microwave processing, in regions 230ba and 230bb that are located below conductors 242a and 242b, V O Since there is no reduction in H and no excessive supply of oxygen, the decrease in carrier concentration can be suppressed.

[0342] In this manner, oxygen vacancies and V are selectively formed in the oxide semiconductor region 230bc. O By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb that function as source and drain regions can be suppressed, and the n-type can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor 200, and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0343] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device having good electrical characteristics.

[0344] In the steps shown in Figures 19B, 19C, and 19D, the microwave treatment was performed after the insulating film 250A was formed, but the present invention is not limited to this. For example, the microwave treatment may be performed before the insulating film 250A is formed, or may be performed both before and after the insulating film 250A is formed. Also, the microwave treatment may be performed after the insulating film 250B, which will be described later, is formed.

[0345] For example, when the insulating film 250A has the above-mentioned two-layer structure, a microwave process is performed, silicon oxide is formed as the lower layer of the insulating film 250A by the PEALD method, and hafnium oxide is formed as the upper layer of the insulating film 250A by the thermal ALD method. Here, it is preferable to perform the microwave process, the PEALD formation of silicon oxide, and the thermal ALD formation of hafnium oxide successively without exposure to the atmosphere. For example, a multi-chamber processing device may be used. The microwave process may be replaced by a process using a plasma-excited reactant (oxidant) in a PEALD device. Here, oxygen gas may be used as the reactant (oxidant).

[0346] Moreover, a heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment. By performing such a treatment, hydrogen in the insulating film 250A and the oxide 230 can be efficiently removed. A part of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a step of performing a heat treatment may be repeated multiple times while maintaining the reduced pressure state after the microwave treatment. By repeatedly performing the heat treatment, hydrogen in the insulating film 250A and the oxide 230 can be more efficiently removed. The heat treatment temperature is preferably 300° C. or more and 500° C. or less.

[0347] Moreover, by modifying the film quality of the insulating film 250A by microwave processing, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230 through the insulator 250 by a post-process such as film formation of a conductive film that becomes the conductor 260, or a post-treatment such as heat treatment.

[0348] Next, the insulating film 250B is formed (see FIGS. 20A to 20D). The insulating film 250B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, similar to the insulating film 250A. Moreover, the insulating film 250B is preferably formed by an ALD method, similar to the insulating film 250A.

[0349] The insulating film 250B is preferably formed using an insulator having a function of suppressing the diffusion of oxygen. By using such an insulator, it is possible to suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260. In other words, it is possible to suppress the oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulating film 250B can be provided using the same material as the insulator 222. The thickness of the insulating film 250B may be 0.5 nm or more and 5 nm or less, preferably 1 nm or more and 3 nm or less, and more preferably 1 nm or more and 2 nm or less. Typically, the thickness of the insulator 250b may be 1.5 nm.

[0350] Specifically, the insulating film 250B may be a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0351] In this embodiment, the insulating film 250B is formed by depositing hafnium oxide using the PEALD method.

[0352] Next, microwave processing is performed in an atmosphere containing oxygen (see Figs. 20A to 20D). Here, the dotted lines in Figs. 20B, 20C, and 20D indicate microwaves, high frequency waves such as RF, oxygen plasma, oxygen radicals, etc. The microwave processing may be performed under conditions that can be used as microwave processing conditions after the formation of the insulating film 250A.

[0353] Even if a material with a large dielectric constant or loss factor is used for the insulating film 250B, by forming the insulating film 250B with the above-mentioned thickness, the microwave can be transmitted through the insulating film 250B and irradiated to the region 230bc of the oxide 230. In addition, since the microwave is blocked by the conductors 242a and 242b, the V O Since there is no reduction in H and no excessive supply of oxygen, the decrease in carrier concentration can be suppressed.

[0354] By performing microwave treatment after forming the insulating film 250B, oxygen vacancies and V O By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb that function as source and drain regions can be suppressed, and the n-type can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor 200, and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0355] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device having good electrical characteristics.

[0356] Next, the conductive film 260A and the conductive film 260B are formed in this order (see FIGS. 21A to 21D). The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed by an ALD method, and the conductive film 260B is formed by a CVD method.

[0357] Next, the oxide 230c, the oxide film 230D, the insulating film 250A, the insulating film 250B, the conductive film 260A, and the conductive film 260B located on the upper layer of the insulator 280 are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230d, the insulator 250 (insulator 250a and insulator 250b), and the conductor 260 (conductor 260a and conductor 260b) (see FIGS. 22A to 22D). At this time, a part of the insulator 280 and the oxide 230d may be removed by polishing. As a result, the insulator 250 is disposed so as to cover the oxide 230 inside the opening formed in the insulator 280 or the like. The insulator 250 is provided so as to contact the upper surface and side surface of the oxide 230d. The conductor 260 is disposed so as to fill the opening and the groove portion through the insulator 250.

[0358] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0359] Next, the insulator 282 is formed over the oxide 230d, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 23A to 23D). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 282 can be reduced. In addition, by forming the insulator 282 in an atmosphere containing oxygen by using a sputtering method, oxygen can be added to the insulator 280 while the insulator 282 is being formed. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to form the insulator 282 while heating the substrate. In addition, it is preferable to use an insulator that has a high function of capturing and fixing hydrogen as the insulator 282. This makes it possible to capture and fix impurities such as water, hydrogen, etc. contained in the insulator 280, etc., and to suppress the diffusion of the impurities to the transistor 200 side. Alternatively, it is possible to suppress the diffusion of the impurities such as water, hydrogen, etc. from an interlayer insulating film disposed outside the insulator 282, etc., to the transistor 200 side.

[0360] In this embodiment, an aluminum oxide film is formed by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas as the insulator 282. By using the pulse DC sputtering method, an insulator with good film quality can be formed.

[0361] Next, microwave processing is performed in an atmosphere containing oxygen (see Figs. 23A to 23D). Here, the dotted lines in Figs. 23B, 23C, and 23D indicate microwaves, high frequency waves such as RF, oxygen plasma, oxygen radicals, etc. The microwave processing may be performed under conditions that can be used as microwave processing conditions after the formation of the insulating film 250A.

[0362] Even when a material with a large dielectric constant or loss factor is used for the insulator 282, by forming the insulator 282 to have a sufficiently small film thickness, the microwaves can pass through the insulator 282. In the microwave processing, the microwaves may be blocked by the conductor 242a, the conductor 242b, and the conductor 260. In this case, the microwaves propagate in the region surrounded by the dashed line in FIG. 23B, that is, in the film of the oxide 230d, the insulator 250a, and the insulator 250b, or at the interface between the adjacent films, and reach a part of the region 230bc of the oxide 230.

[0363] By performing microwave treatment after the formation of the insulator 282, oxygen vacancies and V O By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb that function as source and drain regions can be suppressed, and the n-type can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor 200, and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0364] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device having good electrical characteristics.

[0365] Next, an insulator 284 is formed on the insulator 282 (see FIGS. 24A to 24D). The insulator 284 can be formed of the same material and by the same method as the insulator 282. In particular, it is preferable to use an insulator having a high function of capturing and fixing hydrogen as the insulator 284.

[0366] Next, the insulator 283 is formed over the insulator 284 (see FIGS. 24A to 24D). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 283 is preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 283 can be reduced. The insulator 283 may also be a multilayer structure. For example, silicon nitride may be formed by a sputtering method, and silicon nitride may be formed on the silicon nitride by a CVD method. By enclosing the transistor 200 with the insulator 283 and the insulator 212 that have high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside.

[0367] Next, the insulator 274 is formed on the insulator 283 (see FIGS. 24A to 24D). The insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 274 preferably has a lower dielectric constant than the insulator 214. The insulator 274 also functions as an interlayer film. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. The insulator 274 can be formed, for example, using the same material and method as the insulator 280.

[0368] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. This heat treatment allows oxygen added by the formation of the insulator 282 to diffuse into the insulators 280 and 250 and to be selectively supplied to the channel formation region of the oxide 230. Note that this heat treatment may be performed not only after the formation of the insulator 274 but also after the formation of the insulator 282.

[0369] Next, openings reaching the conductor 242 are formed in the insulators 271, 273, 275, 280, 282, 284, 283, and 274 (see FIGS. 25A to 25D). The openings may be formed by using a lithography method. Note that, in FIG. 25A, the openings have a rectangular shape with rounded corners in top view, but this is not limited thereto. For example, the openings may have a circular shape, an approximately circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape other than a rectangle with rounded corners in top view.

[0370] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIGS. 26A to 26D). The insulating film that will become the insulator 241 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. As the insulating film that will become the insulator 241, it is preferable to use an insulating film that has a function of suppressing oxygen permeation. For example, it is preferable to form an aluminum oxide film by the ALD method. Alternatively, it is preferable to form a silicon nitride film by the PEALD method. Silicon nitride is preferable because it has high blocking properties against hydrogen.

[0371] Moreover, for example, a dry etching method may be used as the anisotropic etching of the insulating film that becomes the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the oxidation of the conductor 240a and the conductor 240b to be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductor 240a and the conductor 240b.

[0372] Next, a conductive film that becomes the conductor 240a and the conductor 240b is formed. The conductive film that becomes the conductor 240a and the conductor 240b is preferably a laminated structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminated structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that becomes the conductor 240 can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0373] Next, a CMP process is performed to remove parts of the conductive film that will become the conductors 240a and 240b, exposing the upper surface of the insulator 283. As a result, the conductive film remains only in the openings, forming the conductors 240a and 240b with flat upper surfaces (see Figures 26A to 26D). Note that the CMP process may remove parts of the upper surfaces of the insulators 283 and 274.

[0374] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0375] Next, the conductive film that becomes the conductor 246 is processed by lithography to form the conductor 246a in contact with the top surface of the conductor 240a and the conductor 246b in contact with the top surface of the conductor 240b. At this time, a part of the insulator 283 in the region where the conductor 246a and the conductor 246b do not overlap with the insulator 283 may be removed.

[0376] Next, the insulator 286 is formed on the conductor 246 and the insulator 283. The insulator 286 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 286 may also be a multi-layer structure. For example, a silicon nitride film may be formed by a sputtering method, and a silicon nitride film may be formed on the silicon nitride by a CVD method.

[0377] 1A to 1D can be manufactured. As shown in FIGS. 5A to 26D, the transistor 200 can be manufactured by the manufacturing method of a semiconductor device described in this embodiment.

[0378] <Microwave processing equipment> A microwave processing apparatus that can be used in the above-described method for manufacturing a semiconductor device will be described below.

[0379] First, the configuration of a manufacturing apparatus that reduces the inclusion of impurities during the manufacture of semiconductor devices and the like will be described with reference to FIGS.

[0380] 27 is a schematic top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 having a cassette port 2761 for accommodating a substrate and an alignment port 2762 for aligning the substrate, an atmosphere-side substrate transfer chamber 2702 for transferring the substrate from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a for loading the substrate and switching the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading the substrate and switching the pressure in the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring the substrate in a vacuum, a chamber 2706a, a chamber 2706b, a chamber 2706c, and a chamber 2706d.

[0381] The atmospheric side substrate transfer chamber 2702 is connected to a load lock chamber 2703a and an unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to a transfer chamber 2704, and the transfer chamber 2704 is connected to a chamber 2706a, a chamber 2706b, a chamber 2706c, and a chamber 2706d.

[0382] A gate valve GV is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere side substrate supply chamber 2701 and the atmosphere side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robot 2763a and the transfer robot 2763b.

[0383] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1×10 -5 The partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0384] The total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.

[0385] In addition, it is desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 44 is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0386] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on external and internal leaks. External leaks are gases that flow in from outside the vacuum system due to tiny holes or poor seals. Internal leaks are caused by leaks from partitions such as valves in the vacuum system and gases released from internal components. To keep the leak rate below the above values, measures must be taken to prevent both external and internal leaks.

[0387] For example, the opening and closing parts of the transfer chamber 2704 and each chamber may be sealed with a metal gasket. The metal gasket is preferably made of a metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. In addition, by using a passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities from the metal gasket is suppressed, and internal leakage can be reduced.

[0388] In addition, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emits less gas containing impurities, is used as a member constituting the manufacturing apparatus 2700. In addition, the above-mentioned metals which emit less gas containing impurities may be used by coating an alloy containing iron, chromium, nickel, etc. Alloys containing iron, chromium, nickel, etc. are rigid, heat-resistant, and suitable for processing. Here, if the surface irregularities of the members are reduced by polishing or the like in order to reduce the surface area, the amount of emitted gas can be reduced.

[0389] Alternatively, the components of the manufacturing apparatus 2700 described above may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0390] It is preferable that the components of the manufacturing apparatus 2700 are constructed solely from metal as much as possible. For example, even if a viewing window made of quartz or the like is installed, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, or the like to suppress outgassing.

[0391] The adsorbed matter present in the transfer chamber 2704 and each chamber does not affect the pressure of the transfer chamber 2704 and each chamber because it is adsorbed to the inner walls, but it causes gas emission when the transfer chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed matter present in the transfer chamber 2704 and each chamber and evacuate them in advance. In addition, the transfer chamber 2704 and each chamber may be baked to promote the desorption of the adsorbed matter. By baking, the desorption speed of the adsorbed matter can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbed matter is removed while introducing an inert gas into the transfer chamber 2704 and each chamber, the desorption speed of water and the like that is difficult to desorb by only exhausting can be further increased. In addition, the desorption speed of the adsorbed matter can be further increased by heating the inert gas introduced to the same temperature as the baking temperature. Here, it is preferable to use a rare gas as the inert gas.

[0392] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as a heated rare gas or oxygen, and then evacuate the transfer chamber 2704 and each chamber again after a certain time has passed. By introducing a heated gas, it is possible to desorb adsorbed substances in the transfer chamber 2704 and each chamber, and it is possible to reduce impurities present in the transfer chamber 2704 and each chamber. It is effective to repeat this process 2 to 30 times, preferably 5 to 15 times. Specifically, by introducing an inert gas or oxygen having a temperature of 40° C. to 400° C., preferably 50° C. to 200° C., the pressure in the transfer chamber 2704 and each chamber is set to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa, and the period for maintaining the pressure is 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Thereafter, the transfer chamber 2704 and each chamber are evacuated for a period of 5 to 300 minutes, preferably 10 to 120 minutes.

[0393] Next, chamber 2706b and chamber 2706c will be described with reference to the schematic cross-sectional view shown in FIG.

[0394] The chamber 2706b and the chamber 2706c are chambers capable of performing microwave processing on an object to be processed, for example. The chamber 2706b and the chamber 2706c differ only in the atmosphere during microwave processing. Since the other configurations are common, they will be described together below.

[0395] The chamber 2706b and the chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. In addition, outside the chamber 2706b and the chamber 2706c, a gas supply source 2801, a valve 2802, a high frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0396] The high frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with a dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is sent to the chambers 2706b and 2706c through a gas pipe 2806 passing through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 has a function of exhausting gas and the like from the chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high frequency power supply 2816 is connected to the substrate holder 2812 via a matching box 2815.

[0397] The substrate holder 2812 has a function of holding the substrate 2811. For example, the substrate holder 2812 has a function of electrostatically or mechanically chucking the substrate 2811. The substrate holder 2812 also has a function as an electrode to which power is supplied from a high frequency power supply 2816. The substrate holder 2812 also has an internal heating mechanism 2813 and has a function of heating the substrate 2811.

[0398] For example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbo molecular pump can be used as the vacuum pump 2817. A cryotrap may be used in addition to the vacuum pump 2817. The use of a cryopump and a cryotrap is particularly preferable because water can be efficiently exhausted.

[0399] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heating processing using high-temperature gas. An inert gas is used as the gas.

[0400] The gas supply source 2801 may be connected to a refiner via a mass flow controller. It is preferable to use a gas with a dew point of -80° C. or less, preferably -100° C. or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) may be used.

[0401] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria). A separate protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. The dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 described later, and thus damage to the dielectric plate 2809 can be mitigated by providing a protective layer. As a result, an increase in particles during processing can be suppressed.

[0402] The high frequency generator 2803 has a function of generating microwaves of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. Then, the microwaves are transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with a plurality of slot holes, and the microwaves pass through the slot holes and the dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, and a high density plasma 2810 can be generated. In the high density plasma 2810, ions and radicals according to the gas species supplied from the gas supply source 2801 exist. For example, oxygen radicals and the like exist.

[0403] At this time, the film on the substrate 2811 can be modified by the ions and radicals generated by the high density plasma 2810. It may be preferable to apply a bias to the substrate 2811 side using a high frequency power supply 2816. For the high frequency power supply 2816, an RF (Radio Frequency) power supply with a frequency of, for example, 13.56 MHz or 27.12 MHz may be used. By applying a bias to the substrate side, the ions in the high density plasma 2810 can be efficiently delivered to the depths of the openings of the film on the substrate 2811.

[0404] For example, oxygen can be introduced from a gas supply source 2801 into the chamber 2706b or the chamber 2706c to perform oxygen radical treatment using a high density plasma 2810.

[0405] Next, chamber 2706a and chamber 2706d will be described with reference to the schematic cross-sectional view shown in FIG.

[0406] The chamber 2706a and the chamber 2706d are chambers capable of irradiating the object to be treated with electromagnetic waves, for example. The only difference between the chamber 2706a and the chamber 2706d is the type of electromagnetic waves. As the other configurations are largely common, they will be described together below.

[0407] The chamber 2706a and the chamber 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. In addition, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the chamber 2706a and the chamber 2706d.

[0408] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is disposed facing a substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 and has a function of heating the substrate 2824.

[0409] A light source having a function of emitting electromagnetic waves such as visible light or ultraviolet light may be used as the lamp 2820. For example, a light source having a function of emitting electromagnetic waves having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0410] For example, lamp 2820 may be a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp.

[0411] For example, the electromagnetic waves emitted from the lamps 2820 can be absorbed in part or in whole by the substrate 2824 to modify a film on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. If the process is performed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0412] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamps 2820, thereby heating the substrate 2824. In that case, the substrate holder 2825 does not need to have the heating mechanism 2826 inside.

[0413] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. For the heating mechanism 2826, refer to the description of the heating mechanism 2813. For the gas supply source 2821, refer to the description of the gas supply source 2801.

[0414] By using the above manufacturing apparatus, it is possible to modify the film while suppressing the inclusion of impurities in the processed object.

[0415] <Modification 1 of the semiconductor device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 30A to 30D.

[0416] Fig. 30A shows a top view of the semiconductor device. Fig. 30B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 30A. Fig. 30C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 30A. Fig. 30D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 30A. In the top view of Fig. 30A, some elements are omitted for clarity.

[0417] 30A to 30D, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration example of semiconductor device> are denoted by the same reference numerals. Note that, in this section, the materials described in detail in <Configuration example of semiconductor device> can be used as the materials constituting the semiconductor device.

[0418] The semiconductor device shown in Figures 30A to 30D is a modified example of the semiconductor device shown in Figures 1A to 1D. The semiconductor device shown in Figures 30A to 30D differs from the semiconductor device shown in Figures 1A to 1D mainly in the shapes of the insulators 284 and 283.

[0419] In the semiconductor device shown in Figures 30A to 30D, the insulator 216, the insulator 222, the insulator 224, the insulator 273, the insulator 275, the insulator 280, and the insulator 282 are patterned. Furthermore, the insulator 284 is structured to cover the insulators 214, the insulator 216, the insulator 222, the insulator 224, the insulator 273, the insulator 275, the insulator 280, and the insulator 282. That is, the insulator 284 contacts the upper surface and side surfaces of the insulator 282, the side surfaces of the insulators 216, the insulator 222, the insulator 224, the insulator 273, the insulator 275, and the insulator 280, and the upper surface of the insulator 214. Furthermore, the insulator 283 is disposed to cover the insulator 284. As a result, insulators 216, 222, 224, 280, and 282, including oxide 230, are isolated from the outside by insulators 283, 284, 214, and 212. In other words, transistor 200 is disposed within an area sealed by insulators 283, 284, 214, and 212.

[0420] For example, the insulators 214, 271, 273, 275, 282, and 284 may be formed using a material having a function of capturing hydrogen and fixing hydrogen. Note that the insulator 284 may be formed using an insulator similar to that of the insulator 282. The insulators 212 and 283 may be formed using a material having a function of suppressing diffusion of hydrogen and oxygen. The insulators 214, 271, 273, 275, 282, and 284 may be formed using a metal oxide having an amorphous structure, such as aluminum oxide. Typically, the insulators 212 and 283 may be formed using silicon nitride. In particular, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 284, since hydrogen may be captured or fixed more effectively. This makes it possible to manufacture a transistor 200 and a semiconductor device having excellent characteristics and high reliability.

[0421] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from entering the sealed region.

[0422] 30A to 30D, the insulator 212 and the insulator 283 are each provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 212 and the insulator 283 may be provided as a stacked structure of two or more layers.

[0423] <Modification 2 of Semiconductor Device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 31A to 31D.

[0424] Fig. 31A shows a top view of the semiconductor device. Fig. 31B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 31A. Fig. 31C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 31A. Fig. 31D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 31A. In the top view of Fig. 31A, some elements are omitted for clarity.

[0425] 31A to 31D, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration Example of Semiconductor Device> or <Modification 1 of Semiconductor Device> are denoted by the same reference numerals. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> or <Modification 1 of Semiconductor Device> can be used as the materials constituting the semiconductor device.

[0426] The semiconductor device shown in Figures 31A to 31D is a modified example of the semiconductor device shown in Figures 30A to 30D. The semiconductor device shown in Figures 31A to 31D differs from the semiconductor device shown in Figures 30A to 30D mainly in the shapes of insulators 214 and 284.

[0427] 31A to 31D, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 273, the insulator 275, the insulator 280, the insulator 282, and the insulator 284 are patterned. The insulator 283 is structured to cover the insulators 212, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 273, the insulator 275, the insulator 280, the insulator 282, and the insulator 284. That is, the insulator 283 contacts the upper surface and side surfaces of the insulator 284, the side surfaces of the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 273, the insulator 275, and the insulator 280, and the upper surface of the insulator 212. As a result, the insulators 214, 216, 222, 224, 280, 282, and 284, including the oxide 230, are isolated from the outside by the insulators 283 and 212. In other words, the transistor 200 is disposed within a region sealed by the insulators 283 and 212.

[0428] For example, the insulators 214, 271, 273, 275, 282, and 284 may be formed using a material having a function of capturing hydrogen and fixing hydrogen. Note that the insulator 284 may be formed using an insulator similar to that of the insulator 282. The insulators 212 and 283 may be formed using a material having a function of suppressing diffusion of hydrogen and oxygen. The insulators 214, 271, 273, 275, 282, and 284 may be formed using a metal oxide having an amorphous structure, such as aluminum oxide. Typically, the insulators 212 and 283 may be formed using silicon nitride. In particular, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 284, since hydrogen may be captured or fixed more effectively. This makes it possible to manufacture a transistor 200 and a semiconductor device having excellent characteristics and high reliability.

[0429] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from entering the sealed region.

[0430] 31A to 31D, the insulator 212 and the insulator 283 are each provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 212 and the insulator 283 may be provided as a stacked structure of two or more layers.

[0431] <Modification 3 of the semiconductor device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 32A and 32B.

[0432] Fig. 32A shows a top view of the semiconductor device. Fig. 32B shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 32A. For cross-sectional views corresponding to the portion indicated by the dashed line A1-A2 in Fig. 32A and the portion indicated by the dashed line A5-A6 in Fig. 32A, Fig. 1B and Fig. 1D can be referred to, respectively. In the top view of Fig. 32A, some elements are omitted for clarity.

[0433] 32A and 32B, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration example of semiconductor device> are denoted by the same reference numerals. Note that, in this section, the materials described in detail in <Configuration example of semiconductor device> can be used as the materials constituting the semiconductor device.

[0434] The semiconductor device shown in FIGS. 32A and 32B is a modified example of the semiconductor device shown in FIGS. 1A to 1D. In the semiconductor device shown in FIGS. 32A and 32B, the transistor 200 has a plurality of channel formation regions (regions 230bc_1 to 230bc_4), which is different from the semiconductor device shown in FIGS. 1A to 1D. Note that, in the semiconductor device shown in FIGS. 32A and 32B, the transistor 200 has four channel formation regions, but this embodiment is not limited to this. The transistor 200 may have two or more channel formation regions.

[0435] In the semiconductor device shown in FIG. 32A and FIG. 32B, a conductor 260 is provided on the upper surface and side surface of a plurality of channel formation regions via an insulator 250. The conductor 242a and the conductor 242b extend in the A5-A6 direction and are electrically connected to the regions 230bc_1 to 230bc_4. The conductor 242a may be electrically connected to a plurality of conductors 240a. The conductor 242b may be electrically connected to a plurality of conductors 240b. The conductor 246a is electrically connected to the conductor 242a via the plurality of conductors 240a. The conductor 246b is electrically connected to the conductor 242b via the plurality of conductors 240b.

[0436] In the semiconductor device shown in FIG. 32A and FIG. 32B, the transistor 200 has a plurality of channel formation regions for one gate electrode, which is different from the configuration of the transistor 200 in the semiconductor device shown in FIG. 1A to FIG. 1D. The transistor 200 can obtain a large on-current by having a plurality of channel formation regions. In addition, since each channel formation region has a structure covered with a gate electrode, that is, an s-channel structure, a large on-current can be obtained in each channel formation region. Alternatively, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is lower than the height of the interface between the top surface of the oxide 230b and the oxide 230c when the bottom surface of the insulator 222 is used as a reference, a large on-current can be obtained in each channel formation region. For other configurations, the configurations of the semiconductor device shown in FIG. 1A to FIG. 1D can be referred to.

[0437] <Applications of semiconductor devices> An example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those described in the above <Structural Example of Semiconductor Device> and <Variation 1 of Semiconductor Device>, will be described below with reference to Figures 33A and 33B. Note that in the semiconductor device shown in Figures 33A and 33B, structures having the same functions as those of the semiconductor device shown in <Variation 1 of Semiconductor Device> (see Figures 30A to 30D) are denoted by the same reference numerals. Note that in this section, the materials described in detail in <Structural Example of Semiconductor Device> and <Variation 1 of Semiconductor Device> can be used as the materials for forming the transistor 200.

[0438] 33A and 33B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated with an insulator 212, an insulator 214, an insulator 284, and an insulator 283. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 33A and 33B, this is not the only possible arrangement. The transistors 200_1 to 200_n may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors may be arranged without any regularity depending on the design.

[0439] As shown in FIG. 33A, a portion where the insulator 214 and the insulator 284 contact each other (hereinafter, referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. In the sealing portion 265, the insulators 212, 214, 284, and 283 have a stacked structure. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With this structure, the plurality of transistors 200_1 to 200_n can be wrapped with the insulators 212, 214, 284, and 283. Thus, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.

[0440] Also, dicing lines (which may be called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. Since the substrate is divided along the dicing lines, a group of transistors surrounded by the sealing portion 265 is taken out as one chip.

[0441] In addition, although Fig. 33A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, the present invention is not limited to this. As shown in Fig. 33B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In Fig. 33B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0442] In this manner, by using a configuration in which the multiple transistors 200_1 to 200_n are surrounded by multiple sealing portions, the number of areas in which the insulator 214 and the insulator 284 are in contact with each other increases, thereby improving the adhesion between the insulator 214 and the insulator 284. This makes it possible to more reliably seal the multiple transistors 200_1 to 200_n.

[0443] In this case, a dicing line may be provided so as to overlap sealing portion 265a or sealing portion 265b, or a dicing line may be provided between sealing portion 265a and sealing portion 265b.

[0444] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0445] The structures, methods, and the like described in this embodiment can be used in appropriate combination with other structures, methods, and the like described in this embodiment or structures, methods, and the like described in other embodiments.

[0446] (Embodiment 2) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0447] [Storage device 1] 34 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0448] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, stored data can be retained for a long time by using the transistor 200 in a memory device. In other words, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.

[0449] 34, a wiring 1001 is electrically connected to a source of a transistor 300, and a wiring 1002 is electrically connected to a drain of the transistor 300. A wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0450] Moreover, the memory device shown in FIG. 34 can be arranged in a matrix to form a memory cell array.

[0451] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0452] Here, in the transistor 300 shown in FIG. 34, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that contacts the upper part of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0453] Note that the transistor 300 illustrated in FIG. 34 is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method.

[0454] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, the insulator 130 is preferably an insulator that can be used as the insulator 286 described in the above embodiment.

[0455] For example, the conductor 112 and the conductor 110 over the conductor 246 can be formed at the same time. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0456] 34, the conductor 112 and the conductor 110 are shown to have a single-layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0457] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer.

[0458] For example, it is preferable to use a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitance element 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitance element 100 can have improved dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitance element 100.

[0459] Examples of high dielectric constant (high-k) material insulators (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0460] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide or resin with voids, etc.

[0461] <Wiring layer> Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Here, a conductor having a function as a plug or wiring may be collectively given the same symbol as a plurality of structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0462] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. A conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as plugs or wirings.

[0463] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0464] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 34, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0465] Similarly, a conductor 218, a conductor constituting the transistor 200 (conductor 205), and the like are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0466] Here, similarly to the insulator 241 shown in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0467] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with the insulator 210, the insulator 212, the insulator 214, and the insulator 222, it is possible to prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from being mixed into the oxide 230 through the conductor 218. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0468] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0469] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0470] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

[0471] For example, the insulator 150, the insulator 210, the insulator 352, the insulator 354, etc. preferably have an insulator with a low relative dielectric constant. For example, the insulator preferably has silicon oxynitride, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen has been added, or silicon oxide having voids, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with a resin to form a laminated structure that is thermally stable and has a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0472] Furthermore, when a transistor using an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stabilized. Therefore, the insulators 214, 212, and 350 can be made of insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0473] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may be used.

[0474] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0475] For example, the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, etc. can be formed of a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductor from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0476] <Wiring or plug of layer provided with oxide semiconductor> Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0477] 34, for example, an insulator 241 may be provided between the insulator 224 and the insulator 280 having excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 275, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0478] In other words, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0479] As the insulator 241, an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, may be used. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, other metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide may be used.

[0480] As described in the above embodiment, the transistor 200 may be sealed with the insulators 212, 214, 282, and 283. Such a structure can reduce the intrusion of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like.

[0481] Here, the conductor 240 penetrates the insulator 283 and the insulator 282, and the conductor 218 penetrates the insulator 214 and the insulator 212, but as described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that is mixed into the inside of the insulators 212, 214, 282, and 283 through the conductors 240 and 218. In this way, the transistor 200 is sealed with the insulators 212, 214, 282, 283, 241, and 217, making it possible to reduce impurities such as hydrogen contained in the insulator 274, etc., from the outside.

[0482] <Dicing line> In the following, a dicing line (sometimes called a scribe line, a dividing line, or a cutting line) that is provided when a large-area substrate is divided into individual semiconductor elements to extract multiple semiconductor devices in chip form will be described. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (split) the substrate into multiple semiconductor devices.

[0483] 34, for example, it is preferable to design the region where the insulator 284 and the insulator 212 contact each other so as to overlap the dicing line. That is, openings are provided in the insulators 282, 280, 275, 273, 224, 222, 216, and 214 near the region that will become the dicing line provided on the outer edge of the memory cell having the multiple transistors 200.

[0484] That is, the insulator 212 and the insulator 284 contact each other through the openings provided in the insulators 282, 280, 275, 273, 224, 222, 216, and 214. For example, the insulators 212 and 284 may be formed using the same material and the same method. By providing the insulators 212 and 284 using the same material and the same method, the adhesion can be increased. For example, it is preferable to use silicon nitride. Also, a structure in which the insulators 214 and 284 contact each other without providing an opening in the insulator 214 may be used. At this time, it is preferable to use aluminum oxide for the insulators 214 and 284.

[0485] With this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 284, and the insulator 283. At least one of the insulator 212, the insulator 214, the insulator 284, and the insulator 283 has a function of suppressing diffusion of oxygen, hydrogen, and water, and therefore, even if the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side direction of the divided substrate and diffusing into the transistor 200.

[0486] This structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. As a result, the oxide in which a channel is formed in the transistor 200 can be an oxide semiconductor with low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0487] In the memory device shown in Fig. 34, the shape of the capacitor 100 is a planar type, but the memory device shown in this embodiment is not limited to this. For example, the shape of the capacitor 100 may be a cylindrical type as shown in Fig. 35. In the memory device shown in Fig. 35, the configuration below the insulator 150 is similar to that of the semiconductor device shown in Fig. 34.

[0488] 35 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the opening formed in the insulator 150 and the insulator 142.

[0489] The conductor 115 functions as the lower electrode of the capacitance element 100, the conductor 125 functions as the upper electrode of the capacitance element 100, and the insulator 145 functions as the dielectric of the capacitance element 100. The capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surface in the openings of the insulators 150 and 142, and the capacitance per unit area can be increased. Therefore, the deeper the opening is, the larger the capacitance of the capacitance element 100 can be. Increasing the capacitance per unit area of ​​the capacitance element 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0490] The insulator 152 may be made of an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be made of an insulator that can be used for the insulator 214.

[0491] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area of ​​the opening overlapping with the transistor 200 is large when viewed from above. With such a configuration, the occupation area of ​​a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0492] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The upper surface of the conductor 115 preferably approximately coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be, for example, a conductor that can be used for the conductor 205.

[0493] The insulator 145 is disposed so as to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film stacked in this order of zirconium oxide, aluminum oxide, and zirconium oxide.

[0494] Moreover, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a material with high dielectric constant (high-k) may be used.

[0495] Examples of insulators made of high dielectric constant (high-k) materials (materials with high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium. By using such high-k materials, the capacitance of the capacitance element 100 can be sufficiently secured even if the insulator 145 is made thick. By making the insulator 145 thick, the leakage current occurring between the conductor 115 and the conductor 125 can be suppressed.

[0496] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN x ), silicon oxide (SiO x ), and silicon nitride (SiN x ) in that order can be used. By using such an insulator having a high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.

[0497] The conductor 125 is disposed so as to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using a conductor that can be used for the conductor 205, for example.

[0498] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0499] [Storage device 2] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIGS. 36A and 36B.

[0500] <Memory device configuration example 1> Fig. 36A is a cross-sectional view of a semiconductor device including a memory device 290. The memory device 290 shown in Fig. 36A includes a capacitor device 292 in addition to the transistor 200 shown in Fig. 1A to Fig. 1D. Fig. 36A corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0501] The capacitance device 292 includes a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 273 and an insulator 275 provided to cover the insulator 271b, and a conductor 294 on the insulator 275. That is, the capacitance device 292 configures a MIM (Metal-Insulator-Metal) capacitance. Note that one of a pair of electrodes included in the capacitance device 292, that is, the conductor 242b, can also serve as a source electrode of a transistor. In addition, a dielectric layer included in the capacitance device 292 can also serve as a protective layer provided in the transistor, that is, the insulator 271, the insulator 273, and the insulator 275. Therefore, a part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitance device 292, so that a semiconductor device with high productivity can be obtained. In addition, one of a pair of electrodes of the capacitor 292, that is, the conductor 242b, also serves as a source electrode of the transistor, so that the area in which the transistor and the capacitor are arranged can be reduced.

[0502] Note that the conductor 294 may be made of, for example, a material that can be used for the conductor 242.

[0503] <Memory device configuration example 2> Fig. 36B is a cross-sectional view of a semiconductor device having a memory device 290 having a structure different from that shown in Fig. 36A. The memory device 290 shown in Fig. 36B has a capacitance device 292 in addition to the transistor 200 shown in Figs. 30A to 30D. Here, unlike the capacitance device 292 shown in Fig. 36A, a part of the capacitance device 292 shown in Fig. 36B is provided in an opening formed in the insulator 280, the insulator 275, the insulator 273, and the insulator 271b. Note that Fig. 36B corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0504] The capacitance device 292 has a conductor 242b, an insulator 293 provided on the conductor 242b, and a conductor 294 provided on the insulator 293. Here, the insulator 293 and the conductor 294 are disposed in an opening formed in the insulator 280, the insulator 275, the insulator 273, and the insulator 271b. The insulator 293 is disposed in contact with the bottom surface and the side wall of the opening. That is, the insulator 293 is in contact with the upper surface of the conductor 242b, the side surface of the insulator 271b, the side surface of the insulator 273, the side surface of the insulator 275, and the side surface of the insulator 280. The insulator 293 is disposed so as to form a recess along the shape of the opening. The conductor 294 is disposed in contact with the upper surface and the side surface of the insulator 293 so as to fill the recess. In addition, the height of the upper surfaces of insulator 293 and conductor 294 may be approximately the same as the height of the upper surfaces of insulator 280, insulator 250, and conductor 260.

[0505] Here, the conductor 242b functions as a lower electrode of the capacitance device 292, the conductor 294 functions as an upper electrode of the capacitance device 292, and the insulator 293 functions as a dielectric of the capacitance device 292. In this manner, the capacitance device 292 constitutes an MIM capacitance. Note that one of the pair of electrodes of the capacitance device 292, i.e., the conductor 242b, can also serve as a source electrode of a transistor. Therefore, a part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitance device 292, so that a semiconductor device with high productivity can be obtained. In add...

Claims

[Claim 1] A first oxide; a first conductor and a second conductor on the first oxide; a first insulator on the first conductor; and a second insulator on the second conductor; and a second oxide provided on the first oxide and in contact with a side surface of the first conductor and a side surface of the second conductor; a third oxide provided on the second oxide and having a region in contact with a side surface of the first insulator and a side surface of the second insulator; a third insulator on the third oxide; and a third conductor on the third insulator; and A semiconductor device having the above structure.

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