Semiconductor storage device

Abstract

To provide a semiconductor storage device having high integration degree; or provide a semiconductor storage device capable of holding memory content even in a case where power is not supplied; or provide a semiconductor storage device having high writable frequency.SOLUTION: In a semiconductor storage device, a memory cell is configured with two transistors and one capacitor, and integration degree of a memory cell array is increased by three-dimensionally arranging the transistors and the capacitor. By forming the transistor for controlling a charge amount of the capacitor provided in the memory cell with a wide-gap semiconductor having a band gap wider than that of silicon and reducing off-state current, charge stored in the capacitor is prevented from leakage. Accordingly, the semiconductor storage device in which memory content can be held even in a case where power is not supplied is provided.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device. [Background technology]

[0002] With the integration of semiconductor memory devices, there is a demand for a reduction in the area occupied by semiconductor devices. For example , In order to increase the integration of transistors, which are one of the semiconductor devices, the channel is perpendicular to the substrate. The so-called vertical transistors are known to form. Using this structure, the source electrode is Alternatively, the drain electrode and the active layer on which the channel is formed overlap, and the transistor is occupied. The area can be reduced (see, for example, Patent Document 1). As a result, the transistor A semiconductor memory device using a plurality of the two can be integrated.

[0003] Incidentally, a semiconductor memory device has a volatile semi-volatile memory that loses its memory content when the power supply is stopped. Conductor storage devices and non-volatile semiconductor memory devices that retain the contents of the memory even when power supply is stopped There is a place.

[0004] A typical example of a volatile semiconductor memory device is DRAM (Dynamic Rando). m Access Memory) and SRAM (Static Random Access ss Memory) and others. These volatile semiconductor memory devices provide power. When stopped, the contents of the memory are lost, but it does not require a large voltage like nonvolatile memory. Therefore, power consumption is relatively small.

[0005] A typical example of a nonvolatile semiconductor memory device is a floating gate memory. Hu The rotating gate memory is between the gate electrode of the transistor and the channel formation region. It has a floating gate and stores the floating gate by holding charge. To do this, the data retention period is extremely long (semi-permanent), and the reflex required for volatile storage devices is It has the advantage that no reshing operation is required (see, for example, Patent Document 2).

[0006] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. As this occurs, the problem arises that the memory element will not function after a specified number of writing occurs. I do. To mitigate the effect of this problem, for example, the number of writes for each memory element is uniformed. The method is adopted. However, to achieve this, complex peripheral circuits are required. Yes. Furthermore, even if this method is adopted, the fundamental problem of life span will not be resolved. In other words, floating gate memory is not suitable for applications where information is frequently rewritten. be.

[0007] To resolve such floating gate memory problems, two transistors and A semiconductor memory device has been proposed that includes a memory cell using a single capacitive element (Patent Documents) 3). The semiconductor memory device according to the present invention is provided with a capacitance on the gate electrode of the first transistor. A second transistor is provided with a stove and a charge is inserted into the capacitor. I do. The second transistor is a material that can sufficiently reduce the off-current of the transistor. , for example, it is made of an oxide semiconductor material that is a wide gap semiconductor. Second Tran The off-current of the distor is sufficiently small so that the capacitor charge does not disappear over a long period of time. . Therefore, the semiconductor memory device can hold information for a long period of time.

[0008] The semiconductor memory device does not have any problems with the function of holding information. However, semiconductors Further integration is desired as a storage device. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2004-356314 A [Patent Document 2] Japanese Patent Publication No. 57-105889 [Patent Document 3] JP 2011-216878 A Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, one aspect of the disclosed invention provides a highly integrated semiconductor memory device. One of the purposes is to do so. Alternatively, it is possible to keep stored contents even when no power is supplied. One object is to provide a semiconductor memory device. Or, there are many times that can be written One object is to provide a semiconductor memory device. [Means for solving the problem]

[0011] The semiconductor memory device according to one aspect of the present invention includes a memory cell that includes two transistors and one cable. The transistors and capacitors are arranged in three dimensions. Me By arranging the transistors and capacitors that make up the Mori cell in three dimensions, the memory cell can be used to create a memory cell. Increases cell density per unit area of the lu array. The transistors provided in the memory cell are One is a transistor that controls the amount of charge in the capacitor. In one aspect of the present invention, Reduce the leakage current of the transistor. In order to reduce the leakage current of the transistor , a semiconductor material having a wider bandgap than silicon is used for the channel region. Thereby , a semiconductor memory device capable of retaining stored content for a certain period even in a situation where no power is supplied is provided .

[0012] That is, one aspect of the present invention has a memory cell including a first transistor, a second transistor, and a capacitor . The first transistor has a first semiconductor layer, a first gate insulating layer in contact with the first semiconductor layer , a first gate electrode in contact with the first gate insulating layer and overlapping the first semiconductor layer, and a source region and a drain region provided so as to sandwich a region overlapping the first gate electrode of the first semiconductor layer . The second transistor is disposed so as to overlap the first gate electrode and has a second semiconductor layer electrically connected to the first gate electrode, a second gate insulating layer in contact with a side surface of the second semiconductor layer , and a second gate electrode formed in contact with the second gate insulating layer and covering at least a part of the side surface of the second semiconductor layer . The capacitor has a capacitance layer in contact with a side surface of the first gate electrode and a first capacitance electrode formed in contact with the capacitance layer and covering at least a part of the side surface of the first gate electrode . The first gate electrode functions as a source electrode or a drain electrode of the second transistor, and the second semiconductor layer is formed so as to overlap the first gate electrode. Therefore, the source electrode and the drain electrode of the second transistor are disposed so as to sandwich the second semiconductor layer substantially perpendicular to the substrate on which the transistor is formed . Thus, the second transistor can have a smaller occupied area compared to, for example, a planar transistor

[0013] . . ​

[0014] Furthermore, the first gate electrode of the first transistor is used as the capacitance electrode of one of the capacitors. Therefore, the area occupying the capacitor can be reduced.

[0015] When the second transistor is turned on, the semiconductor memory device is turned on, and one electrode of the capacitor is not included. That is, a potential difference occurs between the first gate electrode of the first transistor and the other first capacitance electrode. . According to the potential difference, the capacitor holds the charge. After that, the first transistor By setting the switch to the OFF state, the written data can be retained.

[0016] Furthermore, the second semiconductor layer is made of a semiconductor material with a wider band gap than silicon. It is preferred that the semiconductor memory device is included.

[0017] Applying a semiconductor made of a material with a wider band gap than silicon to the second semiconductor layer This reduces the off-current of the second transistor. Therefore, power is supplied. Even in situations where the second transistor is not equipped with silicon, it is possible to maintain the memory content for a longer period of time than a configuration in which the second transistor is equipped with silicon. It is possible to provide a semiconductor memory device that can be held.

[0018] Furthermore, the semiconductor memory device is similar to a floating gate (FG) type nonvolatile memory. , when writing and erasing data, the carrier does not damage the gate insulating layer, Repeated writing and erasing does not deteriorate. That is, the semiconductor memory device is not FG type. It is possible to improve the reliability of data retention than volatile memory. Therefore, it is possible to write It is possible to provide a semiconductor memory device that has a large number of times (for example, more than 1 million times).

[0019] Furthermore, it is preferable that the semiconductor memory device has a second semiconductor layer made of an oxide semiconductor. Preferably.

[0020] By applying an oxide semiconductor to the second semiconductor layer, the off-current of the second transistor is reduced. Therefore, a semiconductor memory device capable of retaining stored content even when power is not supplied can be provided. In addition, since the oxide semiconductor film can be formed at a temperature lower than, for example, 1000°C, which is a temperature commonly used in semiconductor manufacturing processes using silicon wafers, the semiconductor memory device can be easily manufactured. Even when an oxide semiconductor that has not been subjected to heat treatment or the like after film formation is used for the second semiconductor layer, the second transistor can achieve a field-effect mobility exceeding, for example, 100 cm / V·sec. Using such a second transistor with a high field-effect mobility can provide a semiconductor memory device with a high write speed. 2 / V·sec. Also, one aspect of the present invention has a memory cell including a first transistor, a second transistor, and a capacitor. The first transistor has a first semiconductor layer, a first gate insulating layer in contact with the first semiconductor layer, a first gate electrode in contact with the first gate insulating layer and overlapping the first semiconductor layer, and a source region and a drain region provided so as to sandwich a region of the first semiconductor layer overlapping the first gate electrode.

[0021] The second transistor is disposed so as to overlap the first gate electrode and has a second semiconductor layer electrically connected to the first gate electrode, a second gate insulating layer in contact with a side surface of the second semiconductor layer, and a second gate electrode formed so as to cover at least a part of the side surface of the second semiconductor layer in contact with the second gate insulating layer. The capacitor has a first gate electrode and a second semiconductor layer. The first gate electrode is electrically connected to the first gate electrode, and the second semiconductor layer is electrically connected to the second gate electrode. The source region and the drain region are provided so as to sandwich a region of the first semiconductor layer overlapping the first gate electrode. The second transistor is disposed so as to overlap the first gate electrode and has a second semiconductor layer electrically connected to the first gate electrode, a second gate insulating layer in contact with a side surface of the second semiconductor layer, and a second gate electrode formed so as to cover at least a part of the side surface of the second semiconductor layer in contact with the second gate insulating layer. The second semiconductor layer is electrically connected to the first gate electrode, and the second gate insulating layer is in contact with a side surface of the second semiconductor layer. The second gate electrode is formed so as to cover at least a part of the side surface of the second semiconductor layer in contact with the second gate insulating layer. The capacitor has a first gate electrode and a second semiconductor layer. a second capacitance electrode electrically connecting the second capacitance electrode to the capacitance layer; a capacitance layer in contact with the second capacitance electrode; and a first capacitance electrode formed so as to cover at least a part of a side surface of the second capacitance electrode. It is a semiconductor memory device.

[0022] The first gate electrode functions as a source electrode or a drain electrode of the second transistor. The second semiconductor layer is formed so as to overlap the first gate electrode. The source and drain electrodes of the transistor are formed perpendicular to the substrate on which the transistor is formed, in the second semiconductor layer. The second transistor is disposed so as to sandwich the conductor layer. Therefore, the second transistor is, for example, a planar type transistor. The occupied area can be made smaller than that of a resistor.

[0023] The capacitor uses the second capacitance electrode and the first capacitance electrode as capacitance electrodes. The capacitor overlaps the first transistor and the second transistor. Compared to when the first transistor, the capacitor, and the second transistor are formed so that they do not overlap, Therefore, the area occupied by the capacitor can be reduced.

[0024] In addition, the second capacitance electrode is provided to electrically connect the first gate electrode and the second semiconductor layer. It can be easily done.

[0025] When the second transistor is turned on, one electrode of the capacitor, i.e. That is, a potential difference occurs between the second capacitance electrode and the first capacitance electrode. The charge is held in the capacitor. Then, the first transistor is turned off. , the written data can be retained.

[0026] Furthermore, the second semiconductor layer is made of a semiconductor material having a band gap wider than that of silicon. It is preferable that the semiconductor memory device is a semiconductor memory device having a

[0027] The second semiconductor layer is made of a semiconductor material having a band gap wider than that of silicon. Therefore, the off-current of the second transistor can be reduced. It is possible to provide a semiconductor memory device capable of retaining stored contents even in a situation where data cannot be read.

[0028] In addition, the semiconductor memory device is a floating gate (FG) type non-volatile memory. In addition, when writing and erasing data, carriers do not damage the gate insulating layer. The memory does not deteriorate even if the data is written and erased repeatedly. The reliability of data retention can be improved compared to volatile memory. It is possible to provide a semiconductor memory device that can be used many times (for example, more than one million times).

[0029] Furthermore, it is preferable that the second semiconductor layer is made of an oxide semiconductor. I wish.

[0030] By using an oxide semiconductor for the second semiconductor layer, the off-state current of the second transistor is reduced. This provides a semiconductor memory device capable of retaining stored contents even when power is not supplied. In addition, the oxide semiconductor film can be formed by a semiconductor manufacturing process using a silicon wafer. Since the formation can be performed at temperatures lower than the temperatures typically used in the process, for example, 1000°C, The semiconductor memory device can be easily manufactured. In addition, the second semiconductor layer can be easily heated after being formed. Even if an oxide semiconductor that has not been subjected to any treatment is used, the second transistor can be formed with a thickness of, for example, 100 cm 2 It is possible to achieve a field-effect mobility of more than 1 / V·sec. By using a second transistor with high mobility, a semiconductor memory device with high write speed can be obtained. It is possible to do this. Effect of the Invention

[0031] According to one embodiment of the present invention, a highly integrated semiconductor memory device can be provided. It is possible to provide a semiconductor memory device capable of retaining stored contents even when power is not supplied. It is also possible to provide a semiconductor memory device that can be written many times.

[0032] According to one aspect of the present invention, the second semiconductor layer of the second transistor is formed so as to overlap the first gate electrode. By arranging the memory cells in this manner, the integration density of the memory cell array can be improved. The transistor that controls the charge amount of the capacitor provided in the memory cell is made of a material other than silicon. By using semiconductor materials with a wide band gap, the memory can be used even when power is not supplied. In addition, the present invention provides a semiconductor memory device capable of storing a large amount of data. The transistor that controls the charge of the capacitor is a transistor with low leakage current. By doing so, it is possible to provide a semiconductor memory device that is non-volatile and has no limit on the number of times it can be written. This can be done. [Brief description of the drawings]

[0033] [Figure 1] 1A to 1C are a cross-sectional view, a top view, and a circuit diagram of a semiconductor memory device of one embodiment of the present invention. [Diagram 2] 1A to 1C are a cross-sectional view, a top view, and a circuit diagram of a semiconductor memory device of one embodiment of the present invention. [Diagram 3] 1A to 1C are a cross-sectional view, a top view, and a circuit diagram of a semiconductor memory device of one embodiment of the present invention. [Figure 4]1A to 1C are cross-sectional views illustrating respective manufacturing steps of a semiconductor memory device according to one embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional views illustrating respective manufacturing steps of a semiconductor memory device according to one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating respective manufacturing steps of a semiconductor memory device according to one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating respective manufacturing steps of a semiconductor memory device according to one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating respective manufacturing steps of a semiconductor memory device according to one embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating respective manufacturing steps of a semiconductor memory device according to one embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating respective manufacturing steps of a semiconductor memory device according to one embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating respective manufacturing steps of a semiconductor memory device according to one embodiment of the present invention. [Figure 12] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 13] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 14] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 15] FIG. 1 illustrates a crystal structure of an oxide material according to one embodiment of the present invention. [Figure 16] 1 is a circuit diagram of a main part of a semiconductor memory device according to one embodiment of the present invention. [Figure 17] 1A to 1C illustrate a semiconductor device of one embodiment of the present invention. [Figure 18] 1A to 1C illustrate electronic devices according to one embodiment of the present invention. [Figure 19] 1A to 1C illustrate electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the embodiments and details of the present invention. The invention should not be construed as being limited to the description of the embodiments shown below.

[0035] (Embodiment 1) In this embodiment, a configuration example of a semiconductor memory device according to one embodiment of the present invention will be described with reference to FIG. He explains.

[0036] FIG. 1B is a schematic top view of the semiconductor memory device 1, and FIG. 1A is a schematic top view of the semiconductor memory device 1. FIG. 1C is a schematic cross-sectional view taken along dashed line A1-B1. It is.

[0037] The semiconductor memory device 1 exemplified in this embodiment includes a plurality of parallel bit lines 500 and a bit The bit line 500 is perpendicular to the first word line 105 and the second word line 106. 500, a first transistor is provided in an overlapping region of the first word line 105 and the second word line 106. A first transistor 100, a second transistor 200 and a capacitor 300a are formed in the memory. The cell 10 includes a first transistor 100, a second transistor 200, and a capacitor 30. The first word line 105 includes the first capacitance electrode 310a and the second word line 10 6 is electrically connected to the second gate electrode 220.

[0038] ((First Transistor)) The first transistor 100 will be described. The first transistor 100 includes a first semiconductor layer 1 01, a first gate insulating layer 110 in contact with the first semiconductor layer 101, and a first gate insulating layer A first gate electrode 120 is in contact with the first semiconductor layer 110 and overlaps the first semiconductor layer 101. The source region and the drain region are provided so as to sandwich the region overlapping with the first gate electrode 120 of The first gate electrode 120 is a second transistor. The first gate electrode 120 is electrically connected to the second semiconductor layer 201 of the gate electrode 200. , which functions as one electrode of the capacitor 300a.

[0039] One of the source region or the drain region 130 is connected to the bit line 500 via the conductive layer 600. The other of the source region or the drain region 130 is used as a wiring. The source region or drain region 130 of the adjacent first transistor 100 is electrically connected to the In order to reduce the electrical resistance of the source and drain regions 130, The source region 130 and the drain region 130 are doped with a high concentration of impurities. The source or drain region 130 is connected to the source or drain region of the adjacent element by an insulating layer 7. Electrically isolated at 00.

[0040] (First semiconductor layer) The first semiconductor layer 101 is made of, for example, single crystal silicon, polysilicon, or microcrystalline silicon. The first transistor 100 may be made of a silicon or oxide semiconductor. Since it is a transistor that reads information, it has a high switching speed. Therefore, the first semiconductor layer 101 is preferably made of single crystal silicon. is preferred.

[0041] (First gate insulating layer) The first gate insulating layer 110 can be made of an insulating material. For example, silicon oxide can be used. Silicon, hafnium oxide, yttrium oxide, hafnium silicate, hafnium aluminum Nitrogen doped hafnium silicate, nitrogen doped hafnium aluminate The first gate insulating layer 110 can be made of a material such as lanthanum oxide or lanthanum oxide. Therefore, the first transistor 100 can be made of a material suitable for the first semiconductor layer 101. The thickness of the first gate insulating layer 110 may be set to be equal to or smaller than the channel length of the first transistor 100. An appropriate film thickness can be set accordingly.

[0042] (First gate electrode) The material of the first gate electrode 120 is selected based on the electrical conductivity, adhesion to the first gate insulating layer 110, and It is necessary to have low-resistance polysilicon (doped with impurities such as phosphorus to give conductivity). polysilicon), or, for example, molybdenum, titanium, tantalum, copper, tungsten, Metallic materials such as aluminum, chromium, neodymium, scandium, etc., or materials that contain these as their main components The first gate electrode 120 can be formed by using an alloy material having a single layer structure. Alternatively, a laminated structure may be used.

[0043] (Source or drain region) The source or drain region 130 has a good ohmic contact with the source or drain electrode. It is preferable that the resistance in the direction perpendicular to the film thickness direction is low. It is sufficient that the first semiconductor layer 101 can be connected to the region in which the channel is formed without causing resistance. When silicon is used for the first semiconductor layer 101, a shallow pn junction is formed, and the first gate electrode It is preferable that there is no overlap between 120 and the source or drain regions 130 .

[0044] (First interlayer film) The first interlayer film 150 can be made of an insulating material. For example, silicon oxide or silicon oxynitride. Inorganic materials such as silicon, silicon nitride, and aluminum oxide can be used. For example, organic resins such as acrylic resins and polyimide resins can be used.

[0045] (Conductive layer) The conductive layer 600 is only required to be electrically connected to the first semiconductor layer 101 and the bit line 500. For example, For example, it can be formed by embedding a metal and planarizing it using a CMP method or the like.

[0046] (insulating layer) The insulating layer 700 may be made of silicon oxide, silicon nitride, or the like. For example, LOCOS (Local Oxidation of Silicon) method or shallow trench Using the shallow trench isolation (STI) method, A plurality of element formation regions separated by oxide films may be formed on a crystalline semiconductor substrate.

[0047] ((Capacitor)) Next, the capacitor 300a will be described. The capacitor 300a has a first capacitance electrode 31 0a and a capacitance layer 410 in contact with a first gate electrode 120, The first gate electrode of the first transistor 100 functions as one electrode of a capacitor. 120 is used as one of the capacitance electrodes of the capacitor 300a. As a result, the area occupied by the semiconductor memory device can be reduced. It is possible.

[0048] (1st capacitor electrode) The first capacitance electrode 310a is made of, for example, low-resistance polysilicon or molybdenum. Titanium, Tantalum, Copper, Tungsten, Aluminum, Chromium, Neodymium, Scandium The electrode can be formed using a metal material such as aluminum or an alloy material containing these as the main component. The first capacitor electrode 310a is electrically connected to the first word line 105.

[0049] (capacitance layer) The capacitance layer 410 can be made of an insulating material. For example, silicon oxide or silicon oxynitride can be used. Inorganic materials such as silicon and silicon nitride can be used. When using low-resistance polysilicon, an oxide film is formed on its surface by thermal oxidation, etc., and the capacitance It may also be used as layer 410.

[0050] The capacitor 300a is a capacitor having a first gate electrode 120 of the first transistor 100. Therefore, the area occupied by the capacitor 300a is reduced. It is possible.

[0051] ((Second Transistor)) Next, the second transistor 200 will be described. The second transistor 200 is A second semiconductor layer is disposed so as to overlap the first gate electrode 120 and is electrically connected to the first gate electrode 120. A conductor layer 201, a second gate insulating layer 210 in contact with a side surface of the second semiconductor layer 201, and a second gate insulating layer 210 The insulating layer 210 is in contact with the second semiconductor layer 201 and is formed so as to cover at least a part of the side surface of the second semiconductor layer 201. The bit line 500 has a second gate electrode 220 formed on the second semiconductor layer 2. It is electrically connected to 01.

[0052] (Second semiconductor layer) The shape of the second semiconductor layer 201 will be described. The side surface of the second semiconductor layer 201 is The second transistor is covered with the second gate electrode 220 through the edge layer 210. In the gate electrode 200, the second gate electrode 220 covering the side surface of the second semiconductor layer 201 functions as a gate. The first gate electrode 120 in contact with the bottom surface of the second semiconductor layer 201 serves as a source electrode, and the upper surface It is a vertical transistor in which the adjacent bit line 500 functions as a drain electrode. Therefore, the area occupied by the second transistor 200 can be reduced.

[0053] In addition, the second transistor 200 has an extremely small off-state current. It is possible to provide a semiconductor memory device capable of retaining stored contents even when power is not supplied. In addition, it becomes possible to hold data in the capacitor 300a for a long period of time. Therefore, in semiconductor memory devices, periodic data rewrite operations (hereinafter referred to as refresh) are required. This makes it possible to eliminate the need for a refresh operation, or to minimize the frequency of the refresh operation. This makes it possible to make the semiconductor memory device function as a substantially non-volatile semiconductor memory device.

[0054] In addition, since the second transistor 200 is a transistor with an extremely small off-state current, The size of the capacitor 300a that holds the capacitor 300 can be reduced. The reduction in size of 0a reduces the time required for writing and reading, enabling high-speed operation. This can provide a semiconductor memory device.

[0055] The channel length of the second transistor 200 depends on the thickness of the second gate insulating layer 210. For example, For example, it is 10 times or more, preferably 20 times, the diagonal length or diameter of the second semiconductor layer 201. This is preferable because it is possible to suppress the short channel effect.

[0056] In addition, in FIG. 1B, the second semiconductor layer 201 is shown as having a cylindrical shape, but it may have a rectangular shape. For example, if the second semiconductor layer 201 has a rectangular column shape, the second semiconductor layer 201 may be formed near the side surface of the second semiconductor layer 201. Since the effective width of the channel can be made large, the on-current of the second transistor 200 can be increased. In addition, the cylindrical shape has no protruding parts on the side, Since the gate electric field is uniformly applied, the second transistor 200 can be made highly reliable. For example, if it is desired to further increase the on-current, the shape of the bottom surface of the second semiconductor layer 201 can be The shape is a polygon with at least one interior angle exceeding 180°, such as a star polygon (concave). A polygon may also be used.

[0057] The second semiconductor layer 201 is made of a semiconductor having a band gap wider than that of silicon. Specifically, in order to obtain a very high off-resistance, silicon (band gap) is preferably used. A band gap of 1.1 eV is insufficient, and a band gap of 2.5 eV or more (4 eV) is insufficient. A wide band gap semiconductor having a capacitance of 0.1 eV or less, preferably 3 eV or more and 3.8 eV or less. It is necessary to use a conductor, such as an oxide semiconductor, such as indium oxide or zinc oxide. For example, a nitride semiconductor such as gallium nitride, a sulfide semiconductor such as zinc sulfide, etc. may be used. When such a semiconductor is used in the channel formation region, the off-state current of the transistor can be reduced. It can be made smaller.

[0058] The oxide semiconductor is an In-Sn-Ga-Zn oxide semiconductor, which is a quaternary metal oxide. and ternary metal oxides such as In-Ga-Zn oxide semiconductors and In-Sn-Zn oxide semiconductors. Semiconductors, In-Al-Zn oxide semiconductors, Sn-Ga-Zn oxide semiconductors, Al- Ga-Zn oxide semiconductors, Sn-Al-Zn oxide semiconductors, and binary metal oxides In-Zn oxide semiconductors, Sn-Zn oxide semiconductors, Al-Zn oxide semiconductors, Zn-Mg oxide semiconductor, Sn-Mg oxide semiconductor, In-Mg oxide semiconductor, I n-Ga-based oxide semiconductors, indium oxide, tin oxide, zinc oxide, etc. can be used. In this specification, for example, an In-Sn-Ga-Zn-based oxide semiconductor is Metal oxide containing indium (In), tin (Sn), gallium (Ga), and zinc (Zn) , and the stoichiometric composition is not particularly important.

[0059] The oxide semiconductor film may be, for example, non-single-crystal. C Axis Aligned Crystal), polycrystalline, microcrystalline, and amorphous parts The amorphous part has a higher defect level density than the microcrystals and CAAC. The defect density is higher than that of the oxide semiconductor having CAAC. Axis Aligned Crystalline Oxide Semiconductor For details, refer to the sixth embodiment.

[0060] The oxide semiconductor film may include, for example, a CAAC-OS. The c-axis is oriented, and the a-axis and / or b-axis are not macroscopically aligned.

[0061] The oxide semiconductor film may have, for example, microcrystals. The microcrystalline oxide semiconductor film has a thickness of, for example, 1 nm to 10 nm. The film contains microcrystals (also called nanocrystals) of about 100 nm in size.

[0062] The oxide semiconductor film may have, for example, an amorphous portion. The amorphous oxide semiconductor film is a semiconductor in which the atomic arrangement is disordered. The amorphous oxide semiconductor film has no crystalline component. Alternatively, the amorphous oxide semiconductor film has a completely amorphous structure, for example. and has no crystalline parts.

[0063] Note that the oxide semiconductor film may be a CAAC-OS film, a microcrystalline oxide semiconductor film, or an amorphous oxide semiconductor film. The mixed film may be a film having, for example, an amorphous oxide semiconductor region and a microcrystalline oxide semiconductor region. The mixed film has a semiconductor region and a CAAC-OS region. A stack of an oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region. The structure may be

[0064] Note that the oxide semiconductor film may be, for example, single crystal.

[0065] The oxide semiconductor film has a plurality of crystal parts, and the c-axes of the crystal parts are aligned along a normal vector of a surface on which the crystal parts are formed. It is preferable that the crystal orientation of the crystals is parallel to the normal vector of the surface. The directions of the a-axis and the b-axis may be different between the oxide semiconductor films. An example is a CAAC-OS film.

[0066] (Second gate insulating layer) The second gate insulating layer 210 may be made of an insulating material. For example, silicon oxide may be used. Silicon, silicon oxynitride, hafnium oxide, yttrium oxide, hafnium silicate, Hafnium aluminate, nitrogen doped hafnium silicate, nitrogen doped hafnium The acid that satisfies the stoichiometric ratio can be used. Silicon oxide, which contains more oxygen than silicon, is preferred.

[0067] The second gate insulating layer 210 may be formed by using a CVD method, a sputtering method, or the like. The second gate insulating layer 210 can be formed by CVD using a silicon oxide film or a silicon oxynitride film. When forming by the D method, the glow discharge plasma is generated at 3MHz to 30MHz, typically High frequency power in the HF bands of 13.56MHz, 27.12MHz, or above 30MHz Applying high frequency power in the VHF band up to about 300MHz, typically 60MHz. It is preferable to apply microwave power of 1 GHz or more. It is also possible to apply the high frequency power in a pulsed manner or continuously. The acid formed using microwaves of 1 GHz or higher can be used as a continuous wave. The silicon nitride film or silicon oxynitride film has a fixing property in the film and at the interface with the second semiconductor layer 201. The charge is larger than that of silicon oxide film or silicon oxynitride film formed by the conventional plasma CVD method. Therefore, in the second transistor 200, the reliability of electrical characteristics such as the threshold voltage is improved. It can be made higher.

[0068] The thickness of the second gate insulating layer 210 corresponds to the channel length of the second transistor 200. Then, an appropriate film thickness can be set.

[0069] (Second gate electrode) The material of the second gate electrode 220 is selected based on the electrical conductivity, adhesion to the second gate insulating layer 210, and Low-resistance polysilicon or, for example, molybdenum, titanium, tungsten Metallic materials such as tantalum, copper, tungsten, aluminum, chromium, neodymium, and scandium The second gate electrode may be formed of a material selected from the group consisting of fluorine, fluorine-containing ... The second gate electrode 220 may have a single-layer structure or a multi-layer structure. The pole 220 is electrically connected to the second word line 106 .

[0070] (Second interlayer film) The second interlayer film 250 can be made of an insulating material. For example, silicon oxide or silicon oxynitride. Inorganic materials such as silicon, silicon nitride, and aluminum oxide can be used. For example, organic resins such as acrylic resins and polyimide resins can be used.

[0071] (insulating film) The insulating film 251 can be made of an insulating material, such as silicon oxide or silicon oxynitride. Inorganic materials such as silicon nitride and aluminum oxide can be used. It is only necessary to electrically insulate the second gate electrode 220 .

[0072] In FIG. 1, the second gate electrode 220 is connected to the second semiconductor layer 2 via the second gate insulating layer 210. Although the configuration is such that the side surface of 01 is covered, it is sufficient that the configuration is such that at least a portion of the side surface is covered. For example, the second gate electrode 220 is formed only on one side of the second semiconductor layer 201 along the second gate electrode 220. If the gate electrode 220 is provided, the integration density in the direction of the bit line 500 can be increased. On the other hand, if the side surface of the second semiconductor layer 201 is covered as shown in FIG. Since the effective channel width of the transistor 200 can be made large, the on-current can be increased.

[0073] (Bit Line) It is preferable to use a material with low electrical resistance for the bit line 500. For example, aluminum Single layer of aluminum, titanium, tungsten, copper, or laminated film of titanium and aluminum, etc. It is preferable to use

[0074] Next, writing and reading of data to and from the semiconductor memory device will be described.

[0075] <Write data> When writing data, the second transistor 200 is turned on. One electrode of the capacitor 300a, i.e., the first gate electrode 1 of the first transistor 100 A potential difference occurs between the electrode 20 and the other electrode, the capacitance layer 410. Then, the first transistor 100 is turned off. By setting the write state, the written data can be held.

[0076] <Reading data> By determining whether the first transistor 100 is in an on state or an off state, data is read. When the capacitor 300a is held at a high level potential, the first transistor Since the first transistor 100 is turned on, the bit line 500 is connected to the The high level potential given to the bit line is output. The bit line 500 is detected by a read circuit such as a sense amplifier. , reading can be performed.

[0077] As described above, the semiconductor memory device 1 exemplified in this embodiment has the first transistor 100 The gate electrode 120 is used as one electrode of the capacitor 300a. In addition, the area occupied by the capacitor 300a can be reduced. The second transistor 200, which has a very small area, is disposed on the first transistor 100. This makes it possible to reduce the area occupied by the semiconductor memory device.

[0078] In addition, the second transistor 200 using an oxide semiconductor for the second semiconductor layer has an extremely low off-state current. Therefore, the memory contents can be retained even when power is not supplied. In addition, the semiconductor memory device can be a floating-point type. Like a flip-gate (FG) type non-volatile memory, the capacitance is changed when writing and erasing data. The rear does not damage the gate insulating layer, so it does not deteriorate even if the memory is repeatedly written and erased. In other words, the semiconductor memory device has higher reliability of data retention than FG type nonvolatile memory. Therefore, the number of times that it can be written is large (for example, more than 1 million times). This makes it possible to realize a semiconductor memory device.

[0079] (Embodiment 2) In this embodiment, a configuration example of a semiconductor memory device according to one embodiment of the present invention will be described with reference to FIG. He explains.

[0080] FIG. 2B is a schematic top view of the semiconductor memory device 2, and FIG. 2A is a schematic top view of the semiconductor memory device 2. FIG. 2C is a schematic cross-sectional view taken along the dashed line A2-B2. It is.

[0081] The semiconductor memory device 2 exemplified in this embodiment includes a plurality of parallel bit lines 500 and a bit The bit line 500 is perpendicular to the first word line 105 and the second word line 106. 500, a first transistor is provided in an overlapping region of the first word line 105 and the second word line 106. A first transistor 100, a second transistor 200 and a capacitor 300b are formed in the memory. The cell 20 includes a first transistor 100, a second transistor 200, and a capacitor 30. The first word line 105 includes the first capacitance electrode 310b and the second word line 10 6 is electrically connected to the second gate electrode 220.

[0082] ((First Transistor)) The first transistor 100 will be described. The first transistor 100 includes a first semiconductor layer 1 01, a first gate insulating layer 110 in contact with the first semiconductor layer 101, and a first gate insulating layer a first gate electrode 120 that is in contact with the first semiconductor layer 110 and overlaps the first semiconductor layer 101; A sidewall layer 140 in contact with the first gate electrode 120 of the first semiconductor layer 101 A source region and a drain region 130 are provided so as to sandwich a region overlapping with the first interlayer film. The first gate electrode 120 is connected to the second semiconductor layer 20 of the second transistor 200. The first gate electrode 120 is electrically connected to one of the capacitors 300b. It functions as an electrode.

[0083] The first gate electrode 120 is electrically connected to a second capacitance electrode 320 of the capacitor 300b, which will be described later. Connected.

[0084] Either the source region or the drain region 130 is connected to the conductive layer 600a and the first capacitor electrode 310b. The bit line 500 is electrically connected to the buffer layer 310d and the conductive layer 600b formed at the same time. Also, the source or drain region 130 is connected to the source of the adjacent element. The source or drain region is electrically isolated by an insulating layer 700.

[0085] A first semiconductor layer 101, a first gate insulating layer 110, a first gate electrode 120, a source region or The details of the drain region 130, the first interlayer film 150, and the insulating layer 700 are described in the embodiment. 1 can be referred to. For details of the conductive layers 600a and 600b, refer to the conductive layer 60 Please refer to the description of 0.

[0086] (Sidewall layer) The sidewall layer 140 may be made of silicon oxide, silicon nitride, or the like. The side wall layer 140 forms the source or drain region 130 and the channel. The region in which the channel is formed and the drain region (or A lightly doped drain (LDD) region is formed between the drain and source region. It is preferable to use a (operated drain) structure.

[0087] ((Capacitor)) Next, the capacitor 300b will be described. The capacitor 300b has a first gate electrode 1 20 and the second semiconductor layer 201. A second capacitance electrode 320 electrically connects the second capacitance electrode 3 20 and a first capacitance electrode 310b in contact with the capacitance layer 410, The second capacitance electrode 320 functions as one electrode of a capacitor.

[0088] For details of the first capacitance electrode 310b, the description of the first capacitance electrode 310a in the first embodiment can be referred to. For details of the capacitive layer 410, embodiment 1 can be referred to.

[0089] (Second capacitor electrode) The second capacitance electrode 320 is made of, for example, low-resistance polysilicon or molybdenum. , titanium, tantalum, copper, tungsten, aluminum, chromium, neodymium, scandium The insulating layer 11 can be formed by using a metal material such as titanium or an alloy material containing these as a main component. By providing the second capacitance electrode 320, the first gate electrode 120 and the second semiconductor layer 201 Electrical connections can be made easier.

[0090] The width of the second capacitance electrode 320 (the width in the channel formation direction of the first transistor 100) and the second capacitance It is preferable that the ratio of the thickness of the second capacitance electrode 320 is high. If the film thickness is increased, the second capacitance electrode 320 can be used as one electrode of a capacitor. This is because the area occupied by the capacitor can be reduced.

[0091] The capacitor 300b uses a second capacitance electrode 320 and a first capacitance electrode 310b as capacitance electrodes. Therefore, the area occupied by capacitor 300b can be reduced.

[0092] ((Second Transistor)) Next, the second transistor 200 will be described. The second transistor 200 is a second semiconductor The second transistor has a second gate insulating layer 210 and a second gate electrode 220. The gate electrode 200 is disposed so as to overlap the first gate electrode 120. 201 is electrically connected to the first gate electrode 120. In addition, the second gate insulating layer 21 The second gate electrode 220 is in contact with the side surface of the second semiconductor layer 201. The insulating layer 210 is in contact with the second semiconductor layer 201 and is formed so as to cover at least a part of the side surface of the second semiconductor layer 201. In addition, the bit line 500 is electrically connected to the second semiconductor layer 201.

[0093] The first embodiment can be referred to for details of the second transistor. 2. A gate insulating layer 210, a second gate electrode 220, a second interlayer film 250, an insulating film 251, and The details of the bit line 500 can also be referred to in the first embodiment. The first embodiment can also be referred to for writing and reading of data.

[0094] As described above, in the semiconductor memory device 2 exemplified in this embodiment, the second capacitance electrode 320 is 2 serves as a source electrode or a drain electrode of the transistor 200. In the transistor 200, the source and drain electrodes are formed on the substrate that forms the transistor. Thus, the second transistor 200 is, for example, a planar type transistor. Therefore, it is suitable for highly integrated semiconductor memory devices. A storage device can be provided.

[0095] In addition, the second transistor 200, which occupies a very small area relative to the surface area of ​​the substrate, is This arrangement reduces the area occupied by the semiconductor memory device. It can be reduced.

[0096] In addition, by providing the second capacitance electrode 320, the first gate electrode 120 and the second semiconductor layer 2 This makes it easier to connect the electrical components of the device.

[0097] In addition, the second transistor 200 using an oxide semiconductor for the second semiconductor layer 201 has an off-current This is an extremely small transistor. Therefore, even when power is not supplied, the memory contents are preserved. In addition, the semiconductor memory device can store F Like G-type nonvolatile memory, when writing and erasing data, carriers flow into the gate insulating layer. Since it does not damage the memory, it does not deteriorate even if the memory is repeatedly written and erased. Semiconductor memory devices can improve the reliability of data retention compared to FG type nonvolatile memory. Therefore, it is a semiconductor memory device that can be written many times (for example, more than 1 million times). It becomes possible to do so.

[0098] (Embodiment 3) In this embodiment, a configuration example of a semiconductor memory device according to one embodiment of the present invention will be described with reference to FIG. He explains.

[0099] FIG. 3B is a schematic top view of the semiconductor memory device 3, and FIG. 3A shows one of the elements in FIG. 3B. FIG. 3C is a schematic cross-sectional view taken along dashed line A3-B3. It is.

[0100] The semiconductor memory device 3 exemplified in this embodiment includes a plurality of parallel bit lines 500 and a bit The bit line 500 is perpendicular to the first word line 105 and the second word line 106. 500, a first transistor is provided in an overlapping region of the first word line 105 and the second word line 106. A first transistor 100, a second transistor 200 and a capacitor 300c are formed in the memory. The cell 30 includes a first transistor 100, a second transistor 200, and a capacitor 30. The first word line 105 includes the first capacitance electrode 310c and the second word line 10 6 is electrically connected to the second gate electrode 220.

[0101] ((First Transistor)) The first transistor 100 will be described. The first transistor 100 includes a first semiconductor layer 1 01, a first gate insulating layer 110 in contact with the first semiconductor layer 101, and a first gate insulating layer a first gate electrode 120 that is in contact with the first semiconductor layer 110 and overlaps the first semiconductor layer 101; A sidewall layer 140 in contact with the first gate electrode 120 of the first semiconductor layer 101 A source region and a drain region 130 are provided so as to sandwich a region overlapping with the first interlayer film. The first gate electrode 120 is connected to the second semiconductor layer 20 of the second transistor 200. The first gate electrode 120 is electrically connected to one of the electrodes of the capacitor 300c. It functions as an electrode.

[0102] The first gate electrode 120 is electrically connected to a second capacitance electrode 320 of the capacitor 300c, which will be described later. Connected.

[0103] Either the source region or the drain region 130 is connected via the conductive layer 600a and the conductive layer 600b. The source or drain region 13 is electrically connected to the bit line 500. 0 is electrically isolated from the source or drain region of the adjacent element by an insulating layer 700. It is being done.

[0104] A first semiconductor layer 101, a first gate insulating layer 110, a first gate electrode 120, a source region or 1 shows details of the drain region 130, the sidewall layer 140, the first interlayer film 150, and the insulating layer 700. For details, refer to the first embodiment. In addition, the conductive layers 600a and 600b are The description of the conductive layer 600 in the first embodiment can be referred to.

[0105] ((Capacitor)) Next, the capacitor 300c will be described. The capacitor 300c has a first gate electrode 1 20 and the second semiconductor layer 201. A second capacitance electrode 320 electrically connects the second capacitance electrode 3 20 and a first capacitance electrode 310c in contact with the capacitance layer 410, The second capacitance electrode 320 functions as one electrode of a capacitor.

[0106] For details of the first capacitance electrode 310c, the description of the first capacitance electrode 310a in the first embodiment can be referred to. For details of the capacitive layer 410, embodiment 1 can be referred to.

[0107] For details of the second capacitance electrode 320, reference can be made to the second embodiment. The width (the width in the channel formation direction of the first transistor 100) is determined by the capacitance of the capacitor. However, it is also possible to extend the width of the first transistor 100 to the edge of the sidewall layer 140 of the first transistor 100. The width of the second capacitance electrode 320 (the width in the channel formation direction of the first transistor 100) By widening the gap, the tolerance for aligning the second capacitance electrode 320 and the second semiconductor layer 201 is increased. It can be made easier.

[0108] The capacitor 300c uses a second capacitance electrode 320 and a first capacitance electrode 310c as capacitance electrodes. Therefore, the area occupied by capacitor 300c can be reduced.

[0109] ((Second Transistor)) Next, the second transistor 200 will be described. The second transistor 200 is a second semiconductor The second transistor has a second gate insulating layer 210 and a second gate electrode 220. The gate electrode 200 is disposed so as to overlap the first gate electrode 120. 201 is electrically connected to the first gate electrode 120. In addition, the second gate insulating layer 21 The second gate electrode 220 is in contact with the side surface of the second semiconductor layer 201. The insulating layer 210 is in contact with the second semiconductor layer 201 and is formed so as to cover at least a part of the side surface of the second semiconductor layer 201. In addition, the bit line 500 is electrically connected to the second semiconductor layer 201.

[0110] The first embodiment can be referred to for details of the second transistor. 2. A gate insulating layer 210, a second gate electrode 220, a second interlayer film 250, an insulating film 251, and The details of the bit line 500 can also be referred to in the first embodiment. The first embodiment can also be referred to for writing and reading of data.

[0111] As described above, in the semiconductor memory device 3 exemplified in this embodiment, the second capacitance electrode 320 is It functions as a source electrode or a drain electrode of the transistor 200. In the transistor 200, the source electrode and the drain electrode are formed on a substrate on which the transistor is formed. Therefore, the second transistor 200 is, for example, a planar type transistor. Therefore, it is possible to reduce the area occupied by a highly integrated semiconductor memory device. An apparatus can be provided.

[0112] In addition, the second transistor 200, which occupies a very small area relative to the surface area of ​​the substrate, is This arrangement reduces the area occupied by the semiconductor memory device. It can be reduced.

[0113] In addition, by providing the second capacitance electrode 320, the first gate electrode 120 and the second semiconductor layer 2 This makes it easier to connect the electrical components of the device.

[0114] In addition, the second transistor 200 using an oxide semiconductor for the second semiconductor layer 201 has an off-current This is an extremely small transistor. Therefore, even when power is not supplied, the memory contents are preserved. In addition, the semiconductor memory device can store F Like G-type nonvolatile memory, when writing and erasing data, carriers flow into the gate insulating layer. Since it does not damage the memory, it does not deteriorate even if the memory is repeatedly written and erased. Semiconductor memory devices can improve the reliability of data retention compared to FG type nonvolatile memory. Therefore, it is a semiconductor memory device that can be written many times (for example, more than 1 million times). It becomes possible to do so.

[0115] (Embodiment 4) In this embodiment, a manufacturing method of a semiconductor memory device according to one embodiment of the present invention will be described.

[0116] The steps of manufacturing the semiconductor memory device 1 shown in FIG. 1 will be described below with reference to FIGS. The cross-sectional view corresponds to a cross section taken along dashed line A1-B1 in a top view of the semiconductor memory device 1. The diagram shows the state of the area after each process. A top view showing the state after the step is omitted. In this embodiment, single crystal silicon is used for the substrate. The following description will be given for the case where the material is used for the following constituent elements. Please refer to embodiments 1 to 3.

[0117] FIG. 4 shows a semiconductor recording medium in which the steps from forming the insulating layer 700 to the step of forming the capacitance layer 410 have been carried out. 1 shows a cross section of a memory device 1.

[0118] The insulating layer 700 forms electrically isolated regions in the single crystal semiconductor substrate. It is sufficient to separate the transistor 100 (FIG. 4(A)).

[0119] Next, the first gate insulating layer 110 is formed. For example, it may be formed of a thermal oxide film (FIG. 4( B).

[0120] Next, the first gate electrode 120 is formed. The first gate electrode 120 is a low-resistance polysilicon film. The insulating layer 11 may be formed using silicon or a metal such as tungsten (FIG. 4(B)).

[0121] Next, the first gate electrode 120 is processed to a desired gate length by photolithography. (Figure 4(C)).

[0122] Next, impurities are doped into the regions in which the source and drain are to be formed. A drain region 130 is formed. The silicon in the region where the source or drain is to be formed is doped with a desired material. The impurities that can form a transistor of a desired conductivity type can be implanted. This can be done by implantation method or the like (Figure 4(D)).

[0123] Next, the capacitance layer 410 is formed. The capacitance layer 410 functions as an insulating layer of the capacitor (see FIG. 4(E)).

[0124] FIG. 5 shows a process for forming the first interlayer film 150 through a process for forming the second gate insulating layer 210. 1 shows a cross section of the semiconductor memory device 1.

[0125] Next, the first interlayer film 150 is formed. The first interlayer film 150 is made of an insulating material. For example, silicon oxide, silicon oxynitride, silicon nitride, etc. can be formed by the CVD method. Alternatively, aluminum oxide or the like may be formed by a sputtering method.

[0126] Next, the first capacitor electrode 310a is formed by photolithography and etching. The etching process is carried out in a dry It is preferable to use an etching method (FIG. 5(A)).

[0127] The first capacitor electrode 310a may be made of a semiconductor or metal having low electrical resistance. For example, low-resistance polysilicon can be formed by the CVD method. Tantalum, copper, tungsten, aluminum, chromium, neodymium, scandium, etc. The above metal materials or alloy materials mainly composed of these are formed by sputtering. It is also possible.

[0128] Next, the first capacitor electrode 310a is polished until the surface of the first gate electrode 120 is exposed. The polishing may be performed by, for example, a CMP method. Since the surface is exposed, the second semiconductor layer 201 and the first gate electrode 120 to be formed in the next step can be It becomes possible to electrically connect (Figure 5(B)).

[0129] Next, a second semiconductor layer 201 is formed on the exposed surface of the first gate electrode 120. It is preferable to use an oxide semiconductor for the conductor layer 201. For example, the oxide semiconductor film is a sputtered film. It can be formed by a tapping method (Figure 5(C)).

[0130] In this embodiment, the second semiconductor layer 201 and the first gate electrode 120 are formed to overlap each other. However, it is sufficient that the second semiconductor layer 201 is electrically connected to the first gate electrode 120. However, the width of the second semiconductor layer 201 does not need to be the same as that of the first gate electrode 120 .

[0131] Next, a second gate insulating layer 210 is formed so as to cover the second semiconductor layer 201 (FIG. 5(D) )).

[0132] 6, the process of forming the region in which the second gate electrode 220 is to be formed is performed. 1 shows a cross section of a semiconductor memory device 1 that has been subjected to a formation process.

[0133] Next, a second interlayer film 250 is formed, and a region for forming a second gate electrode 220 is photolithographically defined. The etching process creates fine patterns. To form the insulating film, it is preferable to use a dry etching method (FIG. 6(A)).

[0134] A conductive layer 601 is formed so as to be embedded in the pattern formed above (FIG. 6(B)). The material of the conductive layer 601 only needs to be electrically conductive and adhesive to the second gate insulating layer 210. Low-resistance polysilicon or, for example, molybdenum, titanium, tantalum, copper, tungsten Metallic materials such as tin, aluminum, chromium, neodymium, scandium, etc., or The conductive layer 601 can be formed using an alloy material containing It may have a laminated structure.

[0135] Next, the conductive layer 601 is polished until at least the surface of the second gate insulating layer 210 is exposed. The second gate electrode 220 is formed by polishing the surface of the semiconductor substrate 210 (FIG. 6(C)). The polishing is performed by using, for example, a CMP method. By this polishing, polishing is performed until the surface of the second semiconductor layer 201 is exposed, Damage occurs in the second semiconductor layer 201, which causes deterioration of the electrical characteristics of the second transistor. Therefore, it is preferable to polish the conductive layer 601 so that the second gate insulating layer 210 remains. I wish.

[0136] 7, the process from exposing the second semiconductor layer 201 to forming the bit line 500 is performed. 1 shows a cross section of the semiconductor memory device 1.

[0137] The second gate insulating layer 210 is removed by dry etching to expose the second semiconductor layer 201. (Figure 7(A)).

[0138] Next, an insulating film 251 is formed. Next, the source region or drain region of the first transistor 100 is A conductive hole is formed to electrically connect the in-region 130 and the bit line 500. is filled with a conductive layer 600, e.g., aluminum, tungsten, copper, polysilicon, etc. The holes can then be filled with

[0139] Next, the bit line 500 is formed (FIG. 7(B)).

[0140] Through the above steps, the semiconductor memory device 1 can be manufactured.

[0141] In the semiconductor memory device, the first gate electrode is a source electrode or a drain electrode of the second transistor. The second semiconductor layer is formed so as to overlap the first gate electrode. Therefore, the source electrode and the drain electrode of the second transistor are The second semiconductor layer is sandwiched between the first and second transistors, and is disposed perpendicular to the substrate. For example, compared to planar type transistors, the area occupied can be made smaller. This makes it possible to provide a highly integrated semiconductor memory device.

[0142] In addition, the first gate electrode of the first transistor is used as one of the capacitance electrodes of the capacitor. This allows the area occupied by the capacitor to be reduced. A physical storage device can be provided.

[0143] (Embodiment 5) In this embodiment, a manufacturing method of a semiconductor memory device according to one embodiment of the present invention will be described.

[0144] The manufacturing process of the semiconductor memory device 2 shown in FIG. 2 will be described below with reference to FIGS. The cross-sectional views of the process correspond to the cross section taken along dashed line A2-B2 in the top view of the semiconductor memory device 2. The figure shows the state of the area after each process is performed. In this embodiment, the substrate is made of single crystal silicon. The following describes the case where the following materials are used: Embodiments 1 to 4 can be referred to.

[0145] As shown in FIG. 8, the source region and the drain region are doped with impurities after the step of forming the first gate electrode 120. The semiconductor memory device 2 in process has been doped and the conductive layer 600b has been formed. A cross section is shown.

[0146] Up to the step of forming the first gate electrode 120 (FIG. 8(A)), the fourth embodiment can be referred to. can.

[0147] After the first gate electrode 120 is formed, a channel region is formed in the region where the sidewall layer 140 is to be formed. The electrical resistance of the first region is lower than that of the second region, and higher than that of the source region and drain region. The impurity type to be doped is a desired impurity type for the first transistor 100. The selection can be made based on the conduction type (Figure 8(B)).

[0148] Next, the sidewall layer 140 is formed. The method of forming the sidewall layer 140 includes the following steps: For example, a silicon oxide film or a silicon nitride film is formed to cover the first gate electrode 120. Then, the surface is anisotropically etched, that is, etched back (FIG. 8). (C)).

[0149] Next, impurities are doped into the region for forming the source or drain. The source or drain region 130 is formed by diffusing the silicon in the region where the source or drain is to be formed. In this case, it is sufficient to inject impurities capable of forming a transistor of a desired conductivity type. This can be done by ion implantation or the like (FIG. 8(D)).

[0150] Next, a first interlayer film 150 is formed (FIG. 8(E)).

[0151] Next, the source region or drain region 130 of the first transistor 100 and the A conductive hole is formed to electrically connect the bit line 500 formed by the conductive layer 6 Fill with 00b. For example, use aluminum, tungsten, copper, polysilicon, etc. Then, the hole can be filled (FIG. 8(E)).

[0152] 9A to 9C show steps from the formation of the second capacitor electrode 320 to the formation of the insulating layer 152. In FIG.

[0153] The second capacitance electrode 320 is formed so as to be electrically connected to the first gate electrode 120. The conductive layer 321 is formed to be electrically connected to the conductive layer 600b. It is preferable to form the second capacitance electrode 320 from the same material.

[0154] Next, the capacitance layer 410 is formed so as to be in contact with the second capacitance electrode 320 (FIG. 9(A)).

[0155] Next, the first capacitance electrode 310b is formed so as to be in contact with the capacitance layer 410. The width and thickness of the first capacitance electrode 310b can be determined based on the capacitance required at b (see FIG. 9(B)).

[0156] Next, the insulating layer 151 and the insulating layer 152 are formed. The insulating layer 151 and the insulating layer 152 are made of an insulating material. For example, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, At this stage of the process, the insulating layer 151 or the insulating layer 152 may be formed. It is preferable to flatten the surface (FIG. 9(C)).

[0157] FIG. 10 shows the process from the formation of the second interlayer film 250 to the formation of the second gate insulating layer 210. The rear cross-sectional view is shown.

[0158] First, the second interlayer film 250 is formed, and an opening in the region where the second gate electrode 220 is to be formed is formed. (FIG. 10(A)) The opening is preferably formed by dry etching.

[0159] Next, the second gate electrode 220 is formed (FIG. 10(B)).

[0160] Next, an opening is formed in the region where the second semiconductor layer 201 is to be formed. The surface of 20 is exposed. The sidewalls of the opening become the gate insulating layer of the second transistor 200. Therefore, after the opening is formed, the second gate insulating layer 210 is formed on the side of the opening. The second gate insulating layer 210 is preferably formed by a CVD method or a sputtering method (FIG. 10(C)). The film can be formed by using a coating method or the like.

[0161] FIG. 11 shows a cross-sectional view of the semiconductor device after the steps from the formation of the second semiconductor layer 201 to the formation of the bit line 500 are performed. The surface view is shown.

[0162] The second semiconductor layer 201 is formed so as to be electrically connected to the second capacitance electrode 320. In particular, it is preferable to use an oxide semiconductor for the second semiconductor layer 201. The oxide semiconductor film is, for example, The insulating film 11 can be formed by a sputtering method (FIG. 11(A)).

[0163] Next, after forming an insulating film 251, the region overlapping with the second semiconductor layer 201 is removed by etching. At this time, the insulating film 251, the second interlayer film 250, the insulating layer 151 and the insulating layer 152 are removed. It is preferable to form an opening in a region overlapping with the conductive layer 321 (FIG. 11B).

[0164] Next, a conductive layer 600a is formed so as to be electrically connected to the conductive layer 321. A line 500 is formed in electrical contact with the second semiconductor layer 201 .

[0165] Through the above steps, the semiconductor memory device 2 can be manufactured.

[0166] In the semiconductor memory device, the first gate electrode is a source electrode or a drain electrode of the second transistor. The second semiconductor layer is formed so as to overlap the first gate electrode. Therefore, the source electrode and the drain electrode of the second transistor are The second semiconductor layer is sandwiched between the first and second transistors, and is disposed perpendicular to the substrate. For example, compared to planar type transistors, the area occupied can be made smaller. This makes it possible to provide a highly integrated semiconductor memory device.

[0167] The capacitor 300b has a second capacitance electrode 320 and a first capacitance electrode 310b as capacitance electrodes. Since the capacitor 300b is used as a single capacitor, the area occupied by the capacitor 300b can be reduced. As a result, a highly integrated semiconductor memory device can be provided.

[0168] (Embodiment 6) In this embodiment, the oxide semiconductor film described in any of Embodiments 1 to 5 can be used. In this paper, we describe a CAAC-OS film.

[0169] The crystals in the CAAC-OS film are each sized to fit within a cube with one side less than 100 nm. In addition, transmission electron microscope (TEM) The observation image of the CAAC-OS film shows that The boundary between the crystalline regions is not clear. It is not possible to confirm the exact grain boundary. The S film suppresses the decrease in electron mobility caused by grain boundaries.

[0170] The crystal parts included in the CAAC-OS film have, for example, a c-axis that is perpendicular to the normal to the surface on which the CAAC-OS film is formed. Aligned in a direction parallel to the line vector or the surface normal vector and perpendicular to the ab plane When viewed from the normal direction, the metal atoms are arranged in a triangular or hexagonal shape, and when viewed from the direction perpendicular to the c-axis, Metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. The directions of the a-axis and the b-axis may be different between the two. When describing it as straight, it is also in the range of 80° to 100°, preferably 85° to 95°. In addition, when simply describing it as parallel, it is -10° or more and 10° or less, and preferably This also includes the range of -5° to 5°.

[0171] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystals of the crystal parts in the impurity-added region are Sexuality may also decrease.

[0172] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The shape of the CAAC-OS film is Depending on the shape (cross-sectional shape of the surface to be formed or cross-sectional shape of the surface), In addition, the crystallization process such as heat treatment is performed when or after the film is formed. Therefore, the c-axis of the crystal part is The direction is aligned so as to be parallel to the normal vector of the surface on which the light is formed or the normal vector of the surface.

[0173] The electrical characteristics of transistors using CAAC-OS films change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0174] An example of a crystal structure contained in the CAAC-OS film will be described in detail with reference to FIGS. 12 to 15. In addition, unless otherwise specified, the upward direction in FIG. 12 to FIG. 15 is the c-axis direction, and The plane perpendicular to the direction is the ab plane. When simply referring to the upper half and lower half, the ab plane is used as the boundary. In addition, the circled O in Figure 12 indicates a 4-coordinate O. The double circled O indicates a three-coordinate O.

[0175] In Fig. 12(A), one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereafter referred to as 4) adjacent to the In atom are shown. The structure shown here has one metal atom and one nearby oxygen atom. The structure shown in Fig. 12(A) is an octahedral structure, but it is easy to For simplicity, the structure is shown in a plan view. There are three O atoms in each group that are 4-coordinated. The small group shown in Figure 12(A) has a zero charge.

[0176] In Figure 12(B), one pentagonal Ga atom and three trigonal oxygen atoms (hereafter referred to as 3 The structure shows a structure having a 4-coordinated O atom and two 4-coordinated O atoms adjacent to Ga. The 3-coordinated O atom is Both exist on the ab plane. There are four of them, one each in the upper and lower halves of Fig. 12(B). In addition, since In also has a 5-coordination, it can take the structure shown in Figure 12(B). The small group shown in FIG. 12(B) has a charge of 0.

[0177] FIG. 12(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The structure of Fig. 12(C) shows three tetracoordinate O atoms in the upper half and one tetracoordinate O atom in the lower half. The small group shown in FIG. 12(C) has a charge of 0.

[0178] FIG. 12(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The upper half of Figure 12(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 12(D) has a charge of +1.

[0179] Figure 12(E) shows a small group containing two Zn atoms. The upper half of Figure 12(E) shows one Zn atom. The small group shown in Figure 12(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0180] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a It's called the big group.

[0181] Here, we explain the rules for bonding these small groups together. The three Os in the bottom half have three adjacent Ins each in the downward direction, and the three Os in the bottom half have three adjacent Ins in the upward direction. Each has three adjacent In atoms. One O atom in the upper half of the five-coordinate Ga atom has one The lower half of the O has one adjacent Ga atom in the upward direction. The single O in the upper half has one adjacent Zn in the downward direction, and the three O in the lower half have Each has three adjacent Zn. Thus, the number of 4-coordinated O atoms above the metal atom and their The number of adjacent metal atoms below the O is equal, and the number of O atoms below the metal atom with four coordinates is equal. The number of adjacent metal atoms above the O is equal. Since O is 4-coordinated, The sum of the number of neighboring metal atoms and the number of neighboring metal atoms above is 4. Therefore, the metal atom The sum of the number of 4-coordinated O atoms above and the number of 4-coordinated O atoms below another metal atom is When there are four metal atoms, two small groups can bond together. For example, When a hexacoordinate metal atom (In or Sn) is bonded through a tetracoordinate O in the lower half, the tetracoordinate structure is Since there are three O atoms at the 5-coordinated positions, the metal atoms are 5-coordinated (Ga or In) and 4-coordinated (Z n).

[0182] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinate oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0183] Figure 13(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 13(B) shows a large group consisting of three medium groups. FIG. 13C shows the atomic arrangement when the layer structure of FIG. 13B is observed from the c-axis direction.

[0184] In FIG. 13(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate O atoms, as shown in the circle. Similarly, in FIG. 13(A), the upper and lower halves of In are Each has one 4-coordinate O atom, which is indicated by the circle 1. Similarly, in Figure 13 In (A), there is one tetracoordinate O in the lower half and three tetracoordinate O in the upper half. Zn with one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. This shows that:

[0185] In FIG. 13(A), the middle group, which is composed of an In-Sn-Zn-O system layer structure, is Sn has three tetracoordinate O atoms in the upper half and three in the lower half, and one tetracoordinate O atom in the upper half. The In is bonded to the In in the upper and lower halves of the Z atom, which has three tetracoordinate O atoms in the upper half. n, and three tetracoordinate O atoms are bonded to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. and In in the lower half, which is bonded to Zn2 with one 4-coordinated O in the upper half. It bonds to a small group of 4-coordinate O atoms in the lower half of this small group. The structure has three O atoms bonded to Sn atoms in the upper and lower halves. Multiple loops are combined to form large groups.

[0186] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6, respectively. 67, -0.5. For example, In (6 or 5 coordinates), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, a layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. The structure shown in Figure 1 shows a structure that can take a charge of -1. As shown in Figure 2(E), a small group of Zn-containing cations is included. For example, Sn-containing cations are If there is one small group with two Zn atoms per small group, the charges are cancelled out. Therefore, the total charge of the layer structure can be set to zero.

[0187] Specifically, the large group shown in FIG. 13(B) is repeated to form the In-Sn-Zn In-Sn-ZnO crystals (In2SnZn3O8) can be obtained. -The layered structure of the Zn-O system is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) In addition, the number m in the In-Sn-Zn-O system crystals is large. If the thickness is large, the crystallinity is improved, which is preferable.

[0188] In addition, there are oxides of four-component metals, such as In-Sn-Ga-Zn oxides and trimetallic oxides. In-Ga-Zn oxide (also written as IGZO), which is an oxide of the elemental metal, In- Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-C e-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm -Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb- Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Z n-type oxides, In-Tm-Zn-type oxides, In-Yb-Zn-type oxides, In-Lu-Zn In-Zn oxides, Sn-Zn oxides, and Al oxides are binary metal oxides. -Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and I The same applies when n-Ga based materials are used.

[0189] For example, Figure 14(A) shows a model diagram of the middle group that constitutes an In-Ga-Zn system layer structure. Shows.

[0190] In FIG. 14(A), the middle group, which constitutes an In-Ga-Zn-based layer structure, is In has three tetracoordinated O atoms in the upper and lower halves, and one tetracoordinated O atom in the upper half. It bonds to the Zn, and one tetracoordinate O is bonded to each of the three tetracoordinate Os in the lower half of the Zn. It bonds to Ga in the upper and lower halves through one tetracoordinate O in the lower half of the Ga. In this structure, three tetracoordinate O atoms are bonded to In atoms in the upper and lower halves. Multiple medium groups combine to form large groups.

[0191] Figure 14(B) shows a large group consisting of three medium groups. 14B is viewed from the c-axis direction.

[0192] Here, the charges of In (6 or 5 coordinates), Zn (4 coordinates), and Ga (5 coordinates) are Since the valence numbers are +3, +2, and +3, respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge will always be zero.

[0193] The middle group, which constitutes the In-Ga-Zn-based layer structure, is the middle group shown in FIG. Not limited to loops, large groups with different arrangements of In, Ga, and Zn Groups are also possible.

[0194] Specifically, the large group shown in FIG. 14(B) is repeated to form an In-Ga-Zn The In-Ga-Zn system crystals can be obtained. O3(ZnO) n (n is a natural number.)

[0195] In the case of n=1 (InGaZnO4), for example, the crystal structure shown in FIG. 15(A) can be obtained. In the crystal structure shown in FIG. 15(A), as explained in FIG. 12(B), Ga and Since Ga and In have a 5-coordination, a structure in which Ga is replaced by In is also possible.

[0196] In the case of n=2 (InGaZn2O5), for example, the crystal structure shown in FIG. 15(B) In the crystal structure shown in FIG. 15(B), as explained in FIG. Since Ga and In have five-coordinate groups, a structure in which Ga is replaced by In is also possible.

[0197] (Embodiment 7) In this embodiment, a configuration example of a semiconductor memory device according to one embodiment of the present invention will be described with reference to FIG. He explains.

[0198] FIG. 16 is a circuit diagram of a main part of a semiconductor memory device according to one embodiment of the present invention. The device includes a first transistor 1101, a second transistor 1102, and a capacitor 1103. Equipped with.

[0199] The semiconductor memory device includes a gate of a first transistor 1101 and a gate of a second transistor 1102. A node where the first electrode and one electrode of the capacitor 1103 are electrically connected (Retention node R).

[0200] A wiring S2 is electrically connected to the first electrode of the first transistor 1101, and a wiring S3 is electrically connected to the first electrode of the first transistor 1101. The wiring electrically connected to the electrode of the second transistor 1102 is called wiring D. The wiring connected to the first electrode is called wiring W1, and the wiring electrically connected to the second electrode is called wiring S1. The wiring electrically connected to the other electrode of the capacitor 1103 is designated as wiring W2.

[0201] When writing data to the semiconductor memory device, the second transistor 1102 is connected to the wiring W1 in the on state. A predetermined voltage is applied from the wiring S1 to the second electrode of the second transistor 1102. By inputting a potential, a predetermined potential can be written to the retention node R. When a potential that turns off the second transistor 1102 is input to the wiring W1, the holding node R The potential is held at this potential.

[0202] In addition, depending on the potential held at the holding node R, The first transistor 1101 is turned on or off. A potential for readout is input to one of the lines D, and the potential of the other line is detected. This can be done.

[0203] In this manner, when writing or erasing data to or from a semiconductor memory device according to one embodiment of the present invention, In this case, a voltage sufficient to turn on the second transistor 1102 is used. The voltage required to write to the node R is the on state of the first transistor 1101 or A voltage sufficient for controlling the off state is used. Unlike flash memory, it does not require high voltage to operate the storage device, so it consumes very little power. A semiconductor memory device with reduced power consumption can be realized.

[0204] Here, the second transistor 1102 uses silicon as a semiconductor in which a channel is formed. A transistor with reduced leakage current (off-state current) in the off state compared to a transistor with a Specifically, a silicon carbide semiconductor is used as the semiconductor in which the channel is formed. The transistor uses a semiconductor with a wider band gap than silicon. Compound semiconductors are semiconductors with a wide band gap, such as oxide semiconductors, nitride semiconductors, etc.

[0205] In particular, an oxide semiconductor is used as a semiconductor forming the channel of the second transistor 1102. It is preferable that

[0206] In this manner, a transistor with reduced off-state current is used as the second transistor 1102. By this, a semiconductor memory device capable of retaining stored contents even when power is not supplied is obtained. It is possible.

[0207] (Embodiment 8) In this embodiment, the semiconductor memory device disclosed in the above embodiment is used in at least a part thereof. A CPU (Central Processing Unit), which is an example of a semiconductor device, We will explain about this.

[0208] FIG. 17A is a block diagram showing a specific configuration of a CPU. The PU is provided on a substrate 1190 with an ALU 1191 (ALU: Arithmetic logic c unit, arithmetic circuit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, a register controller 1197, and a bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface 1189 (R The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 are provided on a separate chip. Of course, the CPU shown in FIG. 17(A) is merely an example showing a simplified configuration. In fact, actual CPUs have a wide variety of configurations depending on their applications.

[0209] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0210] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0211] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1. The internal clock signal CLK2 is generated by the internal clock generator 100. Supply to the seed circuit.

[0212] In the CPU shown in FIG. 17A, a register 1196 is provided with a memory cell. The memory cell of the register 1196 includes a logic element for inverting the logic (value) and a The present invention includes both of the disclosed semiconductor memory devices.

[0213] In the CPU shown in FIG. 17A, the register controller 1197 controls the ALU 1191. The holding operation in the register 1196 is selected according to the instruction from the register. In the memory cell of the data input device 1196, a logic element that inverts the logic (value) of the data input device is used. Select whether to hold the data in the logic (value) or to hold the data in the semiconductor memory device. When the logic element that inverts the A power supply voltage is supplied to the memory cell. If the semiconductor memory device is selected, the data in the register 1196 is rewritten. Therefore, the supply of the power supply voltage to the memory cells can be stopped.

[0214] Regarding the power supply shutdown, as shown in FIG. 17(B) or FIG. 17(C), A switching element is connected between the nodes to which the power supply potential VDD or VSS is applied. The circuit shown in FIG. 17B and FIG. 17C will be described below. Do the following.

[0215] In FIG. 17B and FIG. 17C, a resistor 1196 controls the supply of a power supply potential to the memory cell. The inverter is provided with a switching element for controlling the supply of power.

[0216] The register 1196 shown in FIG. 17B includes a switching element 1141 and a memory cell 11 42. Specifically, each memory cell 114 2 includes both a logic element that inverts the logic (value) and the semiconductor memory device. Each memory cell 1142 in the memory cell group 1143 is connected to a switching element 1141. A high-level power supply potential VDD is supplied to the memory cell group 1143. Each memory cell 1142 has a potential of the signal IN and a potential of the low-level power supply potential VSS. The rank is given.

[0217] In FIG. 17B, a transistor is used as the switching element 1141. The switching of the transistor is controlled by a signal SigA applied to its gate electrode. do.

[0218] In FIG. 17B, the switching element 1141 has only one transistor. However, there is no particular limitation and a plurality of transistors may be included. When the switching element 1141 has a plurality of transistors functioning as switching elements, The plurality of transistors may be connected in parallel or in series. Alternatively, a combination of series and parallel connections may be used.

[0219] In addition, in FIG. 17C, each memory cell 1142 included in the memory cell group 1143 is A low-level power supply potential VSS is supplied to the resistor 1141 through a switching element 1142. The switching element 1141 enables the memory cell group 1143. It is possible to control the supply of a low-level power supply potential VSS to each memory cell 1142 that corresponds to the Cut.

[0220] A switch is provided between the memory cell group and a node to which the power supply potential VDD or the power supply potential VSS is applied. When a switching element is installed to temporarily stop the CPU operation and cut off the supply of power voltage It is possible to retain data even in this state, and power consumption can be reduced. Specifically, for example, a user of a personal computer inputs information to an input device such as a keyboard. You can stop the CPU from operating while you are no longer entering information, which reduces power consumption. Power consumption can be reduced.

[0221] In addition, electronic devices that use such CPUs consume less power, so for example For example, a relatively small amount of power obtained from solar cells or non-contact power supply (also called wireless power supply) For example, electronic equipment can be operated satisfactorily even with a solar cell module or a non-contact A touch-feed module and a secondary battery ( The configuration will include a lithium-ion battery.

[0222] Here, we have taken the CPU as an example, but the same can also be said for DSP (Digital Signal Processor). processor), custom LSI, FPGA (Field Programmable Gauge It can also be applied to LSIs such as MOSFET's (MOSFET gate arrays).

[0223] (Embodiment 9) The semiconductor memory device disclosed in this specification is applicable to various electronic devices (including gaming machines). The electronic devices include display devices such as televisions and monitors, lighting devices, desktop A laptop or notebook type personal computer, a word processor, a DVD (Digit Still images or videos stored on a recording medium such as a Digital Versatile Disc (DV-1000) Image playback devices, portable CD players, radios, tape recorders, headphones Stereo, stereo, cordless telephone handset, transceiver, portable radio, mobile phone, automatic Car phones, portable game consoles, calculators, personal digital assistants, electronic organizers, electronic books, electronic translators, voice Input devices, video cameras, digital still cameras, electric shavers, microwave ovens, and other high-frequency devices Heating equipment, electric rice cookers, electric washing machines, vacuum cleaners, air conditioners and other air conditioning equipment , dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric coolers Freezers, freezers for storing DNA, smoke detectors, radiation detectors, medical equipment such as dialysis machines, etc. In addition, emergency lights, traffic lights, conveyor belts, elevators, escalators, Industrial robots, power storage systems, and other industrial equipment are also included. Electric motors are also used for vehicles propelled by electric motors using power from non-aqueous secondary batteries. The above-mentioned moving objects include, for example, electric vehicles (EVs), internal combustion engines (ICEs), and Hybrid vehicles (HEVs) that combine engines and electric motors, plug-in hybrid vehicles (PH EVs, tracked vehicles that use these tires and wheels as tracks, and original vehicles including electric-assist bicycles. Mobility-driven bicycles, motorcycles, electric wheelchairs, golf carts, small or large boats, submarines , helicopters, aircraft, rockets, satellites, space probes, interplanetary probes, and spacecraft. Specific examples of these electronic devices are shown in Figs. 18 and 19.

[0224] FIG. 18A shows a portable music player, which has a main body 3021 with a display unit 3023 and a a fixing portion 3022 for inserting the battery, a speaker, an operation button 3024, and an external memory slot 302 The semiconductor memory device and the semiconductor device exemplified in the above embodiment are By applying this to the memory and CPU built into the 3021, power consumption will be further reduced. It can be a portable music player.

[0225] Furthermore, the portable music player shown in FIG. 18(A) may be equipped with an antenna, a microphone function, and a wireless function. By linking it to a mobile phone, you can enjoy wireless hands-free driving while driving a car. Conversation is also possible.

[0226] FIG. 18B shows a computer, which includes a main body 9201 including a CPU, a housing 9202, a display unit 9203, keyboard 9204, external connection port 9205, pointing device 92 06, etc. This makes it possible to realize a computer with reduced power consumption.

[0227] In FIG. 19A, a television device 8000 includes a housing 8001 and a display unit 8002. It displays images on a display unit 8002 and outputs audio from a speaker unit 8003. The semiconductor memory device or the semiconductor device exemplified in the above embodiment can output the signal. The display unit 8002 may be used as a driver circuit for operating the display unit 8002 incorporated in the housing 8001. It is possible.

[0228] The display unit 8002 is a light-emitting device having light-emitting elements such as a liquid crystal display device or an organic EL element in each pixel. Device, electrophoretic display device, DMD (Digital Micromirror Device e) and PDP (Plasma Display Panel), It can be used.

[0229] The television device 8000 may include a receiver, a modem, and the like. The device 8000 can receive general television broadcasts using a receiver and also has a modem. By connecting to a wired or wireless communication network via Communication of information from one person to another (e.g., from sender to receiver) or two-way (e.g., between sender and receiver, or between receivers) It is also possible to do so.

[0230] The television device 8000 also includes a CPU and a memory for performing information communication. The television device 8000 may include the semiconductor memory device exemplified in the above embodiment, It is possible to use a semiconductor device such as a CPU.

[0231] In FIG. 19A, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is shown. is an example of an electrical device using a semiconductor device such as a CPU as exemplified in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CPU 8203, etc. In FIG. 19A, when the CPU 8203 is provided in the indoor unit 8200, However, the CPU 8203 may be provided in the outdoor unit 8204. The CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. By using the CPU illustrated in the above embodiment, an air conditioner with excellent power saving performance can be realized. This can be achieved.

[0232] In FIG. 19A, an electric refrigerator-freezer 8300 includes the CPU exemplified in the above embodiment. The semiconductor device is an example of an electric device including the semiconductor device. The device includes a housing 8301, a door for a refrigerator 8302, a door for a freezer 8303, a CPU 8304, and the like. In FIG. 19A, a CPU 8304 is provided inside a housing 8301. The semiconductor device such as the CPU illustrated in the above embodiment is used as the CPU 8304 of the electric refrigerator-freezer 8300. Its use can help save energy.

[0233] 19B and 19C show an example of an electric vehicle, which is an example of an electric device. The electric vehicle 9700 is equipped with a secondary battery 9701. The force is adjusted by the control circuit 9702 and supplied to the drive device 9703. The circuit 9702 is controlled by a processing device 9704 having a ROM, a RAM, a CPU, etc. (not shown). The semiconductor memory device and the semiconductor device such as the CPU exemplified in the above-mentioned embodiment are controlled by the power supply. By using the same in the processing unit 9704 of the automobile 9700, power saving can be achieved.

[0234] The driving device 9703 is a DC motor or an AC motor alone, or a motor and an internal combustion engine, The processing device 9704 is configured by combining the above. Information on driving (such as acceleration, deceleration, stopping, etc.) and information on driving (such as uphill and downhill slopes, Based on input information (load information, etc.), a control signal is output to the control circuit 9702. 9702 controls the power supplied from the secondary battery 9701 in response to a control signal from the processor 9704. The energy is adjusted to control the output of the drive unit 9703. If an AC motor is installed, In this case, although not shown, an inverter for converting direct current to alternating current is also built in.

[0235] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. can be done. [Explanation of symbols]

[0236] 1. Semiconductor memory device 2. Semiconductor memory device 3. Semiconductor memory device 10 Memory Cells 20 memory cells 30 memory cells 100 First transistor 101 First semiconductor layer 105 1st word line 106 Second Word Line 110 First gate insulating layer 120 First gate electrode 130 Source or drain region 150 First interlayer film 151 Insulating layer 152 Insulating layer 200 Second transistor 201 Second semiconductor layer 210 Second gate insulating layer 220 Second gate electrode 250 Second Interlayer Film 251 Insulating film 300a capacitor 300b capacitor 300c capacitor 310a 1st capacitor electrode 310b 1st capacitor electrode 310c 1st capacitor electrode 320 2nd capacitor electrode 321 Conductive Layer 410 capacitive layer 500 bit lines 700 Insulation Layer 600 Conductive layer 600a conductive layer 600b conductive layer 601 Conductive layer 1101 First transistor 1102 Second transistor 1103 Capacitor 1141 Switching element 1142 Memory Cell 1143 Memory Cell Group 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 3021 Main unit 3022 Fixed part 3023 Display section 3024 Operation button 3025 External Memory Slot 8000 Television Equipment 8001 Case 8002 Display section 8003 Speaker section 8200 indoor unit 8201 Case 8202 Ventilator 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Case 8302 Refrigerator door 8303 Freezer door 8304 CPU 9201 Main unit 9202 Case 9203 Display section 9204 Keyboard 9205 External connection port 9206 Pointing Device 9700 Electric Vehicle 9701 Secondary battery 9702 Control circuit 9703 Drive unit 9704 Processing Equipment

Claims

[Claim 1] a memory cell including a first transistor, a second transistor, and a capacitor; the first transistor has a first semiconductor layer, a first gate insulating layer in contact with the top of the first semiconductor layer, a first gate electrode in contact with the first gate insulating layer and overlapping with the first semiconductor layer, and a source region and a drain region provided to sandwich a region of the first semiconductor layer overlapping with the first gate electrode; the second transistor includes a second semiconductor layer disposed so as to overlap the first gate electrode and electrically connected to the first gate electrode, a second gate insulating layer in contact with a side surface of the second semiconductor layer, and a second gate electrode in contact with the second gate insulating layer and formed so as to cover at least a portion of the side surface of the second semiconductor layer; The capacitor includes a capacitance layer in contact with a side surface of the first gate electrode, and a first capacitance electrode in contact with the capacitance layer and formed so as to cover at least a portion of the side surface of the first gate electrode.

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