Semiconductor drive circuit

Abstract

To provide a semiconductor drive circuit capable of realizing soft shutdown with a simple configuration.SOLUTION: A semiconductor drive circuit 100 for driving a semiconductor element includes a control circuit 110 for inputting an input signal, and generating a set signal and a reset signal based on the input signal. Furthermore, the semiconductor drive circuit 100 includes a drive signal circuit 120 for turning on a drive signal of the semiconductor element according to a rising edge of the set signal and turning off the drive signal according to a rising edge of the reset signal. Furthermore, the semiconductor drive circuit 100 includes a soft cut-off circuit 130 for performing soft turn-off of the drive signal of the semiconductor element more gradually than the turn off of the drive signal by the drive signal circuit 120 according to the rising edges of the set signal and the reset signal when the set signal and the reset signal are turned on simultaneously.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor driver circuit. [Background technology]

[0002] Conventionally, in a device that uses power semiconductor elements to control a load such as a motor, there is a technology related to a power module that incorporates the power semiconductor elements and an integrated circuit chip that controls them in a single package. When an abnormality such as an overcurrent or short circuit occurs at the output terminal of this power module, a technology has been proposed that protects the power module by transmitting an abnormality detection signal inside the power module and performing a cutoff (turn-off) process of the output element. Patent Document 1 discloses a semiconductor device drive circuit. The semiconductor device drive circuit disclosed in Patent Document 1 cuts off the semiconductor switching element slowly by gradually lowering the gate voltage of the semiconductor switching element when an error occurs, thereby providing short-circuit protection. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 098624 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device drive circuit disclosed in Patent Document 1, the error signal detected by the desaturation voltage detection circuit needs to be level-shifted to a high-potential error signal by the second level shift main circuit. However, a level shift circuit such as the second level shift main circuit generally requires many semiconductor elements, which increases the circuit size.

[0005] The present invention has been made in view of the problems inherent in the conventional technology, and an object of the present invention is to provide a semiconductor driver circuit capable of realizing a soft shutdown with a simple configuration. [Means for solving the problem]

[0006] A semiconductor driving circuit according to an embodiment of the present invention is a semiconductor driving circuit for driving a semiconductor element, and includes a control circuit that receives an input signal and generates a set signal and a reset signal based on the input signal, a driving signal circuit that turns on the driving signal for the semiconductor element in response to a rising edge of the set signal and turns off the driving signal in response to the rising edge of the reset signal, and a soft shutoff circuit that, when the set signal and the reset signal are turned on simultaneously, softly turns off the driving signal for the semiconductor element in response to the rising edges of the set signal and the reset signal more gradually than when the driving signal circuit turns off the driving signal. Effect of the Invention

[0007] According to the present invention, it is possible to provide a semiconductor driver circuit capable of realizing soft shutdown with a simple configuration. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a configuration of a semiconductor driving circuit according to the first embodiment. [Diagram 2] FIG. 2 is a timing chart for explaining the operation of the semiconductor driving circuit according to the first embodiment. [Diagram 3] FIG. 3 is a circuit diagram showing an outline of a control circuit provided in the semiconductor drive circuit according to the first embodiment. [Figure 4] FIG. 4 is a timing chart for explaining the operation of the control circuit provided in the semiconductor drive circuit according to the first embodiment. [Diagram 5] FIG. 5 is a diagram showing a configuration of a semiconductor driving circuit according to the second embodiment. [Figure 6]FIG. 6 is a circuit diagram showing an outline of a control circuit provided in the semiconductor drive circuit according to the second embodiment. [Figure 7] FIG. 7 is a timing chart for explaining the operation of the control circuit provided in the semiconductor drive circuit according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a semiconductor driver circuit 100 according to some embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts in the driver circuit according to each embodiment will be denoted by the same reference numerals and the description thereof will be omitted.

[0010] (First embodiment) Fig. 1 is a diagram showing the configuration of a semiconductor drive circuit 100 according to a first embodiment. The semiconductor drive circuit 100 according to this embodiment is a device that drives a load (three-phase motor 300). In the example shown in Fig. 1, the configuration of the semiconductor drive circuit 100 that controls the power supplied from a power source 400 to a U terminal of the three-phase motor 300 is shown. Note that the semiconductor drive circuit 100 that supplies power to the V terminal and W terminal has the same configuration as the circuit shown in Fig. 1, and therefore will not be shown or described here.

[0011] The semiconductor driving circuit 100 includes a high-side semiconductor element QH, a low-side semiconductor element QL, a high-side driving IC chip HSDIC, and a low-side driving IC chip LSDIC. The semiconductor driving circuit 100 operates based on a control signal from a control IC 200. In this embodiment, the high-side semiconductor element QH and the low-side semiconductor element QL are power semiconductor elements, and the gate terminals are connected to the high-side driving IC chip HSDIC and the low-side driving IC chip LSDIC, respectively. The power semiconductor elements may be, for example, IGBTs (Insulated Gate Bipolar Transistors). In this embodiment, the high-side semiconductor element QH corresponds to a semiconductor element.

[0012] The control IC 200 is a circuit that controls the semiconductor driver circuit 100, and transmits control signals to the high side driver IC chip HSDIC and the low side driver IC chip LSDIC. The control IC 200 also acquires information about anomalies transmitted from the low side driver IC chip LSDIC, and transmits the information to the high side driver IC chip HSDIC. In the first embodiment, the transmission of abnormality information to the high side driver IC chip HSDIC is performed by an alert signal Alert. The high side driver IC chip HSDIC and the low side driver IC chip LSDIC are driven by power supplied to power supply terminals VCCHU and VCCL, respectively.

[0013] The semiconductor driver circuit 100 controls the three-phase motor 300 by sending drive signals from the high-side driver IC chip HSDIC and the low-side driver IC chip LSDIC to the gates of the high-side semiconductor element QH and the low-side semiconductor element QL.

[0014] The high side drive IC chip HSDIC includes a control circuit 110 in the low voltage domain LA, and includes a level shifter, a drive signal circuit 120, and a soft cutoff circuit 130 in the high voltage domain HA. The high side drive IC chip HSDIC and the low side drive IC chip LSDIC may be integrated into one chip, or the high side and low side may be configured on separate chips.

[0015] 1, the low side driver IC chip LSDIC includes a low side control circuit 141 and a low side driver circuit 142 for driving the low side semiconductor element QL. The low side driver IC chip LSDIC also includes a semiconductor element 143 and a comparator 144 for transmitting information related to an abnormality detected at the current detection terminal sense to the control IC 200.

[0016] The control circuit 110 receives an input signal HIN and generates a set signal Set and a reset signal Reset based on the input signal HIN. The control circuit 110 also receives an alert signal Alert from the control IC 200, and when the alert signal Alert is on, turns on the set signal Set and the reset signal Reset simultaneously. Note that in this embodiment, the simultaneous on of the set signal Set and the reset signal Reset is not limited to a timing at which the set signal Set and the reset signal Reset are completely on at the same time. For example, as long as the timing is such that the drive signal circuit 120 and the soft cutoff circuit 130 described later detect that the set signal Set and the reset signal Reset are turned on at the same time, a small time difference may be included in the timing of the simultaneous on of the set signal Set and the reset signal Reset.

[0017] The drive signal circuit 120 turns on the drive signal HO for the high-side semiconductor element QH in response to a rising edge of the set signal Set, and turns off the drive signal HO in response to a rising edge of the reset signal Reset. Furthermore, the drive signal circuit 120 turns off the drive signal HO when the set signal Set and the reset signal Reset are simultaneously turned on. In this specification, turning off the drive signal HO by the drive signal circuit 120 may be referred to as a "normal turn off" to distinguish it from a soft turn off, which will be described later.

[0018] The soft shutdown circuit 130 generates a drive signal HO for soft-shutdown of the high-side semiconductor element QH in response to the rising edges of the set signal Set and the reset signal Reset. Specifically, when the set signal Set and the reset signal Reset are simultaneously turned on, the soft shutdown circuit 130 generates a drive signal HO for soft-shutdown of the high-side semiconductor element QH. That is, when the set signal Set and the reset signal Reset are simultaneously turned on, the soft shutdown circuit 130 soft-turns off the drive signal HO in response to the rising edges of the set signal Set and the reset signal Reset. This soft turn-off by the soft shutdown circuit 130 turns off the drive signal HO more gently than when the drive signal circuit 120 turns off the drive signal HO.

[0019] In this embodiment, the time required for soft turn-off is at least three times longer than the time required for turning off the drive signal HO by the drive signal circuit 120. Note that the embodiment in which the time required for soft turn-off is at least three times longer than the time required for turning off by the drive signal circuit 120 does not limit the configuration of this embodiment. For example, the configuration may be such that the time required for soft turn-off is about three to ten times longer than the time required for turning off by the drive signal circuit 120.

[0020] Furthermore, when the set signal Set and the reset signal Reset are simultaneously turned on, as described above, the drive signal HO is turned off normally by the drive signal circuit 120 and softly turned off by the soft cutoff circuit 130. In this case, since the soft turn-off requires at least three times the time of the normal turn-off operation, the gate voltage of the high-side semiconductor element QH is actually cut off when the soft turn-off is completed.

[0021] FIG. 2 is a timing chart for explaining the operation of the semiconductor driver circuit 100 according to the first embodiment.

[0022] First, in the normal turn-on operation shown in period T1 (time t1 to time t3) in FIG. 2, the control circuit 110 generates a set signal Set in response to the rising edge of the high-side input signal HIN (time t2). The set signal Set generated by the control circuit 110 is level-shifted and transmitted to the drive signal circuit 120 and the soft shutoff circuit 130. Based on the transmitted set signal Set, the drive signal circuit 120 transitions the drive signal HO, which is the gate drive signal for the high-side semiconductor element QH, from "L" (off) to "H" (on) (time t2 to time t3). Note that the soft shutoff circuit 130 does not perform soft turn-off processing at time t2 because the reset signal Reset is off at this timing.

[0023] 2 (time t4 to time t6), the normal turn-off operation is performed as follows: the control circuit 110 generates a reset signal Reset in response to the falling edge of the input signal HIN (time t5). The reset signal Reset generated by the control circuit 110 is level-shifted and transmitted to the drive signal circuit 120. Based on the transmitted reset signal Reset, the drive signal circuit 120 transitions the drive signal HO, which is the gate drive signal for the high-side semiconductor element QH, from "H" (on) to "L" (off) (time t5 to time t6). Note that the soft shutoff circuit 130 does not perform soft turn-off processing at time t2 because the set signal Set is off at this timing.

[0024] Next, a description will be given of the operation of the semiconductor driver circuit 100 when an abnormality occurs during the period T3 (time t10 to time t14) in Fig. 2. When an abnormality such as an overcurrent occurs in the high-side semiconductor element QH or the low-side semiconductor element QL, which are the output elements of the semiconductor driver circuit 100, the overcurrent is detected by the current detection terminal sense of the low-side semiconductor element QL.

[0025] The current detection terminal SENSE transmits an abnormality to the low side driver IC chip LSDIC, and information indicating the abnormality is transmitted to the control IC 200 from the abnormality detection output terminal FO of the low side driver IC chip LSDIC.

[0026] Thereafter, based on the information transmitted from the abnormality detection output terminal FO, the control IC 200 transmits an abnormality detection signal in the form of the abnormality detection signal terminal (alert signal Alert) of the high side drive IC chip HSDIC transitioning from “L” to “H”.

[0027] The control circuit 110 generates signal pulses for both the set signal Set and the reset signal Reset at the same time at the rising edge of the alert signal Alert. Both the set signal Set and the reset signal Reset are level-shifted and transmitted to the drive signal circuit 120 and the soft shutoff circuit 130.

[0028] The soft shutoff circuit 130 transitions from "H" (ON) to "L" (OFF) with a gradual fall such that the device is turned off more slowly than usual based on the set signal Set and the reset signal Reset (time t13 to time t14). Furthermore, the drive signal circuit 120 transitions the drive signal HO of the high side semiconductor element QH from "H" (ON) to "L" (OFF) at the normal timing based on the reset signal Reset. Here, the drive signal HO is transitioned to "L" (OFF) by the drive signal circuit 120 and the soft shutoff circuit 130, but is transitioned gently from "H" (ON) to "L" (OFF) by the soft shutoff circuit 130.

[0029] In this way, when an abnormality occurs, the semiconductor driver circuit 100 softly turns off the drive signal HO for the high side semiconductor element QH, thereby softly shutting down the high side semiconductor element QH and reducing the surge voltage that occurs at the output terminal when the element is cut off.

[0030] 3 is a schematic circuit diagram of a control circuit 110 provided in the semiconductor driver circuit 100 according to the first embodiment. As shown in FIG 3, the control circuit 110 includes a pulse generating unit 111, a set signal generating circuit 112a, and a reset signal generating circuit 112b.

[0031] The pulse generating unit 111 generates a pulse set signal P_Set, a pulse alert signal P_Alert, and a pulse reset signal P_Reset based on the input signal HIN and the alert signal Alert.

[0032] The set signal generating circuit 112a generates the set signal Set based on the pulse set signal P_Set or the pulse alert signal P_Alert. Specifically, as shown in Fig. 3, the set signal generating circuit 112a is configured with a logical sum circuit, and generates the set signal Set by the logical sum of the pulse set signal P_Set and the pulse alert signal P_Alert.

[0033] The reset signal generating circuit 112b generates a reset signal Reset based on the pulse reset signal P_Reset or the pulse alert signal P_Alert. Specifically, as shown in Fig. 3, the reset signal generating circuit 112b is configured with a logical sum circuit, and generates the reset signal Reset by logical summing the pulse reset signal P_Reset and the pulse alert signal P_Alert.

[0034] FIG. 4 is a timing chart for explaining the operation of the control circuit 110 provided in the semiconductor driver circuit 100 according to the first embodiment.

[0035] In response to the rising edge of the input signal HIN at time t1 in Fig. 4, the pulse generating section 111 generates a pulse set signal P_Set. Furthermore, the set signal generating circuit 112a outputs a set signal Set in response to the pulse set signal P_Set.

[0036] In response to the falling edge of the input signal HIN at time t2 in Fig. 4, the pulse generating section 111 generates a pulse reset signal P_Reset. Furthermore, the reset signal generating circuit 112b outputs a reset signal Reset in response to the pulse reset signal P_Reset.

[0037] The operation based on the rising edge of the input signal HIN at time t3 in FIG. 4 is the same as the operation at time t1 described above, and therefore a description thereof will be omitted here.

[0038] In response to the rising edge of the alert signal Alert at time t4 in Fig. 4, the pulse generating unit 111 generates a pulse alert signal P_Alert. In addition, the set signal generating circuit 112a and the reset signal generating circuit 112b output a set signal Set and a reset signal Reset in response to the pulse alert signal P_Alert.

[0039] As described above, the semiconductor driver circuit 100 according to the first embodiment is a semiconductor driver circuit 100 for driving a semiconductor element. The semiconductor driver circuit 100 includes a control circuit 110 that receives an input signal HIN and generates a set signal and a reset signal based on the input signal HIN. The semiconductor driver circuit 100 also includes a drive signal circuit 120 that turns on the drive signal of the semiconductor element in response to a rising edge of the set signal and turns off the drive signal in response to a rising edge of the reset signal. The semiconductor driver circuit 100 also includes a soft shutoff circuit 130 that softly turns off the drive signal of the semiconductor element in response to the rising edges of the set signal and the reset signal when the set signal and the reset signal are simultaneously turned on. The soft shutoff circuit 130 also softly turns off the drive signal of the semiconductor element more gently than the drive signal circuit 120 turns off the drive signal.

[0040] This eliminates the need for a level shifter that shifts the voltage of the abnormality detection signal to a high voltage, making it possible to reduce the size of the circuit. That is, the semiconductor driver circuit 100 according to the first embodiment can achieve soft shutdown with a simple configuration.

[0041] Furthermore, the time required for soft turn-off by the soft shutoff circuit 130 of the semiconductor driver circuit 100 may be at least three times longer than the time required for turning off the drive signal by the drive signal circuit 120. This enables the semiconductor driver circuit 100 to gently shut off the semiconductor element, thereby making it possible to reduce the surge voltage generated at the output terminal when the semiconductor element is shut off.

[0042] Furthermore, the control circuit 110 of the semiconductor driver circuit 100 may receive an alert signal Alert, and when the alert signal Alert is on, turn on the set signal Set and the reset signal Reset simultaneously. This eliminates the need for the semiconductor driver circuit 100 to provide a path for the alert signal from the control circuit 110 to the drive signal circuit 120 and the soft shutdown circuit 130. In other words, the semiconductor driver circuit 100 does not need to provide a level shifter that shifts the level of the alert signal to a high voltage, making it possible to reduce the size of the circuit.

[0043] Furthermore, the control circuit 110 may include a pulse generating unit 111 that generates a pulse set signal P_Set, a pulse alert signal P_Alert, and a pulse reset signal P_Reset based on the input signal HIN and the alert signal Alert. The control circuit 110 may also include a set signal generating circuit 112a that generates a set signal Set based on the pulse set signal P_Set or the pulse alert signal P_Alert. The control circuit 110 may also include a reset signal generating circuit 112b that generates a reset signal Reset based on the pulse reset signal P_Reset or the pulse alert signal P_Alert. This allows the semiconductor drive circuit 100 to configure a circuit that simultaneously turns on the set signal Set and the reset signal Reset in response to the rising edge of the alert signal Alert with a simple configuration, thereby making it possible to reduce the size of the semiconductor drive circuit 100.

[0044] Second Embodiment As described above, one specific embodiment has been described, but the above-mentioned embodiment is merely an example and is not intended to limit the embodiments. For example, in the above-mentioned embodiment, a form in which both the set signal Set and the reset signal Reset are simultaneously raised based on the alert signal Alert input from the control IC 200 has been exemplified.

[0045] Here, we will further explain the configuration of the semiconductor driver circuit 100 according to the second embodiment, which applies a pulse wave that changes between on, off, and on at intervals shorter than the filter time constant of the filter circuit 113 to the input signal HIN when an abnormality is detected, and which differs from the first embodiment.

[0046] 5 is a diagram showing the configuration of a semiconductor driving circuit 100 according to a second embodiment. The semiconductor driving circuit 100 according to the second embodiment differs from the configuration of the semiconductor driving circuit 100 according to the first embodiment shown in FIG. 1 in that there is no alert signal Alert transmitted from the control IC 200 to the semiconductor driving circuit 100.

[0047] Fig. 6 is a schematic circuit diagram of a control circuit 110 provided in a semiconductor driver circuit 100 according to a second embodiment. As shown in Fig. 6, the control circuit 110 according to the second embodiment includes a filter circuit 113, a first pulse converter circuit 114a, a second pulse converter circuit 114b, a third pulse converter circuit 114c, and a logical OR circuit 112c. The control circuit 110 according to the second embodiment also includes a TFF circuit 115, a first DFF circuit 116a, a second DFF circuit 116b, a set signal generating circuit 112e, and a reset signal generating circuit 112d.

[0048] The filter circuit 113 performs a filter process on the input signal HIN for a predetermined time. Generally, in order to eliminate the influence of noise and the like, a drive signal to a power module such as a high-side semiconductor element QH undergoes a filter process, is delayed, and then outputs a set signal Set or a reset signal Reset. Therefore, if the signal input to the filter circuit 113 changes from "H" to "L" to "H" in a time shorter than the time constant of the filter circuit 113, a pulse waveform after the filter process is not generated, thereby making it possible to prevent malfunction due to a noise waveform.

[0049] The process in the filter circuit 113 will be specifically described with reference to the timing chart of Fig. 7. Fig. 7 is a timing chart for describing the operation of the semiconductor drive circuit 100 according to the second embodiment. In response to the rising edge of the input signal HIN at time t1 in Fig. 7, a second pulse set signal P2_Set is generated at the timing of time t2 via the filter circuit 113 and a second pulse conversion circuit 114b described later. Similarly, in response to the falling edge of the input signal HIN at time t3 in Fig. 7, a second pulse reset signal P2_Reset is generated at the timing of time t4 via the filter circuit 113 and a second pulse conversion circuit 114b described later.

[0050] As shown in FIG. 7, the second pulse set signal P2_Set and the second pulse reset signal P2_Reset generated via the filter circuit 113 and the second pulse conversion circuit 114b are generated with a predetermined time delay.

[0051] On the other hand, as shown from time t8 to time t9 in Fig. 7, when the input signal HIN input to the filter circuit 113 changes from "H" to "L" to "H" in a period shorter than the filter time constant (period (i) in the figure), the signal is processed in the same manner as noise removal. That is, in response to the change in the input signal HIN from time t8 to time t9, the second pulse set signal P2_Set and the second pulse reset signal P2_Reset are not generated, as shown by "x" in Fig. 7.

[0052] In addition, in the control circuit 110 of the semiconductor drive circuit 100 according to the second embodiment, the input signal HIN is also used as a signal converted into a pulse by the first pulse conversion circuit 114a without passing through the filter circuit 113. As a result, the semiconductor drive circuit 100 according to the second embodiment can make the semiconductor drive circuit 100 recognize the pulse waveform input of the input signal HIN for a very short time as described above as a signal at the time of abnormality detection. That is, the semiconductor drive circuit 100 according to the second embodiment can reduce the size of the circuit by not using a dedicated signal (terminal) at the time of abnormality detection. Also, in a high-voltage power module, there is a problem of ensuring an insulation distance, and there are cases where the number of terminals that can be installed on the power module is limited. In such a situation, there are cases where it is not possible to install a terminal for transmitting abnormality detection, and the configuration of the semiconductor drive circuit 100 according to the second embodiment can be utilized.

[0053] The first pulse conversion circuit 114a outputs a first pulse set signal P1_Set in response to a rising edge of the input signal HIN, and outputs a first pulse reset signal P1_Reset in response to a falling edge of the input signal HIN.

[0054] The second pulse conversion circuit 114b outputs a second pulse set signal P2_Set in response to a rising edge of the output signal of the filter circuit 113, and outputs a second pulse reset signal P2_Reset in response to a falling edge of the output signal of the filter circuit 113.

[0055] The logical sum circuit 112c outputs a logical sum signal C of the first pulse reset signal P1_Reset and the second pulse reset signal P2_Reset.

[0056] The TFF circuit 115 (TFF: toggle flip-flop) inverts the on / off state of the TFF output signal TO in response to the rising edge of the logical sum signal C.

[0057] The first DFF circuit 116a (DFF: delay flip-flop) delays the TFF output signal TO in response to the rising edge of the first pulse set signal P1_Set, and outputs the first delay signal DO1.

[0058] The second DFF circuit 116b delays the first delayed signal DO1 in response to the rising edge of the first pulse reset signal P1_Reset, and outputs the second delayed signal DO2.

[0059] The third pulse conversion circuit 114c generates a pulse alert signal P_Alert in response to the rising edge of the second delay signal DO2.

[0060] The reset signal generating circuit 112d generates a reset signal Reset based on the second pulse reset signal P2_Reset or the pulse alert signal P_Alert. That is, the reset signal generating circuit 112d is configured with a logical sum circuit, similar to the reset signal generating circuit 112b of the semiconductor driving circuit 100 according to the first embodiment. That is, the reset signal generating circuit 112d generates the reset signal Reset by logical summing the second pulse reset signal P2_Reset and the pulse alert signal P_Alert.

[0061] The set signal generating circuit 112e generates the set signal Set based on the second pulse set signal P2_Set or the pulse alert signal P_Alert. That is, the set signal generating circuit 112e is configured of a logical sum circuit, similar to the set signal generating circuit 112a of the semiconductor driving circuit 100 according to the first embodiment. That is, the set signal generating circuit 112e generates the set signal Set by the logical sum of the second pulse set signal P2_Set and the pulse alert signal P_Alert.

[0062] As described above, in the second embodiment, the input signal HIN is a signal to which a pulse wave (pulse signal) that changes between on, off, and on in a time shorter than the time constant of the filter circuit 113 is applied when an abnormality is detected in the semiconductor drive circuit 100.

[0063] That is, in the second embodiment, the control IC 200 transmits information regarding an abnormal state by applying a pulse signal having a duration shorter than the time constant of the filter circuit 113 to the input signal HIN based on the information transmitted via the abnormality detection output terminal FO.

[0064] FIG. 7 is a timing chart for explaining the operation of the semiconductor driving circuit 100 according to the second embodiment.

[0065] At time t1 in Fig. 7, the first pulse set signal P1_Set is generated in the first pulse conversion circuit 114a in response to the rising edge of the input signal HIN. At time t2, the second pulse set signal P2_Set is generated via the filter circuit 113 and the second pulse conversion circuit 114b. As shown at times t1 and t2 in Fig. 7, the second pulse set signal P2_Set is generated with a delay from the first pulse set signal P1_Set by the delay amount in the filter circuit 113. In the example shown in Fig. 7, the delay time in the filter circuit 113 is diagrammatically indicated by a rectangle with a diagonal line pattern.

[0066] Furthermore, at time t2, in response to the second pulse set signal P2_Set, the set signal generating circuit 112e generates the set signal Set, and the drive signal HO is turned on.

[0067] 7, in response to the falling edge of the input signal HIN, a first pulse reset signal P1_Reset (time t3) and a second pulse reset signal P2_Reset (time t4) are generated. Note that, like the second pulse set signal P2_Set, the second pulse reset signal P2_Reset is generated with a delay from the first pulse reset signal P1_Reset by the amount of delay in the filter circuit 113.

[0068] Furthermore, at time t4, the reset signal generation circuit 112d generates the reset signal Reset in response to the second pulse reset signal P2_Reset, and the drive signal HO is turned off normally.

[0069] A turn-on process is performed at times t5 and t6 in Fig. 7. This turn-on process is the same as the turn-on process at times t1 and t2 described above, and therefore a description thereof will be omitted here.

[0070] An abnormality is detected at time t7 in Fig. 7, and at times t8 and t9, a pulse signal (pulse wave) of period (i) is applied to the input signal HIN of the control IC 200. As described above, this period (i) is shorter than the time constant of the filter circuit 113. As a result, no pulse signal is generated in the second pulse conversion circuit 114b (see "x" in the figure). That is, at times t8 and t9, only the first pulse reset signal P1_Reset and the first pulse set signal P1_Set are generated by the first pulse conversion circuit 114a, respectively.

[0071] At time t8, the OR signal C is generated in the OR circuit 112c, and the TFF output signal TO is turned on in the TFF circuit 115. At time t9, in the first DFF circuit 116a, the TFF output signal TO is delayed by the first pulse set signal P1_Set and output as the first delayed signal DO1.

[0072] At time t10, in the second DFF circuit 116b, the first delay signal DO1 is delayed by the first pulse reset signal P1_Reset, and the second delay signal DO2 is turned on. In response to the rising edge of the second delay signal DO2, the third pulse conversion circuit 114c generates a pulse alert signal P_Alert and inputs it to the set signal generation circuit 112e and the reset signal generation circuit 112d.

[0073] At time t10, the set signal Set and the reset signal Reset are simultaneously turned on, so that a soft turn-off is performed by the soft shutoff circuit 130 in the period from time t11 to time t12, similar to the semiconductor drive circuit 100 of the first embodiment.

[0074] As described above, in the semiconductor driver circuit 100 according to the second embodiment, the control circuit 110 may include a filter circuit 113 that performs a filter process on the input signal HIN for a predetermined time. The control circuit 110 may also include a first pulse conversion circuit 114a that outputs a first pulse set signal P1_Set in response to a rising edge of the input signal HIN and outputs a first pulse reset signal P1_Reset in response to a falling edge of the input signal HIN. The control circuit 110 may also include a second pulse conversion circuit 114b. The second pulse conversion circuit 114b outputs a second pulse set signal P2_Set in response to a rising edge of the output signal of the filter circuit 113 and outputs a second pulse reset signal P2_Reset in response to a falling edge of the output signal of the filter circuit 113. The control circuit 110 may also include a logical OR circuit 112c that outputs a logical OR signal C of the first pulse reset signal P1_Reset and the second pulse reset signal P2_Reset. The control circuit 110 may also include a TFF circuit 115 that inverts the on / off state of the TFF output signal TO in response to a rising edge of the OR signal C. The control circuit 110 may also include a first DFF circuit 116a that delays the TFF output signal TO in response to a rising edge of the first pulse set signal P1_Set to output a first delay signal DO1. The control circuit 110 may also include a second DFF circuit 116b that delays the first delay signal DO1 in response to a rising edge of the first pulse reset signal P1_Reset to output a second delay signal DO2. The control circuit 110 may also include a third pulse conversion circuit 114c that generates a pulse alert signal P_Alert in response to a rising edge of the second delay signal DO2. The control circuit 110 may also include a reset signal generation circuit 112d that generates a reset signal Reset based on the second pulse reset signal P2_Reset or the pulse alert signal P_Alert. The control circuit 110 may also include a set signal generating circuit 112e that generates the set signal Set based on the second pulse set signal P2_Set or the pulse alert signal P_Alert.Furthermore, the input signal HIN of the control circuit 110 may be a signal to which a pulse wave that changes between on, off, and on in a time shorter than the time constant of the filter circuit 113 is applied when an abnormality in the semiconductor drive circuit 100 is detected.

[0075] As a result, the semiconductor driver circuit 100 according to the second embodiment does not need to have a dedicated terminal for inputting the alert signal Alert, and the circuit can be made smaller. Also, in a high-voltage power module, there is a problem of ensuring insulation distance, and the number of terminals that can be installed on the power module may be limited. In such a situation, it may not be possible to install a terminal for transmitting an abnormality detection, and the configuration of the semiconductor driver circuit 100 according to the second embodiment can be utilized.

[0076] (Other embodiments) Although the embodiments have been described in detail with reference to the drawings, the present embodiments are not limited to the contents described in the above embodiments. The components described above include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the configurations described above can be appropriately combined. Various omissions, substitutions, or modifications of the configurations can be made without departing from the spirit of the embodiments.

[0077] In the above-described embodiment, a semiconductor driving device including the semiconductor driving circuit 100 and the control IC 200 is also included in the scope of this embodiment.

[0078] The features of the semiconductor driver circuit 100 will be described below.

[0079] The semiconductor driver circuit 100 according to the first embodiment is a semiconductor driver circuit 100 for driving a semiconductor element. The semiconductor driver circuit 100 includes a control circuit 110 that receives an input signal HIN and generates a set signal and a reset signal based on the input signal HIN. The semiconductor driver circuit 100 also includes a drive signal circuit 120 that turns on the drive signal of the semiconductor element in response to a rising edge of the set signal and turns off the drive signal in response to a rising edge of the reset signal. The semiconductor driver circuit 100 also includes a soft shutoff circuit 130 that softly turns off the drive signal of the semiconductor element in response to the rising edges of the set signal and the reset signal when the set signal and the reset signal are simultaneously turned on. The soft shutoff circuit 130 also softly turns off the drive signal of the semiconductor element more slowly than the drive signal circuit 120 turns off the drive signal.

[0080] With this configuration, the semiconductor driver circuit 100 does not need to include a level shifter that shifts the voltage of the abnormality detection signal to a high voltage, and the circuit size can be reduced. That is, the semiconductor driver circuit 100 according to the first embodiment can achieve soft shutdown with a simple configuration.

[0081] The time required for the soft turn-off by the soft cutoff circuit 130 of the semiconductor driver circuit 100 according to the second embodiment may be at least three times longer than the time required for the drive signal circuit 120 to turn off the drive signal.

[0082] This configuration enables the semiconductor driver circuit 100 to gently shut off the semiconductor element, thereby reducing the surge voltage generated at the output terminal when the semiconductor element is shut off.

[0083] The control circuit 110 of the semiconductor driver circuit 100 according to the third embodiment may receive an alert signal Alert, and when the alert signal Alert is on, turn on the set signal Set and the reset signal Reset simultaneously.

[0084] With this configuration, the semiconductor driver circuit 100 does not need to provide a path for the alert signal from the control circuit 110 to the drive signal circuit 120 and the soft shutoff circuit 130. In other words, the semiconductor driver circuit 100 does not need to provide a level shifter that shifts the voltage of the alert signal to a high voltage, making it possible to reduce the size of the circuit.

[0085] The control circuit 110 of the semiconductor driver circuit 100 according to the fourth aspect may include a pulse generating unit 111. The pulse generating unit 111 may generate a pulse set signal P_Set, a pulse alert signal P_Alert, and a pulse reset signal P_Reset based on the input signal HIN and the alert signal Alert. The control circuit 110 may also include a set signal generating circuit 112a that generates a set signal Set based on the pulse set signal P_Set or the pulse alert signal P_Alert. The control circuit 110 may also include a reset signal generating circuit 112b that generates a reset signal Reset based on the pulse reset signal P_Reset or the pulse alert signal P_Alert.

[0086] With this configuration, the semiconductor driver circuit 100 can configure a circuit that simultaneously turns on the set signal Set and the reset signal Reset in response to the rising edge of the alert signal Alert, with a simple configuration, thereby enabling a reduction in scale.

[0087] The control circuit 110 of the semiconductor driver circuit 100 according to the fifth embodiment may include a filter circuit 113 that performs a filter process on the input signal HIN for a predetermined time. The control circuit 110 may also include a first pulse conversion circuit 114a that outputs a first pulse set signal P1_Set in response to a rising edge of the input signal HIN and outputs a first pulse reset signal P1_Reset in response to a falling edge of the input signal HIN. The control circuit 110 may also include a second pulse conversion circuit 114b. The second pulse conversion circuit 114b outputs a second pulse set signal P2_Set in response to a rising edge of the output signal of the filter circuit 113 and outputs a second pulse reset signal P2_Reset in response to a falling edge of the output signal of the filter circuit 113. The control circuit 110 may also include a logical OR circuit 112c that outputs a logical OR signal C of the first pulse reset signal P1_Reset and the second pulse reset signal P2_Reset. The control circuit 110 may also include a TFF circuit 115 that inverts the on / off state of the TFF output signal TO in response to a rising edge of the OR signal C. The control circuit 110 may also include a first DFF circuit 116a that delays the TFF output signal TO in response to a rising edge of the first pulse set signal P1_Set to output a first delay signal DO1. The control circuit 110 may also include a second DFF circuit 116b that delays the first delay signal DO1 in response to a rising edge of the first pulse reset signal P1_Reset to output a second delay signal DO2. The control circuit 110 may also include a third pulse conversion circuit 114c that generates a pulse alert signal P_Alert in response to a rising edge of the second delay signal DO2. The control circuit 110 may also include a reset signal generation circuit 112d that generates a reset signal Reset based on the second pulse reset signal P2_Reset or the pulse alert signal P_Alert. The control circuit 110 may also include a set signal generating circuit 112e that generates the set signal Set based on the second pulse set signal P2_Set or the pulse alert signal P_Alert.Furthermore, the input signal HIN of the control circuit 110 may be a signal to which a pulse wave that changes between on, off, and on in a time shorter than the time constant of the filter circuit 113 is applied when an abnormality in the semiconductor drive circuit 100 is detected.

[0088] This configuration eliminates the need for a dedicated terminal for inputting the alert signal Alert in the semiconductor drive circuit 100, making it possible to miniaturize the circuit. Also, in high-voltage power modules, there is a problem of ensuring insulation distance, and the number of terminals that can be installed in the power module may be limited. In such a situation, it may not be possible to install a terminal for transmitting an abnormality detection, and the configuration of the semiconductor drive circuit 100 according to this embodiment can be utilized. [Explanation of symbols]

[0089] 100 Semiconductor driver circuit 110 Control circuit 111 Pulse generation unit 112a, 112e set signal generating circuit 112b, 112d Reset signal generating circuit 112c OR circuit 113 Filter Circuit 114a First pulse conversion circuit 114b Second pulse conversion circuit 114c Third pulse conversion circuit 115 TFF circuit 116a First DFF circuit 116b Second DFF circuit 120 Drive signal circuit 130 Soft cutoff circuit 141 Low side control circuit 142 Low side drive circuit 143 Semiconductor Devices 144 Comparator 200 Control IC 300 Three-phase motor 400 power supply

Claims

1. A semiconductor driver circuit for driving a semiconductor element, comprising: a control circuit that receives an input signal and generates a set signal and a reset signal based on the input signal; a drive signal circuit that turns on a drive signal for the semiconductor element in response to a rising edge of the set signal and turns off the drive signal in response to a rising edge of the reset signal; a soft cutoff circuit that, when the set signal and the reset signal are turned on simultaneously, softly turns off the drive signal of the semiconductor element more slowly than when the drive signal circuit turns off the drive signal in response to a rising edge of the set signal and the reset signal.

2. 2. The semiconductor driver circuit according to claim 1, wherein the time required for the soft turn-off by the soft shut-off circuit is at least three times longer than the time required for the drive signal circuit to turn off the drive signal.

3. 3. The semiconductor driver circuit according to claim 1, wherein the control circuit receives an alert signal, and when the alert signal is on, turns on the set signal and the reset signal simultaneously.

4. The control circuit includes: a pulse generating unit that generates a pulse set signal, a pulse alert signal, and a pulse reset signal based on the input signal and the alert signal; a set signal generating circuit that generates the set signal based on the pulse set signal or the pulse alert signal; The semiconductor drive circuit according to claim 3 , further comprising: a reset signal generating circuit that generates the reset signal based on the pulse reset signal or the pulse alert signal.

5. The control circuit includes: a filter circuit that performs a filtering process on the input signal for a predetermined period of time; a first pulse conversion circuit that outputs a first pulse set signal in response to a rising edge of the input signal and outputs a first pulse reset signal in response to a falling edge of the input signal; a second pulse conversion circuit that outputs a second pulse set signal in response to a rising edge of an output signal of the filter circuit and outputs a second pulse reset signal in response to a falling edge of the output signal of the filter circuit; a logical OR circuit that outputs a logical OR signal of the first pulse reset signal and the second pulse reset signal; a TFF circuit that inverts an on / off state of a TFF output signal in response to a rising edge of the logical sum signal; a first DFF circuit that delays the TFF output signal in response to a rising edge of the first pulse set signal to output a first delayed signal; a second DFF circuit that delays the first delayed signal in response to a rising edge of the first pulse reset signal and outputs a second delayed signal; a third pulse conversion circuit for generating a pulse alert signal in response to a rising edge of the second delayed signal; a reset signal generating circuit that generates the reset signal based on the second pulse reset signal or the pulse alert signal; a set signal generating circuit that generates the set signal based on the second pulse set signal or the pulse alert signal, 3. The semiconductor drive circuit according to claim 1, wherein the input signal is a signal to which a pulse wave that changes between on, off, and on in a time shorter than a time constant of the filter circuit is applied when an abnormality is detected in the semiconductor drive circuit.

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