Board and manufacturing method of board

Abstract

To realize a high-density arrangement.SOLUTION: A board 21 includes: a base section 21F2; a film section 36 that is arranged on a base surface 21F2S of the base section 21F2, and has a first surface 36A abutting on the base surface 21F2S, and a second surface 36B having larger dimensions in a first direction along the base surface 21F2S than the first surface 36A while being positioned in a side opposite to the first surface 36A; a first conductive section 37 made of a conductive film 21F4 while being arranged adjacently to the film section 36 on the base surface 21F2S; and a second conductive section 38 made of a part apart from the first conductive section 37 in the conductive film 21F4 while being arranged on the second surface 36B of the film section 36.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a substrate and a method for manufacturing a substrate. [Background technology]

[0002] Conventionally, the substrate constituting a liquid crystal display device and a manufacturing method thereof are described in the following Patent Document 1. Patent Document 1 discloses a TFT array substrate as a substrate. In Patent Document 1, a resist film is formed on an insulating substrate, the resist film of the pattern of the gate wiring and the gate electrode is removed, a groove is formed in the insulating substrate by wet etching using the resist film pattern, a metal film is deposited by sputtering while leaving the resist film, the resist film is peeled off to lift off the metal film, and the gate wiring and the gate electrode are embedded in the insulating substrate, thereby flattening the gate wiring and the gate electrode, and an insulating liquid material is applied between the groove and the gate wiring and the gate electrode and baked to form a flattening film, and a TFT array substrate is manufactured using a well-known method. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-268343 Summary of the Invention [Problem to be solved by the invention]

[0004] In the TFT array substrate described in Patent Document 1, the gate wiring and the gate electrode are provided in a state of being embedded in a groove of an insulating substrate. The groove in which the gate wiring and the gate electrode are embedded is provided by wet etching the insulating substrate using a resist film pattern. The precision of the resist film pattern depends on the performance of the equipment for patterning the resist film, but there is a limit to how much the performance can be improved. For this reason, it has been difficult to respond to cases where it is required to arrange the gate wiring at a higher density.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to achieve high-density arrangement. [Means for solving the problem]

[0006] (1) A substrate related to the technology described in this specification comprises a base portion, a film portion arranged on a base surface of the base portion, the film portion having a first surface in contact with the base surface and a second surface located opposite the first surface and having a dimension in a first direction along the base surface larger than the first surface, a first conductive portion arranged adjacent to the film portion on the base surface and made of a conductive film, and a second conductive portion arranged on the second surface of the film portion and made of a portion of the conductive film different from the first conductive portion.

[0007] (2) In addition to the above (1), the second conductive portion may have a hanging portion hanging down from the second surface side toward the base surface side, and the first conductive portion may have an overlapping portion overlapping the hanging portion in a planar view.

[0008] (3) In addition to the above (1) or (2), the substrate may be configured such that the film portion is made of a conductive material.

[0009] (4) In addition to the above (3), the upper substrate may further include wiring and a pixel electrode, the conductive film being made of a transparent electrode material, the film portion being made of a metal material, the film portion and the second conductive portion constituting the wiring, and the first conductive portion constituting the pixel electrode.

[0010] (5) In addition to the above (1) or (2), the substrate may be configured such that the film portion is made of an insulating material.

[0011] (6) In addition to any one of (1) to (5) above, the substrate may have a film portion including a first film portion having the first surface and made of a first material, and a second film portion disposed on the first film portion, having the second surface, and made of a second material having an etching rate lower than that of the first material.

[0012] (7) A substrate related to the technology described in this specification comprises a base portion, and a film portion arranged on a base surface of the base portion, the film portion having a first surface in contact with the base surface, a second surface located on the opposite side of the first surface and having a dimension smaller or the same as that of the first surface in a first direction along the base surface, a third surface rising from the first surface side toward the second surface side, and a fourth surface located on the opposite side of the third surface in the first direction and rising from the first surface side toward the second surface side, a first conductive portion arranged on the third surface of the film portion and made of a conductive film, and a second conductive portion arranged on the fourth surface of the film portion and made of a portion of the conductive film different from the first conductive portion.

[0013] (8) In addition to the above (7), the substrate may further include an insulating film arranged between the film portion and the conductive film, the film portion being made of a conductive material, and the first conductive portion and the second conductive portion being arranged on the insulating film.

[0014] (9) A method for manufacturing a substrate related to the technology described in this specification includes forming a film on a base surface of a base portion, patterning the film to provide a film portion arranged on the base surface, the film portion having a first surface in contact with the base surface and a second surface located opposite the first surface and having a dimension in a first direction along the base surface larger than that of the first surface, forming a conductive film on the film portion, providing a first conductive portion arranged adjacent to the film portion on the base surface by a portion of the conductive film, and providing a second conductive portion arranged on the second surface of the film portion by a portion of the conductive film other than the first conductive portion.

[0015] (10) In addition to the above (9), the method for manufacturing the substrate may include sequentially depositing, as the film, a first film made of a first material and a second film made of a second material having an etching rate lower than that of the first material on the base surface, and etching the first film and the second film to provide the film portion consisting of a first film portion having the first surface made of a remaining portion of the first film, and a second film portion having the second surface made of a remaining portion of the second film.

[0016] (11) A method for manufacturing a substrate related to the technology described in this specification includes forming a film on a base surface of a base portion, patterning the film to provide a film portion arranged on the base surface, the film portion having a first surface in contact with the base surface, a second surface located on the opposite side of the first surface and having a dimension smaller or the same as that of the first surface in a first direction along the base surface, a third surface rising from the first surface side toward the second surface side, and a fourth surface located on the opposite side of the third surface in the first direction and rising from the first surface side toward the second surface side, forming a conductive film on the film portion, and etching the conductive film to provide a first conductive portion arranged on the third surface of the film portion by a part of the conductive film, and a second conductive portion arranged on the fourth surface of the film portion by a part of the conductive film other than the first conductive portion. Effect of the Invention

[0017] The techniques described herein allow for high density deployment. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a plan view of a liquid crystal panel, a driver, a flexible substrate, and the like that constitute a liquid crystal display device according to a first embodiment. [Diagram 2] 1 is a cross-sectional view of a liquid crystal panel, a driver, a flexible substrate, and the like according to the first embodiment; [Diagram 3] FIG. 1 is a circuit diagram showing an electrical configuration of an array substrate that constitutes a liquid crystal panel according to a first embodiment. [Figure 4] 1 is a cross-sectional view of a display area of ​​a liquid crystal panel according to a first embodiment. [Diagram 5] 1 is a cross-sectional view showing a film portion, a first conductive portion, and a second conductive portion according to a first embodiment; [Figure 6] FIG. 7 is a cross-sectional view similar to FIG. 5 , illustrating a state in which the resist film is exposed through a photomask in a sixth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view similar to FIG. 5, illustrating a state in which etching of the third metal film is started using the developed resist film as a mask in a sixth step included in the manufacturing method of the array substrate according to the first embodiment; [Figure 8] FIG. 7 is a cross-sectional view similar to FIG. 5 , illustrating a state in which etching of the third metal film is completed in a sixth step included in the manufacturing method of the array substrate according to the first embodiment; [Figure 9] FIG. 6 is a cross-sectional view similar to FIG. 5 , illustrating a state in which a first transparent electrode film is formed in a sixth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 10] FIG. 11 is a cross-sectional view showing a film portion, a first conductive portion, and a second conductive portion according to a second embodiment. [Figure 11] FIG. 11 is a cross-sectional view similar to FIG. 10, illustrating a state in which etching of the third metal film is started using the developed resist film as a mask in a sixth step included in the manufacturing method of the array substrate according to the second embodiment; [Figure 12]FIG. 11 is a cross-sectional view similar to FIG. 10 , illustrating a state in which etching of the third metal film is completed in a sixth step included in the method for manufacturing the array substrate according to the second embodiment; [Figure 13] FIG. 11 is a plan view of a liquid crystal panel, a driver, a flexible substrate, and the like that constitute a liquid crystal display device according to a third embodiment. [Figure 14] FIG. 11 is a plan view showing lead-out wiring provided on an array substrate of a liquid crystal panel according to a third embodiment; [Figure 15] 11 is a cross-sectional view showing a film portion, a first conductive portion, and a second conductive portion according to a third embodiment. [Figure 16] FIG. 16 is a cross-sectional view similar to FIG. 15, illustrating a state in which a resist film is exposed through a photomask in a first step included in a manufacturing method of an array substrate according to a third embodiment. [Figure 17] FIG. 16 is a cross-sectional view similar to FIG. 15, illustrating a state in which etching of a first metal film is started using a developed resist film as a mask in a first step included in a manufacturing method of an array substrate according to a third embodiment; [Figure 18] FIG. 16 is a cross-sectional view similar to FIG. 15, illustrating a state in which etching of a first metal film is completed in a first step included in a manufacturing method of an array substrate according to a third embodiment; [Figure 19] 16 is a cross-sectional view similar to FIG. 15, illustrating a state in which a second metal film is formed in a third step after a second step included in the manufacturing method of the array substrate according to the third embodiment; [Figure 20] FIG. 16 is a cross-sectional view similar to FIG. 15, illustrating a state in which etching of the second metal film is started in a third step included in the manufacturing method of the array substrate according to the third embodiment; [Figure 21] FIG. 11 is a cross-sectional view showing a film portion, a first conductive portion, and a second conductive portion according to a fourth embodiment. [Figure 22] 11 is a cross-sectional view showing a film portion, a first conductive portion, and a second conductive portion according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] <Embodiment 1> A first embodiment will be described with reference to Fig. 1 to Fig. 9. In this embodiment, a liquid crystal display device 10 having a display function and a touch panel function (position input function) is illustrated. Note that the X-axis, Y-axis, and Z-axis are shown in a part of each drawing, and each axis direction is drawn to be the direction shown in each drawing. Also, the upper side of Fig. 2, Fig. 4 to Fig. 9 is the front side, and the lower side of the drawings is the back side.

[0020] 1, a liquid crystal display device 10 includes at least a horizontally elongated rectangular liquid crystal panel (display device, display panel) 11 capable of displaying images, and a backlight device (illumination device) which is an external light source that irradiates the liquid crystal panel 11 with light to be used for display. The backlight device is disposed on the rear side (back side) of the liquid crystal panel 11, and includes a light source (e.g., an LED) that emits white light and an optical member that converts the light from the light source into planar light by applying an optical effect. The central portion of the screen of the liquid crystal panel 11 is a display area AA where an image is displayed. In contrast, a frame-shaped outer peripheral portion surrounding the display area AA on the screen of the liquid crystal panel 11 is a non-display area NAA where no image is displayed.

[0021] The liquid crystal panel 11 will be described in detail with reference to FIG. 1 and FIG. 2. As shown in FIG. 1 and FIG. 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20, 21. The front side (front side) of the pair of substrates 20, 21 is an opposing substrate (CF substrate) 20, and the back side (rear side) is an array substrate (substrate) 21. The opposing substrate 20 and the array substrate 21 are each formed by laminating various films on the inner side of glass substrates 20GS, 21GS. A liquid crystal layer (medium layer) 22 containing liquid crystal molecules, which are a substance whose optical properties change with the application of an electric field, is disposed between the pair of substrates 20, 21. A seal portion 23 that seals the liquid crystal layer 22 is disposed between the outer peripheral ends of the pair of substrates 20, 21. The seal portion 23 is formed in a rectangular frame shape (endless ring shape) so as to surround the liquid crystal layer 22. A polarizing plate 14 is attached to the outer surface side of each of the substrates 20, 21.

[0022] 1 and 2, the short side dimension of the counter substrate 20 is shorter than the short side dimension of the array substrate 21. The counter substrate 20 is attached to the array substrate 21 in such a manner that one end in the short side direction (Y-axis direction) is aligned with the array substrate 21. Therefore, the other end in the short side direction of the array substrate 21 is an exposed portion 21A that protrudes laterally and is exposed relative to the counter substrate 20. The entire exposed portion 21A is a non-display area NAA, and is equipped with a driver (mounted component, signal supply unit) 12 and a flexible substrate 13 for supplying various signals related to the display function and touch panel function described below.

[0023] The driver 12 shown in FIG. 1 and FIG. 2 is composed of an LSI chip having a driving circuit therein. The driver 12 is mounted on the exposed portion 21A of the array substrate 21 by COG (Chip On Glass). The driver 12 processes various signals transmitted by the flexible substrate 13. The driver 12 supplies various signals (e.g., image signals, touch signals, etc.) to wiring in the display area AA (specifically, source wiring 27 and touch wiring 30 described later). The flexible substrate 13 is configured by forming a number of wiring patterns on a base material made of a synthetic resin material (e.g., polyimide resin, etc.) having insulating properties and flexibility. As shown in FIG. 1 and FIG. 2, one end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit substrate. The flexible substrate 13 is connected to an end of the exposed portion 21A on the opposite side to the display area AA side in the Y-axis direction with respect to the driver 12.

[0024] The liquid crystal panel 11 according to this embodiment has both a display function for displaying an image and a touch panel function for detecting a position (input position) input by a user based on the displayed image. A touch panel pattern for exerting the touch panel function is integrated (in-cell) in the liquid crystal panel 11. This touch panel pattern is a so-called projected capacitive type, and its detection method is a self-capacitive type. As shown in FIG. 1, the touch panel pattern is composed of a plurality of touch electrodes (position detection electrodes) 29 arranged in a matrix on the plate surface of the liquid crystal panel 11. The touch electrodes 29 are arranged in a display area AA of the liquid crystal panel 11. Therefore, the display area AA of the liquid crystal panel 11 is approximately coincident with a touch area (position input area) where an input position can be detected, and the non-display area NAA is approximately coincident with a non-touch area (non-position input area) where an input position cannot be detected. When a user approaches a conductive finger (position input object) to the surface (display surface) of the liquid crystal panel 11 to input a position based on an image of the display area AA of the liquid crystal panel 11 that the user is viewing, a capacitance is formed between the finger and the touch electrode 29. As a result, the capacitance detected at the touch electrode 29 near the finger changes as the finger approaches, and becomes different from that of the touch electrode 29 far from the finger, so that it is possible to detect the input position based on the change. Note that the specific number of touch electrodes 29 installed can be changed as appropriate, in addition to the number shown in FIG. 1. The touch electrode 29 has an approximately rectangular shape in a plan view, and the dimension of one side is about several mm. Therefore, the size of the touch electrode 29 in a plan view is much larger than a pixel described later, and the touch electrode 29 is arranged in a range that spans multiple pixels in the X-axis direction and the Y-axis direction.

[0025] Next, the configuration of the display area AA in the array substrate 21 will be described with reference to FIG. 3. As shown in FIG. 3, at least a TFT (thin film transistor, switching element) 24 and a pixel electrode 25 are provided on the inner surface side of the display area AA of the array substrate 21. The TFTs 24 and the pixel electrodes 25 are arranged in a matrix shape (row and column shape) with a space between them along the X-axis direction and the Y-axis direction. Around the TFTs 24 and the pixel electrodes 25, gate wiring (scanning wiring) 26 and source wiring (image wiring, signal wiring) 27 that are orthogonal (intersecting) to each other are arranged. The gate wiring 26 extends along the X-axis direction. The source wiring 27 extends along the Y-axis direction. The TFT 24 has a gate electrode 24A connected to the gate wiring 26, a source electrode 24B connected to the source wiring 27, a drain electrode 24C connected to the pixel electrode 25, and a semiconductor portion 24D made of a semiconductor material and connected to the source electrode 24B and the drain electrode 24C. The TFT 24 is driven based on a scanning signal supplied to the gate electrode 24A by the gate wiring 26. Then, a potential related to an image signal (data signal) supplied from the driver 12 to the source electrode 24B by the source wiring 27 is supplied to the drain electrode 24C via the semiconductor portion 24D. As a result, the pixel electrode 25 is charged to the potential related to the image signal. The pixel electrode 25 is disposed in a region surrounded by the gate wiring 26 and the source wiring 27, and has a planar shape of, for example, a substantially rectangular shape.

[0026] As shown in FIG. 3, a common electrode 28 is formed on the inner surface of the display area AA of the array substrate 21 so as to overlap all the pixel electrodes 25. The common electrode 28 extends over almost the entire display area AA. In the common electrode 28, a plurality of slits extending along the long side direction of each pixel electrode 25 are formed in the portion overlapping each pixel electrode 25. Note that the slits are not shown in FIG. 3. When a potential difference occurs between the pixel electrode 25 and the common electrode 28 overlapping each other as the pixel electrode 25 is charged, a fringe electric field (oblique electric field) including a component along the plate surface of the array substrate 21 and a component in the normal direction to the plate surface of the array substrate 21 is generated between the opening edge of the slit and the pixel electrode 25. Therefore, the alignment state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled by utilizing this fringe electric field. That is, the liquid crystal panel 11 according to this embodiment operates in a FFS (Fringe Field Switching) mode. This common electrode 28 constitutes the above-mentioned touch electrode 29. In addition to the above-mentioned slits, the common electrode 28 has partition slits that separate adjacent touch electrodes 29. The partition slits divide the common electrode 28 into a grid pattern and make up a plurality of touch electrodes 29 that are electrically independent from each other.

[0027] As shown in FIG. 3, a plurality of touch wirings (wirings, position detection wirings) 30 connected to a plurality of touch electrodes 29 are provided on the inner surface side of the display area AA of the array substrate 21. The touch wirings 30 extend along the Y-axis direction and are parallel to the source wirings 27. The plurality of touch wirings 30 are individually connected to the plurality of touch electrodes 29. A common signal (reference potential signal) related to the display function and a touch signal (position detection signal) related to the touch function are supplied to the touch wirings 30 from the driver 12 at different timings (time division). The timing when the common signal is supplied from the driver 12 to the touch wirings 30 is the display period, and the timing when the touch signal is supplied from the driver 12 to the touch wirings 30 is the sensing period (position detection period). During the display period, the common signal is supplied to all the touch wirings 30, so that all the touch electrodes 29 become the reference potential and function as the common electrodes 28. In this way, the liquid crystal display device 10 according to this embodiment is provided with a display function, a touch panel function, and high definition, so that a plurality of drivers 12 are implemented and the plurality of drivers 12 are designed to have high functionality.

[0028] As shown in FIG. 4, the display area AA on the inner surface side of the counter substrate 20 is provided with three color filters 32 that exhibit blue (B), green (G), and red (R). The color filters 32 that exhibit different colors are arranged side by side so as to be adjacent to each other in the extending direction (X-axis direction) of the gate wiring 26. The color filters 32 that exhibit different colors extend along the extending direction (Y-axis direction) of the source wiring 27. In this way, the color filters 32 that exhibit different colors are arranged in a striped pattern as a whole. These color filters 32 are arranged so as to overlap with each pixel electrode 25 on the array substrate 21 side in a plan view. In this liquid crystal panel 11, the red, green, and blue color filters 32 arranged along the X-axis direction and the three pixel electrodes 25 facing each color filter 32 each constitute a pixel of three colors. In this liquid crystal panel 11, the red, green, and blue pixels that are adjacent to each other along the X-axis direction constitute a display pixel that can display a color of a predetermined gradation. In addition, a black matrix 33 is provided on the counter substrate 20 to separate a plurality of color filters 32 exhibiting different colors from one another. The black matrix 33 has a lattice shape in a plan view, and overlaps with a plurality of gate lines 26 and source lines 27. An overcoat film 34 is provided on the color filters 32 (on the liquid crystal layer 22 side) so as to be flat, and is disposed in a solid manner over almost the entire area of ​​the counter substrate 20. An alignment film 35 is provided on the overcoat film 34 to align liquid crystal molecules contained in the liquid crystal layer 22.

[0029] Here, various films laminated on the inner surface side of the array substrate 21 will be described mainly with reference to Fig. 4. As shown in Fig. 4, the array substrate 21 is laminated with a first metal film, a gate insulating film 21F1, a semiconductor film, a second metal film, a first interlayer insulating film (base portion) 21F2, a third metal film (film) 21F3, a first transparent electrode film (conductive film) 21F4, a second interlayer insulating film (insulating film) 21F5, a second transparent electrode film, and an alignment film 31 in this order from the lower layer side (glass substrate 21GS side). Of these, the third metal film 21F3 is illustrated in Fig. 7, and the first transparent electrode film 21F4 is illustrated in Fig. 9. The first metal film, the second metal film, and the third metal film 21F3 are each a single layer film made of one type of metal material selected from Cu (copper), Ti (titanium), AL (aluminum), Mo (molybdenum), W (tungsten), etc., or a laminated film or alloy made of different types of metal materials, and thus have electrical conductivity and light shielding properties. Among these, the third metal film 21F3 may be made of a laminated film such as Cu / Ti, Ti / Al / Ti, Mo / Al / Mo, etc. The first metal film constitutes the gate wiring 26 and the gate electrode 24A of the TFT 24, etc. The second metal film constitutes the source wiring 27, the source electrode 24B and the drain electrode 24C of the TFT 24, etc. The third metal film 21F3 constitutes a part of the touch wiring 30, etc. The film thickness of the third metal film 21F3 is greater than the film thickness of the first transparent electrode film 21F4. The semiconductor film is made of a thin film using, for example, an oxide semiconductor, amorphous silicon, or the like as a material, and constitutes the semiconductor portion 24D of the TFT 24, etc. The first transparent electrode film 21F4 and the second transparent electrode film are made of a transparent electrode material (for example, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide)). The first transparent electrode film 21F4 constitutes a part of the touch wiring 30, the pixel electrode 25, etc. The second transparent electrode film constitutes the common electrode 28 (touch electrode 29), etc. The alignment film 31 is made of polyamide, etc. The alignment film 31 is located on the innermost surface of the array substrate 21, and aligns the liquid crystal molecules contained in the liquid crystal layer 22.

[0030] The gate insulating film 21F1, the first interlayer insulating film 21F2, and the second interlayer insulating film 21F5 are each made of SiN. x (Silicon nitride), SiOx (Silicon oxide), SiO x N y The gate insulating film 21F1 is made of an inorganic material such as silicon oxynitride. The gate insulating film 21F1 keeps the first metal film on the lower layer side and the semiconductor film and second metal film on the upper layer side in an insulated state. For example, the intersection of the gate wiring 26 made of the first metal film and the source wiring 27 made of the second metal film is kept in an insulated state by the gate insulating film 21F1. In addition, the overlapping portion of the gate electrode 24A made of the first metal film and the semiconductor part 24D made of the semiconductor film is kept in an insulated state by the gate insulating film 21F1. The first interlayer insulating film 21F2 keeps the semiconductor film and second metal film on the lower layer side in an insulated state, and the third metal film 21F3 and first transparent electrode film 21F4 on the upper layer side. The touch wiring 30 made of the third metal film 21F3 and the first transparent electrode film 21F4 is arranged to overlap the source wiring 27 made of the second metal film via the first interlayer insulating film 21F2. The touch wiring 30 and the source wiring 27 that overlap each other are kept in an insulated state by the first interlayer insulating film 21F2. The second interlayer insulating film 21F5 keeps the third metal film 21F3 and the first transparent electrode film 21F4 on the lower layer side insulated from the second transparent electrode film on the upper layer side. For example, the overlapping portion of the touch wiring 30 and the pixel electrode 25 including the first transparent electrode film 21F4 and the common electrode 28 (touch electrode 29) made of the second transparent electrode film is kept in an insulated state by the second interlayer insulating film 21F5.

[0031] As described above, in the array substrate 21 according to the present embodiment, as shown in Fig. 7 and Fig. 9, the third metal film 21F3 and the first transparent electrode film 21F4 are continuously provided on the base surface 21F2S, which is the upper surface of the first interlayer insulating film 21F2, without an insulating film therebetween. As shown in Fig. 5, the third metal film 21F3 constitutes the film portion 36 arranged on the base surface 21F2S, while the first transparent electrode film 21F4 constitutes the first conductive portion 37 arranged on the base surface 21F2S and the second conductive portion 38 arranged on the film portion 36. The film portion 36 and the second conductive portion 38 overlapping each other constitute the touch wiring 30, while the first conductive portion 37 constitutes the pixel electrode 25. The touch wiring 30 has a laminated structure of a film portion 36 made of a metal material and a second conductive portion 38 made of a transparent electrode material, and therefore has high conductivity and low wiring resistance compared to a case where the touch wiring is made of only one of the film portion 36 and the second conductive portion 38. The touch wiring 30 also has a low resistance compared to a first conductive portion 37 (pixel electrode 25) described below. This makes it difficult for the touch signal and common signal transmitted by the touch wiring 30 to become dull. On the other hand, the pixel electrode 25 is made of the first conductive portion 37 made of a transparent electrode material, and therefore the pixel electrode 25 can be guaranteed to have translucency, and the pixel electrode 25 can be charged to generate an electric field between the pixel electrode 25 and the common electrode 28.

[0032] 5, the film portion 36 made of the third metal film 21F3 has a cross-sectional shape in the X-axis direction (first direction) that is an inverted taper shape (inverted trapezoid shape). The X-axis direction is along the base surface 21F2S of the first interlayer insulating film 21F2 and perpendicular (intersects) with the extending direction (Y-axis direction) of the touch wiring 30, that is, the width direction of the touch wiring 30. The film portion 36 is configured such that the dimension (width dimension) in the X-axis direction increases continuously and gradually from the base surface 21F2S side to the opposite side in the Z-axis direction. The dimension (height dimension) of the film portion 36 in the Z-axis direction is larger than the dimension in the Z-axis direction of a first conductive portion 37 described later. The cross-sectional shape of the film portion 36 in the X-axis direction is symmetrical.

[0033] As shown in FIG. 5, the film portion 36 has a first surface 36A in contact with the base surface 21F2S of the first interlayer insulating film 21F2, a second surface 36B located on the opposite side to the first surface 36A, and a pair of third surfaces 36C connecting at least a part between the first surface 36A and the second surface 36B. The first surface 36A can be said to be the bottom surface of the film portion 36, and is at the same height in the Z-axis direction as the base surface 21F2S with which it is in contact. The second surface 36B can be said to be the top surface of the film portion 36, and is disposed higher than the first surface 36A and the base surface 21F2S by the thickness of the film portion 36. The third surface 36C can be said to be the side surface of the film portion 36. The first surface 36A and the second surface 36B are aligned at their respective central positions in the X-axis direction. The second surface 36B has a larger dimension in the X-axis direction than the first surface 36A. The third surfaces 36C are arranged to face the back side, i.e., the base surface 21F2S side. The third surfaces 36C are inclined surfaces inclined with respect to the X-axis direction. The pair of third surfaces 36C have the same inclination angle with respect to the X-axis direction. The interior angle that the third surfaces 36C form with respect to the X-axis direction is an obtuse angle.

[0034] As shown in FIG. 5, the first conductive portion 37 made of the first transparent electrode film 21F4 is disposed adjacent to the above-mentioned film portion 36 in the X-axis direction on the base surface 21F2S. At least two first conductive portions 37 are disposed so as to sandwich the film portion 36 from both sides in the X-axis direction. In contrast, the second conductive portion 38 is formed of a portion of the first transparent electrode film 21F4 other than the first conductive portion 37, and is disposed on the second surface 36B of the film portion 36. The second conductive portion 38 is disposed at a position (higher position) away from the base surface 21F2S in the Z-axis direction by the height of the film portion 36. Here, the height of the film portion 36 is equal to the film thickness of the third metal film 21F3, while the thickness of the first conductive portion 37 is equal to the film thickness of the first transparent electrode film 21F4, so that the height of the film portion 36 is greater than the thickness of the first conductive portion 37. In addition, since the second surface 36B of the film portion 36 is larger in the dimension in the X-axis direction than the first surface 36A, when the first transparent electrode film 21F4 is formed during manufacturing, a discontinuity occurs between the first conductive portion 37 and the second conductive portion 38. This ensures electrical independence between the first conductive portion 37 and the second conductive portion 38. In this embodiment, since it is not necessary to form a resist film on the first transparent electrode film 21F4 and pattern the resist film as in the conventional method, it is possible to increase the arrangement density of the first conductive portion 37 and the second conductive portion 38 regardless of the performance of the equipment (exposure device, etc.) for patterning the resist film. In this way, according to this embodiment, the first conductive portion 37 and the second conductive portion 38 can be arranged at a higher density than in the conventional method.

[0035] As shown in FIG. 5, the second conductive part 38 has a hanging part 38A that hangs down from the second surface 36B side of the film part 36 toward the base surface 21F2S side. The hanging parts 38A are provided in pairs at both ends of the second conductive part 38 in the X-axis direction. The pair of hanging parts 38A are located outward in the X-axis direction from both ends of the film part 36 in the X-axis direction. The hanging parts 38A are arranged so that the lower end position is between the second surface 36B and the base surface 21F2S in the Z-axis direction. In contrast, the first conductive part 37 has an overlapping part 37A that overlaps with the hanging part 38A in a plan view. The overlapping part 37A is provided in pairs at both ends of the first conductive part 37 in the X-axis direction. The overlapping part 37A is arranged at a position directly below at least the hanging part 38A, and faces the lower end of the hanging part 38A with a gap in the Z-axis direction. A portion of the overlapping portion 37A overlaps with an end portion of the film portion 36 in the X-axis direction in a plan view, and is located directly below a portion (the end portion in the X-axis direction) of the third surface 36C. In this manner, the first conductive portion 37 and the second conductive portion 38 are arranged without any gaps in a plan view. This allows the arrangement density of the first conductive portion 37 and the second conductive portion 38 to be increased.

[0036] The present embodiment has the above-described structure, and the manufacturing method of the liquid crystal panel 11 will now be described. The manufacturing method of the liquid crystal panel 11 includes a counter substrate manufacturing process (CF substrate manufacturing process) for manufacturing the counter substrate 20, an array substrate manufacturing process (substrate manufacturing process) for manufacturing the array substrate 21, and a bonding process for bonding the manufactured counter substrate 20 and array substrate 21 together. Of these processes, the array substrate manufacturing process will be described below.

[0037] The array substrate manufacturing process includes at least a first step of forming the gate wiring 26 and the gate electrode 24A, a second step of forming the gate insulating film 21F1, a third step of forming the semiconductor portion 24D, a fourth step of forming the source wiring 27, the source electrode 24B, the drain electrode 24C, and the like, a fifth step of forming the first interlayer insulating film 21F2, a sixth step of forming the touch wiring 30 and the pixel electrode 25, and the like, a seventh step of forming the second interlayer insulating film 21F5, an eighth step of forming the common electrode 28 (touch electrode 29), and the like, and a ninth step of forming the alignment film 31. The sixth and seventh steps will be described with reference to FIGS. 5 to 9.

[0038] In the sixth step, as shown in FIG. 6, the third metal film 21F3 is formed in a solid state on the base surface 21F2S of the first interlayer insulating film 21F2, and further, the resist film PR1 is formed in a solid state on the third metal film 21F3. After that, the resist film PR1 is exposed to light using an exposure device and a photomask PM1. The resist film PR1 used in the sixth step is made of a positive-type photosensitive resist material. Here, the photomask PM1 will be described. The photomask PM1 includes a transparent base material PM1A having a sufficiently high light transmittance and a light shielding film PM1B formed on the main surface of the base material PM1A. The light shielding film PM1B shields the exposure light from the light source of the exposure device and has a partial opening PM1C. In the photomask PM1, the formation range of the light shielding film PM1B is a light shielding region that blocks light, and the formation range of the opening PM1C (the non-formation range of the light shielding film PM1B) is a light transmitting region that transmits light. The light shielding film PM1B is provided so as to overlap with a plurality of touch wirings 30.

[0039] In the sixth step, when the exposure light emitted from the light source of the exposure tool is irradiated onto the resist film PR1 through the photomask PM1 configured as described above, the area of ​​the resist film PR1 overlapping with the light-shielding film PM1B is not exposed, and the area of ​​the resist film PR1 overlapping with the opening PM1C is selectively exposed. When development is performed following exposure, as shown in Fig. 7, the exposed portion of the positive resist film PR1 is removed because it is dissolved by the developer at a high rate, i.e., its dissolution rate is high. On the other hand, the dissolution rate of the unexposed portion is slower, so it remains.

[0040] After the resist film PR1 is patterned as described above, the third metal film 21F3 is etched using the resist film PR1 as a mask, as shown in FIG. 7. At this time, either wet etching using an etching solution or dry etching using vacuum discharge plasma can be performed. When the third metal film 21F3 is patterned by etching the third metal film 21F3, a film portion 36 having a cross-sectional shape in the X-axis direction with an inverse tapered shape is provided, as shown in FIG. 8. To form such a film portion 36 with an inverse tapered shape by wet etching, for example, an etching solution that easily penetrates into the metal material of the third metal film 21F3 may be selected and used. To form such a film portion 36 with an inverse tapered shape by dry etching, the total flow rate of the reaction gas may be increased by increasing the amount of oxygen-based gas contained in the reaction gas, as compared to the case where the film portion is formed with a forward tapered shape. The inversely tapered film portion 36 thus provided has a first surface 36A in contact with the base surface 21F2S of the first interlayer insulating film 21F2, a second surface 36B located on the opposite side to the first surface 36A and having a dimension in the X-axis direction larger than that of the first surface 36A, and a third surface 36C oriented toward the base surface 21F2S. Thereafter, the resist film PR1 remaining on the film portion 36 is peeled off.

[0041] In the sixth step, as shown in FIG. 9, the first transparent electrode film 21F4 is formed in a solid state on the film portion 36 and the base surface 21F2S. The formed first transparent electrode film 21F4 includes a portion disposed on the second surface 36B of the film portion 36 and a portion disposed on the base surface 21F2S. Of the portions of the first transparent electrode film 21F4 disposed on the second surface 36B of the film portion 36, the portions protruding from both ends of the film portion 36 in the X-axis direction hang down, and the lower ends of each are physically separated from the portions disposed on the base surface 21F2S. In other words, a break occurs due to a step caused by the film portion 36 between the second conductive portion 38, which is a portion of the first transparent electrode film 21F4 disposed on the second surface 36B of the film portion 36, and the first conductive portion 37, which is a portion disposed on the base surface 21F2S. This ensures electrical independence between the first conductive portion 37 and the second conductive portion 38. In this way, when providing the first conductive portion 37 and the second conductive portion 38 made of the first transparent electrode film 21F4, there is no need to pattern a resist film as in the conventional method, so the density of the first conductive portion 37 and the second conductive portion 38 does not depend on the pattern of the resist film as in the conventional method. Therefore, according to this embodiment, the arrangement density of the first conductive portion 37 and the second conductive portion 38 can be increased compared to the conventional method.

[0042] After completing the sixth step as described above, the seventh step is performed to deposit the second interlayer insulating film 21F5. Then, as shown in Fig. 5, the first conductive portion 37 and the second conductive portion 38 are covered with the second interlayer insulating film 21F5, and the gap between the hanging portion 38A of the second conductive portion 38 and the overlapping portion 37A of the first conductive portion 37 is filled. This ensures insulation between the first conductive portion 37 and the second conductive portion 38.

[0043] As described above, the array substrate (substrate) 21 of this embodiment includes a first interlayer insulating film (base portion) 21F2, a film portion 36 arranged on the base surface 21F2S of the first interlayer insulating film 21F2, the film portion 36 having a first surface 36A in contact with the base surface 21F2S and a second surface 36B located opposite the first surface 36A and having a dimension in a first direction along the base surface 21F2S larger than the first surface 36A, a first conductive portion 37 arranged adjacent to the film portion 36 on the base surface 21F2S and made of a first transparent electrode film (conductive film) 21F4, and a second conductive portion 38 arranged on the second surface 36B of the film portion 36 and made of a portion of the first transparent electrode film 21F4 other than the first conductive portion 37.

[0044] The second conductive portion 38 located on the second surface 36B of the film portion 36 is arranged higher than the base surface 21F2S with respect to the first conductive portion 37 located on the base surface 21F2S by the amount of the film portion 36. In addition, since the second surface 36B of the film portion 36 has a larger dimension in the first direction along the base surface 21F2S than the first surface 36A, a discontinuity occurs between the first conductive portion 37 and the second conductive portion 38, which are separate parts of the first transparent electrode film 21F4. This ensures electrical independence between the first conductive portion 37 and the second conductive portion 38. In this way, the density of the first conductive portion 37 and the second conductive portion 38 does not depend on the pattern of the resist film as in the conventional case, so that a higher density arrangement than in the conventional case can be realized.

[0045] Further, second conductive portion 38 has hanging portion 38A hanging down from second surface 36B side toward base surface 21F2S side, and first conductive portion 37 has overlapping portion 37A overlapping hanging portion 38A in plan view. In this manner, first conductive portion 37 and second conductive portion 38 are arranged without any gaps in plan view. This allows the arrangement density of first conductive portion 37 and second conductive portion 38 to be increased.

[0046] Moreover, the film portion 36 is made of a conductive material. In this way, the film portion 36 and the second conductive portion 38 are conductive to each other, and therefore have a lower resistance than the first conductive portion 37. Therefore, when a signal is transmitted by the film portion 36 and the second conductive portion 38, the signal is less likely to be distorted.

[0047] The touch wiring (wiring) 30 and the pixel electrode 25 are also provided, and the first transparent electrode film 21F4 is made of a transparent electrode material, the film portion 36 is made of a metal material, the film portion 36 and the second conductive portion 38 constitute the touch wiring 30, and the first conductive portion 37 constitutes the pixel electrode 25. Since the pixel electrode 25 is constituted by the first conductive portion 37 made of a transparent electrode material, the light transmittance of the pixel electrode 25 can be ensured, and the pixel electrode 25 can be charged to generate an electric field. Since the touch wiring 30 is constituted by the film portion 36 made of a metal material and the second conductive portion 38 made of a transparent electrode material, the signal transmitted by the touch wiring 30 is less likely to be dulled.

[0048] In addition, the manufacturing method of the array substrate 21 of this embodiment includes forming a third metal film 21F3 on the base surface 21F2S of the first interlayer insulating film 21F2, patterning the third metal film 21F3 to provide a film portion 36 arranged on the base surface 21F2S, the film portion 36 having a first surface 36A in contact with the base surface 21F2S and a second surface 36B located opposite the first surface 36A and having a larger dimension in a first direction along the base surface 21F2S than the first surface 36A, forming a first transparent electrode film 21F4 on the film portion 36, providing a first conductive portion 37 arranged adjacent to the film portion 36 on the base surface 21F2S by a part of the first transparent electrode film 21F4, and providing a second conductive portion 38 arranged on the second surface 36B of the film portion 36 by a part of the first transparent electrode film 21F4 other than the first conductive portion 37.

[0049] The film portion 36 is provided by patterning the third metal film 21F3 formed on the base surface 21F2S, and the second surface 36B has a larger dimension in the first direction along the base surface 21F2S than the first surface 36A. When the first transparent electrode film 21F4 is formed on the film portion 36, a discontinuity occurs between the second conductive portion 38, which is a portion of the first transparent electrode film 21F4 arranged on the second surface 36B of the film portion 36, and the first conductive portion 37, which is a portion of the first transparent electrode film 21F4 arranged on the base surface 21F2S. This ensures electrical independence between the first conductive portion 37 and the second conductive portion 38. In this way, the density of the first conductive portion 37 and the second conductive portion 38 does not depend on the pattern of the resist film as in the conventional case, so that a higher density arrangement than in the conventional case can be realized.

[0050] <Embodiment 2> A second embodiment will be described with reference to Figures 10 to 12. In this second embodiment, a case where the configuration of the membrane part 136 is changed is shown. Note that a duplicated description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0051] As shown in FIG. 10, the film portion 136 according to this embodiment has a laminated structure of a first film portion 39 and a second film portion 40 made of different materials. The first film portion 39 has a first surface 136A in contact with the base surface 121F2S and is made of a first material. For example, Cu or Al is used as the first material of the first film portion 39. The first film portion 39 also has a part of the third surface 136C (a part connected to the first surface 136A). The second film portion 40 is disposed on the first film portion 39, has a second surface 136B, and is made of a second material having a lower etching rate than the first material. With respect to the etching rate when etching the third metal film 121F3 (see FIG. 11) in the sixth step included in the manufacturing method of the array substrate 121, the second material of the second film portion 40 has a lower etching rate than the first material of the first film portion 39. For example, ITO or Ti is used as the second material of the second film portion 40. The second film portion 40 may have a larger dimension in the Z-axis direction than the first film portion 39. The second film portion 40 also has a portion of the third surface 136C (a portion continuing to the second surface 136B). In this way, when the third metal film 121F3 is etched in the sixth step, a large amount of the first material of the first film portion 39 is removed, whereas a large amount of the second material of the second film portion 40 remains, so that the film portion 136 having the third surface 136C oriented toward the base surface 121F2S can be easily provided.

[0052] Next, the sixth step included in the manufacturing method of the array substrate 121 will be described in detail. In the sixth step, as shown in Fig. 11, a first film 121F3A made of the first material arranged on the base surface 121F2S and a second film 121F3B made of the second material arranged on the first film 121F3A are sequentially formed to form the third metal film 121F3. Here, when wet etching is performed as the etching described below, for example, Cu is used as the first material of the first film 121F3A, and for example, ITO is used as the material of the second film 121F3B having a lower etching rate than Cu, so that the third metal film 121F3 is, for example, an ITO / Cu laminated film. On the other hand, when dry etching is used as the etching method, for example, Al is used as the first material of the first film 121F3A, and for example, Ti is used as the material of the second film 121F3B having a lower etching rate than Al, so that the third metal film 121F3 is, for example, a Ti / Al laminate film.

[0053] In the sixth step, when the third metal film 121F3 is etched, as shown in FIG. 12, the first film 121F3A and the second film 121F3B are selectively removed, and the remaining part of the first film 121F3A forms the first film portion 39, and the remaining part of the second film 121F3B forms the second film portion 40. At this time, the first film portion 39, which has a higher etching rate than the second film portion 40, is largely removed, whereas the second film portion 40, which has a lower etching rate than the first material of the first film portion 39, remains largely. This makes it possible to easily provide the film portion 136, which is composed of the first film portion 39 having the first surface 136A, which is smaller in dimension in the X-axis direction than the second surface 136B, and the second film portion 40, which has the second surface 136B, which is larger in dimension in the first direction than the first surface 136A.

[0054] As described above, according to the array substrate 121 of the present embodiment, the film portion 136 has a first film portion 39 having a first surface 136A and made of a first material, and a second film portion 40 arranged on the first film portion 39, having a second surface 136B, and made of a second material having a lower etching rate than the first material. In manufacturing, a first film (film) 121F3A made of a first material and a second film (film) 121F3B made of a second material are continuously formed, and then the two films 121F3A and 121F3B are etched together to provide the film portion 136 having the first film portion 39 and the second film portion 40. Since the second material of the second film portion 40 has a lower etching rate than the first material of the first film portion 39, the film portion 136 can be easily provided by performing etching.

[0055] In addition, the manufacturing method of the array substrate 121 of this embodiment sequentially forms a first film 121F3A made of a first material and a second film 121F3B made of a second material having an etching rate lower than that of the first material as the third metal film 121F3 on the base surface 121F2S, and then etches the first film 121F3A and the second film 121F3B to provide a film portion 136 consisting of a first film portion 39 having a first surface 136A by the remaining part of the first film 121F3A and a second film portion 40 having a second surface 136B by the remaining part of the second film 121F3B. In this way, when etching the first film 121F3A and the second film 121F3B, the first film 121F3A having a higher etching rate than the second film 121F3B is removed more than the second film 121F3B having a lower etching rate than the first film 121F3A. This makes it possible to easily provide a membrane portion 136 consisting of a first membrane portion 39 having a first surface 136A whose dimension in the first direction is smaller than that of the second surface 136B, and a second membrane portion 40 having a second surface 136B whose dimension in the first direction is larger than that of the first surface 136A.

[0056] <Embodiment 3> A third embodiment will be described with reference to Fig. 13 to Fig. 20. In this third embodiment, a film portion 42, a first conductive portion 43, and a second conductive portion 44 different from those in the first embodiment are provided. Note that a duplicated description of the structure, action, and effect similar to those in the first embodiment will be omitted.

[0057] In the non-display area NAA of the array substrate 221 constituting the liquid crystal panel 211 according to the present embodiment, as shown in FIG. 13, the lead-out wiring 41 is provided from the source wiring 227. The lead-out wiring 41 is connected to the end of the source wiring 227 extending along the Y-axis direction in the display area AA that is closer to the driver 212 in the Y-axis direction. In the non-display area NAA, the lead-out wiring 41 extends from the arrangement area of ​​the driver 212 toward the display area AA. Here, the long side dimension of the driver 212 is smaller than the short side dimension of the display area AA. Therefore, the lead-out wiring 41 is routed so as to spread out in a fan shape from the driver 212 side toward the display area AA side. Accordingly, a part of the lead-out wiring 41 is a diagonal wiring part 41A extending along a diagonal direction with respect to the X-axis direction and the Y-axis direction as shown in FIG. 14. The arrangement pitch of the diagonal wiring parts 41A is narrower than the arrangement pitch of the source wirings 227.

[0058] Here, for example, when high definition of the liquid crystal panel 211 is required, the number of source wirings 227 and lead wirings 41 to be installed will be increased. In addition, for example, when a narrower frame of the liquid crystal panel 211 is required, the non-display area NAA of the array substrate 221 will be narrowed. In either case, it becomes necessary to narrow the arrangement pitch of the multiple diagonal wiring parts 41A, and there is a tendency to require arranging the diagonal wiring parts 41A at a high density. The configuration of the lead wiring 41 for realizing the high-density arrangement of the diagonal wiring parts 41A will be described in detail below.

[0059] The cross-sectional configuration of the lead-out wiring 41 will be described with reference to Fig. 15. As shown in Fig. 15, the multiple lead-out wirings 41 according to this embodiment include a first lead-out wiring 41α made of a film portion 42 arranged on the base surface 221GS1, which is the upper surface of the glass substrate (base portion) 221GS, a second lead-out wiring 41β made of a first conductive portion 43 arranged on the upper layer side of the film portion 42 via a gate insulating film (insulating film) 221F1, and a third lead-out wiring 41γ made of a second conductive portion 44 arranged on the upper layer side of the film portion 42 via the gate insulating film 221F1. That is, the three lead-out wirings 41α to 41γ are configured by the film portion 42, the first conductive portion 43, and the second conductive portion 44. A plurality of each of the film portions 42, the first conductive portion 43, and the second conductive portion 44 are provided.

[0060] 15, the film portion 42 constituting the first lead-out wiring 41α has a cross-sectional shape in the X-axis direction (first direction) that is forward tapered (trapezoidal). The X-axis direction is along the base surface 221GS1 of the glass substrate 221GS and perpendicular (intersects) with the extending direction of the lead-out wiring 41, that is, the width direction of the lead-out wiring 41. The film portion 42 is configured such that the dimension (width dimension) in the X-axis direction continuously and gradually decreases from the base surface 221GS1 side to the opposite side in the Z-axis direction. The film portion 42 has a cross-sectional shape in the X-axis direction that is symmetrical.

[0061] As shown in FIG. 15, the film portion 42 has a first surface 42A in contact with the base surface 221GS1 of the glass substrate 221GS, a second surface 42B located on the opposite side to the first surface 42A, and a third surface 42C and a fourth surface 42D connecting the first surface 42A and the second surface 42B. The first surface 42A can be said to be the bottom surface of the film portion 42, and is at the same height in the Z-axis direction as the base surface 221GS1 with which it is in contact. The second surface 42B can be said to be the top surface of the film portion 42, and is disposed higher than the first surface 42A and the base surface 221GS1 by the thickness of the film portion 42. The third surface 42C and the fourth surface 42D can both be said to be side surfaces of the film portion 42. The first surface 42A and the second surface 42B have the same center position in the X-axis direction. The second surface 42B has a smaller dimension in the X-axis direction than the first surface 42A. The third surface 42C rises from the first surface 42A side toward the second surface 42B side, and is arranged so as to face the front side, that is, the opposite side to the base surface 221GS1 side. The fourth surface 42D is located on the opposite side of the third surface 42C in the X-axis direction, and rises from the first surface 42A side toward the second surface 42B side. Like the third surface 42C, the fourth surface 42D is also arranged so as to face the front side, that is, the opposite side to the base surface 221GS1 side. Both the third surface 42C and the fourth surface 42D are inclined surfaces inclined with respect to the X-axis direction. The third surface 42C and the fourth surface 42D have the same inclination angle with respect to the X-axis direction. The interior angle that the third surface 42C and the fourth surface 42D form with respect to the X-axis direction is an acute angle, and may be, for example, greater than 45° and less than 90°. The film portion 42 having such a configuration is covered by the gate insulating film 221F1 on the upper layer side. In the gate insulating film 221F1, a portion covering the film portion 42 has a cross-sectional shape that follows the outer shape of the film portion 42, and includes portions that are parallel to each of the second surface 42B, the third surface 42C, and the fourth surface 42D.

[0062] The first conductive portion 43 constituting the second lead-out wiring 41β is disposed on the third surface 42C of the film portion 42 via the gate insulating film 221F1, as shown in FIG. 15. The first conductive portion 43 has a cross-sectional shape inclined with respect to the X-axis direction so as to be parallel to the third surface 42C of the film portion 42. The inclination angle of the first conductive portion 43 with respect to the X-axis direction is approximately equal to the inclination angle of the third surface 42C with respect to the X-axis direction. The second conductive portion 44 constituting the third lead-out wiring 41γ is disposed on the fourth surface 42D of the film portion 42 via the gate insulating film 221F1. The second conductive portion 44 has a cross-sectional shape inclined with respect to the X-axis direction so as to be parallel to the fourth surface 42D of the film portion 42. The inclination angle of the second conductive portion 44 with respect to the X-axis direction is approximately equal to the inclination angle of the fourth surface 42D with respect to the X-axis direction.

[0063] The film portion 42 described above is made of a first metal film 221F6 arranged on the base surface 221GS1 of the glass substrate 221GS, as shown in FIG. 17. The first lead wiring 41α formed by the film portion 42 is connected to the source wiring 227 (see FIG. 13) to be connected through a contact hole provided in the gate insulating film 221F1. The first conductive portion 43 is made of a second metal film (conductive film) 221F7 arranged on the gate insulating film 221F1, as shown in FIG. 20. The second conductive portion 44 is made of a portion of the second metal film 221F7 that is different from the first conductive portion 43. In manufacturing, the first conductive portion 43 and the second conductive portion 44 are provided by etching the second metal film 221F7 formed on the film portion 42. Here, as described above, the second surface 42B of the film portion 42 is smaller in dimension in the X-axis direction than the first surface 42A, so when the second metal film 221F7 is etched, the portions of the second metal film 221F7 arranged on the third surface 42C and the fourth surface 42D rising from the first surface 42A side toward the second surface 42B side are selectively left, and the first conductive portion 43 and the second conductive portion 44 are provided by these portions. In this embodiment, since it is not necessary to form a resist film on the second metal film 221F7 and pattern the resist film as in the conventional method, it is possible to increase the arrangement density of the first conductive portion 43 and the second conductive portion 44 regardless of the performance of the equipment (exposure device, etc.) for patterning the resist film. Thus, according to this embodiment, the first conductive portion 43 and the second conductive portion 44 can be arranged at a higher density than in the conventional method. Furthermore, the film portion 42 made of the first metal film 221F6 and the first conductive portion 43 and the second conductive portion 44 made of the second metal film 221F7 are insulated by the gate insulating film 221F1 interposed therebetween, thereby ensuring their electrical independence from each other.

[0064] Next, the first to third steps included in the manufacturing method of the array substrate 221 will be described in detail. In the first step, as shown in FIG. 16, a first metal film 221F6 is formed in a solid state on the base surface 221GS1 of the glass substrate 221GS, and a resist film PR2 is further formed in a solid state on the first metal film 221F6. After that, the resist film PR2 is exposed to light using an exposure device and a photomask PM2. The resist film PR2 used in the first step is made of a positive-type photosensitive resist material. Here, the photomask PM2 will be described. The photomask PM2 includes a transparent base material PM2A having sufficiently high light transmittance and a light-shielding film PM2B formed on the main surface of the base material PM2A. The light-shielding film PM2B blocks exposure light from a light source of the exposure device and has a partial opening PM2C. In the photomask PM2, the area where the light shielding film PM2B is formed is a light shielding area that blocks light, and the area where the opening PM2C is formed (the area where the light shielding film PM2B is not formed) is a light transmitting area that transmits light. The light shielding film PM2B is provided so as to overlap the multiple first extraction wirings 41α.

[0065] In the first step, when the exposure light emitted from the light source of the exposure tool is irradiated onto the resist film PR2 through the photomask PM2 configured as described above, the area of ​​the resist film PR2 overlapping with the light-shielding film PM2B is not exposed, and the area of ​​the resist film PR2 overlapping with the opening PM2C is selectively exposed. When development is performed following exposure, as shown in Fig. 17, the exposed portion of the positive resist film PR2 is removed because it is dissolved by the developer at a high rate, that is, its dissolution rate is high. On the other hand, the dissolution rate of the unexposed portion is slower, so it remains.

[0066] After the resist film PR2 is patterned as described above, the first metal film 221F6 is etched using the resist film PR2 as a mask, as shown in FIG. 17. At this time, either wet etching using an etching solution or dry etching using vacuum discharge plasma can be performed. When the first metal film 221F6 is patterned by etching the first metal film 221F6, a film portion 42 having a forward tapered cross-sectional shape in the X-axis direction is provided, as shown in FIG. 18. The forward tapered film portion 42 thus provided has a first surface 42A in contact with the base surface 221GS1 of the glass substrate 221GS, a second surface 42B located on the opposite side to the first surface 42A and having a larger dimension in the X-axis direction than the first surface 42A, and a third surface 42C oriented toward the base surface 221GS1. Thereafter, the resist film PR2 remaining on the film portion 42 is peeled off.

[0067] In the second step, as shown in FIG. 19, the gate insulating film 221F1 is formed in a solid shape on the film portion 42 and the base surface 221GS1. The formed gate insulating film 221F1 includes a portion disposed on the second surface 42B, the third surface 42C, and the fourth surface 42D of the film portion 42, and a portion disposed on the base surface 221GS1, and the former of these has a cross-sectional shape following the film portion 42. Subsequently, in the third step, the second metal film 221F7 is formed in a solid shape on the gate insulating film 221F1. The formed second metal film 221F7 is parallel to the gate insulating film 221F1, and the portion disposed on the portion of the gate insulating film 221F1 that lies on the film portion 42 has a cross-sectional shape following the film portion 42.

[0068] Then, in the third step, as shown in FIG. 20, the second metal film 221F7 is directly etched without a predetermined mask. That is, in the conventional method, a resist film is formed on the second metal film 221F7, and the second metal film 221F7 is etched using the resist film patterned by an exposure device or the like as a mask. In contrast, in this embodiment, the entire second metal film 221F7 is etched without the need for such a patterned resist film. At this time, it is preferable to perform dry etching using vacuum discharge plasma, but wet etching using an etching solution may also be used. When etching is performed, the parts of the second metal film 221F7 that are arranged on the third surface 42C and the fourth surface 42D of the film part 42 through the gate insulating film 221F1 are selectively left without being removed by etching because they have a greater height in the Z-axis direction than the other parts. The first conductive part 43 arranged on the third surface 42C and the second conductive part 44 arranged on the fourth surface 42D are provided by the remaining parts. In this way, when providing the first conductive portion 43 and the second conductive portion 44 made of the second metal film 221F7, there is no need to pattern a resist film as in the conventional method, and therefore the density of the first conductive portion 43 and the second conductive portion 44 does not depend on the pattern of the resist film as in the conventional method. Therefore, according to this embodiment, the arrangement density of the first conductive portion 43 and the second conductive portion 44 can be increased compared to the conventional method.

[0069] As described above, the array substrate 221 of the present embodiment includes a glass substrate (base portion) 221GS, a film portion 42 disposed on a base surface 221GS1 of the glass substrate 221GS, and a first surface 42A in contact with the base surface 221GS1, a second surface 42B located on the opposite side to the first surface 42A and having a dimension smaller or equal to that of the first surface 42A in a first direction along the base surface 221GS1, and a second surface 42B extending from the first surface 42A side to the second surface 42B side. The film portion 42 has a third surface 42C rising from the first surface 42A toward the second surface 42B, and a fourth surface 42D located on the opposite side of the third surface 42C in the first direction and rising from the first surface 42A toward the second surface 42B, a first conductive portion 43 arranged on the third surface 42C of the film portion 42 and made of a second metal film (conductive film) 221F7, and a second conductive portion 44 arranged on the fourth surface 42D of the film portion 42 and made of a portion of the second metal film 221F7 other than the first conductive portion 43.

[0070] The second surface 42B of the film portion 42 is smaller or equal in size to the first surface 42A in the first direction along the base surface 221GS1. Therefore, when the second metal film 221F7 formed on the film portion 42 during manufacturing is etched, the portions of the second metal film 221F7 arranged on the third surface 42C and the fourth surface 42D rising from the first surface 42A side toward the second surface 42B side are selectively left, and the first conductive portion 43 and the second conductive portion 44 are provided by these portions. In this way, the density of the first conductive portion 43 and the second conductive portion 44 does not depend on the pattern of the resist film as in the conventional case, so that a higher density arrangement than in the conventional case can be realized.

[0071] Also, there is provided a gate insulating film (insulating film) 221F1 arranged between the film portion 42 and the second metal film 221F7, the film portion 42 being made of a conductive material, and the first conductive portion 43 and the second conductive portion 44 being arranged on the gate insulating film 221F1. Signals and the like can be transmitted by the film portion 42 made of a conductive material. The gate insulating film 221F1 is interposed between the film portion 42 made of a conductive material and the first conductive portion 43 and the second conductive portion 44, thereby ensuring electrical independence from each other.

[0072] Further, the manufacturing method of the array substrate 221 of this embodiment includes forming a first metal film (film) 221F6 on the base surface 221GS1 of the glass substrate 221GS, patterning the first metal film 221F6 to form a film portion 42 arranged on the base surface 221GS1, the film portion 42 including a first surface 42A in contact with the base surface 221GS1, a second surface 42B located on the opposite side to the first surface 42A and having a dimension smaller or equal to that of the first surface 42A in a first direction along the base surface 221GS1, and a third surface 42B rising from the first surface 42A side toward the second surface 42B side. A film portion 42 is provided having a first surface 42C and a fourth surface 42D located on the opposite side of the third surface 42C in the first direction from the first surface 42A and rising from the first surface 42A toward the second surface 42B, and a first transparent electrode film (conductive film) 21F4 is formed on the film portion 42, and the second metal film 221F7 is etched to provide a first conductive portion 43 arranged on the third surface 42C of the film portion 42 by a part of the second metal film 221F7, and a second conductive portion 44 arranged on the fourth surface 42D of the film portion 42 by a part of the second metal film 221F7 other than the first conductive portion 43.

[0073] The film portion 42 is provided by patterning the first metal film 221F6 formed on the base surface 221GS1, and the second surface 42B has a dimension in the first direction along the base surface 221GS1 that is smaller than or equal to the first surface 42A. Therefore, when the second metal film 221F7 formed on the film portion 42 is etched, the portion of the second metal film 221F7 arranged on the third surface 42C of the film portion 42 and the portion arranged on the fourth surface 42D of the film portion 42 are selectively left, and the first conductive portion 43 and the second conductive portion 44 are provided by these portions. In this way, the density of the first conductive portion 43 and the second conductive portion 44 does not depend on the pattern of the resist film as in the conventional case, so that a higher density arrangement than in the conventional case can be realized.

[0074] <Embodiment 4> A fourth embodiment will be described with reference to Fig. 21. In this fourth embodiment, a configuration of a membrane part 342 is changed from that of the third embodiment. Note that a duplicated description of the structure, action, and effect similar to those of the third embodiment will be omitted.

[0075] As shown in FIG. 21, the film part 342 according to this embodiment is made of a gate insulating film 321F1. That is, the film part 342 is made of an insulating material. Accordingly, in this embodiment, the multiple lead-out wirings 341 are made of a first conductive part 343 and a second conductive part 344. The first conductive part 343 is disposed so as to be directly placed on the third surface 342C of the film part 342, and the second conductive part 344 is disposed so as to be directly placed on the fourth surface 342D of the film part 342. Even with this configuration, the same actions and effects as those of the third embodiment can be obtained.

[0076] <Embodiment 5> A fifth embodiment will be described with reference to Fig. 22. In the fifth embodiment, the configuration of the film portion 436 described in the first embodiment is changed, and the lead-out wiring 441 described in the third embodiment is configured using the first conductive portion 437 and the second conductive portion 438 described in the first embodiment. Note that a duplicated description of the structure, action, and effect similar to those of the first and third embodiments will be omitted.

[0077] As shown in FIG. 22, the film portion 436, the first conductive portion 437, and the second conductive portion 438 according to this embodiment are arranged in the non-display area NAA of the array substrate 421, and among them, the first conductive portion 437 and the second conductive portion 438 constitute the lead-out wiring 441 described in the third embodiment (see FIG. 13). The film portion 436 is arranged on the base surface 421GS1 of the glass substrate (base portion) 421GS, and is made of the gate insulating film 421F1. That is, the film portion 436 is made of an insulating material. The first conductive portion 437 is arranged adjacent to the film portion 436 on the base surface 421GS1 of the glass substrate 421GS, and is made of a part of the second metal film. The first conductive portion 437 constitutes the fourth lead-out wiring 441δ included in the plurality of lead-out wirings 441. The second conductive portion 438 is arranged on the second surface 436B of the film portion 436, and is made of a part of the second metal film other than the first conductive portion 437. The second conductive portion 438 is included in the plurality of lead-out wirings 441 and constitutes a fifth lead-out wiring 441ε separate from the fourth lead-out wiring 441δ. In this way, the film portion 436 is made of an insulating material, so that the conductivity of the first conductive portion 437 and the second conductive portion 438 are equivalent. Therefore, the wiring resistance of the fourth lead-out wiring 441δ constituted by the first conductive portion 437 and the fifth lead-out wiring 441ε constituted by the second conductive portion 438 are equivalent. This makes it difficult for a difference to occur in the dullness that may occur between the image signal transmitted by the fourth lead-out wiring 441δ and the image signal transmitted by the fifth lead-out wiring 441ε. Even with this configuration, the same actions and effects as those of the first and third embodiments described above can be obtained.

[0078] As described above, according to this embodiment, the film portion 436 is made of an insulating material. In this way, the conductivity of the first conductive portion 437 and the second conductive portion 438 becomes equivalent. Therefore, when a signal is transmitted by the first conductive portion 437 and the second conductive portion 438, for example, a difference in dullness that may occur between the signal transmitted by the first conductive portion 437 and the signal transmitted by the second conductive portion 438 is unlikely to occur.

[0079] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0080] (1) In the configurations described in the first, second and fifth embodiments, the membrane portion 36, 136, 436 may be configured so that the third surface 36C is substantially parallel to the base surface 21F2S, 121F2S and the first surface 36A, 136A.

[0081] (2) In the configurations described in the third and fourth embodiments, the dimension in the X-axis direction of the second surface 42B of the membrane portion 42, 342 may be equal to the dimension in the X-axis direction of the first surface 42A. In this case, the cross-sectional shape of the membrane portion 42, 342 in the X-axis direction is rectangular, and the third surface 42C, 342C and the fourth surface 42D, 342D are approximately perpendicular to the base surface 221GS1 in the X-axis direction.

[0082] (3) In the configurations described in the first, second and fifth embodiments, the second conductive portion 38, 438 may not have the hanging portion 38A.

[0083] (4) In the configurations described in the first and second embodiments, the wiring other than the touch wiring 30 may be formed by the film portions 36, 136 and the second conductive portion .

[0084] (5) In the configurations described in the first and second embodiments, electrodes and wiring other than the pixel electrode 25 can also be formed from the first conductive portion 37.

[0085] (6) In the configurations described in the first and second embodiments, the first conductive portion 37 and the second conductive portion 38 can be made of a metal material (metal film). In that case, it is also possible to configure wiring using the film portions 36, 136 and the first conductive portion 37, and to configure another wiring using the second conductive portion 38. It is also possible to configure the film portions 36, 136 using an insulating material, and to configure wiring using the first conductive portion 37 made of a metal material.

[0086] (7) In the configurations described in the first and second embodiments, the common electrode 28 may be of a non-divided configuration, and the liquid crystal panel 11 may not have a built-in touch panel function. In that case, instead of the touch wiring 30, a common wiring that supplies a common signal to the common electrode 28 may be formed by the film portions 36, 136 and the second conductive portion 38.

[0087] (8) In the configurations described in embodiments 3 to 5, the extraction wiring 41, 341, 441 connected to wiring other than the source wiring 227 (e.g., the gate wiring 26, etc.) can also be composed of any of the film portion 42, 342, the first conductive portion 43, 343, and the second conductive portion 44, 344.

[0088] (9) In the configurations described in embodiments 3 to 5, wiring other than the lead-out wiring 41, 341, 441 (e.g., gate wiring 26, source wiring 227, etc.) can also be formed from any of the film portion 42, 342, the first conductive portion 43, 343, and the second conductive portion 44, 344.

[0089] (10) The base portion may be something other than the first interlayer insulating film 21F2 and the glass substrate 221GS, 421GS.

[0090] (11) The resist films PR1 and PR2 may be of a negative type instead of a positive type.

[0091] (12) The planar shape of the liquid crystal panel 11, 211 may be a vertically long rectangle, a square, a circle, a semicircle, an oval, an ellipse, a trapezoid, or the like.

[0092] (13) The liquid crystal panels 11 and 211 may be of a reflective or semi-transmissive type other than a transmissive type.

[0093] (14) A display panel other than the liquid crystal panel 11, 211 (such as an organic electroluminescence (EL) display panel) may be used. [Explanation of symbols]

[0094] 21,121,221,321,421...array substrate (substrate), 21F2...first interlayer insulating film (base portion), 21F2S,121F2S...base surface, 21F3,121F3...third metal film (film), 21F4...first transparent electrode film (conductive film), 25...pixel electrode, 30...touch wiring (wiring), 36,136,436...film portion, 36A,136A...first surface, 36B,136B,436B...second surface, 37,437...first conductive portion, 37A...overlapping portion, 38,438...second conductive portion, 38A...hanging portion, 39...third 1 film portion, 40... second film portion, 42, 342... film portion, 42A... first surface, 42B... second surface, 42C, 342C... third surface, 42D, 342D... fourth surface, 43, 343... first conductive portion, 44, 344... second conductive portion, 121F3A... first film, 121F3B... second film, 221GS, 421GS... glass substrate (base portion), 221GS1, 421GS1... base surface, 221F1, 321F1, 421F1... gate insulating film (insulating film), 221F6... first metal film (film), 221F7... second metal film (conductive film)

Claims

1. A base portion; a membrane portion disposed on a base surface of the base portion, the membrane portion having a first surface in contact with the base surface and a second surface located on the opposite side to the first surface and having a dimension in a first direction along the base surface larger than that of the first surface; a first conductive portion arranged adjacent to the film portion on the base surface and made of a conductive film; a second conductive portion disposed on the second surface of the film portion and consisting of a portion of the conductive film separate from the first conductive portion.

2. the second conductive portion has a hanging portion hanging down from the second surface side toward the base surface side, The substrate according to claim 1 , wherein the first conductive portion has an overlapping portion that overlaps the hanging portion in a plan view.

3. 3. The substrate according to claim 1, wherein the film portion is made of a conductive material.

4. The pixel electrode includes wiring and a pixel electrode. the conductive film is made of a transparent electrode material, The film portion is made of a metal material, the film portion and the second conductive portion constitute the wiring, The substrate according to claim 3 , wherein the first conductive portion constitutes the pixel electrode.

5. 3. The substrate according to claim 1, wherein the film portion is made of an insulating material.

6. 3. The substrate according to claim 1, wherein the film portion comprises a first film portion having the first surface and made of a first material, and a second film portion arranged on the first film portion, having the second surface, and made of a second material having a lower etching rate than the first material.

7. A base portion; a film portion disposed on a base surface of the base portion, the film portion having a first surface in contact with the base surface, a second surface located on the opposite side to the first surface and having a dimension equal to or smaller than the first surface in a first direction along the base surface, a third surface rising from the first surface side toward the second surface side, and a fourth surface located on the opposite side to the third surface in the first direction and rising from the first surface side toward the second surface side; a first conductive portion arranged on the third surface of the film portion and made of a conductive film; a second conductive portion disposed on the fourth surface of the film portion and consisting of a portion of the conductive film separate from the first conductive portion.

8. an insulating film disposed between the film portion and the conductive film, The film portion is made of a conductive material, The substrate according to claim 7 , wherein the first conductive portion and the second conductive portion are disposed on the insulating film.

9. forming a film on a base surface of a base portion, and patterning the film to provide a film portion disposed on the base surface, the film portion having a first surface in contact with the base surface and a second surface located on the opposite side to the first surface and having a dimension in a first direction along the base surface larger than that of the first surface; A method for manufacturing a substrate, comprising: forming a conductive film on the film portion; providing a first conductive portion arranged adjacent to the film portion on the base surface using a portion of the conductive film; and providing a second conductive portion arranged on the second surface of the film portion using a portion of the conductive film other than the first conductive portion.

10. As the film, a first film made of a first material and a second film made of a second material having an etching rate lower than that of the first material are sequentially formed on the base surface; 10. A method for manufacturing a substrate as described in claim 9, wherein the first film and the second film are etched to provide the film portion consisting of a first film portion having the first surface made of a remaining portion of the first film, and a second film portion having the second surface made of a remaining portion of the second film.

11. a film is formed on a base surface of a base portion, and the film is patterned to provide a film portion disposed on the base surface, the film portion having a first surface in contact with the base surface, a second surface located on the opposite side to the first surface and having a dimension equal to or smaller than that of the first surface in a first direction along the base surface, a third surface rising from the first surface side toward the second surface side, and a fourth surface located on the opposite side to the third surface in the first direction and rising from the first surface side toward the second surface side; A method for manufacturing a substrate, comprising: depositing a conductive film on the membrane portion; and etching the conductive film to provide a first conductive portion arranged on the third surface of the membrane portion by a portion of the conductive film; and providing a second conductive portion arranged on the fourth surface of the membrane portion by a portion of the conductive film other than the first conductive portion.

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