Semiconductor storage device and manufacturing method of semiconductor storage device

Abstract

To suppress a short circuit failure at a contact even when the contact contacts with a dummy pillar.SOLUTION: A semiconductor storage device comprises: a laminate in which a plurality of first conductive layers and a plurality of first insulation layers are alternately laminated one layer by one layer, and that has a step part having the plurality of first conductive layers processed in step-wise; a contact that is arranged in the step part and is connected to any of the plurality of first conductive layers; and a first pillar that is extended in a lamination direction of the laminate within the laminate being slipped off the step part, and forms each memory cell at an intersection part with at least one portion of the plurality of first conductive layers. The contact reaches to the first conductive layer of a connection target by penetrating through a second conductive layer which is arranged above the first conductive layer being the connection target of the contact, of the plurality of first conductive layers.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device. [Background technology]

[0002] In semiconductor memory devices such as 3D non-volatile memories, memory cells are formed in a three-dimensional structure in which multiple conductive layers are stacked. In order to extract these conductive layers, multiple contacts are arranged to be connected to the stepped portions of the multiple conductive layers. In addition, multiple dummy pillars are arranged in the stack to support the stack. If contact occurs between these contacts and the dummy pillars, a short circuit may occur in the contacts. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-042874 A [Patent Document 2] JP 2019-153693 A [Patent Document 3] JP 2016-046439 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can suppress short-circuit defects at a contact even when the contact comes into contact with a dummy pillar. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment includes a stack having a staircase portion in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one layer at a time, and the plurality of first conductive layers are processed into a staircase shape, a contact arranged in the staircase portion and connected to one of the plurality of first conductive layers, and a first pillar extending in the stacking direction of the stack outside the staircase portion within the stack and forming a memory cell at each intersection with at least a portion of the plurality of first conductive layers, and the contact penetrates a second conductive layer of the plurality of first conductive layers that is arranged above a first conductive layer to be connected to the contact, and reaches the first conductive layer to be connected. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing an example of a schematic configuration of a semiconductor memory device according to an embodiment. [Diagram 2] 1 is a cross-sectional view showing an example of a configuration of a semiconductor memory device according to an embodiment. [Diagram 3] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 4] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Diagram 5] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 6] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 7] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 8] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 9] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 10] 1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 11]1A to 1C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to an embodiment. [Figure 12] 11 is an enlarged cross-sectional view taken along the X direction illustrating details of a process for forming a contact in the semiconductor memory device according to the embodiment. FIG. [Figure 13] 11 is an enlarged cross-sectional view taken along the X direction illustrating details of a process for forming a contact in the semiconductor memory device according to the embodiment. FIG. [Figure 14] 11 is an enlarged cross-sectional view taken along the X direction illustrating details of a process for forming a contact in the semiconductor memory device according to the embodiment. FIG. [Figure 15] 11 is an enlarged cross-sectional view taken along the X direction illustrating a process for forming a contact of a semiconductor memory device according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiment. In addition, the components in the following embodiment include those that a person skilled in the art can easily imagine or that are substantially the same.

[0008] (Example of the configuration of a semiconductor memory device) 1 is a cross-sectional view showing an example of a schematic configuration of a semiconductor memory device 1 according to an embodiment, in which hatching is omitted for ease of viewing.

[0009] As shown in FIG. 1, the semiconductor memory device 1 includes a semiconductor substrate SB on which, in this order from the bottom of the page, an electrode film EL, a source line SL, a plurality of word lines WL, and a peripheral circuit CBA are provided.

[0010] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and the source line SL and the electrode film EL are electrically connected to each other via the plugs PG. Although not shown, electrode pads for supplying power and signals from outside to the semiconductor memory device 1 are provided in the same layer as the electrode film EL. A plurality of word lines WL are stacked on the source line SL.

[0011] A memory region MR is arranged in the center of the word lines WL in the layer direction, and staircase regions SR are arranged at both ends of the word lines WL.

[0012] In the memory region MR, a plurality of pillars PL are arranged, which penetrate the plurality of word lines WL in the stacking direction. The lower ends of the pillars PL reach the source lines SL. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. This configures the semiconductor memory device 1 as, for example, a three-dimensional non-volatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0013] In the staircase region SR, the word lines WL are processed in a staircase shape and terminate in the staircase region SR. At this time, as the word lines WL constituting the terrace portion move from the upper layer side to the lower layer side as they move away from the memory region MR, the height position of the terrace portion decreases toward the source line SL side.

[0014] Contacts CC connected to the word lines WL of each layer are disposed on the terraces of each stage formed by the word lines WL. The word lines WL stacked in multiple layers are individually drawn out by these contacts CC.

[0015] More specifically, a write voltage, a read voltage, etc. are applied from these contacts CC to a memory cell included in a memory region MR in the center of the plurality of word lines WL via a word line WL at the same height as the memory cell.

[0016] The word lines WL, the pillars PL, and the contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around these structures.

[0017] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. A peripheral circuit CBA including transistors TR and wiring is arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cells from the contacts CC are controlled by the peripheral circuit CBA electrically connected to these contacts CC. In this way, the peripheral circuit CBA controls the electrical operation of the memory cells.

[0018] The peripheral circuit CBA is covered with an insulating layer 40, and this insulating layer 40 is joined to an insulating layer 50 that covers a plurality of word lines WL, etc., to form a semiconductor memory device 1 including a configuration of a plurality of word lines WL, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0019] Next, a detailed configuration example of the semiconductor memory device 1 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0020] More specifically, Fig. 2(a) is a cross-sectional view along the Y direction in a memory region MR of the semiconductor memory device 1. Fig. 2(b) is a cross-sectional view along the X direction in a staircase region SR of the semiconductor memory device 1. Structures below an insulating layer 60 and above an insulating layer 53, which will be described later, are omitted in Figs. 2(a) and 2(b).

[0021] FIG. 2(c) is an enlarged cross-sectional view of a pillar PL at the height position of an arbitrary word line WL.

[0022] In this specification, both the X direction and the Y direction are directions along the direction of the plane of the word lines WL, and the X direction and the Y direction are perpendicular to each other. The direction in which the word lines WL are electrically drawn out may be called the first direction, and this first direction is along the X direction. The direction intersecting the first direction may be called the second direction, and this second direction is along the Y direction. However, since the semiconductor memory device 1 may include manufacturing errors, the first direction and the second direction are not necessarily perpendicular to each other.

[0023] In addition, in this specification, the direction in which the terrace surface of the word line WL of each step in the staircase region SR faces is defined as the upward direction in the semiconductor memory device 1.

[0024] 2(a), the source line SL has a multi-layer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are stacked in this order on an insulating layer 60. The intermediate source line BSL is disposed below the memory region MR of the stack LM.

[0025] The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers, etc. Among them, at least the intermediate source line BSL may be a conductive polysilicon layer or the like in which impurities are diffused.

[0026] The source line SL is connected to the peripheral circuit CBA via the electrode film EL by a through contact (not shown) that extends through the insulating layer 50 on the outside of the laminate LM from the electrode film EL to the peripheral circuit CBA.

[0027] A laminated body LM is disposed on the source line SL. The laminated body LM includes laminated bodies LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated one by one.

[0028] The stacked body LMa is disposed above the source line SL. One or more select gate lines may be disposed below the word line WL in the lowest layer of the stacked body LMa. The stacked body LMb is disposed on the stacked body LMa. One or more select gate lines may be disposed above the word line WL in the top layer of the stacked body LMb.

[0029] The number of stacked word lines WL and select gate lines in the laminate LM is arbitrary. The word lines WL and select gate lines as the first conductive layer are, for example, a tungsten layer or a molybdenum layer. The insulating layer OL as the first insulating layer is, for example, a silicon oxide layer.

[0030] The upper surface of the laminate LM is covered with an insulating layer 52. The insulating layer 52 is covered with an insulating layer 53. The insulating layers 52 and 53, together with an insulating layer 51 described below, each constitute a part of the insulating layer 50 shown in FIG.

[0031] As described above, the multilayer body LM is divided in the Y direction by a plurality of plate-shaped contacts LI. That is, the plate-shaped contacts LI are aligned in the Y direction and extend in the stacking direction and the X direction of the multilayer body LM.

[0032] In this way, the plate contact LI extends continuously in the stack LM from one end to the other end in the X direction of the stack LM. The plate contact LI also passes through the stack LM and the upper source line DSLb, and reaches the intermediate source line BSL in the memory region MR.

[0033] Each of the plate-shaped contacts LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer, etc. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer, etc.

[0034] The insulating layer 54 covers side walls of the plate-shaped contacts LI facing each other in the Y direction. The conductive layer 24 is filled inside the insulating layer 54 and is electrically connected to the source lines SL including the intermediate source lines BSL. However, instead of the plate-shaped contacts LI, a plate-shaped member filled with an insulating layer may penetrate the laminate LM and extend in the X direction to divide the laminate LM in the Y direction.

[0035] In the memory region MR, a plurality of pillars PL are distributed and arranged, penetrating the stacked body LM, the upper source line DSLb, and the intermediate source line BSL to reach the lower source line DSLa.

[0036] The pillars PL as the multiple first pillars are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape, for example, a circular, elliptical, or oval shape in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0037] The pillar PL has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side at a portion penetrating the laminate LMa and at a portion penetrating the laminate LMb. Alternatively, the pillar PL has a bowing shape in which the diameter and cross-sectional area are maximum at a predetermined position between the upper layer side and the lower layer side at a portion penetrating the laminate LMa and at a portion penetrating the laminate LMb.

[0038] Each of the multiple pillars PL has a memory layer ME extending in the stacking direction within the stack LM, a channel layer CN penetrating the stack LM and connecting to an intermediate source line BSL, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR that serves as the core material of the pillar PL.

[0039] As shown in FIG. 2(c), the memory layer ME has a multi-layer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order from the outer periphery of the pillar PL. More specifically, the memory layer ME is disposed on the side surface of the pillar PL except for the depth position of the intermediate source line BSL. The memory layer ME is also disposed on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0040] The channel layer CN penetrates the stacked body LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, and reaches the depth of the lower source line DSLa. More specifically, the channel layer CN is disposed on the side and bottom surface of the pillar PL via the memory layer ME. However, a part of the channel layer CN contacts the intermediate source line BSL on the side, and is thereby electrically connected to the source line SL including the intermediate source line BSL. A core layer CR is filled further inside the channel layer CN.

[0041] Each of the pillars PL has a cap layer CP at its upper end. The cap layer CP is disposed at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN, and is connected to the channel layer CN. The cap layer CP is also connected to a bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stack LM in the Y direction so as to intersect with the lead-out direction of the word line WL.

[0042] In Fig. 2(a), a plug CH is connected to only one of the six pillars PL. The remaining pillars PL are connected to other bit lines BL extending in the Y direction parallel to the bit lines BL shown in Fig. 2(a) at positions different from the cross section shown in Fig. 2(a) via plugs CH not shown in Fig. 2(a).

[0043] The block insulating layer BK and the tunnel insulating layer TN of the memory layer ME, and the core layer CR are, for example, silicon oxide layers, etc. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer, etc. The channel layer CN and the cap layer CP are, for example, semiconductor layers such as a polysilicon layer or an amorphous silicon layer.

[0044] As shown in Fig. 2(c), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL facing each word line WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0045] In addition, when the stack LM has select gate lines above and below the word line WL, select gates are formed in the portions facing these select gate lines, and when a predetermined voltage is applied from the select gate lines, the select gates are turned on or off, so that the memory cells MC of the pillar PL to which the select gates belong can be selected or unselected.

[0046] As shown in Fig. 2(b), the staircase region SR has a staircase portion SCP in which the word lines WL are processed in a staircase shape. Fig. 2(b) shows some of the word lines WL processed in a staircase shape.

[0047] A stopper layer SPs is disposed on the staircase portion SCP as a second insulating layer that covers the staircase portion SCP so as to conform to the staircase shape of the staircase portion SCP. In addition, a stopper layer SPw is disposed on the terrace surface of each step of the staircase portion SCP via the stopper layer SPs as a second conductive layer.

[0048] At this time, the stopper layer SPs is disposed on the step surface of each step of the staircase portion SCP, and the stopper layer SPw is not disposed on the step surface, so that, for example, the word line WL having the end processed in a stepped shape on the step surface and the stopper layer SPw on the terrace surface of the step below it are prevented from coming into contact with each other and becoming electrically conductive therebetween.

[0049] The staircase portion SCP is further covered with an insulating layer 51 via these stopper layers SPs and SPw. The insulating layer 51 as the third insulating layer reaches, for example, the height position of the uppermost layer of the laminate LM, and the insulating layers 52 and 53 also cover the upper surface of the insulating layer 51. As described above, the insulating layer 51 also constitutes a part of the insulating layer 50 in FIG.

[0050] Here, the stopper layer SPs and the insulating layer 51 are, for example, silicon oxide layers, etc. The stopper layer SPw is, for example, a tungsten layer or a molybdenum layer, etc., similar to the above-mentioned word line WL.

[0051] In the staircase region SR, the source line SL includes an intermediate insulating layer SCO interposed between the upper source line DSLb and the lower source line DSLa instead of the intermediate source line BSL. The intermediate insulating layer SCO is, for example, a silicon oxide layer.

[0052] Therefore, in the staircase region SR, the plate-shaped contact LI penetrates the insulating layer 51, the stacked body LM, and the upper source line DSLb to reach the intermediate insulating layer SCO.

[0053] In addition, a plurality of contacts CC and a plurality of columnar parts HR are arranged in the staircase region SR. As described later, these columnar parts HR have a role of supporting the components when the laminate LM is formed from a laminate in which a sacrificial layer and an insulating layer are laminated, and do not contribute to the function of the semiconductor memory device 1.

[0054] Each contact CC penetrates the insulating layer 51 and the stopper layers SPw, SPs and is connected to a word line WL immediately below the insulating layer OL that constitutes the terrace surface of each step of the staircase portion SCP.

[0055] Each contact CC has an extension CCp extending through the insulating layer 51 and a bottom end CCe including a portion penetrating the stopper layers SPw and SPs. The outer shape of the bottom end CCe is larger than the outer shape of the extension CCp. That is, the contact CC has an expanded diameter at the bottom end CCe. The contact CC has a conductive layer 25 such as a tungsten layer or a copper layer, and the conductive layer 25 extends continuously from the extension CCp to the bottom end CCe.

[0056] At this time, the stopper layer SPw through which the contact CC penetrates is electrically connected to the word line WL to which the contact CC is connected via the lower end CCe of the contact CC. However, as described above, the stopper layer SPw is not in contact with the word line WL other than the word line WL to which the contact CC is connected, including the word line WL having its end on the step surface one level above the terrace surface on which the stopper layer SPw is disposed. Therefore, no problems in electrical characteristics, such as a short circuit between multiple word lines WL via the stopper layer SPw, occur.

[0057] The conductive layer 25 of each contact CC is connected to an upper-layer wiring MX arranged in an insulating layer 53 via a plug V0 arranged in an insulating layer 52. This upper-layer wiring MX is electrically connected to the above-mentioned peripheral circuit CBA (see FIG. 1).

[0058] With this configuration, the word lines WL of each layer can be electrically drawn out from both ends of the laminate LM in the X direction. That is, with the above configuration, a predetermined voltage can be applied from the peripheral circuit CBA to the memory cells MC via the upper layer wiring MX, the contacts CC, the word lines WL, etc., to operate the memory cells MC as memory elements.

[0059] The columnar portion HR as a second pillar passes through the stepped stacked bodies LMb, LMa, the upper source line DSLb, and the intermediate insulating layer SCO, and reaches the lower source line DSLa.

[0060] More specifically, each columnar portion HR extends from each terrace surface of the stepped portion SCP through the word lines WL and insulating layers OL below the terrace surfaces into the laminate LM. Therefore, the dimension of the columnar portion HR in the extension direction decreases from the portion where the word lines WL on the upper layer side are processed in a stepped shape to the portion where the word lines WL on the lower layer side are processed in a stepped shape.

[0061] These columnar portions HR are distributed over the entire stepped portion SCP and are arranged, for example, in a grid or staggered pattern when viewed from the stacking direction of the laminate LM. Each columnar portion HR has a cross-sectional shape along the XY plane that is, for example, circular, elliptical, or oval.

[0062] Taking the example of the columnar portion HR penetrating the relatively upper word line WL, the columnar portion HR has a tapered shape in which the diameter and cross-sectional area decrease from the upper side to the lower side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb, or the columnar portion HR has a bowing shape in which the diameter and cross-sectional area are maximum at a predetermined position between the upper side and the lower side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb.

[0063] The entire columnar portion HR is a single insulating layer 56 such as a silicon oxide layer. In other words, the columnar portion HR is substantially composed of the insulating layer 56 of a single material. Here, being substantially a single material may include cases in which the element ratios of the components of the columnar portion HR are different within one columnar portion HR or between multiple columnar portions HR, and cases in which the types and amounts of impurities contained are different, and also allows the columnar portion HR of a single material to contain voids.

[0064] Since the columnar portion HR is thus a single piece of the insulating layer 56, it cannot have an electrical effect on other components, and interference with the adjacent plate-like contacts LI and contacts CC is permitted.

[0065] At the same height position of the laminate LM, the cross-sectional area of ​​the columnar portion HR in the direction along the XY plane is larger than, for example, the cross-sectional area of ​​the pillar PL in the direction along the XY plane. Also, the pitch between the multiple columnar portions HR is larger than, for example, the pitch between the multiple pillars PL, and the arrangement density of the columnar portions HR per unit area of ​​the word line WL in the laminate LM is lower than the arrangement density of the pillars PL per unit area of ​​the word line WL.

[0066] In this way, by configuring the pillars PL to have a smaller cross-sectional area and a narrower pitch than, for example, the columnar portions HR, a large number of memory cells MC can be formed at high density within the stack LM of a given size, thereby increasing the storage capacity of the semiconductor memory device 1. On the other hand, since the columnar portions HR are used exclusively to support the stack LM, the manufacturing load can be reduced by not configuring them with a precise structure having a small cross-sectional area and a narrow pitch like, for example, the pillars PL.

[0067] (Method of manufacturing semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described with reference to Figures 3 to 14. Figures 3 to 11 are diagrams illustrating, in order, some of the steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0068] 3 and 4 show the stacks LMsa and LMsb as the first stack, which is the stack LM before the word lines WL are formed, and how various components are formed in the stacks LMsa and LMsb. 3 and 4 are cross-sectional views along the X direction of the region that will later become the memory region MR and the staircase region SR.

[0069] As shown in FIG. 3(a), a lower source line DSLa, an intermediate sacrificial layer SCN or an intermediate insulating layer SCO, and an upper source line DSLb are formed in this order on a supporting substrate SS.

[0070] The support substrate SS may be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate, etc. The above-mentioned insulating layer 60 (see FIG. 2, etc.) may be formed on the upper surface side of the support substrate SS.

[0071] The intermediate sacrificial layer SCN is formed in a region on the support substrate SS that will later become the memory region MR, and the intermediate insulating layer SCO is formed in a region on the support substrate SS that will later become the staircase region SR. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL. As described above, the intermediate insulating layer SCO is, for example, a silicon oxide layer.

[0072] In addition, a laminate LMsa is formed on the upper source line DSLb, in which insulating layers NL as a plurality of first insulating layers and insulating layers OL as a plurality of second insulating layers are alternately laminated one by one. The insulating layers NL are, for example, silicon nitride layers, and function as sacrificial layers that are later replaced with a conductive material to become the word lines WL.

[0073] As shown in FIG. 3B, a plurality of memory holes MHa and a plurality of holes HLa extending in the stacking direction of the stacked body LMsa are formed, for example, at once. The memory holes MHa are parts that will later become the lower structure of the pillar PL. The holes HLa are parts that will later become the lower structure of the columnar portion HR.

[0074] As shown in FIG. 3(c), the memory holes MHa and holes HLa are filled with a sacrificial layer 26 such as an amorphous silicon layer or a CVD-carbon layer.

[0075] As a result, in the region that will later become the memory region MR, a pillar PLc is formed in which the memory holes MHa are filled with the sacrificial layer 26. Also, in the region that will later become the staircase region SR, a columnar portion HRc is formed in which the holes HLa are filled with the sacrificial layer 26.

[0076] 3(d), a laminate LMsb is formed by alternately stacking insulating layers NL as a plurality of first insulating layers and insulating layers OL as a plurality of second insulating layers, covering the laminate LMsa and the insulating layer 51 of the staircase portion. The insulating layers NL of the laminate LMsb are later replaced with conductive layers to become word lines WL.

[0077] As shown in Fig. 4(a), a plurality of memory holes MHb and a plurality of holes HLb extending in the stacking direction of the stacked body LMsb are formed, for example, at once. The memory holes MHb are portions that will later become the upper structure of the pillar PL. The holes HLb are portions that will later become the upper structure of the columnar portion HR.

[0078] The memory holes MHb are arranged in a region that will later become the memory region MR, and pass through the multilayer body LMsb to reach the upper ends of the pillars PLc formed in the multilayer body LMsa.

[0079] The holes HLb are arranged in a region that will later become the staircase region SR, and penetrate the insulating layer 51 and the multilayer body LMsb, each reaching the upper end of the columnar portion HRc formed in the multilayer body LMsa.

[0080] As shown in FIG. 4(b), the sacrificial layer 26 is removed from the pillar PLc and columnar portion HRc at the bottom of the memory hole MHb and the hole HLb.

[0081] As a result, a plurality of memory holes MH are formed, each of which opens at the bottom of a plurality of memory holes MHb, and which penetrate the stacked bodies LMsb and LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. Also, a plurality of holes HL are formed, each of which opens at the bottom of a plurality of holes HLb, and which penetrate the insulating layer 51, the stacked bodies LMsb and LMsa, the upper source line DSLb, and the intermediate insulating layer SCO to reach the lower source line DSLa.

[0082] In addition, when the sacrificial layer 26 filled in the pillars PLc and the columnar portions HRc is a CVD-carbon layer or the like, when the mask pattern, etc. used in the processing of FIG. 4(a) described above is removed by ashing using oxygen plasma or the like, the sacrificial layer 26 can be removed from these pillars PLc and columnar portions HRc all at once.

[0083] 4(c), the memory holes MH are covered with a mask layer such as a photoresist layer, and the holes HL are filled with an insulating layer 56 such as a silicon oxide layer, thereby forming columnar portions HR penetrating the stacks LMsa and LMsb.

[0084] Next, the manner in which the pillars PL are formed will be described with reference to FIGS.

[0085] 5 and 6 are cross-sectional views along the Y direction of a region that will later become the memory region MR, and show a cross section equivalent to the above-mentioned FIG. 2(a).

[0086] As shown in FIG. 5(a), in a region that will later become the memory region MR, a plurality of memory holes MH penetrating the stacked bodies LMsa and LMsb have already been formed.

[0087] As shown in Fig. 5(b), a multilayer insulating layer MEb, a semiconductor layer CNb, and an insulating layer CRb are formed in this order in the memory hole MH. As a result, the multilayer insulating layer MEb and the semiconductor layer CNb are disposed on the side surface of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, and the insulating layer CRb is filled in the center of the memory hole MH.

[0088] The multilayer insulating layer MEb is an insulating layer having a multilayer structure that will later become the memory layer ME. The semiconductor layer CNb is a layer that will later become the channel layer CN. The insulating layer CRb is a silicon oxide layer or the like that will later become the core layer CR.

[0089] The multilayer insulating layer MEb, the semiconductor layer CNb, and the insulating layer CRb are also formed in this order on the upper surface of the laminate LMsb.

[0090] As shown in FIG. 5(c), the insulating layer CRb, the semiconductor layer CNb, and the multilayer insulating layer MEb are sequentially etched back to remove them from the upper surface of the laminated body LMsb, and a recess DN is formed at the upper end of the memory hole MH.

[0091] As a result, in the memory hole MH, the memory layer ME, the channel layer CN, and the core layer CR are formed in this order from the outer periphery.

[0092] As shown in Fig. 6(a), a semiconductor layer CPb is formed in the recess DN at the upper end of the memory hole MH. The semiconductor layer CPb is a layer that will later become the cap layer CP. The semiconductor layer CPb is also formed on the upper surface of the stacked body LMsb.

[0093] As shown in FIG. 6(b), the semiconductor layer CPb on the upper surface of the laminated body LMsb is removed by CMP or the like, and a cap layer CP is formed on the upper end of the memory hole MH.

[0094] As shown in Fig. 6(c), an insulating layer OL is deposited on the topmost layer of the laminate LMsb that has been thinned by CMP, etc. This forms a pillar PL in which the cap layer CP is buried in the topmost insulating layer OL.

[0095] However, at this point, the memory layer ME covers the entire side wall of the pillar PL, and a portion of the side surface of the channel layer CN is not exposed from the memory layer ME.

[0096] In the region that will later become the staircase region SR, a plurality of columnar portions HR have already been formed, and the region is hardly affected by the processes in Figures 5 and 6. However, the upper ends of the columnar portions HR are also buried in the uppermost insulating layer OL by the processes in Figures 6(b) and (c).

[0097] Next, how the staircase structure and contacts CC are formed in the region that will later become the staircase region SR will be shown with reference to Figures 7 to 9. Figures 7 to 9 are cross-sectional views along the X direction of the region that will later become the staircase region SR.

[0098] 7(a), the insulating layers NL and OL are processed into a staircase shape in a region that will later become the staircase region SR. Such processing can be performed by repeating slimming of a mask pattern 72 such as a photoresist layer and etching of the insulating layers NL and OL sequentially exposed from the mask pattern 72 multiple times.

[0099] That is, a mask pattern is formed on the upper surface of the laminate LMsb, and the insulating layers NL and OL in the exposed portions are etched away one by one, for example. Then, the ends of the mask pattern are recessed by a process using oxygen plasma or the like to newly expose the upper surface of the laminate LMsb, and the insulating layers NL and OL are further etched away one by one. By repeating such a process multiple times, the above-mentioned stepped shape is first formed in the laminate LMsb.

[0100] 7(b), the repeated process of slimming the mask pattern 72 and etching the insulating layers NL and OL is continued for the laminated body LMsa as well, so that a staircase shape is formed in the laminated body LMsa as well.

[0101] 7(a) and 7(b), the columnar portions HR formed penetrating the laminates LMsa and LMsb are also etched away in parallel with the processing of each layer of the laminates LMsa and LMsb, thereby forming a plurality of columnar portions HR extending from each step-shaped terrace surface formed on the laminates LMsa and LMsb and penetrating the insulating layers NL and OL below these terrace surfaces.

[0102] 7(c), the stopper layers SPs and SPn are formed in this order so as to conform to the step shapes of the stacked bodies LMsa and LMsb. As described above, the stopper layer SPs is, for example, a silicon oxide layer. The stopper layer SPn as the third insulating layer is, for example, a silicon nitride layer, which will later be replaced by a tungsten layer or the like to become the stopper layer SPw described above.

[0103] As shown in Fig. 8(a), of the stopper layers SPn covering the staircase shapes of the laminates LMsa and LMsb, the stopper layers SPn on the step surfaces are removed while leaving the stopper layers SPn on the terrace surfaces. Such processing can be performed by a process using anisotropic etching such as RIE (Reactive Ion Etching).

[0104] As described above, the stopper layer SPn, which is a silicon nitride layer or the like, is formed with the stopper layer SPs, which is a silicon oxide layer or the like, interposed therebetween, and the stopper layer SPn is further removed from the step surface of the staircase shape, so that the stopper layer SPn on a specified terrace surface is included in the step one level above that terrace surface, and is prevented from coming into contact with the insulating layer NL, which is also a silicon nitride layer or the like.

[0105] As shown in FIG. 8(b), an insulating layer 51 is formed as a fourth insulating layer such as a silicon oxide layer, covering the staircase shape of the laminates LMsa, LMsb up to the height position of the unprocessed portions of the laminates LMsa, LMsb via stopper layers SPs, SPn.

[0106] 8(c), a plurality of contact holes CL are formed so as to penetrate the insulating layer 51 and reach the stopper layer SPn covering the terrace surface of each step. This processing can be performed by etching the insulating layer 51 under conditions that provide high selectivity between the insulating layer 51 containing different materials and the stopper layer SPn.

[0107] 9(a), the stopper layers SPn, SPs and the insulating layer OL exposed at the bottom of each contact hole CL are sequentially removed by, for example, wet etching, etc. More specifically, the bottom of the contact hole CL is treated with a remover for the stopper layer SPn, which is a silicon nitride layer or the like, and then the bottom of the contact hole CL is treated with a remover for the stopper layer SPs, which is a silicon oxide layer or the like, and the insulating layer OL.

[0108] As a result, a plurality of contact holes CL are obtained, each of which reaches the insulating layer NL located immediately below the terrace surface of each step. At this time, for example, by using wet etching as described above, the contact holes CL are obtained in which the outer shape of the lower end including the penetrating portion through the stopper layers SPn, SPs and the insulating layer OL is larger than the outer shape of the other portions.

[0109] As described above, the stopper layer SPn is formed with the stopper layer SPs interposed therebetween, and the stopper layer SPn is removed from the step faces of the staircase shape, which prevents the insulating layer NL having the ends on the step faces of each step from being removed during the wet etching process.

[0110] 9(b), a conductive layer 25 serving as a metal layer such as a tungsten layer is filled into each contact hole CL, thereby obtaining a plurality of contacts CC each having an extension portion CCp extending through the insulating layer 51 and a lower end portion CCe having a diameter larger than that of the extension portion CCp.

[0111] Next, the formation of the source lines SL and the word lines WL will be shown with reference to Figures 10 and 11. Figures 10 and 11 are cross-sectional views along the Y direction of a region that will later become the memory region MR, similar to Figures 5 and 6 described above.

[0112] 10A, a slit ST is formed so as to penetrate the stacked bodies LMsb, LMsa and the upper source line DSLb and reach the intermediate sacrificial layer SCN. Also, an insulating layer 54s is formed on the side walls of the slit ST facing each other in the Y direction.

[0113] The slits ST also extend in the stacks LMsa and LMsb in the direction along the X-direction. Therefore, in a region (not shown) that will later become the staircase region SR, the lower end of the slits ST reaches the intermediate insulating layer SCO.

[0114] As shown in FIG. 10(b), a removal solution for the intermediate sacrificial layer SCN, such as hot phosphoric acid, is poured through a slit ST whose sidewalls are protected by an insulating layer 54s to remove the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0115] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Also, a part of the memory layer ME on the outer periphery of the pillar PL is exposed in the gap layer GPs.

[0116] At this time, since the sidewalls of the slits ST are protected by the insulating layer 54s, the insulating layer NL in the stacks LMsa and LMsb is prevented from being removed as well. In addition, in the region that will later become the staircase region SR, there is no intermediate sacrificial layer SCN between the lower source line DSLa and the upper source line DSLb, and no gap layer GPs is formed.

[0117] As shown in Fig. 10(c), a chemical solution is appropriately poured into the gap layer GPs through the slit ST to sequentially remove the block insulating layer BK, the charge storage layer CT, and the tunnel insulating layer TN (see Fig. 2(c)) of the memory layer ME exposed in the gap layer GPs. As a result, the memory layer ME is removed from a part of the side wall of the pillar PL, and a part of the inner channel layer CN is exposed in the gap layer GPs.

[0118] 10(d), a raw material gas such as amorphous silicon is injected from the slit ST whose sidewall is protected by the insulating layer 54s, and the gap layer GPs is filled with amorphous silicon, etc. The support substrate SS is also heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, thereby forming an intermediate source line BSL including polysilicon, etc.

[0119] As a result, a part of the channel layer CN of the pillar PL is connected to the source line SL at the side surface via the intermediate source line BSL.

[0120] At this time, in the region that will later become the staircase region SR, the gap layer GPs is not formed between the lower source line DSLa and the upper source line DSLb, and therefore the intermediate source line BSL is not formed either.

[0121] As shown in FIG. 11(a), the insulating layer 54s on the side wall of the slit ST is temporarily removed.

[0122] 11(b), a remover for the insulating layer NL, such as hot phosphoric acid, is poured into the laminates LMsa and LMsb from the slits ST to remove the insulating layers NL of the laminates LMsa and LMsb. This forms the laminates LMga and LMgb having a plurality of gap layers GP from which the insulating layers NL between the insulating layers OL have been removed.

[0123] The laminated bodies LMga, LMgb, which include a plurality of gap layers GP, have a fragile structure. In the region that will later become the memory region MR, a plurality of pillars PL support the fragile laminated bodies LMga, LMgb. On the other hand, in the region that will later become the staircase region SR, a plurality of columnar parts HR support the laminated bodies LMga, LMgb.

[0124] Such a support structure of the pillars PL and the columnar portions HR prevents the remaining insulating layer OL from bending and the laminates LMga, LMgb from being distorted or collapsed.

[0125] In the region that will later become the staircase region SR, the slits ST also penetrate the stopper layer SPn formed on the terrace surface of each step of the staircase shape. Therefore, the above process also removes the stopper layer SPn, which is, for example, a silicon nitride layer, and a gap layer is formed in that portion.

[0126] 11(c), a source gas of a conductive material such as tungsten or molybdenum is injected into the laminates LMga, LMgb from the slits ST to fill the gap layers GP of the laminates LMga, LMgb with the conductive material to form a plurality of word lines WL, etc. This forms a laminate LM as a second laminate including laminates LMa, LMb in which a plurality of word lines WL, etc. and a plurality of insulating layers OL are alternately stacked one by one.

[0127] As described above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN and the process of forming the word line WL from the insulating layer NL are also called a replacement process.

[0128] In the region that will later become the staircase region SR, the conductive material is also filled into the gap layer that is generated by removing the stopper layer SPn through the slits ST, thereby forming the above-mentioned stopper layer SPw.

[0129] At this time, as described above, contact between the stopper layer SPn and the insulating layer NL of each stage is suppressed, so that the replaced stopper layer SPw is prevented from being electrically connected to the word line WL. Also, as described above, before replacing the stopper layer SPn, at least the contact hole CL is formed, so that the process of forming the contact CC is easier than, for example, forming the contact CC by penetrating the hard stopper layer SPw.

[0130] Thereafter, an insulating layer 54 is formed on the side wall of the slit ST, and the insulating layer 54 is filled with the conductive layer 24 to form the plate-like contact LI. However, the slit ST may be filled with the insulating layer 54 or the like without forming the conductive layer 24 to form a plate-like member.

[0131] An insulating layer 52 is formed on the upper surface of the insulating layer 51 covering the upper surface of the laminate LM and the staircase region SR, and a plug V0 is formed through the insulating layer 52 to be connected to the contact CC. A plug CH is formed through the insulating layer 52 to be connected to the pillar PL. An insulating layer 53 is further formed on the insulating layer 52, and upper layer wiring MX and bit lines BL, etc., connected to the plugs V0 and CH are formed. An electrode pad, etc., for electrical conduction with the peripheral circuit CBA is formed on the upper surface of the insulating layer 53.

[0132] Incidentally, the plugs V0 and CH, the upper layer wiring MX, the bit line BL, and the like may be formed collectively by using, for example, a dual damascene method.

[0133] Moreover, the peripheral circuit CBA is formed on a semiconductor substrate SB separate from the support substrate SS on which the laminate LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. that lead the peripheral circuit CBA to the surface of the insulating layer 40 are formed in the insulating layer 40, and are connected to electrode pads, etc. formed on the upper surface of the insulating layer 40.

[0134] Next, the support substrate SS and the semiconductor substrate SB are bonded together with their respective insulating layers 50, 40, and the electrode pads in the insulating layers 50, 40 are connected. Thereafter, the support substrate SS is removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 in which the plug PG is formed.

[0135] In this manner, the semiconductor memory device 1 of the embodiment is manufactured.

[0136] Here, the above-mentioned process of forming the contacts CC will be described in more detail. Figures 12 to 14 are enlarged cross-sectional views along the X direction illustrating the details of the process of forming the contacts CC of the semiconductor memory device 1 according to the embodiment.

[0137] As described above, when forming the staircase shape in the region that will later become the staircase region SR, the already formed columns HR are also processed together with the stacks LMsa and LMsb. Due to such processing, the shape of the upper end of the columns HR can vary in various ways. Figure 12 shows some examples of shapes that the columns HR can have.

[0138] 12(a) shows an example in which the processing rate of the columnar portion HR is substantially equal to the processing rate of the laminates LMsa and LMsb, for example. In such a case, the upper end of the columnar portion HR exposed on the terrace surface of each step of the staircase shape formed on the laminates LMsa and LMsb becomes substantially flat.

[0139] As shown in Fig. 12(b), from the above state, substantially flat stopper layers SPs, SPn are sequentially formed on the generally substantially flat step-shaped terrace surface including the upper surface of the columnar portion HR. In the example of Fig. 12(b), the contact CC formed thereafter reaches, for example, the terrace surface between the multiple columnar portions HR without misalignment. Even in such a contact CC, the lower end CCe including the penetrating portion of the stopper layers SPs, SPn, etc. is expanded in diameter in the direction along the XY plane along the surfaces of the stopper layers SPs, SPn, etc.

[0140] 12(c) shows an example in which the processing rate of the columnar portion HR is higher than that of the laminates LMsa and LMsb. In such a case, the upper end of the columnar portion HR is recessed into a mortar-shaped shape from the terrace surface of each step of the staircase shape formed on the laminates LMsa and LMsb. In this case, the terrace surfaces around the columnar portion HR may also be recessed into a mortar-shaped shape toward the columnar portion HR.

[0141] As shown in Fig. 12(d), the stopper layers SPs, SPn are sequentially formed along the terrace surface that slopes down toward the columnar portion HR in a mortar-cone shape to cover the terrace surface in the same mortar-cone shape. However, if the contact CC formed thereafter is formed without misalignment and while avoiding interference with the columnar portion HR, the contact CC will avoid the mortar-cone shaped portion and reach the approximately flat portion of the terrace surface. Therefore, the lower end CCe of the contact CC including the penetrating portion of the stopper layers SPs, SPn, etc. is expanded in diameter in the direction along the XY plane along the surface of the flat portion of the stopper layers SPs, SPn, etc.

[0142] 12(e) shows an example in which the processing rate of the columnar portion HR is lower than that of the laminates LMsa and LMsb, for example. In such a case, the upper end of the columnar portion HR has a conical shape protruding from the terrace surface of each step of the staircase shape formed on the laminates LMsa and LMsb.

[0143] 12(f), the stopper layers SPs, SPn are sequentially formed so as to cover the upper ends of the columnar portions HR protruding from the terrace surface. However, if the contacts CC formed thereafter are formed without misalignment and while avoiding interference with the columnar portions HR, the contacts CC will reach the substantially flat portion of the terrace surface, avoiding the protruding portions of the columnar portions HR and the stopper layers SPs, SPn. Therefore, the lower ends CCe of the contacts CC including the penetrating portions of the stopper layers SPs, SPn, etc. are expanded in diameter in the direction along the XY plane along the surfaces of the flat portions of the stopper layers SPs, SPn, etc.

[0144] Next, an example in which the contact CC is misaligned and comes into contact with the columnar portion HR is shown in FIG. 13 and FIG.

[0145] FIG. 13 shows an example in which the columnar portion HR and the terrace surface around it have a mortar-shaped depression toward the center of the columnar portion HR, and the contact CC is misaligned.

[0146] FIG. 13(a) is an example of a stepped shape in which the terrace surface is shaped like a mortar, similar to the above-mentioned FIG. 12(c).

[0147] 13(b), stopper layers SPs, SPn are sequentially formed along the cone-shaped terrace surface, and an insulating layer 51 is formed via these stopper layers SPs, SPn to cover the staircase shape.

[0148] 13(c), a contact hole CL is formed which penetrates the insulating layer 51 and reaches the stopper layer SPn covering the terrace surface. At this time, in the example of FIG. 13(c), a positional deviation occurs in the contact hole CL, and the lower end of the contact hole CL reaches the mortar-shaped portion of the stopper layer SPn.

[0149] As shown in Fig. 13(d), the bottom surface of the contact hole CL is wet-etched to form the contact hole CL that reaches the insulating layer NL immediately below the terrace surface. At this time, the lower end of the contact hole CL including the penetrating portion of the stopper layer SPn is expanded in diameter along the surface of the stopper layer SPn. In the example of Fig. 13(d), the lower end of the contact hole CL expands toward the columnar portion HR along the surface of the mortar-shaped stopper layer SPn at one end, and expands in the direction along the XY plane along the substantially flat surface of the stopper layer SPn at the other end.

[0150] As shown in FIG. 13(e), a conductive layer 25 is filled into the contact hole CL having the expanded lower end to form a contact CC.

[0151] 13(f), the insulating layers NL of the laminates LMsa and LMsb are then replaced to form a laminate LM having a plurality of word lines WL. At this time, the stopper layers SPn are also similarly replaced with a conductive material to form stopper layers SPw.

[0152] As a result, the contacts CC are connected at their lower ends CCe to the upper surface of the word line WL and to the end surface of the word line WL exposed at the end of the mortar-shaped inclined surface. This also results in the stopper layer SPw having electrical conduction with the word line WL to which the contacts CC are connected via the lower ends CCe of the contacts CC. However, even in this case, as described above, there is no contact between the stopper layer SPw and the other word lines WL, so no problems with electrical characteristics occur.

[0153] FIG. 14 shows an example in which the entire terrace surface including the upper surface of the columnar portion HR has a substantially flat shape, or the columnar portion HR protrudes from the terrace surface in a conical shape, and the contact CC is misaligned.

[0154] Fig. 14(a) is an example of a stepped structure with a substantially flat terrace surface, similar to Fig. 12(a) described above. In this case, the stopper layers SPs, SPn are formed in sequence along the substantially flat terrace surface. An insulating layer 51 is formed through the stopper layers SPs, SPn to cover the stepped structure.

[0155] Also, a contact hole CL is formed which penetrates the insulating layer 51 and reaches the stopper layer SPn covering the terrace surface. At this time, a positional deviation occurs in the contact hole CL, and the lower end of the contact hole CL is formed at a position where it partially overlaps with one of the columnar portions HR in the stacking direction of the stacked bodies LMsa and LMsb.

[0156] As shown in FIG. 14(b), the bottom surface of the contact hole CL is wet-etched to form the contact hole CL that reaches the insulating layer NL directly below the terrace surface. At this time, the terrace surface including the upper end of the columnar portion HR is substantially flat. Therefore, the lower end of the contact hole CL including the penetrating portion of the stopper layer SPn is expanded in the direction along the XY plane along the surface of the stopper layer SPn.

[0157] 14(c), a conductive layer 25 is filled into the contact hole CL having the expanded lower end to form a contact CC. After that, the insulating layer NL and the stopper layer SPn of the laminates LMsa and LMsb are replaced to form a laminate LM having a plurality of word lines WL and a stopper layer SPw.

[0158] As a result, the contact CC is connected to the upper surface of the word line WL at a part of the lower end CCe. In the example of Fig. 14(c), one end of the lower end CCe of the contact CC extends onto the upper end of the columnar portion HR, and electrical continuity with the word line WL is not obtained. However, the other end of the lower end CCe of the contact CC extends onto the word line WL, and electrical continuity with the word line WL is obtained.

[0159] This also brings the stopper layer SPw into electrical conduction with the word line WL to be connected to the contact CC via the lower end CCe of the contact CC.

[0160] Fig. 14(d) shows an example in which the columnar portion HR protrudes from the terrace surface in a conical shape, similar to Fig. 12(e) described above. In this case, the stopper layers SPs, SPn are sequentially formed on the terrace surface to cover the protruding columnar portion HR. In addition, an insulating layer 51 is formed through these stopper layers SPs, SPn to cover the step shape.

[0161] Also, a contact hole CL is formed which penetrates the insulating layer 51 and reaches the stopper layer SPn covering the terrace surface. At this time, a positional deviation occurs in the contact hole CL, and the lower end of the contact hole CL is formed at a position where it partially overlaps with one of the columnar portions HR in the stacking direction of the stacked bodies LMsa and LMsb.

[0162] As shown in Fig. 14(e), the bottom surface of the contact hole CL is wet-etched to form the contact hole CL that reaches the insulating layer NL immediately below the terrace surface. At this time, the upper end of the columnar portion HR protrudes from the terrace surface. Therefore, in the example of Fig. 14(e), the lower end of the contact hole CL spreads out along the upper end of the protruding columnar portion HR at one end side, and spreads out in the direction along the XY plane along the surface of the approximately flat stopper layer SPn at the other end side.

[0163] 14(f), a conductive layer 25 is filled into the contact hole CL having the expanded lower end to form a contact CC. After that, the insulating layer NL and the stopper layer SPn of the laminates LMsa and LMsb are replaced to form a laminate LM having a plurality of word lines WL and a stopper layer SPw.

[0164] As a result, the contact CC is connected solely to the upper surface of the word line WL through a portion of the lower end CCe. In the example of Fig. 14(f), one end of the lower end CCe of the contact CC extends over the protruding portion of the columnar portion HR, and electrical continuity with the word line WL is not obtained. However, the other end of the lower end CCe of the contact CC extends over the word line WL, and electrical continuity with the word line WL is obtained.

[0165] This also brings the stopper layer SPw into electrical conduction with the word line WL to be connected to the contact CC via the lower end CCe of the contact CC.

[0166] As described above, according to the embodiment of the semiconductor memory device 1, the contact CC is more reliably connected to the word line WL to be connected, regardless of the shape of the columnar portion HR that is processed in parallel when forming the staircase shape, and regardless of whether or not a positional shift occurs in the contact CC.

[0167] (Comparative Example) Semiconductor memory devices such as 3D non-volatile memories are manufactured through a process of forming a stack of multiple word lines by replacing a stack of multiple sacrificial layers, for example. After that, a process of forming contacts on terraces where the word lines are drawn out in a stepped manner is performed.

[0168] When forming the contacts, for example, a plurality of contact holes with different depths are formed at once by penetrating an insulating layer covering the staircase portion. At this time, in order to prevent some of the contact holes with different depths from penetrating the word line to be connected, a stopper layer covering the staircase portion may be formed in advance.

[0169] In addition, in order to support the structure of the stacked body during replacement, multiple pillars may be formed in the staircase portion of the semiconductor memory device. Even if the contact is formed out of position relative to the arrangement position of the pillar during contact formation, the provision of the stopper layer as described above prevents the contact from being formed through the pillar.

[0170] Such a stopper layer is formed, for example, containing the same material as the sacrificial layer. Therefore, when forming a word line from the sacrificial layer, the stopper layer is removed in advance at the position where the slit is to be formed so that the stopper layer is not replaced together with the sacrificial layer. However, in recent years, the number of layers of the word line has tended to increase, and the difference in height between the upper layer and the lower layer of the staircase portion has also increased. For this reason, it has become extremely difficult to open the stopper layer by exposing the mask pattern used to remove the stopper layer.

[0171] In addition, if the step portion is formed after the columnar portion is formed, the terrace surface may be processed into a mortar shape toward the columnar portion due to the difference in processing rate between the sacrificial layer that constitutes the stack and the insulating layer that constitutes the columnar portion. If a stopper layer cannot be used due to the increased difficulty of exposing the mask pattern, the risk of poor contact formation due to the word line to be connected penetrating increases even further. This is shown in Figure 15.

[0172] FIG. 15 is an enlarged cross-sectional view taken along the X direction illustrating a process for forming a contact CCx of a semiconductor memory device according to a comparative example.

[0173] 15 shows an example in which the entire terrace surface including the upper surface of the columnar portion HRx has a substantially flat shape, or the terrace surface has a mortar-shaped configuration toward the columnar portion HRx and the contact CCx is misaligned. As shown in FIG. 15, in the comparative example, the insulating layer 51 directly covers the staircase shape.

[0174] FIG. 15(a) shows an example of a stepped shape in which the terrace surface is approximately flat.

[0175] As shown in FIG. 15(b), a replacement process forms a plurality of word lines WL from a plurality of insulating layers NL, and then a contact hole CLx is formed that penetrates the insulating layer 51 and the insulating layer OL that constitutes the terrace surface and reaches the insulating layer NL directly below.

[0176] At this time, the contact hole CLx is misaligned, and the lower end of the contact hole CLx is formed at a position where it partially overlaps with one of the columnar portions HRx in the stacking direction of the laminates LMsa and LMsb. As a result, the lower end of the contact hole CLx may partially reach a layer lower than the insulating layer NL, which is the target, via the columnar portion HRx.

[0177] As shown in Fig. 15(c), a contact CCx is formed by filling a conductive layer into the contact hole CLx, part of which reaches the lower layer. In the example of Fig. 15(c), the lower end of the contact CCx stops at the insulating layer OL immediately below the word line WL to be connected, and is not connected to the word line WL further below.

[0178] Therefore, no short circuit occurs between the word line WL to which the contact CCx is connected and the word line WL in the layer below. However, because the bottom end of the contact CCx extends to directly above the word line WL in the layer below, there is a risk that the withstand voltage between the word lines WL may be insufficient. Furthermore, if the bottom end of the contact CCx extended further downward, a short circuit would occur between these word lines WL.

[0179] 15D shows an example of a stepped shape in which the terrace surface becomes bowl-shaped toward the columnar portion HR. In this case, the depth of the bottom end of the contact hole CLx increases, and the risk of a short circuit between the word lines WL increases.

[0180] As shown in FIG. 15(e), the lower end of the contact hole CLx, which penetrates the insulating layer 51 and the insulating layer OL and reaches the insulating layer NL directly below, extends further downward via the columnar portion HRx and reaches the word line WL below the word line WL to be connected.

[0181] As shown in Fig. 15(f), a contact CCx is formed by filling a conductive layer into the contact hole CLx, part of which reaches the lower layer. In the example of Fig. 15(f), the lower end of the contact CCx is connected to both the word line WL to be connected and the word line WL in the layer below it, causing a short circuit between these word lines WL.

[0182] As described above, in the manufacturing process of a semiconductor memory device, misalignment may occur when forming a contact hole. If a misaligned contact hole interferes with a columnar portion, it may reach a position deeper than the word line to be connected, resulting in insufficient voltage resistance or a short circuit between the word lines.

[0183] Such defects become more noticeable when the terrace surface around the columnar portion is shaped like a mortar when the stepped shape is formed.

[0184] According to the semiconductor memory device 1 of the embodiment, the contact CC penetrates the stopper layer SPw arranged above the word line WL to which the contact CC is to be connected, among the multiple word lines WL, and reaches the word line WL to which the contact CC is to be connected.

[0185] As described above, the stopper layer SPw is a replacement for the stopper layer SPn used when forming the contact hole CL. By forming the contact hole CL using the stopper layer SPn in this manner, even if the contact hole CL is misaligned, it is possible to suppress insufficient breakdown voltage and short circuit between the word lines WL.

[0186] According to the embodiment of the semiconductor memory device 1, the contact CC extends along the surface of the bowl-shaped stopper layer SPw at the lower end CCe including the penetrating portion of the stopper layer SPw, and is connected to the word line WL to be connected at at least a portion of the lower end CCe.

[0187] As described above, if the terrace surface is processed into a mortar-cone shape toward the columnar portion HR when forming the staircase shape, the risk of short-circuiting between the word lines WL increases. However, even in this case, the lower end portion CCe of the contact CC spreads along the surface of the mortar-cone shaped stopper layer SPw, so that it is possible to suppress insufficient breakdown voltage and short-circuiting between the word lines WL.

[0188] According to the semiconductor memory device 1 of the embodiment, the lower end of the contact CC is in contact with the upper end of the columnar portion HR. In this way, even if the contact CC and the columnar portion HR interfere with each other, it is possible to suppress insufficient breakdown voltage and short circuit between the word lines WL.

[0189] According to the semiconductor memory device 1 of the embodiment, the stopper layer SPw is not connected to any of the word lines WL except the word line WL to which the contact CC is connected. This allows the stopper layer SPn to be replaced when replacing the stacked bodies LMsa and LMsb. This makes it possible to easily introduce the stopper layer SPn into the staircase portion SCP without the need to remove the stopper layer SPn in advance at the position where the slit ST is to be formed.

[0190] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, after forming at least contact holes CL, the multiple insulating layers NL are replaced with multiple word lines WL to form a laminate LM in which multiple word lines WL and multiple insulating layers OL are stacked alternately one layer at a time.

[0191] In this way, by forming the contact hole CL before the insulating layer NL and the stopper layer SPn are replaced by the word line WL and the stopper layer SPw, respectively, it is not necessary to form the contact hole CL by penetrating the stopper layer SPw, and the formation of the contact CC is facilitated.

[0192] According to the semiconductor memory device 1 of the embodiment, the stopper layer SPw is disposed above the word line WL to which the contact CC is connected via the stopper layer SPs. By providing the stopper layer SPs in this manner, it is possible to protect the stacked body LM, for example, when the stopper layer SPn before replacement is processed in various ways.

[0193] According to the semiconductor memory device 1 of the embodiment, the stopper layer SPs is also disposed on the step faces of the plurality of word lines WL that are processed in a stepped shape, thereby preventing the word line WL above the word line WL to be connected to the contact CC from being connected to the stopper layer SPw at its end face that the word line WL has on the step face.

[0194] In the above embodiment, the staircase region SR including the staircase portion SCP is arranged at both ends of the laminate LM in the X direction. However, for example, a staircase region including a staircase portion formed by digging out the center of the laminate in a mortar shape may be arranged within the laminate.

[0195] In the above embodiment, the peripheral circuit CBA that contributes to the operation of the memory cell MC is arranged on the semiconductor substrate SB bonded above the stack LM. However, the stack may be stacked above the peripheral circuit including the transistor arranged on the semiconductor substrate. Alternatively, the stack may be arranged on the same semiconductor substrate as the peripheral circuit.

[0196] In the above embodiment, the semiconductor memory device 1 includes a two-tier stack LM including stacks LMa and LMb. However, the semiconductor device may include a one-tier stack, or a stack of three or more tiers. In a multi-tier type semiconductor memory device, it is easy to further increase the number of stacks of the word lines WL.

[0197] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0198] 1...semiconductor memory device, CC...contact, CN...channel layer, HR...columnar portion, LI...plate-shaped contact, LM, LMa, LMb, LMga, LMgb, LMsa, LMsb...stacked body, MC...memory cell, MR...memory region, NL, OL...insulating layer, 51...insulating layer, PL...pillar, SCP...staircase portion, SPn, SPs, SPw...stopper layer, SR...staircase region, ST...slit, WL...word line.

Claims

1. a laminate in which a plurality of first conductive layers and a plurality of first insulating layers are alternately laminated one by one, and the plurality of first conductive layers have a staircase portion processed into a staircase shape; a contact disposed in the step portion and connected to any one of the first conductive layers; a first pillar extending in a stacking direction of the stack within the stack apart from the step portion and forming a memory cell at each intersection with at least a portion of the plurality of first conductive layers; The contact is the contact penetrates a second conductive layer disposed above a first conductive layer to which the contact is to be connected among the plurality of first conductive layers, and reaches the first conductive layer to which the contact is to be connected; Semiconductor memory device.

2. The second conductive layer comprises: comprising the same material as the plurality of first conductive layers; 2. The semiconductor memory device according to claim 1.

3. Further, a second pillar is provided in the step portion, the second pillar extending in the stacking direction within the stack, The second conductive layer comprises: The second pillar is recessed in a mortar shape from the periphery of the second pillar toward the second pillar.

2. The semiconductor memory device according to claim 1.

4. The contact is a lower end including a through portion of the second conductive layer, the lower end extending along a surface of the second conductive layer having a mortar shape; At least a portion of the lower end is connected to the first conductive layer of the connection target.

4. The semiconductor memory device according to claim 3.

5. The lower end of the contact in contact with the top end of the second pillar; 4. The semiconductor memory device according to claim 3.

6. The second conductive layer comprises: The contact is disposed above a first conductive layer to which the contact is to be connected via a second insulating layer.

4. The semiconductor memory device according to claim 3.

7. The second insulating layer comprises: Also disposed on step surfaces of the plurality of first conductive layers which are processed in a stepped shape.

7. The semiconductor memory device according to claim 6.

8. forming a first laminate in which a plurality of first insulating layers and a plurality of second insulating layers are alternately laminated one by one; forming a first pillar having a semiconductor layer extending in a stacking direction of the first stack within the first stack; forming a second pillar extending in the stacking direction within the first stack at a position different from that of the first pillar; forming a staircase portion by processing the first insulating layers into a staircase shape in a region of the first stack in which the second pillars are formed; forming a third insulating layer that covers the staircase portion so as to conform to a staircase shape of the staircase portion and that contains the same material as the plurality of first insulating layers; a contact hole is formed at a position overlapping a terrace surface of the staircase portion in the stacking direction, using the third insulating layer as a stopper layer. A method for manufacturing a semiconductor memory device.

9. the lower end of the contact hole is made to reach a first insulating layer below the terrace surface that overlaps with the contact hole in the stacking direction, among the plurality of first insulating layers, by penetrating the third insulating layer exposed at the lower end of the contact hole; The method for manufacturing a semiconductor memory device according to claim 8 .

10. filling the contact holes with a metal layer to form contacts; After forming at least the contact hole, replacing the plurality of first insulating layers with a plurality of conductive layers to form a second laminate in which the plurality of conductive layers and the plurality of second insulating layers are alternately laminated one by one; A memory cell can be formed at each intersection between the first pillar and at least a portion of the first conductive layers; a conductive layer of the plurality of conductive layers that is below the terrace surface and overlaps with the contact in the stacking direction is connected to the contact; The method for manufacturing a semiconductor memory device according to claim 9 .

11. When forming the second laminate, a slit extending within the first laminate in a first direction intersecting the lamination direction and the lamination direction, dividing the first laminate in a second direction intersecting the lamination direction and the first direction, and penetrating the third insulating layer; replacing the third insulating layer as well as the first insulating layers with the conductive layers through the slits; The method for manufacturing a semiconductor memory device according to claim 10.

12. When forming the third insulating layer, removing the third insulating layer covering the step surface of the staircase portion while leaving the third insulating layer covering the terrace surface; The method for manufacturing a semiconductor memory device according to claim 10.

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