Upper arm drive circuit

Abstract

To prevent malfunction of an upper arm switching element by a fact that output of a power conversion circuit becomes negative potential and is undershot.SOLUTION: An upper arm drive circuit comprises: a first switching element SW1 connected between a gate and a reference potential terminal of an upper arm switching element Q1; a second switching element SW2 of which the drain is connected with a gate of the first switching element SW1; and a potential control circuit 4, wherein the potential control circuit 4 controls potential of a source of the second switching element SW2 to first potential in which the first switching element SW1 can maintain on even when the second switching element SW2 is turned on due to malfunction in a first period in which at least the reference potential terminal of the upper arm switching element Q1 becomes low potential and is undershot, and controls the potential of the source of the second switching element SW2 to second potential which is lower than the first potential and in which the first switching element SW1 can be turned off when the second switching element SW2 is turned on in a second period following the first period.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an upper arm driver circuit. [Background technology]

[0002] With the rise in awareness of environmental conservation worldwide, the demand for energy conservation has increased, and power conversion devices (inverters) are being widely adopted in various fields. For power conversion devices installed in the drive systems of railway vehicles, air conditioners, etc., high reliability, as well as high performance and efficiency, are becoming important issues.

[0003] A typical power conversion device includes a power conversion circuit consisting of a bridge circuit having upper and lower arms each made up of a switching element and a freewheeling diode connected in inverse parallel to the switching element, an upper arm drive circuit that drives and controls the switching element of the upper arm, and a lower arm drive circuit that drives and controls the switching element of the lower arm.

[0004] An example of a technique related to an upper arm drive circuit is Patent Document 1. FIG. 2A and the abstract of Patent Document 1 state that "an upper arm drive circuit capable of stably controlling an upper arm without malfunctioning even when the output of a power conversion device becomes negative potential in a power conversion device having a bridge circuit composed of upper and lower arms is provided," and that "an upper arm drive circuit for driving and controlling an upper arm switching element of a power conversion device includes an upper arm gate voltage output wiring connected to a gate of the upper arm switching element, a first upper arm drive circuit reference potential wiring, an upper arm gate voltage reference potential wiring connected to an inverter output of the power conversion device, and an upper arm drive circuit reference potential wiring potential control circuit for controlling the first upper arm drive circuit reference potential wiring to a potential lower than the reference potential when the inverter output is equal to or lower than a predetermined potential lower than a reference potential, and the first upper arm drive circuit reference potential wiring is connected to the reference potential via the upper arm drive circuit reference potential wiring potential control circuit." [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2022-146525 Summary of the Invention [Problem to be solved by the invention]

[0006] In Patent Document 1, when the inverter output of the power conversion device becomes negative potential, the upper arm driver circuit reference potential wiring (12) is immediately controlled to become negative potential.

[0007] For example, in FIG. 2A of Patent Document 1, when the inverter output (8) is negative, the upper arm drive circuit reference potential wiring (12) is the same as the inverter output (8). In this state, in order to prevent the upper arm IGBT (2) from malfunctioning and turning on, the upper arm drive MOSFET (10) must be on and the upper arm drive MOSFET (9) must be off. Here, the upper arm drive MOSFET (10) has a weak ability to maintain its on state, and if noise is introduced, the upper arm drive MOSFET (9) may malfunction and turn on, causing the charge of the gate of the upper arm drive MOSFET (10) to be drained and turned off. As a result, the charge of the gate of the upper arm IGBT (2) cannot be drained, and in this state, if noise or the like is introduced into the gate of the upper arm IGBT (2), the upper arm IGBT (2) may malfunction and turn on.

[0008] In particular, immediately after the upper arm IGBT (2) is turned off, the inverter output (8) becomes negative potential and an undershoot occurs. During the period in which the undershoot occurs, that is, the period from when the undershoot starts to when the undershoot ends and the steady state negative potential is reached, noise that turns off the upper arm drive MOSFET (10) is likely to occur, and thus there has been a problem in that the upper arm IGBT (2) is likely to malfunction.

[0009] An object of the present invention is to provide an upper arm driver circuit that can prevent malfunction of an upper arm switching element caused by the output of a power conversion circuit being at a negative potential and undershooting. [Means for solving the problem]

[0010] In order to solve the above-mentioned problems, an upper arm drive circuit of the present invention is an upper arm drive circuit for driving an upper arm switching element of a power conversion circuit, and includes: a first switching element having a drain connected to a gate of the upper arm switching element and a source connected to a reference potential terminal of the upper arm switching element; a second switching element having a drain connected to the gate of the first switching element; and a potential control circuit connected to a reference potential, the reference potential terminal of the upper arm switching element, and a source of the second switching element, for controlling the potential of the source of the second switching element, In a first period starting immediately after the upper arm switching element is turned off and including at least the time when the reference potential terminal of the upper arm switching element is at a negative potential and the undershoot ends, the potential of the source of the second switching element is controlled to a first potential at which the first switching element can be kept on even if the second switching element is turned on due to a malfunction, and in a second period starting from the end of the first period and before the upper arm switching element is turned on, the potential of the source of the second switching element is controlled to a second potential that is lower than the first potential and allows the first switching element to be turned off when the second switching element is turned on. Effect of the Invention

[0011] According to the upper arm driver circuit of the present invention, it is possible to prevent malfunction of the upper arm switching element caused by the output of the power conversion circuit becoming negative potential and undershooting. [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 is a circuit diagram showing a schematic configuration of an upper arm drive circuit according to the first embodiment. [Diagram 2] 4 is a timing chart illustrating the operation of the upper arm driver circuit according to the first embodiment. [Diagram 3] 4 is a circuit diagram illustrating an operation of the upper arm driver circuit of the first embodiment in a first period. [Figure 4] 4 is a circuit diagram illustrating an operation of the upper arm driver circuit of the first embodiment in a second period. [Diagram 5] 6 is a circuit diagram illustrating an operation of the upper arm driver circuit of the first embodiment in a third period. [Figure 6] 6 is a circuit diagram illustrating an operation of the upper arm driver circuit of the first embodiment in a fourth period. [Figure 7] FIG. 11 is a circuit diagram showing a schematic configuration of an upper arm drive circuit according to a second embodiment. [Figure 8] FIG. 11 is a circuit diagram showing a schematic configuration of an upper arm drive circuit according to a third embodiment. [Figure 9] FIG. 13 is a circuit diagram showing a schematic configuration of an upper arm drive circuit according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and duplicated explanations will be omitted. EXAMPLES

[0014] FIG. 1 is a circuit diagram showing a schematic configuration of an upper arm driver circuit according to the first embodiment.

[0015] The power conversion device 3 has an upper arm drive circuit 1, a power conversion circuit 2, and a lower arm drive circuit (not shown).

[0016] The power conversion circuit 2 has an upper-arm switching element Q1 and a lower-arm switching element Q2 connected in series between a DC power supply potential VDC and a reference potential GND, an upper-arm freewheeling diode DQ1 connected in anti-parallel to the upper-arm switching element Q1, and a lower-arm freewheeling diode DQ2 connected in anti-parallel to the lower-arm switching element Q2. An AC output of the power conversion circuit 2 is output from a connection node between the upper-arm switching element Q1 and the lower-arm switching element Q2 to an output terminal OUT.

[0017] The upper arm switching element Q1 and the lower arm switching element Q2 may be, for example, an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET). When a MOSFET is used, a body diode built into the MOSFET may be used as the upper arm freewheel diode DQ1 and the lower arm freewheel diode DQ2. In this embodiment, a case where the upper arm switching element Q1 and the lower arm switching element Q2 are N-type switching elements will be described as an example. The reference potential GND is, for example, a ground potential, but is not limited to this.

[0018] The upper arm drive circuit 1 is a drive circuit that drives the upper arm switching element Q1, and the lower arm drive circuit (not shown) is a drive circuit that drives the lower arm switching element Q2.

[0019] The upper arm driver circuit 1 of this embodiment includes a first switching element SW1, a second switching element SW2, and a potential control circuit 4.

[0020] The drain of the first switching element SW1 is connected to the gate of the upper-arm switching element Q1, and the source is connected to the reference potential terminal of the upper-arm switching element Q1. By turning on the first switching element SW1, the gate of the upper-arm switching element Q1 and the reference potential terminal are shorted, and charge can be extracted from the gate of the upper-arm switching element Q1. For example, an N-type MOSFET can be used as the first switching element SW1.

[0021] The drain of the second switching element SW2 is connected to the gate of the first switching element SW1. As the second switching element SW2, for example, an N-type MOSFET can be used.

[0022] The potential control circuit 4 is connected to a reference potential GND, a reference potential terminal of the upper arm switching element Q1, and a source of the second switching element SW2, and controls the potential of the source of the second switching element SW2. The reference potential GND is, for example, a ground potential, but is not limited to this. The reference potential GND of the upper arm driver circuit 1 may be the same as or different from the reference potential GND of the power conversion circuit 2.

[0023] The potential control circuit 4 of this embodiment shows an example having a first circuit 5 provided between a reference potential GND and the source of the second switching element SW2, and a second circuit 6 provided between the reference potential terminal of the upper arm switching element Q1 and the source of the second switching element SW2.

[0024] The first circuit 5 of this embodiment shows an example having a third switching element SW3 that turns on and off between the reference potential GND and the source of the second switching element SW2, and a first diode D1 that is connected in parallel to the third switching element SW3, has a cathode connected to the reference potential GND, and has an anode connected to the source of the second switching element SW2.

[0025] The second circuit of this embodiment shows an example having a second diode D2 having a cathode connected to the reference potential terminal of the upper arm switching element Q1 and an anode connected to the source of the second switching element SW2, and a first resistor R1 connected in series with the second diode D2.

[0026] The connection node N is a connection node between the reference potential GND, the reference potential terminal of the upper arm switching element Q1, and the source of the second switching element.

[0027] The upper arm driver circuit 1 of this embodiment preferably further includes a second resistor R2 connected to the gate of the upper arm switching element Q1, and a Zener diode ZD having a cathode connected to the gate of the upper arm switching element Q1 and an anode connected to the reference potential terminal of the upper arm switching element Q1. The second resistor R2 serves as a gate resistor of the upper arm switching element Q1. The second resistor R2 is connected between the gate of the upper arm switching element Q1 and an upper arm driver circuit (not shown) that applies an ON signal to the gate of the upper arm switching element Q1. FIG. 1 shows an example in which the second resistor R2 is connected to the right side of the drain of the first switching element SW1 (the side closer to the gate of the upper arm switching element Q1), but is not limited to this, and the second resistor R2 may be connected to the left side of the drain of the first switching element SW1. The Zener diode ZD serves to limit the voltage between the gate of the upper arm switching element Q1 and the reference potential terminal to protect the upper arm switching element Q1.

[0028] The upper arm driver circuit 1 of this embodiment preferably further includes a third diode D3 having a cathode connected to the gate of the first switching element SW1 and an anode connected to the source of the first switching element SW1.

[0029] The upper arm driver circuit 1 of this embodiment preferably further includes a third resistor R3 connected between the source of the second switching element SW2 and the potential control circuit 4. The location of the third resistor R3 is not limited thereto, and the third resistor R3 may be provided at another location.

[0030] The upper arm driver circuit 1 of this embodiment also includes a gate driver circuit (not shown) that applies an on signal to the gate of the upper arm switching element Q1, a control circuit (not shown) for controlling the operation of the first switching element SW1, a control circuit (not shown) for controlling the operation of the second switching element SW2, a control circuit (not shown) for controlling the operation of the third switching element SW3, and a discharge circuit (not shown) for withdrawing charge from the gate of the upper arm switching element Q1, but detailed explanations are omitted.

[0031] Fig. 2 is a timing chart illustrating the operation of the upper arm driver circuit of Example 1. In Fig. 2, the horizontal axis represents time t.

[0032] In Fig. 2, Q1 indicates the on / off state of the upper-arm switching element Q1. Note that there is a delay time between when an on signal or an off signal is applied to the gate of the upper-arm switching element Q1 and when the upper-arm switching element Q1 actually turns on or off. Fig. 2 shows the timing when the upper-arm switching element Q1 actually turns on or off, rather than the timing of the on signal or off signal.

[0033] In FIG. 2, OUT indicates the potential of the output terminal OUT of the power conversion circuit 2, and the vertical axis is the potential V. GND indicates the potential of the reference potential GND, and in this embodiment, an example of 0V will be used for explanation. The output terminal OUT of the power conversion circuit 2 is connected to the reference potential terminal of the upper arm switching element Q1 and the source of the first switching element SW1, so that these potentials are the same. The output of the power conversion circuit 2 (the potential of the reference potential terminal of the upper arm switching element Q1 is also the same) is positive during the period when the upper arm switching element Q1 is on, and is negative during the period when the upper arm switching element Q1 is off. Furthermore, the explanation will be given assuming that an undershoot UND occurs immediately after the upper arm switching element Q1 is turned off, and that the potential becomes negative in a steady state after the undershoot UND ends. In particular, during the period when the undershoot UND occurs, noise is likely to occur, which is likely to cause malfunction of the switching element.

[0034] 2, N indicates the potential of the connection node N, and the vertical axis is the potential V. In this embodiment, the potential of the connection node N is described as being approximately the same as the potential of the source of the second switching element SW2. The potential of the connection node N is a first potential V1 in the first period T1, the third period T3, and the fourth period T4, and is a second potential V2 lower than the first potential V1 in the second period T2. The first potential V1 is approximately the same as the potential of the reference potential GND, and the second potential V2 is approximately the same as the negative potential of the output of the power conversion circuit 2.

[0035] In FIG. 2, SW3 indicates the on / off state of the third switching element SW3, which is on in the first period T1 and the fourth period T4 and off in the second period T2 and the third period T3.

[0036] The potential control circuit 4 of this embodiment controls the potential of the source of the second switching element SW2 to a first potential V1 at which the first switching element SW1 can be kept on even if the second switching element SW2 is turned on due to a malfunction during a first period T1 that starts immediately after the upper-arm switching element Q1 is turned off and includes at least the time when the reference potential terminal of the upper-arm switching element Q1 is at a negative potential and the undershoot UND ends, and controls the potential of the source of the second switching element SW2 to a second potential V2 that is lower than the first potential V1 and can turn off the first switching element SW1 when the second switching element SW2 is turned on during a second period T2 that starts immediately after the upper-arm switching element Q1 is turned off and includes the time when the reference potential terminal of the upper-arm switching element Q1 is at a negative potential and the undershoot UND ends. This makes it possible to prevent the upper-arm switching element from malfunctioning due to the output of the power conversion circuit 2 being at a negative potential and the undershoot UND ending.

[0037] It is preferable that the first period T1 is longer than the second period T2, so that the first period T1 can be made longer to prevent malfunction due to noise.

[0038] Moreover, it is desirable that the second period T2 is equal to or longer than the delay time from when an ON signal is applied to the gate of the upper-arm switching element Q1 from a gate drive circuit (not shown) until the upper-arm switching element Q1 is turned on. In order to lengthen the first period T1, it is desirable to switch to the second period T2 immediately before turning on the upper-arm switching element Q1. If the second period T2 is set to be equal to the delay time, the first period T1 can be lengthened. If the second period T2 is set to be longer than the delay time, the first period T1 becomes shorter, but it is possible to accommodate variations in the delay time.

[0039] Next, a specific operation will be described with reference to FIG. 3 to FIG.

[0040] FIG. 3 is a circuit diagram illustrating the operation of the upper arm driver circuit in the first period according to the first embodiment.

[0041] In the first period T1, as shown in FIG. 3, the upper arm switching element Q1 is in an OFF state, the first switching element SW1 is ON, the second switching element SW2 is OFF, and the third switching element SW3 is ON.

[0042] Since the output of the power conversion circuit 2 is at a negative potential, a current i flows from the reference potential GND through the third switching element SW3, the first resistor R1, and the second diode D2. At this time, the potential of the connection node N is the first potential V1, which is almost the same as the potential of the reference potential GND. In the second circuit 6 of this embodiment, since the forward voltage of the second diode D2 alone cannot bear the potential difference between the potential of the reference potential GND and the potential of the output of the power conversion circuit 2, the first resistor R1 is provided to share the potential difference.

[0043] Here, let us consider a case where noise occurs during the undershoot UND and the second switching element SW2 malfunctions and turns on. In this case, the second switching element SW2 turns on and conducts, so the gate of the first switching element SW1 also becomes the first potential V1. At this time, the output of the power conversion circuit 2 is at a negative potential, so the gate of the first switching element SW1 has a higher potential than the source. Therefore, even if the second switching element SW2 malfunctions and turns on, the first switching element SW1 can be kept on. The first potential V1 needs to be a potential at which the first switching element SW1 can be kept on even if the second switching element SW2 malfunctions and turns on, so it is sufficient that the first potential V1 is a potential higher than the negative potential of the output of the power conversion circuit 2 by the threshold value of the first switching element SW1.

[0044] Since the first switching element SW1 remains on, the short circuit between the gate of the upper arm switching element Q1 and the reference potential terminal is maintained, and even if noise is generated and enters the gate of the upper arm switching element Q1, the charge on the gate of the upper arm switching element Q1 can be extracted via the first switching element SW1, thereby preventing the upper arm switching element Q1 from malfunctioning and turning on.

[0045] FIG. 4 is a circuit diagram illustrating the operation of the upper arm driver circuit in the second period according to the first embodiment.

[0046] In the second period T2, as shown in FIG. 4, the upper arm switching element Q1 is changed from off to on (turned on).

[0047] For this purpose, the third switching element SW3 is turned off. Since the output of the power conversion circuit 2 is a negative potential, the potential of the connection node N becomes substantially the same as the negative potential of the output of the power conversion circuit 2 through the second diode D2. This makes it possible to set the potential of the source of the second switching element SW2 to a second potential V2 that is lower than the first potential V1 and can turn off the first switching element SW1 when the second switching element SW2 is turned on. In order to be able to turn off the first switching element SW1, the second potential V2 should be set to a potential lower than the potential of the gate of the first switching element SW1 that is the sum of the negative potential of the output of the power conversion circuit 2 and the threshold of the first switching element SW1.

[0048] Then, the second switching element SW2 is turned from off to on by a control circuit (not shown) to make it conductive. Since the output of the power conversion circuit 2 is at a negative potential, charge is extracted from the gate of the first switching element SW1, and a current i flows through the path shown in Fig. 4, turning off the first switching element SW1 (changing it from on to off).

[0049] An on signal is applied to the gate of the upper arm switching element Q1 from a gate drive circuit (not shown). When the first switching element SW1 is turned off, the first switching element SW1 becomes non-conductive, and the potential between the reference potential terminal and the gate of the upper arm switching element Q1 becomes equal to or higher than a threshold value, so that the upper arm switching element Q1 is turned on.

[0050] The reason why the third switching element SW3 is turned off in the second period T2 is that if the third switching element SW3 remains on and the potential of the connection node N remains at the first potential V1, as explained in FIG. 3, the first switching element SW1 will be maintained on even if the second switching element SW2 is turned on, and the upper arm switching element Q1 cannot be turned on even if an on signal is applied to the gate of the upper arm switching element Q1.

[0051] FIG. 5 is a circuit diagram illustrating the operation of the upper arm driver circuit in the third period according to the first embodiment.

[0052] In the third period T3, as shown in Fig. 5, the upper arm switching element Q1 is on, the potential of the output of the power conversion circuit 2 is positive, the first switching element SW1 is off, the second switching element SW2 is on, and the third switching element SW3 is off. At this time, the current i from the output of the power conversion circuit 2 flows to the reference potential GND via the third diode D3, the second switching element SW2, the third resistor R3, the connection node N, and the first diode D1 along the path shown in Fig. 5.

[0053] If the third resistor R3 were not provided, a nearly short-circuit state would result, which would cause a problem of burning out the first diode D1, the second switching element SW2, and the third diode D3, which are elements in the path of the current i, and especially the second switching element SW2. In contrast, in this embodiment, the third resistor R3 prevents these elements from burning out, and reduces the current i that steadily flows while the upper arm switching element Q1 is on, thereby reducing power consumption.

[0054] Furthermore, in the state of Figure 5, the current i flows through the third diode D3, causing the source of the first switching element SW1 to have a higher potential than the gate, and a reverse bias can be created between the gate and source of the first switching element SW1 by the forward voltage of the third diode D3, so that the first switching element SW1 can be reliably maintained in the off state.

[0055] FIG. 6 is a circuit diagram illustrating the operation of the upper arm driver circuit in the fourth period according to the first embodiment.

[0056] 6, in order to turn off the upper-arm switching element Q1, a discharge circuit (not shown) draws out charge from the gate of the upper-arm switching element Q1, thereby turning off the upper-arm switching element Q1. Also, a control circuit (not shown) turns off the second switching element SW2, and turns on the first switching element SW1, thereby keeping the upper-arm switching element Q1 off.

[0057] As described above, according to the upper arm driver circuit 1 of the embodiment, it is possible to prevent malfunction of the upper arm switching element caused by the output of the power conversion circuit 2 being at a negative potential and undershooting.

[0058] Note that a signal having the inverse logic to the ON or OFF signal applied to the gate of the upper-arm switching element Q1 may be used as a signal for turning on or off the third switching element SW3, thereby simplifying the configuration of a control circuit (not shown) for controlling the operation of the third switching element SW3. EXAMPLES

[0059] FIG. 7 is a circuit diagram showing a schematic configuration of an upper arm driver circuit according to the second embodiment.

[0060] Example 2 is a modification of Example 1, in which the third switching element SW3 in the first circuit 5 is a MOSFET, and the first diode D1 is configured as a body diode built into the MOSFET. As the third switching element SW3, for example, an N-type MOSFET can be used.

[0061] According to this embodiment, the first circuit 5 can have a simple configuration. EXAMPLES

[0062] FIG. 8 is a circuit diagram showing a schematic configuration of an upper arm driver circuit according to the third embodiment.

[0063] Example 3 is a modified example of Example 1, and is an example in which the second circuit 6 has a fourth switching element SW4 that switches on and off between the reference potential terminal of the upper arm switching element Q1 and the source of the second switching element SW2.

[0064] The fourth switching element SW4 may be operated with the inverse logic of the third switching element SW3. EXAMPLES

[0065] FIG. 9 is a circuit diagram showing a schematic configuration of an upper arm driver circuit according to the fourth embodiment.

[0066] Example 4 is a modification of Example 1. The potential control circuit 4 of this example includes a fifth switching element SW5 that selectively switches on between the source of the second switching element SW2 and the reference potential GND and between the source of the second switching element SW2 and the reference potential terminal of the upper arm switching element Q1, and a first diode D1 that is connected in parallel to the fifth switching element SW5, has a cathode connected to the reference potential GND, and has an anode connected to the source of the second switching element SW2.

[0067] This embodiment corresponds to an embodiment in which the third switching element SW3 and the fourth switching element SW4 of the third embodiment are combined into one to form a fifth switching element SW5.

[0068] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied. [Explanation of symbols]

[0069] 1 Upper arm drive circuit 2. Power Conversion Circuit 3. Power conversion device 4. Potential control circuit 5. First Circuit 6 Second Circuit SW1 First switching element SW2 Second switching element SW3 Third switching element SW4 Fourth switching element D1 First diode D2 Second diode D3 Third diode ZD Zener diode R1 First resistor R2 Second resistor R3 Third Resistor N connected nodes Q1 Upper arm switching element Q2 Lower arm switching element DQ1 Upper arm freewheel diode DQ2 Lower arm freewheel diode VDC DC power supply potential OUT Output terminal GND Reference potential UND Undershoot t time T1 First period T2 Second Period T3 Third Period T4 Fourth Period V potential V1 First potential V2 Second potential i current

Claims

1. An upper arm driver circuit for driving an upper arm switching element of a power conversion circuit, a first switching element having a drain connected to the gate of the upper arm switching element and a source connected to a reference potential terminal of the upper arm switching element; a second switching element having a drain connected to the gate of the first switching element; a potential control circuit connected to a reference potential, a reference potential terminal of the upper arm switching element, and a source of the second switching element, and configured to control a potential of the source of the second switching element; the potential control circuit controls the potential of the source of the second switching element to a first potential at which the first switching element can remain on even if the second switching element is turned on due to a malfunction, during a first period from immediately after the upper arm switching element is turned off and including at least the time when the reference potential terminal of the upper arm switching element is at a negative potential and an undershoot ends, and controls the potential of the source of the second switching element to a second potential that is lower than the first potential and at which the first switching element can be turned off when the second switching element is turned on, during a second period from the end of the first period to before the upper arm switching element is turned on.

2. In claim 1, The upper arm drive circuit according to claim 1, wherein the first period is longer than the second period.

3. In claim 1, a gate drive circuit that applies an on signal or an off signal to a gate of the upper arm switching element; The upper arm drive circuit according to claim 1, wherein the second period is equal to or longer than a delay time from when an on signal is applied to the gate of the upper arm switching element until the upper arm switching element is turned on.

4. In claim 1, an upper arm drive circuit characterized in that the potential control circuit has a first circuit provided between the reference potential and a source of the second switching element, and a second circuit provided between a reference potential terminal of the upper arm switching element and the source of the second switching element.

5. In claim 4, an upper arm drive circuit characterized in that the first circuit includes a third switching element that turns on and off between the reference potential and a source of the second switching element, and a first diode that is connected in parallel to the third switching element, has a cathode connected to the reference potential, and has an anode connected to the source of the second switching element.

6. In claim 5, 2. An upper arm driver circuit according to claim 1, wherein the third switching element is a MOSFET, and the first diode is a body diode built into the MOSFET.

7. In claim 4, The upper arm drive circuit characterized in that the second circuit includes a second diode having a cathode connected to a reference potential terminal of the upper arm switching element and an anode connected to a source of the second switching element, and a first resistor connected in series with the second diode.

8. In claim 4, The upper arm driver circuit according to claim 1, wherein the second circuit has a fourth switching element that turns on and off between a reference potential terminal of the upper arm switching element and a source of the second switching element.

9. In claim 1, the potential control circuit comprises: a fifth switching element that selectively switches on between a source of the second switching element and the reference potential or a source of the second switching element and a reference potential terminal of the upper arm switching element; and a first diode that is connected in parallel to the fifth switching element, has a cathode connected to the reference potential and an anode connected to the source of the second switching element.

10. In claim 1, a second resistor connected to a gate of the upper arm switching element; a Zener diode having a cathode connected to the gate of the upper arm switching element and an anode connected to a reference potential terminal of the upper arm switching element.

11. In claim 1, an upper arm drive circuit comprising: a third diode having a cathode connected to the gate of the first switching element and an anode connected to the source of the first switching element;

12. In claim 1, an upper arm driver circuit comprising: a third resistor connected between the source of the second switching element and the potential control circuit;

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