Nitride semiconductor device and method of manufacturing nitride semiconductor device

Abstract

To suppress an increase in a gate leakage current in a nitride semiconductor device.SOLUTION: A nitride semiconductor device 10 includes: an electron travelling layer 22 comprising a first nitride semiconductor; an electron supply layer 24 formed on the electron travelling layer 22 and comprising a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; a gate layer 28 formed on the electron supply layer 24 and comprising a third nitride semiconductor containing acceptor type impurities; and a gate electrode 30 formed on an upper face 28A of the gate layer 28. The gate electrode 30 has an area smaller than that of the upper face 28A of the gate layer 28 in plan view. The upper face 28A of the gate layer 28 includes a first area 74 which is covered with the gate electrode 30 and a second area 76 which is not covered with the gate electrode 30. The surface roughness of the gate layer 28 in the second area 76 is within ±10% of the surface roughness of the gate layer 28 in the first area 74.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use two-dimensional electron gas (2DEG) formed near the interface of semiconductor heterojunctions as a conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and higher frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes a silicon substrate, an electron transit layer formed of a gallium nitride (GaN) layer, and an electron supply layer formed of an aluminum gallium nitride (AlGaN) layer. In the electron transit layer, a 2DEG is formed near the interface of the heterojunction between the electron transit layer and the electron supply layer. In the nitride semiconductor device of Patent Document 1, a GaN layer doped with acceptor-type impurities (p-type GaN layer) is provided on the electron supply layer and directly below the gate electrode. In this configuration, the p-type GaN layer raises the energy level of the conduction band near the heterojunction interface between the electron transit layer and the electron supply layer in the region directly below it, so that the channel directly below the p-type GaN layer can be eliminated. This realizes a normally-off operation of the nitride semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-73506 A

[0005] [overview] When a gate electrode is formed on a p-type GaN layer, etching damage may occur in the p-type GaN layer, which may increase the gate leakage current.

[0006] A nitride semiconductor device according to an embodiment of the present disclosure includes an electron transit layer made of a first nitride semiconductor, an electron supply layer formed on the electron transit layer and made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor, a gate layer formed on the electron supply layer and made of a third nitride semiconductor containing acceptor-type impurities, the gate layer including a bottom surface in contact with the electron supply layer and a top surface opposite to the bottom surface, and a gate electrode formed on the top surface of the gate layer. The gate electrode has an area smaller than that of the top surface of the gate layer in a plan view. The top surface of the gate layer includes a first region covered by the gate electrode and a second region not covered by the gate electrode. The surface roughness of the second region of the gate layer is within ±10% of the surface roughness of the first region of the gate layer.

[0007] Other features and aspects will become apparent from the following detailed description, the drawings, and the claims. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is an enlarged plan view of the nitride semiconductor device shown in FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the nitride semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is an enlarged view of a portion of FIG. [Diagram 5] FIG. 5 is an atomic force microscope image of the surface of a GaN layer used as a gate layer of a nitride semiconductor device. [Figure 6] 6A to 6C are schematic cross-sectional views for illustrating an exemplary manufacturing process for a nitride semiconductor device. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the state of the gate layer after the step shown in FIG. [Figure 14] FIG. 14 is a diagram showing a gate electrode etching process in the comparative example. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a state of the gate layer after a gate layer etching step in the comparative example.

[0009] [Detailed Description] Hereinafter, some embodiments of the nitride semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, for simplicity and clarity of illustration and description, components shown in the drawings are not necessarily drawn to scale. Also, for simplicity and clarity of illustration, hatching may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] (Schematic structure of nitride semiconductor device) An exemplary nitride semiconductor device 10 according to an embodiment will be described with reference to FIGS. 1 to 4. In this embodiment, the nitride semiconductor device 10 may be configured as a semiconductor chip on which a high electron mobility transistor (HEMT) is formed. FIG. 1 is a schematic plan view of the exemplary nitride semiconductor device 10 according to an embodiment. FIG. 2 is an enlarged plan view of the nitride semiconductor device 10. FIG. 3 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F3-F3 in FIG. 2. FIG. 4 is an enlarged view of a portion of FIG. 3.

[0012] 1 to 4, the Z-axis direction of the mutually orthogonal X, Y and Z axes is a direction orthogonal to the surface of the semiconductor substrate 18 (see FIG. 3). Note that the term "planar view" used in this specification means viewing the nitride semiconductor device 10 from above along the Z-axis direction, unless otherwise specified explicitly.

[0013] 1, the nitride semiconductor device 10 may include a gate pad 12, a source pad 14, and a drain pad 16 formed on an upper surface 10A having a rectangular shape in a plan view. The gate pad 12, the source pad 14, and the drain pad 16 may be electrically connected to a gate electrode, a source electrode, and a drain electrode (for example, a gate electrode 30, a source electrode 34, and a drain electrode 36 shown in FIG. 2) of a HEMT formed in a semiconductor chip, respectively. The gate pad 12, the source pad 14, and the drain pad 16 may constitute external connection terminals of the nitride semiconductor device 10.

[0014] 1, the nitride semiconductor device 10 includes a plurality of source pads 14 and a plurality of drain pads 16. The plurality of source pads 14 and the plurality of drain pads 16 may be arranged alternately in the X-axis direction. The number of pads 12, 14, and 16 arranged on the upper surface 10A can be determined arbitrarily according to the needs of a particular application.

[0015] The layout of the gate pad 12, the source pad 14, and the drain pad 16 is not limited to the example shown in Figure 1. The gate pad 12, the source pad 14, and the drain pad 16 can be arranged in any other layout.

[0016] Fig. 3 shows a schematic cross-sectional view of a HEMT active area located below the source pad 14 or the drain pad 16 shown in Fig. 1. As shown in Fig. 3, the nitride semiconductor device 10 may include a semiconductor substrate 18 and a buffer layer 20 formed on the semiconductor substrate 18.

[0017] The semiconductor substrate 18 may be formed of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. In one example, the semiconductor substrate 18 may be a Si substrate. The thickness of the semiconductor substrate 18 may be, for example, 200 μm or more and 1500 μm or less.

[0018] The buffer layer 20 may include one or more nitride semiconductor layers. The buffer layer 20 may be made of any material capable of suppressing the occurrence of warping or cracking of the nitride semiconductor device 10 due to the difference in thermal expansion coefficient between the semiconductor substrate 18 and a layer (such as the electron transit layer 22 described below) formed on the buffer layer 20. For example, the buffer layer 20 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having a different aluminum (Al) composition. For example, the buffer layer 20 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0019] In one example, the buffer layer 20 may include a first buffer layer which is an AlN layer formed on the semiconductor substrate 18, and a second buffer layer which is an AlGaN layer formed on the AlN layer. The first buffer layer may be, for example, an AlN layer having a thickness of 100 nm to 300 nm, while the second buffer layer may include a plurality of AlGaN layers having different compositions, each having a thickness of 100 nm to 300 nm. In order to suppress leakage current in the buffer layer 20, impurities may be introduced into a portion of the buffer layer 20 to make the buffer layer 20 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the concentration of the impurity may be, for example, 4×10 16 cm -3 It can be more than that.

[0020] The nitride semiconductor device 10 further includes an electron transit layer 22 and an electron supply layer 24 formed on the electron transit layer 22. The electron transit layer 22 may be formed on the buffer layer 20. The electron transit layer 22 is made of a first nitride semiconductor. The first nitride semiconductor may include GaN. The thickness of the electron transit layer 22 may be, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the electron transit layer 22, impurities may be introduced into a part of the electron transit layer 22 to make the electron transit layer 22 semi-insulating except for the surface layer region. In this case, the impurity may be, for example, C. The impurity concentration in the electron transit layer 22 may be, for example, 4×10 16 cm -3 or more. That is, the electron transit layer 22 may include a plurality of GaN layers having different impurity concentrations, for example, a C-doped GaN layer and a non-doped GaN layer. In this case, the C-doped GaN layer may be formed on the buffer layer 20. The C-doped GaN layer may have a thickness of 0.3 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer may be 5×10 17 cm -3 More than 9×10 19 cm -3The following can be adopted. The non-doped GaN layer is formed on the C-doped GaN layer and can have a thickness of 0.05 μm or more and 0.4 μm or less. The non-doped GaN layer is in contact with the electron supply layer 24. In one example, the electron traveling layer 22 may include a C-doped GaN layer with a thickness of 0.4 μm and a non-doped GaN layer with a thickness of 0.4 μm. Also, the C concentration in the C-doped GaN layer may be about 2×10 19 cm -3 or so.

[0021] The electron supply layer 24 is composed of a second nitride semiconductor having a larger bandgap than the first nitride semiconductor. The second nitride semiconductor may include AlGaN. In one example, the electron supply layer 24 is composed of Al x Ga 1-x N, where x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The electron supply layer 24 may have a thickness of 5 nm or more and 20 nm or less. In one example, the electron supply layer 24 may have a thickness of 8 nm or more.

[0022] The first nitride semiconductor (e.g., GaN) constituting the electron traveling layer 22 and the second nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 24 have different lattice constants from each other. Therefore, the electron traveling layer 22 and the electron supply layer 24 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron traveling layer 22 and the electron supply layer 24 and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the electron traveling layer 22 near the hetero-junction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 26 spreads in the electron traveling layer 22 at a position close to the hetero-junction interface between the electron traveling layer 22 and the electron supply layer 24 (e.g., within a range of about several nm from the interface). The 2DEG 26 in the electron traveling layer 22 functions as a channel of the nitride semiconductor device 10. The sheet carrier density of the 2DEG 26 generated in the electron traveling layer 22 can be increased by increasing at least one of the Al composition and the thickness of the electron supply layer 24.

[0023] (Gate layer and gate electrode) 3, the nitride semiconductor device 10 further includes a gate layer 28 formed on the electron supply layer 24, and a gate electrode 30. The gate layer 28 may be formed on a part of the electron supply layer 24. The gate layer 28 includes a bottom surface 28B in contact with the electron supply layer 24 and an upper surface 28A opposite to the bottom surface 28B. The gate electrode 30 is formed on the upper surface 28A of the gate layer 28.

[0024] The gate layer 28 is composed of a third nitride semiconductor containing acceptor-type impurities. The third nitride semiconductor may include GaN. In this embodiment, the gate layer 28 may be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the gate layer 28 is 7×10 18 cm -3 More than 1×10 20 cm -3 It can be as follows:

[0025] The gate electrode 30 may be composed of one or more metal layers. In one example, the gate electrode 30 may be composed of titanium nitride (TiN). In another example, the gate electrode 30 may include a first metal layer composed of Ti and a second metal layer composed of TiN provided on the first metal layer. The gate electrode 30 may form a Schottky junction with the gate layer 28. The thickness of the gate electrode 30 may be, for example, 50 nm to 200 nm.

[0026] The nitride semiconductor device 10 may further include a passivation layer 32 covering the electron supply layer 24, the gate layer 28, and the gate electrode 30. The passivation layer 32 has a first opening 32A and a second opening 32B. The first opening 32A and the second opening 32B are spaced apart in the X-axis direction. The gate layer 28 is located between the first opening 32A and the second opening 32B. More specifically, the gate layer 28 may be located between the first opening 32A and the second opening 32B, and closer to the first opening 32A than the second opening 32B. The passivation layer 32 may be made of, for example, silicon nitride (SiN), silicon dioxide (SiO 2 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 The passivation layer 32 may be formed of at least one of AlN, AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 32 may be, for example, 80 nm or more and 150 nm or less.

[0027] An upper surface 30A of the gate electrode 30 is covered with a passivation layer 32. A bottom surface 30B of the gate electrode 30 is in contact with an upper surface 28A of the gate layer 28. A side surface 30C of the gate electrode 30 is covered with the passivation layer 32. The gate electrode 30 has an area smaller than the upper surface 28A of the gate layer 28 in a plan view. Therefore, the side surface 30C of the gate electrode 30 is not flush with the side surface 28C of the gate layer 28.

[0028] (Source and drain electrodes) The nitride semiconductor device 10 further includes a source electrode 34 in contact with the electron supply layer 24 through the first opening 32A, and a drain electrode 36 in contact with the electron supply layer 24 through the second opening 32B. The source electrode 34 and the drain electrode 36 may be formed of one or more metal layers (e.g., any combination of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, an AlCu layer, etc.).

[0029] At least a portion of the source electrode 34 is filled in the first opening 32A, and therefore can make ohmic contact with the 2DEG 26 directly below the electron supply layer 24 through the first opening 32A. Similarly, at least a portion of the drain electrode 36 is filled in the second opening 32B, and therefore can make ohmic contact with the 2DEG 26 directly below the electron supply layer 24 through the second opening 32B.

[0030] (field plate electrode) The nitride semiconductor device 10 may optionally further include a field plate electrode 38 formed on the passivation layer 32 and extending at least partially into a region between the gate layer 28 and the drain electrode 36 in a plan view. In the example shown in FIG. 3, the field plate electrode 38 is formed integrally with the source electrode 34. Of the electrodes formed integrally, the source electrode 34 may include at least a portion embedded in the first opening 32A of the passivation layer 32, and the field plate electrode 38 may include the remaining portion. Note that the field plate electrode 38 may not necessarily be continuous with the source electrode 34 as long as it is electrically connected to the source electrode 34.

[0031] The field plate electrode 38 is spaced apart from the drain electrode 36. The field plate electrode 38 may include an end portion 38A that is located between the drain electrode 36 (second opening 32B) and the gate layer 28 in a plan view.

[0032] The field plate electrode 38 can alleviate electric field concentration near the end of the gate electrode 30 when a drain voltage is applied to the drain electrode 36 in a zero bias state where no gate voltage is applied to the gate electrode 30.

[0033] (Cross-sectional shape of gate layer) The gate layer 28 may include a ridge portion 40 that is in contact with the electron supply layer 24 and includes an upper surface 28A, and a first extension portion 42 and a second extension portion 44 that are in contact with the electron supply layer 24 and extend outward from the ridge portion 40 in a planar view and are thinner than the ridge portion 40. In the present disclosure, the first extension portion 42 and the second extension portion 44 may be collectively referred to as an "extension portion." Since the first extension portion 42 and the second extension portion 44 are thinner than the ridge portion 40, the upper surface 42A of the first extension portion 42 and the upper surface 44A of the second extension portion 44 are located lower than the upper surface 28A of the gate layer 28 in the Z-axis direction. The side surface 28C of the gate layer 28 connects the upper surface 28A of the gate layer 28 to the upper surface 42A of the first extension portion 42 and the upper surface 44A of the second extension portion 44.

[0034] The first extension portion 42 extends from the ridge portion 40 toward the first opening 32A. The first extension portion 42 partially covers the surface of the electron supply layer 24 between the ridge portion 40 and the first opening 32A in a plan view. The first extension portion 42 does not reach the source electrode 34 embedded in the first opening 32A.

[0035] The second extension portion 44 extends from the ridge portion 40 toward the second opening 32B. The second extension portion 44 partially covers the surface of the electron supply layer 24 between the ridge portion 40 and the second opening 32B in a plan view. The second extension portion 44 does not reach the drain electrode 36 embedded in the second opening 32B.

[0036] The ridge portion 40 is between the first extension portion 42 and the second extension portion 44, and is formed integrally with the first extension portion 42 and the second extension portion 44. Due to the presence of the first extension portion 42 and the second extension portion 44, the bottom surface 28B of the gate layer 28 has a larger area than the top surface 28A. In the example shown in FIG. 3, the second extension portion 44 may extend longer toward the outside of the ridge portion 40 in a planar view than the first extension portion 42. That is, the second extension portion 44 may have a larger dimension in the X-axis direction than the first extension portion 42. The first extension portion 42 may have a dimension in the X-axis direction of, for example, 0.2 μm or more and 0.3 μm or less. On the other hand, the second extension portion 44 may have a dimension in the X-axis direction of, for example, 0.2 μm or more and 0.6 μm or less.

[0037] The ridge portion 40 corresponds to a relatively thick portion of the gate layer 28. The ridge portion 40 may have a thickness of, for example, 80 nm or more and 150 nm or less. In one example, the ridge portion 40 may have a thickness greater than 110 nm. The first extension portion 42 and the second extension portion 44 have a thickness smaller than the thickness of the ridge portion 40. In one example, the first extension portion 42 and the second extension portion 44 may have a thickness equal to or less than half the thickness of the ridge portion 40.

[0038] As shown in FIG. 4, the first extension portion 42 may include a first step portion 46 having a substantially constant thickness, and a first intermediate portion 48 connecting the first step portion 46 to the ridge portion 40. In this specification, the term "substantially constant thickness" refers to the thickness being within the range of manufacturing variation (e.g., 20%). In one example, the thickness of the first step portion 46 may be 5 nm or more and 25 nm or less. The thickness of the first intermediate portion 48 may be equal to or more than the thickness of the first step portion 46 and less than the thickness of the ridge portion 40.

[0039] Similarly, the second extension portion 44 may include a second step portion 50 having a substantially constant thickness, and a second intermediate portion 52 connecting the second step portion 50 to the ridge portion 40. In one example, the thickness of the second step portion 50 may be 5 nm or more and 25 nm or less. The thickness of the second intermediate portion 52 may be equal to or more than the thickness of the second step portion 50 and less than the thickness of the ridge portion 40. The second step portion 50 may have the same thickness as the first step portion 46.

[0040] (Plane layout of nitride semiconductor device) Next, an example of a planar layout of the nitride semiconductor device 10 will be described with reference to FIG. 2. FIG. 2 mainly shows the active region of the HEMT located below the source pad 14 or the drain pad 16 shown in FIG. 1. In FIG. 2, the gate electrode 30, the source electrode 34, the drain electrode 36, and the field plate electrode 38 are drawn with dashed lines. In addition, for the passivation layer 32, the first opening 32A and the second opening 32B are drawn with solid lines, and the other parts are shown transparently. In addition, in FIG. 2, the first extension portion 42 and the second extension portion 44 are omitted.

[0041] 2, the gate layer 28 may be formed to surround the drain electrode 36 in a plan view. The gate layer 28 may include a main body portion 54 extending in the Y-axis direction and a connection portion 56 connecting two adjacent main body portions 54. The main body portion 54 of the gate layer 28 is disposed between the first opening 32A and the second opening 32B of the passivation layer 32.

[0042] The gate electrode 30 is disposed so as to overlap with the gate layer 28 in a planar view. Thus, like the gate layer 28, the gate electrode 30 may be formed so as to surround the drain electrode 36 in a planar view. The gate electrode 30 may include a main body portion 58 extending in the Y-axis direction and a connection portion 60 connecting two adjacent main body portions 58.

[0043] The nitride semiconductor device 10 may include a gate wiring 62, a source wiring 64, and a drain wiring 66. In FIG. 2, the gate wiring 62, the source wiring 64, and the drain wiring 66 are depicted by dashed lines. The gate wiring 62, the source wiring 64, and the drain wiring 66 are located above the source electrode 34 and the drain electrode 36 in the Z-axis direction. The gate wiring 62 may extend in the X-axis direction and be disposed above the connection portion 60 of the gate electrode 30. The source wiring 64 and the drain wiring 66 may extend in the X-axis direction and be disposed so as to intersect with the source electrode 34 and the drain electrode 36 in a plan view. In one example, the gate electrode 30 may be electrically connected to the gate wiring 62 through a via 68 disposed on the connection portion 60. The source electrode 34 may be electrically connected to the source wiring 64 through a via 70. The drain electrode 36 may be electrically connected to the drain wiring 66 through a via 72. The gate wiring 62, the source wiring 64, and the drain wiring 66 may be electrically connected to the gate pad 12, the source pad 14, and the drain pad 16 shown in FIG. 1, respectively.

[0044] The planar layout of the nitride semiconductor device 10 is not limited to the example shown in Fig. 2. Any other planar layout can be applied to the nitride semiconductor device 10. (Surface condition of gate layer) Returning to FIG. 4, the surface state of the gate layer 28 will be described. As shown in FIG. 4, the upper surface 28A of the gate layer 28 includes a first region 74 covered by the gate electrode 30 and a second region 76 not covered by the gate electrode 30. That is, the first region 74 is a region in contact with the gate electrode 30 (bottom surface 30B), while the second region 76 is a region not in contact with the gate electrode 30. The second region 76 is in contact with the passivation layer 32. The second region 76 extends between the side surface 30C of the gate electrode 30 and the side surface 28C of the gate layer 28. In a plan view, the first region 74 overlaps with the gate electrode 30, while the second region 76 is adjacent to the gate electrode 30 (see FIG. 2).

[0045] As described later with reference to FIGS. 6 to 12, in the manufacturing process of the nitride semiconductor device 10, the first region 74 and the second region 76 are subjected to different processes. Specifically, the first region 74 corresponds to an unetched surface since it is covered with the gate electrode 30, whereas the second region 76 corresponds to an etched surface. However, in this embodiment, the surface roughness of the first region 74 is approximately the same as the surface roughness of the second region 76. Specifically, the surface roughness of the second region 76 of the gate layer 28 is within ±10% of the surface roughness of the first region 74 of the gate layer 28. The surface roughness can be expressed by a root mean square value (RMS value). The surface roughness of the first region 74 and the surface roughness of the second region 76 of the gate layer 28 may be less than 1 nm.

[0046] The surface roughness in the first region 74 of the gate layer 28 may be less than the surface roughness of the upper surfaces 42A, 44A of the extensions 42, 44. Similarly, the surface roughness in the second region 76 of the gate layer 28 may be less than the surface roughness of the upper surfaces 42A, 44A of the extensions 42, 44.

[0047] Additionally, the surface roughness in the first region 74 of the gate layer 28 may be smaller than the surface roughness of the side surface 28C of the gate layer 28. Similarly, the surface roughness in the second region 76 of the gate layer 28 may be smaller than the surface roughness of the side surface 28C of the gate layer 28.

[0048] FIG. 5 is an atomic force microscope image (AFM image) of the surface of the GaN layer used as the gate layer 28 of the nitride semiconductor device 10. The AFM image shown in FIG. 5 shows the surface of the GaN layer after epitaxial growth. In the example of FIG. 5, the surface roughness (RMS value) of the GaN layer is about 0.78 nm. A plurality of pits P and a plurality of steps S can be observed on the surface of the GaN layer. As will be described later, since there is no or almost no damaged layer due to etching in the first region 74 and the second region 76 of the gate layer 28, the surface roughness of the first region 74 and the second region 76 may be equivalent to that of the surface of the GaN layer after epitaxial growth. Therefore, in the first region 74 and the second region 76, a plurality of pits P and a plurality of steps S can be observed, similar to the surface of the GaN layer after epitaxial growth shown in FIG. 5. Thus, in this embodiment, the upper surface 28A of the gate layer 28 may have a plurality of pits P formed in the first region 74. Furthermore, the upper surface 28A of the gate layer 28 may have a plurality of steps S formed in the first region 74. Similarly, the upper surface 28A of the gate layer 28 may have a plurality of pits P formed in the second region 76. Furthermore, the upper surface 28A of the gate layer 28 may have a plurality of steps S formed in the second region 76.

[0049] (Method of Manufacturing Nitride Semiconductor Device) Next, an example of a method for manufacturing the nitride semiconductor device 10 will be described with reference to Fig. 6 to Fig. 12. Fig. 6 to Fig. 12 are schematic cross-sectional views showing exemplary manufacturing steps for the nitride semiconductor device 10. For ease of understanding, in Fig. 6 to Fig. 12, the same components as those in Fig. 3 are denoted by the same reference numerals.

[0050] A method for manufacturing the nitride semiconductor device 10 includes forming a first nitride semiconductor layer 78, forming a second nitride semiconductor layer 80 having a larger band gap than the first nitride semiconductor layer 78 on the first nitride semiconductor layer 78, and forming a third nitride semiconductor layer 82 containing acceptor-type impurities on the second nitride semiconductor layer 80.

[0051] 6, a buffer layer 20, a first nitride semiconductor layer 78, a second nitride semiconductor layer 80, and a third nitride semiconductor layer 82 are sequentially stacked on a semiconductor substrate 18, which is, for example, a Si substrate. The buffer layer 20, the first nitride semiconductor layer 78, the second nitride semiconductor layer 80, and the third nitride semiconductor layer 82 can be epitaxially grown by using a metal organic chemical vapor deposition (MOCVD) method.

[0052] Although detailed illustration is omitted, in one example, the buffer layer 20 may be a multi-layer buffer layer. The multi-layer buffer layer may include an AlN layer (first buffer layer) formed on the semiconductor substrate 18, and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer may be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in that order from the side closest to the AlN layer.

[0053] The first nitride semiconductor layer 78 formed on the buffer layer 20 may be a GaN layer. Furthermore, the second nitride semiconductor layer 80 formed on the first nitride semiconductor layer 78 may be an AlGaN layer. The second nitride semiconductor layer 80 has a larger band gap than the first nitride semiconductor layer 78. The first nitride semiconductor layer 78 and the second nitride semiconductor layer 80 correspond to the electron transit layer 22 and the electron supply layer 24 shown in FIG. 3, respectively.

[0054] The third nitride semiconductor layer 82 may be a GaN layer containing acceptor-type impurities. In one example, the third nitride semiconductor layer 82 containing acceptor-type impurities can be formed by doping with magnesium during the growth of the third nitride semiconductor layer 82. The amount of magnesium doped into the third nitride semiconductor layer 82 can be determined, for example, by the amount of doping gas (e.g., biscyclopentadienylmagnesium (Cp 2 The thickness of the third nitride semiconductor layer 82 can be adjusted by controlling the flow rate of 1×10 18 cm-3 More than 1×10 20 cm -3 It may contain magnesium as an impurity at a concentration of less than 10000000.

[0055] The method for manufacturing the nitride semiconductor device 10 further includes forming a metal layer 84 on the third nitride semiconductor layer 82, and forming a gate electrode 30 on the third nitride semiconductor layer 82 by selectively removing the metal layer 84.

[0056] 7, a metal layer 84 is formed on the third nitride semiconductor layer 82. The metal layer 84 may be, for example, a TiN layer. Then, a first hard mask layer 88 is formed on the metal layer 84. The first hard mask layer 88 may be, for example, a SiN layer.

[0057] 8, the metal layer 84 and the first hard mask layer 88 are selectively removed by lithography and etching. As a result, a portion of the metal layer 84 corresponding to the gate electrode 30 shown in FIG. 3 and the first hard mask layer 88 covering the upper surface of that portion are left on the third nitride semiconductor layer 82. In this way, the gate electrode 30 is formed in the first region 86 of the third nitride semiconductor layer 82. In other words, the first region 86 of the third nitride semiconductor layer 82 is a region covered by the gate electrode 30.

[0058] Here, forming the gate electrode 30 may include performing chemical etching on the third nitride semiconductor layer 82. In the final stage of etching the metal layer 84 and the first hard mask layer 88, the surface of the third nitride semiconductor layer 82 other than the first region 86 is exposed. At this time, the surface of the third nitride semiconductor layer 82 may be damaged by etching (e.g., physical etching such as plasma etching) used to remove the metal layer 84. Therefore, in at least a part of the etching process (e.g., the final stage), chemical etching is performed on the exposed surface of the third nitride semiconductor layer 82, so that the damaged layer formed on the surface of the third nitride semiconductor layer 82 can be removed.

[0059] Additionally or alternatively, forming the gate electrode 30 may include performing atomic layer etching (ALE) on the third nitride semiconductor layer 82. In ALE, a reactive gas is chemically reacted with an atomic layer on the top surface of an etching target (e.g., the third nitride semiconductor layer 82), and the reacted layer (e.g., a monoatomic layer) can be selectively etched by ion irradiation. By performing ALE on the exposed surface of the third nitride semiconductor layer 82, a damaged layer formed on the surface of the third nitride semiconductor layer 82 can be removed.

[0060] The method for manufacturing the nitride semiconductor device 10 further includes selectively removing the third nitride semiconductor layer 82 to form the gate layer 28. 9, a second hard mask layer 90 is formed to cover the gate electrode 30, the first hard mask layer 88, and the third nitride semiconductor layer 82. The second hard mask layer 90 may be, for example, a SiN layer.

[0061] 10, the second hard mask layer 90 is selectively removed by anisotropic etching. The anisotropic etching mainly proceeds in the thickness direction of the second hard mask layer 90, and as a result, the portions of the second hard mask layer 90 that cover the side surfaces of the gate electrode 30 and the first hard mask layer 88 are left behind.

[0062] As shown in FIG. 11, the third nitride semiconductor layer 82 is etched using the first hard mask layer 88 and the second hard mask layer 90. The portion of the third nitride semiconductor layer 82 located under the first hard mask layer 88 and the second hard mask layer 90 is not etched, and as a result, a first portion 92 corresponding to the ridge portion 40 of the gate layer 28 described with reference to FIG. 3 is formed. On the other hand, the portion of the third nitride semiconductor layer 82 not covered by the first hard mask layer 88 and the second hard mask layer 90 is etched, and as a result, a second portion 96 shown in FIG. 11 is formed. The thickness of the second portion 96 of the third nitride semiconductor layer 82 may be half or less of the thickness of the first portion 92. The upper surface of the first portion 92 of the third nitride semiconductor layer 82 includes the first region 86 covered by the gate electrode 30 and the second region 94 covered by the second hard mask layer 90. The first region 86 and the second region 94 respectively correspond to the first region 74 and the second region 76 of the gate layer 28 shown in FIG.

[0063] 12, the third nitride semiconductor layer 82 is selectively removed so that a part of the second portion 96 corresponding to the first extension 42 and the second extension 44 remains. As a result, the gate layer 28 including the ridge portion 40, the first extension 42, and the second extension 44 is formed. The gate layer 28 includes a bottom surface 28B in contact with the second nitride semiconductor layer 80 and an upper surface 28A opposite to the bottom surface 28B. The gate electrode 30 has an area smaller than the upper surface 28A of the gate layer 28 in a plan view. The upper surface 28A of the gate layer 28 includes a first region 74 (a first region 86 of the third nitride semiconductor layer 82) covered by the gate electrode 30 and a second region 76 (a second region 94 of the third nitride semiconductor layer 82) not covered by the gate electrode 30. The surface roughness of the second region 76 is within ±10% of the surface roughness of the first region 74.

[0064] Although not shown, the manufacturing method of the nitride semiconductor device 10 further includes forming a passivation layer 32 covering the second nitride semiconductor layer 80 (electron supply layer 24), the gate layer 28, and the gate electrode 30, forming a first opening 32A and a second opening 32B in the passivation layer 32, and forming a source electrode 34 in contact with the second nitride semiconductor layer 80 through the first opening 32A and a drain electrode 36 in contact with the second nitride semiconductor layer 80 through the second opening 32B. In this way, the nitride semiconductor device 10 shown in FIG. 3 can be obtained.

[0065] (Gate layer condition after etching) FIG. 13 is a schematic cross-sectional view showing the state of the gate layer 28 after the step shown in FIG. 11. A first portion 92 and a second portion 96 are formed in the third nitride semiconductor layer 82 by etching using the first hard mask layer 88 and the second hard mask layer 90. Dry etching may be used for etching the third nitride semiconductor layer 82. In this case, a damage layer D having a relatively rough surface may be formed on the surface of the third nitride semiconductor layer 82 to be etched by ion bombardment. As shown in FIG. 13, the damage layer D may be formed on the surface exposed to the plasma of the dry etching, that is, the side surface of the first portion 92 and the upper surface of the second portion 96. The surface roughness (RMS value) of the third nitride semiconductor layer 82 on which the damage layer D is formed may exceed 1 nm. It should be understood that the damage layer D is exaggerated in FIG. 13 for ease of understanding.

[0066] On the other hand, no damage layer is formed in the first region 86 of the third nitride semiconductor layer 82 covered by the gate electrode 30. Similarly, no damage layer is formed in the second region 94 of the third nitride semiconductor layer 82 covered by the second hard mask layer 90. Note that the second region 94 may have already been affected by the etching of the gate electrode 30. However, even if a damage layer is formed in the second region 94 during the etching of the gate electrode 30, the damage layer is removed by chemical etching and / or ALE prior to the formation of the second hard mask layer 90.

[0067] The first portion 92 of the third nitride semiconductor layer 82 corresponds to the ridge portion 40 of the gate layer 28 shown in Fig. 3. A part of the second portion 96 of the third nitride semiconductor layer 82 corresponds to the extensions 42, 44 of the gate layer 28 shown in Fig. 3. The surface roughness of the first region 86 and the second region 94 may be smaller than the surface roughness of the side surface 28C (the side surface of the ridge portion 40) of the gate layer 28 and the upper surfaces 42A, 44A of the extensions 42, 44.

[0068] (Functions of nitride semiconductor devices) The operation of the nitride semiconductor device 10 will be described below. The nitride semiconductor device 10 includes a gate layer 28 including a bottom surface 28B in contact with the electron supply layer 24 and a top surface 28A opposite to the bottom surface 28B, and a gate electrode 30 formed on the top surface 28A of the gate layer 28. The gate electrode 30 has an area smaller than the top surface 28A of the gate layer 28 in a plan view. The top surface 28A of the gate layer 28 includes a first region 74 covered by the gate electrode 30 and a second region 76 not covered by the gate electrode 30. The surface roughness of the second region 76 of the gate layer 28 is within ±10% of the surface roughness of the first region 74 of the gate layer 28. That is, the surface roughness of the second region 76 of the gate layer 28 is approximately equal to the surface roughness of the first region 74. The fact that the second region 76 has a surface roughness equivalent to that of the first region 74 that is not damaged by etching means that there is no or almost no layer damaged by etching in the second region 76 of the gate layer 28.

[0069] If a damage layer is formed in the second region 76 of the gate layer 28, a relatively large gate leakage current may occur. Since the second region 76 extends between the side surface 30C of the gate electrode 30 and the side surface 28C of the gate layer 28, the second region 76 may become a path for a leakage current flowing through the surfaces of the gate electrode 30 and the gate layer 28. In addition, the portion of the gate layer 28 located near the side surface 30C of the gate electrode 30 is a place where an electric field is relatively likely to concentrate. Therefore, the amount of the gate leakage current may be largely dependent on the surface state of the second region 76.

[0070] In this embodiment, the surface roughness in the second region 76 of the gate layer 28 is within ±10% of the surface roughness in the first region 74 of the gate layer 28. Since the second region 76 of the gate layer 28 has a surface roughness equivalent to that of the first region 74 that is not damaged by etching, an increase in gate leakage current can be suppressed.

[0071] To further explain how the nitride semiconductor device 10 of this embodiment suppresses an increase in gate leakage current, an etching step in a comparative example will be described with reference to FIGS.

[0072] Fig. 14 is a diagram showing an etching step of the gate electrode 30 in a comparative example. In the comparative example, chemical etching and / or ALE are not performed in the etching step of the gate electrode 30 shown in Fig. 8. As a result, a damage layer D having a relatively rough surface formed by ion bombardment remains on a surface 100 of the third nitride semiconductor layer 82 except for the first region 86 covered by the gate electrode 30. The surface roughness (RMS value) of the third nitride semiconductor layer 82 with the damage layer D formed thereon can exceed 1 nm.

[0073] FIG. 15 is a schematic cross-sectional view showing a state of the gate layer 28 after the etching process of the gate layer 28 in the comparative example. As shown in FIG. 15, a first portion 92 and a second portion 96 are formed in the third nitride semiconductor layer 82 by etching using the first hard mask layer 88 and the second hard mask layer 90. Since the second hard mask layer 90 is formed after the process shown in FIG. 14, a damage layer D exists under the second hard mask layer 90. Therefore, unlike the present embodiment shown in FIG. 13, the second region 102 of the comparative example covered by the second hard mask layer 90 has the damage layer D. As a result, the surface roughness in the second region 102 of the third nitride semiconductor layer 82 is significantly larger than the surface roughness in the first region 86 covered by the gate electrode 30. Due to the presence of the damage layer D in the second region 102, the gate leakage current increases in the comparative example.

[0074] In this regard, in the present embodiment, since the damaged layer in the second region 76 of the gate layer 28 is removed, the surface roughness in the second region 76 of the gate layer 28 is substantially equivalent to the surface roughness in the first region 74 covered by the gate electrode 30. Therefore, according to the nitride semiconductor device 10 of the present embodiment, it is possible to reduce the gate leakage current.

[0075] The nitride semiconductor device 10 of this embodiment has the following advantages. (1) The nitride semiconductor device 10 includes a gate layer 28 including a bottom surface 28B in contact with the electron supply layer 24 and a top surface 28A opposite to the bottom surface 28B, and a gate electrode 30 formed on the top surface 28A of the gate layer 28. The gate electrode 30 has an area smaller than the top surface 28A of the gate layer 28 in a plan view. The top surface 28A of the gate layer 28 includes a first region 74 covered by the gate electrode 30 and a second region 76 not covered by the gate electrode 30. The surface roughness of the second region 76 of the gate layer 28 is within ±10% of the surface roughness of the first region 74 of the gate layer 28. According to this configuration, the second region 76 has a surface roughness substantially equivalent to that of the first region 74 in which no damage layer due to etching is formed, and therefore an increase in gate leakage current can be suppressed.

[0076] (2) The surface roughness of the second region 76 of the gate layer 28 may be smaller than the surface roughness of the side surface 28C of the gate layer 28. With this configuration, the surface roughness of the second region 76 located closer to the gate electrode 30 can be made smaller than that of the side surface 28C of the gate layer 28, thereby efficiently suppressing an increase in gate leakage current.

[0077] (4) The surface roughness of the second region 76 of the gate layer 28 may be smaller than the surface roughness of the upper surfaces 42A, 44A of the extensions 42, 44. With this configuration, the surface roughness of the second region 76 located closer to the gate electrode 30 can be made smaller than that of the upper surfaces 42A, 44A of the extensions 42, 44 of the gate layer 28, and therefore an increase in the gate leakage current can be efficiently suppressed.

[0078] (5) The gate layer 28 may include a ridge portion 40 that is in contact with the electron supply layer 24 and includes an upper surface 28A of the gate layer 28, and extension portions 42, 44 that are in contact with the electron supply layer 24 and extend outward from the ridge portion 40 in a planar view. The extension portions 42, 44 are thinner than the ridge portion 40. When the gate layer 28 includes the extension portions 42, 44 that are thinner than the ridge portion 40, local electric field concentration in the gate layer 28 can be suppressed. Therefore, the gate reliability of the nitride semiconductor device 10 can be improved.

[0079] (6) Forming the gate electrode 30 may include chemically etching the third nitride semiconductor layer 82. This makes it possible to chemically remove a damaged layer in the third nitride semiconductor layer 82 caused by the etching for forming the gate electrode 30. As a result, an increase in the gate leakage current of the nitride semiconductor device 10 can be suppressed.

[0080] (7) Forming the gate electrode 30 may include performing atomic layer etching (ALE) on the third nitride semiconductor layer 82. This makes it possible to remove a damaged layer of the third nitride semiconductor layer 82 caused by the etching for forming the gate electrode 30 with precision at the atomic layer level. As a result, an increase in the gate leakage current of the nitride semiconductor device 10 can be suppressed.

[0081] [Example of change] The above embodiment can be modified as follows. 4, the gate electrode 30 is located at the center of the upper surface 28A of the gate layer 28, so the second region 76 extends symmetrically on both sides of the first region 74. However, the second region 76 may extend asymmetrically on both sides of the first region 74. For example, the gate electrode 30 may be located closer to the drain electrode 36 on the upper surface 28A of the gate layer 28, so that the second region 76 closer to the first opening 32A is wider than the second region 76 closer to the second opening 32B.

[0082] The gate layer 28 does not have to include the extensions 42, 44. In other words, the gate layer 28 may be formed to have a substantially uniform thickness. Chemical etching and / or ALE may be performed in the etching step of the gate layer 28. In this case, the surface roughness in the second region 76 of the gate layer 28 may be substantially equivalent (for example, within ±10%) to the surface roughness of the side surface 28C (side surface of the ridge portion 40) of the gate layer 28 and / or the top surfaces 42A, 44A of the extensions 42, 44.

[0083] One or more of the various examples described in this specification may be combined to the extent that they are not technically inconsistent. In this specification, the phrase "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0084] As used herein, the term "on" includes the meanings "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude structures in which other layers are formed between the first and second layers.

[0085] The directional terms used herein, such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," "rear," and the like, depend on the particular orientation of the device being described and illustrated. Various alternative orientations can be envisioned in this disclosure, and therefore these directional terms should not be construed in a narrow sense.

[0086] For example, the Z-axis direction used in this specification does not necessarily have to be the vertical direction, and does not necessarily have to completely coincide with the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0087] [Note] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference numbers of the corresponding components in the embodiments. The reference numbers are shown as examples for the purpose of aiding understanding, and the components described in each appendix should not be limited to the components indicated by the reference numbers.

[0088] (Appendix 1) an electron transit layer (22) made of a first nitride semiconductor; an electron supply layer (24) formed on the electron transit layer (22) and made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; a gate layer (28) formed on the electron supply layer (24) and made of a third nitride semiconductor containing an acceptor-type impurity, the gate layer (28) including a bottom surface (28B) in contact with the electron supply layer (24) and an upper surface (28A) opposite to the bottom surface (28B); a gate electrode (30) formed on the upper surface (28A) of the gate layer (28); Equipped with the gate electrode (30) has an area smaller than the upper surface (28A) of the gate layer (28) in a plan view, and the upper surface (28A) of the gate layer (28) includes a first region (74) that is covered by the gate electrode (30) and a second region (76) that is not covered by the gate electrode (30); A nitride semiconductor device, wherein the surface roughness of the second region (76) of the gate layer (28) is within ±10% of the surface roughness of the first region (74) of the gate layer (28).

[0089] (Appendix 2) 2. The nitride semiconductor device according to claim 1, wherein the upper surface (28A) of the gate layer (28) has a plurality of pits (P) formed in the second region (76).

[0090] (Appendix 3) 3. The nitride semiconductor device according to claim 1, wherein the upper surface (28A) of the gate layer (28) has a plurality of steps (S) formed in the second region (76).

[0091] (Appendix 4) The nitride semiconductor device according to any one of claims 1 to 3, wherein the second region (76) extends between a side surface (30C) of the gate electrode (30) and a side surface (28C) of the gate layer (28).

[0092] (Appendix 5) 5. The nitride semiconductor device according to claim 4, wherein a surface roughness of the second region (76) of the gate layer (28) is smaller than a surface roughness of the side surface (28C) of the gate layer (28).

[0093] (Appendix 6) The gate layer (28) is a ridge portion (40) in contact with the electron supply layer (24) and including the upper surface (28A) of the gate layer (28); an extension portion (42, 44) that is in contact with the electron supply layer (24) and extends outward from the ridge portion (40) in a plan view and is thinner than the ridge portion (40); 6. The nitride semiconductor device according to any one of claims 1 to 5, comprising:

[0094] (Appendix 7) 7. The nitride semiconductor device according to claim 6, wherein a surface roughness of the second region (76) of the gate layer (28) is smaller than a surface roughness of upper surfaces (42A, 44A) of the extensions (42, 44).

[0095] (Appendix 8) The nitride semiconductor device according to any one of claims 1 to 7, further comprising a passivation layer (32) covering the electron supply layer (24), the gate layer (28), and the gate electrode (30), and the second region (76) is in contact with the passivation layer (32).

[0096] (Appendix 9) Further comprising a source electrode (34) and a drain electrode (36); The passivation layer (32) has a first opening (32A) and a second opening (32B); the gate layer (28) is located between the first opening (32A) and the second opening (32B); the source electrode (34) is in contact with the electron supply layer (24) through the first opening (32A); the drain electrode (36) is in contact with the electron supply layer (24) through the second opening (32B); 9. The nitride semiconductor device according to claim 8.

[0097] (Appendix 10) the first nitride semiconductor includes GaN; the second nitride semiconductor includes AlGaN; The third nitride semiconductor includes GaN, 10. The nitride semiconductor device according to any one of claims 1 to 9.

[0098] (Appendix 11) forming a first nitride semiconductor layer (78); forming a second nitride semiconductor layer (80) on the first nitride semiconductor layer (78), the second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer (78); forming a third nitride semiconductor layer (82) containing an acceptor-type impurity on the second nitride semiconductor layer (80); forming a metal layer (84) on the third nitride semiconductor layer (82); forming a gate electrode (30) on the third nitride semiconductor layer (82) by selectively removing the metal layer (84); By selectively removing the third nitride semiconductor layer (82), a gate layer (28) is formed including a bottom surface (28B) in contact with the second nitride semiconductor layer (80) and an upper surface (28A) opposite to the bottom surface (28B). Including, the gate electrode (30) has an area smaller than the upper surface (28A) of the gate layer (28) in a plan view, and the upper surface (28A) of the gate layer (28) includes a first region (74) that is covered by the gate electrode (30) and a second region (76) that is not covered by the gate electrode (30); A method for manufacturing a nitride semiconductor device, wherein the surface roughness in the second region (76) is within ±10% of the surface roughness in the first region (74).

[0099] (Appendix 12) 12. The method for manufacturing a nitride semiconductor device according to claim 11, wherein forming the gate electrode (30) includes chemically etching the third nitride semiconductor layer (82).

[0100] (Appendix 13) 12. The method for manufacturing a nitride semiconductor device according to claim 11, wherein forming the gate electrode (30) includes performing atomic layer etching on the third nitride semiconductor layer (82).

[0101] (Appendix 14) The method for manufacturing a nitride semiconductor device according to any one of claims 11 to 13, wherein the upper surface (28A) of the gate layer (28) has a plurality of pits (P) formed in the second region (76).

[0102] (Appendix 15) The method for manufacturing a nitride semiconductor device according to any one of Appendices 11 to 14, wherein the upper surface (28A) of the gate layer (28) has a plurality of steps (S) formed in the second region (76).

[0103] (Appendix 16) 16. The method for manufacturing a nitride semiconductor device according to any one of claims 11 to 15, wherein the second region (76) extends between a side surface (30C) of the gate electrode (30) and a side surface (28C) of the gate layer (28).

[0104] (Appendix 17) 17. The method for manufacturing a nitride semiconductor device according to claim 16, wherein a surface roughness of the second region (76) is smaller than a surface roughness of the side surface (28C) of the gate layer (28).

[0105] (Appendix 18) The method for manufacturing a nitride semiconductor device according to any one of Appendices 11 to 17, further comprising forming a passivation layer (32) covering the second nitride semiconductor layer (80), the gate layer (28), and the gate electrode (30), wherein the second region (76) is in contact with the passivation layer (32).

[0106] (Appendix 19) forming a first opening (32A) and a second opening (32B) in the passivation layer (32); Forming a source electrode (34) and a drain electrode (36) Further comprising: the gate layer (28) is located between the first opening (32A) and the second opening (32B); the source electrode (34) is in contact with the second nitride semiconductor layer (80) through the first opening (32A); The drain electrode (36) is in contact with the second nitride semiconductor layer (80) through the second opening (32B). 19. A method for manufacturing a nitride semiconductor device according to claim 18.

[0107] (Appendix 20) the first nitride semiconductor layer (78) is a GaN layer; the second nitride semiconductor layer (80) is an AlGaN layer, The third nitride semiconductor layer (82) is a GaN layer containing acceptor-type impurities. 20. A method for manufacturing a nitride semiconductor device according to any one of claims 11 to 19.

[0108] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0109] 10...Nitride semiconductor device 10A…Top surface 12…Gate pad 14…Sauce Pad 16…Drain pad 18...Semiconductor substrate 20…Buffer layer 22...Electron transport layer 24…electron supply layer 26...Two-dimensional electron gas (2DEG) 28…Gate layer 28A…Top surface 28B…Bottom surface 28C…side 30...Gate electrode 30A…Top surface 30B…Bottom surface 30C…side 32…passivation layer 32A…1st opening 32B…Second opening 34...Source electrode 36...Drain electrode 38...Field plate electrode 40…Ridge 42...First extension part 44…Second extension part 46…First step section 48…First intermediate section 50…Second step section 52…Second intermediate section 54,58…Main body 56,60…Connection 62…Gate wiring 64…Source wiring 66…Drain wiring 68,70,72…Beer 74…First area 76…Second area 78...First nitride semiconductor layer 80...Second nitride semiconductor layer 82...Third nitride semiconductor layer 84...Metal layer 86…First area 88…First hard mask layer 90…Second hard mask layer 92…Part 1 94…Second area 96…Second part 100…Surface 102…Second area P…pit S…Step D: Damage layer

Claims

1. an electron transit layer made of a first nitride semiconductor; an electron supply layer formed on the electron transit layer and made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; a gate layer formed on the electron supply layer and made of a third nitride semiconductor containing an acceptor-type impurity, the gate layer including a bottom surface in contact with the electron supply layer and an upper surface opposite to the bottom surface; a gate electrode formed on the top surface of the gate layer; Equipped with the gate electrode has an area smaller than that of the upper surface of the gate layer in a plan view, and the upper surface of the gate layer includes a first region that is covered by the gate electrode and a second region that is not covered by the gate electrode; a surface roughness of the second region of the gate layer is within ±10% of a surface roughness of the first region of the gate layer.

2. The nitride semiconductor device according to claim 1 , wherein said top surface of said gate layer has a plurality of pits formed in said second region.

3. The nitride semiconductor device according to claim 1 , wherein said top surface of said gate layer has a plurality of steps formed in said second region.

4. The nitride semiconductor device according to claim 1 , wherein said second region extends between a side surface of said gate electrode and a side surface of said gate layer.

5. The nitride semiconductor device according to claim 4 , wherein a surface roughness of said second region of said gate layer is smaller than a surface roughness of said side surface of said gate layer.

6. The gate layer is a ridge portion in contact with the electron supply layer and including the upper surface of the gate layer; an extension portion that is in contact with the electron supply layer and extends outward from the ridge portion in a plan view and is thinner than the ridge portion; The nitride semiconductor device according to claim 1 , comprising:

7. The nitride semiconductor device according to claim 6 , wherein a surface roughness of said second region of said gate layer is smaller than a surface roughness of an upper surface of said extension portion.

8. 6. The nitride semiconductor device according to claim 1, further comprising a passivation layer covering said electron supply layer, said gate layer, and said gate electrode, said second region being in contact with said passivation layer.

9. Further comprising a source electrode and a drain electrode, the passivation layer has a first opening and a second opening; the gate layer is located between the first opening and the second opening; the source electrode is in contact with the electron supply layer through the first opening, the drain electrode is in contact with the electron supply layer through the second opening; The nitride semiconductor device according to claim 8 .

10. the first nitride semiconductor includes GaN; the second nitride semiconductor includes AlGaN; The third nitride semiconductor includes GaN. The nitride semiconductor device according to any one of claims 1 to 5.

11. forming a first nitride semiconductor layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer, the second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer; forming a third nitride semiconductor layer containing an acceptor-type impurity on the second nitride semiconductor layer; forming a metal layer on the third nitride semiconductor layer; forming a gate electrode on the third nitride semiconductor layer by selectively removing the metal layer; selectively removing the third nitride semiconductor layer to form a gate layer including a bottom surface in contact with the second nitride semiconductor layer and an upper surface opposite to the bottom surface; Including, the gate electrode has an area smaller than that of the upper surface of the gate layer in a plan view, and the upper surface of the gate layer includes a first region that is covered by the gate electrode and a second region that is not covered by the gate electrode; A method for manufacturing a nitride semiconductor device, wherein the surface roughness of the second region is within ±10% of the surface roughness of the first region.

12. The method for manufacturing a nitride semiconductor device according to claim 11 , wherein forming the gate electrode includes chemically etching the third nitride semiconductor layer.

13. The method for manufacturing a nitride semiconductor device according to claim 11 , wherein forming the gate electrode includes performing atomic layer etching on the third nitride semiconductor layer.

14. The method for manufacturing a nitride semiconductor device according to claim 11, wherein the upper surface of the gate layer has a plurality of pits formed in the second region.

15. The method for manufacturing a nitride semiconductor device according to claim 11 , wherein the top surface of the gate layer has a plurality of steps formed in the second region.

16. 14. The method for manufacturing a nitride semiconductor device according to claim 11, wherein the second region extends between a side surface of the gate electrode and a side surface of the gate layer.

17. The method for manufacturing a nitride semiconductor device according to claim 16 , wherein a surface roughness of the second region is smaller than a surface roughness of the side surface of the gate layer.

18. The method for manufacturing a nitride semiconductor device according to any one of claims 11 to 13, further comprising forming a passivation layer covering the second nitride semiconductor layer, the gate layer, and the gate electrode, wherein the second region is in contact with the passivation layer.

19. forming a first opening and a second opening in the passivation layer; Forming source and drain electrodes Further comprising: the gate layer is located between the first opening and the second opening; the source electrode is in contact with the second nitride semiconductor layer through the first opening, the drain electrode is in contact with the second nitride semiconductor layer through the second opening; The method for manufacturing a nitride semiconductor device according to claim 18.

20. the first nitride semiconductor layer is a GaN layer; the second nitride semiconductor layer is an AlGaN layer; The third nitride semiconductor layer is a GaN layer containing an acceptor-type impurity. The method for manufacturing a nitride semiconductor device according to any one of claims 11 to 13.

Images