Nitride semiconductor device

Abstract

To provide a nitride semiconductor device capable of alleviating electric field concentration in a gate layer and reducing gate-source capacitance.SOLUTION: A nitride semiconductor device 10 includes a passivation layer 50 covering a gate layer 30, and a field plate electrode 60 on the passivation layer 50. The gate layer 30 includes a gate layer body part 32 and a drain-side extension unit 36. The passivation layer 50 includes a first portion 52A overlapping both the drain-side extension unit 36 and the field plate electrode 60 in a plan view, a second portion 52B consecutive to the first portion 52A and located between the drain-side extension unit 36 and a drain opening 50B; and a first step part 54 located in a region including a boundary 53 between the first portion 52A and the second portion 52B. The first portion 52A has a first thickness T1 from the upper surface 54A of a step to the upper surface of the drain-side extension unit 36. The second portion 52B has a second thickness T2 from the lower surface 54B of the step to the upper surface of an electron supply layer 28. The first thickness T1 is greater than the second thickness T2.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using nitride semiconductors such as gallium nitride (GaN) are being commercialized. Patent Document 1 describes an example of a normally-off type HEMT using a nitride semiconductor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-73506 A

[0004] [overview] In general, a nitride semiconductor device includes a field plate electrode that covers the upper part of the gate layer in order to reduce an electric field locally applied to an end of the gate layer. The field plate electrode is formed integrally with the source electrode or is electrically connected to the source electrode. In this configuration, the presence of the field plate electrode above the gate layer increases the source-gate capacitance. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an enlarged portion of the nitride semiconductor device of FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the nitride semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view showing an enlarged portion of the nitride semiconductor device of FIG. [Diagram 5] 5A to 5C are schematic cross-sectional views illustrating exemplary manufacturing steps for the nitride semiconductor device of FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing an exemplary manufacturing process subsequent to FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing an exemplary manufacturing process subsequent to FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing an exemplary manufacturing process subsequent to FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing an exemplary manufacturing process subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing an exemplary manufacturing process subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing an exemplary manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing an exemplary manufacturing process subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view of an illustrative nitride semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view of an illustrative nitride semiconductor device according to the third embodiment.

[0006] [Detailed Description] Hereinafter, embodiments of a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings.

[0007] In addition, for simplicity and clarity of illustration and description, the components shown in the drawings are not necessarily drawn to scale. For ease of understanding, features may be enlarged, and the dimensional ratio of each component is not necessarily the same in each drawing. The accompanying drawings are merely illustrative of embodiments of the present disclosure, and should not be considered as limiting the present disclosure.

[0008] The terms "first", "second", "third", etc., used in this disclosure are used to clearly distinguish components of the object, and are not used to rank the objects. In addition, the expression "at least one" used in this disclosure means one or more of the desired multiple options. As an example, if the number of options is two, the expression "at least one" means only one option or both of the two options. As another example, if the number of options is three or more, the expression "at least one" means only one option or any combination of two or more options.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] [First embodiment] [1. Schematic structure of nitride semiconductor device] Fig. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to a first embodiment. The nitride semiconductor device 10 includes a chip body 12. The Z-axis direction of the mutually orthogonal XYZ axes shown in Fig. 1 and other drawings is a direction orthogonal to the main surface (top surface 13 in Fig. 1) of the chip body 12. The term "plan view" used in this disclosure refers to viewing the nitride semiconductor device 10 from above along the Z-axis direction, unless otherwise explicitly stated.

[0011] The nitride semiconductor device 10 includes at least one gate pad 14, at least one source pad 16, and at least one drain pad 18. For example, the nitride semiconductor device 10 includes one gate pad 14, a plurality of source pads 16, and a plurality of drain pads 18. The gate pad 14, the source pad 16, and the drain pad 18 are formed on the upper surface 13 of the chip body 12, and can be used as external connection terminals of the nitride semiconductor device 10.

[0012] The gate pad 14, the source pad 16, and the drain pad 18 are each formed, for example, in a rectangular shape in a plan view. The gate pad 14 is disposed at one corner of the upper surface 13. The source pad 16 and the drain pad 18 each extend in one direction in a plan view, that is, in the Y-axis direction in FIG. 1. The source pads 16 and the drain pads 18 are alternately disposed in the X-axis direction perpendicular to the Y-axis direction.

[0013] Fig. 2 is a schematic plan view showing an enlarged portion of the nitride semiconductor device 10 of Fig. 1. Also, Fig. 3 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F3-F3 shown in Fig. 2. The nitride semiconductor device 10 can be configured as a high electron mobility transistor (HEMT) using a nitride semiconductor.

[0014] As shown in FIG. 3, the nitride semiconductor device 10 includes a semiconductor substrate 20, a nucleation layer 22 formed on the semiconductor substrate 20, a buffer layer 24 formed on the nucleation layer 22, an electron transit layer 26 formed on the buffer layer 24, and an electron supply layer 28 formed on the electron transit layer 26.

[0015] The semiconductor substrate 20 may be formed of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. For example, the semiconductor substrate 20 is a Si substrate. The thickness of the semiconductor substrate 20 may be, for example, 200 μm or more and 1500 μm or less. The Z-axis direction corresponds to the thickness direction of the semiconductor substrate 20.

[0016] The nucleation layer 22 is made of a nitride semiconductor. For example, the nucleation layer 22 may be formed as an aluminum nitride (AlN) layer having a thickness of 100 nm or more and 500 nm or less. The nucleation layer 22 may be included as the bottom layer of the buffer layer 24.

[0017] The buffer layer 24 can be composed of any material that can suppress the occurrence of wafer warping and cracks due to the mismatch in the coefficient of thermal expansion between the semiconductor substrate 20 and the electron traveling layer 26. The buffer layer 24 can include one or more nitride semiconductor layers. The buffer layer 24 can include, for example, at least one of an AlN layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 24 can be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0018] The electron traveling layer 26 is composed of a nitride semiconductor. The electron traveling layer 26 can be, for example, a GaN layer. The thickness of the electron traveling layer 26 can be, for example, 0.1 μm or more and 2 μm or less. The electron traveling layer 26 may include one or more nitride semiconductor layers. Also, in order to suppress the leakage current in the electron traveling layer 26, impurities may be introduced into a part of the electron traveling layer 26 to make the region other than the surface layer region of the electron traveling layer 26 semi-insulating. In that case, the impurity is, for example, C, and the concentration of the impurity can be, for example, 1×10 19 cm -3 or more at the peak concentration. GaN is an example of a first nitride semiconductor.

[0019] The electron supply layer 28 is composed of a nitride semiconductor having a larger bandgap than the electron traveling layer 26. The electron supply layer 28 can be, for example, an AlGaN layer. Since the bandgap increases as the Al composition increases, the electron supply layer 28, which is an AlGaN layer, has a larger bandgap than the electron traveling layer 26, which is a GaN layer. In one example, the electron supply layer 28 is composed of Al x Ga 1-x N, where x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The thickness of the electron supply layer 28 can be, for example, 5 nm or more and 20 nm or less. AlGaN is an example of a second nitride semiconductor.

[0020] The electron transit layer 26 and the electron supply layer 28 have different lattice constants in the bulk region. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layer 26 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 28 form a heterojunction of a lattice mismatched system. Due to spontaneous polarization of the electron transit layer 26 and the electron supply layer 28 and piezoelectric polarization caused by compressive stress applied to the heterojunction of the electron transit layer 26, the energy level of the conduction band of the electron transit layer 26 near the heterojunction interface between the electron transit layer 26 and the electron supply layer 28 becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 27 is formed in the electron transit layer 26 at a position close to the heterojunction interface between the electron transit layer 26 and the electron supply layer 28 (e.g., at a distance of about several nm from the interface).

[0021] The nitride semiconductor device 10 further includes a gate layer 30 formed on a portion of the electron supply layer 28 , and a gate electrode 40 formed on the gate layer 30 . The gate layer 30 is made of a nitride semiconductor. For example, the gate layer 30 is made of a nitride semiconductor having a band gap smaller than that of the electron supply layer 28 and containing acceptor-type impurities. In one example, the gate layer 30 is a GaN layer doped with acceptor-type impurities (p-type GaN layer). The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), and C. The maximum concentration of the acceptor-type impurities in the gate layer 30 is, for example, 7×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0022] The gate electrode 40 includes one or more metal layers. For example, the gate electrode 40 may be a titanium nitride (TiN) layer. Alternatively, the gate electrode 40 may be formed by a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 40 may form a Schottky junction with the gate layer 30. The thickness of the gate electrode 40 may be, for example, 50 nm or more and 200 nm or less.

[0023] The nitride semiconductor device 10 further includes a passivation layer 50. The passivation layer 50 covers the electron supply layer 28, the gate layer 30, and the gate electrode 40. The passivation layer 50 may be made of a material including any one of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 50 may be, for example, 50 nm or more and 200 nm or less. The passivation layer 50 includes a source opening 50A and a drain opening 50B that each expose a part of the upper surface of the electron supply layer 28.

[0024] The nitride semiconductor device 10 further includes a source electrode 42 in contact with the electron supply layer 28 through a source opening 50A in the passivation layer 50, and a drain electrode 44 in contact with the electron supply layer 28 through a drain opening 50B in the passivation layer 50.

[0025] The source electrode 42 and the drain electrode 44 include one or more metal layers. For example, the source electrode 42 and the drain electrode 44 may be formed by one or any combination of a Ti layer, a TiN layer, an Al layer, an aluminum silicon copper (AlSiCu) layer, and an aluminum copper (AlCu) layer. At least a part of the source electrode 42 is filled in the source opening 50A and is in ohmic contact with the 2DEG 27 directly below the electron supply layer 28 through the source opening 50A. Similarly, at least a part of the drain electrode 44 is filled in the drain opening 50B and is in ohmic contact with the 2DEG 27 directly below the electron supply layer 28 through the drain opening 50B. Although not shown, the semiconductor substrate 20 is electrically connected to the source electrode 42, and a voltage having the same potential as that of the source electrode 42 is applied to the semiconductor substrate 20.

[0026] When the gate layer 30 is formed of a nitride semiconductor containing acceptor-type impurities, the conductive path (channel) is cut off by depleting the 2DEG 27 in the region directly below the gate layer 30 at zero bias when no voltage is applied to the gate electrode 40. This realizes a normally-off HEMT with a positive threshold voltage.

[0027] 2. Example Structure of Gate Layer 3, the gate layer 30 is located between the source opening 50A and the drain opening 50B in the X-axis direction. The gate layer 30 is spaced apart from both the source opening 50A and the drain opening 50B, and is located closer to the source opening 50A than the drain opening 50B.

[0028] The gate layer 30 includes a gate layer body 32 including an upper surface of the gate layer 30, and a source side extension 34 and a drain side extension 36 each thinner than the gate layer body 32. The gate layer body 32, the source side extension 34, and the drain side extension 36 are all in contact with the electron supply layer 28. Due to the presence of the source side extension 34 and the drain side extension 36, the lower surface of the gate layer 30 has a larger area than the upper surface of the gate layer 30.

[0029] The gate layer main body 32 is formed integrally with the source side extension 34 and the drain side extension 36. For example, the gate layer main body 32 is formed to have a ridge-like cross section (a substantially rectangular cross section). However, the cross-sectional shape of the gate layer main body 32 is not particularly limited, and may be, for example, a trapezoidal cross section or another cross-sectional shape. The thickness of the gate layer main body 32 may be determined in consideration of various parameters including the gate threshold voltage. The thickness of the gate layer main body 32 may be, for example, 80 nm or more and 150 nm or less.

[0030] The source side extension 34 extends from the gate layer body 32 toward the source opening 50A. A passivation layer 50 is present between the source electrode 42 embedded in the source opening 50A and the source side extension 34. On the other hand, the drain side extension 36 extends from the gate layer body 32 toward the drain opening 50B. A passivation layer 50 is present between the drain electrode 44 embedded in the drain opening 50B and the drain side extension 36. Each of the source side extension 34 and the drain side extension 36 may have a thickness that is, for example, half or less than that of the gate layer body 32.

[0031] The drain side extension 36 may have a larger dimension in the X-axis direction than the source side extension 34. The dimension (length) in the X-axis direction of the source side extension 34 may be, for example, not less than 0.2 μm and not more than 0.3 μm. The dimension (length) in the X-axis direction of the drain side extension 36 may be, for example, not less than 0.2 μm and not more than 0.6 μm.

[0032] The source side extension 34 and the drain side extension 36 may each include a flat portion of a substantially constant thickness. The thickness of the flat portion of the source side extension 34 and the thickness of the flat portion of the drain side extension 36 may be, for example, 5 nm or more and 25 nm or less. In this specification, the term "substantially constant thickness" refers to the thickness being within the range of manufacturing variation (for example, 20%). Also, as shown in FIG. 3, the source side extension 34 and the drain side extension 36 may each include an intermediate portion between the flat portion and the gate layer main body 32 that is thicker than the flat portion. In one example, the intermediate portion may have a thickness that gradually decreases as it moves away from the gate layer main body 32.

[0033] [3. Example Structure of Field Plate Electrode] As shown in FIG. 3, the nitride semiconductor device 10 further includes a field plate electrode 60 provided on the passivation layer 50 and electrically connected to the source electrode 42. In the example of FIG. 3, the field plate electrode 60 is integrally formed with the source electrode 42 and is provided as a part of the source electrode 42. Therefore, a voltage having the same potential as that of the source electrode 42 is applied to the field plate electrode 60. The field plate electrode 60 is also called a source field plate. The field plate electrode 60 covers the entire gate layer 30 in a plan view.

[0034] The field plate electrode 60 is spaced apart from the drain electrode 44. The field plate electrode 60 includes an end 61 located between the gate layer 30 (drain side extension portion 36) and the drain electrode 44 (drain opening 50B) in a plan view. The field plate electrode 60 plays a role in reducing electric field concentration near the end of the gate electrode 40 and near the end of the gate layer 30 when a drain voltage is applied to the drain electrode 44 in a zero bias state in which no gate input voltage is applied to the gate electrode 40.

[0035] [4. Example Planar Layout of Nitride Semiconductor Device] Next, an exemplary planar layout of the HEMT structure (nitride semiconductor device 10) will be described with reference to Fig. 2. For clarity, the passivation layer 50 is omitted in Fig. 2. Also, the source opening 50A, the drain opening 50B, and the field plate electrode 60 are depicted by dashed lines.

[0036] 2, the nitride semiconductor device 10 includes a gate wiring 72, a source wiring 74, and a drain wiring 76. The gate wiring 72, the source wiring 74, and the drain wiring 76 are formed on an interlayer insulating layer (not shown) that covers the source electrode 42 and the drain electrode 44. For example, the gate wiring 72 is connected to the gate electrode 40 by a gate connection conductor 73 that penetrates the interlayer insulating layer and extends to the gate electrode 40. The source wiring 74 is connected to the source electrode 42 by a source connection conductor 75 that penetrates the interlayer insulating layer. The drain wiring 76 is connected to the drain electrode 44 by a drain connection conductor 77 that penetrates the interlayer insulating layer.

[0037] The nitride semiconductor device 10 includes a plurality of transistor elements each having a HEMT structure in an element region. Although Fig. 2 shows only a plurality of transistor elements aligned in the X-axis direction, in reality, the transistor elements may be aligned in both the X-axis direction and the Y-axis direction.

[0038] The drain electrode 44 is provided for each transistor element and extends in the Y-axis direction in a planar view. The source electrode 42 is provided, for example, so as to surround each drain electrode 44 in a planar view. As described with reference to FIG. 3, the source electrode 42 includes a field plate electrode 60. That is, the field plate electrode 60 is formed integrally with the source electrode 42 and extends toward the adjacent drain electrode 44 in a planar view. Note that, in the example of FIG. 2, the source electrode 42 is formed continuously in the X-axis direction across multiple transistor elements adjacent in the X-axis direction, but may be separated into multiple parts in the X-axis direction.

[0039] The gate layer 30 and the gate electrode 40 are provided for each transistor element. Each gate layer 30 and each gate electrode 40 is formed in an annular shape so as to surround one of the drain electrodes 44 in a plan view.

[0040] 5. Example Structure of Passivation Layer Next, an exemplary structure of the passivation layer 50 will be described with reference to Figures 3 and 4. Figure 4 is a schematic cross-sectional view showing an enlarged portion of the nitride semiconductor device 10 of Figure 3.

[0041] 4, the passivation layer 50 includes a first portion 52A that overlaps with both the drain-side extension 36 of the gate layer 30 and the field plate electrode 60 in a plan view. The passivation layer 50 also includes a second portion 52B that is continuous with the first portion 52A and is located between the drain-side extension 36 and the drain opening 50B. The passivation layer 50 also includes a first step portion 54 that is located in a region that includes a boundary 53 between the first portion 52A and the second portion 52B. The first step portion 54 includes a step upper surface 54A, a step lower surface 54B that is lower than the step upper surface 54A, and a step wall 54C that connects the step upper surface 54A and the step lower surface 54B.

[0042] The first portion 52A has a first thickness T1 from the step upper surface 54A to the upper surface of the drain-side extension 36. The second portion 52B has a second thickness T2 from the step lower surface 54B to the upper surface of the electron supply layer 28. The passivation layer 50 is formed such that the first thickness T1 is greater than the second thickness T2. The second thickness T2 may be, for example, 50 nm or more and 150 nm or less, and is 100 nm in the first embodiment. The first thickness T1 may be, for example, 100 nm or more and 200 nm or less, and is 150 nm in the first embodiment. The ratio of the first thickness T1 to the second thickness T2, i.e., T1 / T2, may be, for example, greater than 1 and less than 3.

[0043] The first portion 52A predominantly includes a region having a first thickness T1. In the example of Fig. 4, the region of the first thickness T1 is the entirety or substantially the entirety of the first portion 52A. The second portion 52B predominantly includes a region having a second thickness T2. In the example of Fig. 4, the region of the second thickness T2 is the entirety or substantially the entirety of the second portion 52B.

[0044] The first portion 52A is formed such that the first thickness T1 is greater than the thickness of the drain-side extension portion 36. In the example of FIG. 4, the sum of the first thickness T1 and the thickness of the drain-side extension portion 36 is greater than the thickness of the gate layer main body portion 32 and is smaller than the sum of the thickness of the gate layer main body portion 32 and the thickness of the gate electrode 40.

[0045] The passivation layer 50 further includes a third portion 55A that overlaps with both the source-side extension 34 of the gate layer 30 and the field plate electrode 60 in a planar view. The passivation layer 50 also includes a fourth portion 55B that is continuous with the third portion 55A and is located between the source-side extension 34 and the source opening 50A. The passivation layer 50 also includes a second step portion 57 that is located in a region that includes a boundary 56 between the third portion 55A and the fourth portion 55B. The second step portion 57 includes a step upper surface 57A, a step lower surface 57B that is lower than the step upper surface 57A, and a step wall 57C that connects the step upper surface 57A and the step lower surface 57B.

[0046] The third portion 55A has a third thickness T3 from the step upper surface 57A to the upper surface of the source-side extension portion 34. The fourth portion 55B has a fourth thickness T4 from the step lower surface 57B to the upper surface of the electron supply layer 28. The passivation layer 50 is formed such that the third thickness T3 is greater than the fourth thickness T4. The fourth thickness T4 may be, for example, 50 nm or more and 150 nm or less, and is 100 nm in the first embodiment. The third thickness T3 may be, for example, 100 nm or more and 200 nm or less, and is 150 nm in the first embodiment. The ratio of the third thickness T3 to the fourth thickness T4, i.e., T3 / T4, may be, for example, greater than 1 and less than 3.

[0047] The third portion 55A predominantly includes a region having a third thickness T3. In the example of Fig. 4, the region of the third thickness T3 is the entirety or substantially the entirety of the third portion 55A. Also, the fourth portion 55B predominantly includes a region having a fourth thickness T4. In the example of Fig. 4, the region of the fourth thickness T4 is the entirety or substantially the entirety of the fourth portion 55B.

[0048] 4, the sum of the third thickness T3 and the source-side extension 34 is greater than the thickness of the gate layer main body 32 and is smaller than the sum of the thickness of the gate layer main body 32 and the thickness of the gate electrode 40.

[0049] 6. Exemplary Manufacturing Method of Nitride Semiconductor Device Next, an exemplary method for manufacturing the nitride semiconductor device 10 will be described. 5 to 12 are schematic cross-sectional views showing the manufacturing process of the nitride semiconductor device 10. In order to facilitate understanding, reference symbols indicating members including final components of the nitride semiconductor device 10 or members corresponding thereto are used in Fig. 5 to 12.

[0050] 5, a nucleation layer 22, a buffer layer 24, an electron transit layer 26, and an electron supply layer 28 are formed in this order by epitaxial growth on a semiconductor substrate 20, which is, for example, a Si substrate. For the epitaxial growth process, for example, a metal organic chemical vapor deposition (MOCVD) method can be used.

[0051] The nucleation layer 22, the buffer layer 24, the electron transit layer 26, and the electron supply layer 28 may be formed of any nitride semiconductor layers corresponding to those layers described with reference to Fig. 3. In the first embodiment, for example, the nucleation layer 22 is an AlN layer, the buffer layer 24 is a graded AlGaN layer, the electron transit layer 26 is a GaN layer, and the electron supply layer 28 is an AlGaN layer.

[0052] 6, a nitride semiconductor layer corresponding to the gate layer 30 is formed by epitaxial growth on the electron supply layer 28. In the first embodiment, the nitride semiconductor layer corresponding to the gate layer 30 is, for example, a p-type GaN layer doped with Mg as an acceptor-type impurity.

[0053] 7, a gate electrode 40 is formed on the nitride semiconductor layer corresponding to the gate layer 30. The gate electrode 40 can be formed by forming an electrode layer (not shown) by, for example, a sputtering method, and then selectively etching the electrode layer using a mask (not shown). In the first embodiment, the gate electrode 40 is, for example, a TiN layer.

[0054] 8, the nitride semiconductor layer in FIG. 7 corresponding to the gate layer 30 is selectively etched using a mask M1 to form a gate layer main body 32. As described above, the cross-sectional shape of the gate layer main body 32 is not particularly limited. After the gate layer main body 32 is formed, the mask M1 is removed.

[0055] 9, the nitride semiconductor layer in FIG. 8 corresponding to the gate layer 30 is further selectively etched using the mask M2 to form the source side extension 34 and the drain side extension 36. This forms the gate layer 30 including the gate layer main body 32, the source side extension 34, and the drain side extension 36. After the gate layer 30 in FIG. 9 is formed, the mask M2 is removed.

[0056] 10, an insulating layer corresponding to the passivation layer 50 is formed. This insulating layer is formed such that the thickness of the passivation layer 50 on the drain-side extension 36 reaches a first thickness T1 (see FIG. 4) and the thickness of the passivation layer 50 on the source-side extension 34 reaches a third thickness T3 (see FIG. 4). In the first embodiment, the passivation layer 50 is, for example, a SiN layer.

[0057] 11, the insulating layer in FIG. 10 corresponding to the passivation layer 50 is selectively etched using a mask M3 to form a first portion 52A and a second portion 52B through a first step portion 54, and a third portion 55A and a fourth portion 55B through a second step portion 57. Then, the mask M3 is removed. In the process of FIG. 11, etching is performed until the second portion 52B has a second thickness T2 (see FIG. 4) and the fourth portion 55B has a fourth thickness T4 (see FIG. 4).

[0058] 12, a source opening 50A and a drain opening 50B are formed in the passivation layer 50. Then, an electrode layer including a source electrode 42 (including a field plate electrode 60 in the first embodiment) and a drain electrode 44 is formed by, for example, a sputtering method. Thereafter, the electrode layer in FIG. 12 is selectively etched using a mask (not shown), thereby forming the source electrode 42 and the drain electrode 44 as shown in FIG.

[0059] [7. Function of nitride semiconductor device] The nitride semiconductor device 10 includes a field plate electrode 60 that covers the upper part of the gate layer 30 in order to relieve an electric field locally applied to an end part of the gate layer 30. In the first embodiment, the field plate electrode 60 is formed integrally with the source electrode 42. Therefore, a source potential is applied to the field plate electrode 60. In this configuration, the field plate electrode 60 relieves electric field concentration at the end part of the gate layer 30.

[0060] Generally, in a configuration in which a field plate electrode is provided above the gate layer, the source-gate capacitance increases compared to a configuration in which no field plate electrode is provided. In the configuration of the present disclosure, the passivation layer 50 is formed taking this into consideration. In the first embodiment, the passivation layer 50 includes a first portion 52A, a second portion 52B, and a first step portion 54. The first portion 52A is a portion of the passivation layer 50 that overlaps both the drain side extension portion 36 of the gate layer 30 and the field plate electrode 60 in a plan view. The second portion 52B is a portion of the passivation layer 50 that is continuous with the first portion 52A and is located between the drain side extension portion 36 and the drain opening 50B. The first step portion 54 is a portion of the passivation layer 50 that is located in a region including the boundary 53 between the first portion 52A and the second portion 52B.

[0061] In such a configuration, the function of the field plate electrode 60 to alleviate the electric field concentration at the end of the drain-side extension 36 depends on the thickness of the passivation layer 50, and in particular, the smaller the thickness of the second portion 52B, the higher the function becomes. That is, the function of alleviating the electric field concentration at the end of the drain-side extension 36 depends mainly on the thickness of the second portion 52B rather than the thickness of the first portion 52A. The passivation layer 50 is formed so that the first thickness T1 of the first portion 52A is larger than the second thickness T2 of the second portion 52B. In this configuration, the function of alleviating the electric field concentration at the end of the drain-side extension 36 can be effectively maintained while reducing the source-gate capacitance formed between the field plate electrode 60 and the drain-side extension 36 (gate layer 30) via the first portion 52A.

[0062] The passivation layer 50 also includes a third portion 55A, a fourth portion 55B, and a second step portion 57. The third portion 55A is a portion of the passivation layer 50 that overlaps with both the source side extension portion 34 of the gate layer 30 and the field plate electrode 60 in a planar view. The fourth portion 55B is a portion of the passivation layer 50 that is continuous with the third portion 55A and is located between the source side extension portion 34 and the source opening 50A. The second step portion 57 is a portion of the passivation layer 50 that is located in a region including a boundary 56 between the third portion 55A and the fourth portion 55B.

[0063] The function of the field plate electrode 60 to alleviate the electric field concentration at the end of the source-side extension 34 depends on the thickness of the passivation layer 50, and in particular, the smaller the thickness of the fourth portion 55B, the higher the function becomes. That is, the function of alleviating the electric field concentration at the end of the source-side extension 34 depends mainly on the thickness of the fourth portion 55B rather than the thickness of the third portion 55A. The passivation layer 50 is formed so that the third thickness T3 of the third portion 55A is larger than the fourth thickness T4 of the fourth portion 55B. In this configuration, the function of alleviating the electric field concentration at the end of the source-side extension 34 can be effectively maintained while reducing the source-gate capacitance formed between the field plate electrode 60 and the source-side extension 34 (gate layer 30) via the third portion 55A.

[0064] The nitride semiconductor device 10 of the first embodiment has the following advantages. (1-1) The passivation layer 50 includes a first portion 52A formed on the drain-side extension 36 and having a first thickness T1, and a second portion 52B formed on the electron supply layer 28 and having a second thickness T2. The passivation layer 50 is formed such that the first thickness T1 of the first portion 52A is greater than the second thickness T2 of the second portion 52B. With this configuration, it is possible to effectively maintain the function of alleviating electric field concentration at the end of the drain-side extension 36 while reducing the source-gate capacitance.

[0065] (1-2) The ratio of the first thickness T1 to the second thickness T2 is greater than 1 and not greater than 3. With this configuration, it is possible to more effectively obtain the function of reducing the source-gate capacitance while mitigating the electric field concentration at the end of the drain-side extension portion 36.

[0066] (1-3) The first portion 52A predominantly includes a region having the first thickness T1, and the second portion 52B predominantly includes a region having the second thickness T2. This configuration can more effectively reduce the source-gate capacitance while mitigating the electric field concentration at the end of the drain-side extension portion 36.

[0067] (1-4) The first thickness T1 is not less than 100 nm and not more than 200 nm. With this configuration, the source-gate capacitance can be effectively reduced. (1-5) The second thickness T2 is not less than 50 nm and not more than 150 nm. With this configuration, the electric field concentration at the end of the drain-side extension portion 36 can be effectively alleviated.

[0068] (1-6) The first thickness T1 is greater than the thickness of the drain-side extension portion 36. By making the first thickness T1 greater than the thickness of the drain-side extension portion 36 in this manner, the source-gate capacitance can be effectively reduced.

[0069] (1-7) The sum of the first thickness T1 and the thickness of the drain-side extension portion 36 is greater than the thickness of the gate layer main body portion 32 and is smaller than the sum of the thickness of the gate layer main body portion 32 and the thickness of the gate electrode 40. According to this configuration, the source-gate capacitance can be reduced more effectively.

[0070] (1-8) The passivation layer 50 includes a third portion 55A formed on the source-side extension 34 and having a third thickness T3, and a fourth portion 55B formed on the electron supply layer 28 and having a fourth thickness T4. The passivation layer 50 is formed such that the third thickness T3 of the third portion 55A is greater than the fourth thickness T4 of the fourth portion 55B. With this configuration, it is possible to effectively maintain the function of alleviating electric field concentration at the end of the source-side extension 34 while reducing the source-gate capacitance.

[0071] (1-9) The ratio of the third thickness T3 to the fourth thickness T4 is greater than 1 and not greater than 3. With this configuration, it is possible to more effectively obtain the function of reducing the source-to-gate capacitance while mitigating the electric field concentration at the end of the source-side extension portion 34.

[0072] (1-10) Moreover, the third portion 55A predominantly includes a region having the third thickness T3, and the fourth portion 55B predominantly includes a region having the fourth thickness T4. With this configuration, it is possible to more effectively obtain the function of reducing the source-to-gate capacitance while mitigating the electric field concentration at the end of the source-side extension portion 34.

[0073] (1-11) The third thickness T3 is not less than 100 nm and not more than 200 nm. With this configuration, the source-gate capacitance can be effectively reduced. (1-12) The fourth thickness T4 is not less than 50 nm and not more than 150 nm. With this configuration, the electric field concentration at the end of the source-side extension portion 34 can be effectively alleviated.

[0074] (1-13) The third thickness T3 is greater than the thickness of the source-side extension portion 34. By making the third thickness T3 greater than the thickness of the source-side extension portion 34 in this manner, the source-gate capacitance can be effectively reduced.

[0075] (1-14) The sum of the third thickness T3 and the thickness of the source-side extension portion 34 is greater than the thickness of the gate layer main body portion 32 and is smaller than the sum of the thickness of the gate layer main body portion 32 and the thickness of the gate electrode 40. According to this configuration, the source-gate capacitance can be reduced more effectively.

[0076] [Second embodiment] 13 is a schematic plan view of an exemplary nitride semiconductor device 10 according to the second embodiment. The second embodiment differs from the first embodiment in that the thickness of the first portion 52A and the thickness of the third portion 55A of the passivation layer 50 are changed. Other configurations are similar to those of the first embodiment, and therefore detailed description of similar configurations will be omitted.

[0077] As shown in FIG. 13, in the second embodiment, the first portion 52A of the passivation layer 50 has a plurality of different thicknesses. For example, the first portion 52A includes a first region 521A having a first thickness T1 and a second region 521B located closer to the gate layer main body 32 than the first region 521A and having a thickness T1A larger than the first thickness T1. That is, the first region 521A has a larger area than the second region 521B in a plan view. In the example of FIG. 13, the first portion 52A includes the first region 521A more predominantly than the second region 521B. The first thickness T1 of the first region 521A is still larger than the second thickness T2 of the second portion 52B.

[0078] In this configuration, for example, by making the first thickness T1 of the first region 521A smaller than that in the first embodiment, the function of alleviating electric field concentration at the end of the drain-side extension 36 can be improved. In addition, by having the first portion 52A have a plurality of different thicknesses (the first thickness T1 and the thickness T1A), the average thickness of the first portion 52A can be increased. This can reduce the gate-source capacitance.

[0079] In the second embodiment, the boundary 53 between the first portion 52A and the second portion 52B is located closer to the drain opening 50B than the end of the drain-side extension portion 36. In this way, the boundary 53 does not necessarily need to exactly coincide with the position of the end of the drain-side extension portion 36 in a plan view, and may be slightly shifted.

[0080] Similarly, in the second embodiment, the third portion 55A of the passivation layer 50 has a plurality of different thicknesses. For example, the third portion 55A includes a third region 551A having a third thickness T3 and a fourth region 551B located closer to the gate layer body 32 than the third region 551A and having a thickness T3A larger than the third thickness T3. In the example of FIG. 13, the third portion 55A includes the third region 551A more predominantly than the fourth region 551B. That is, in a plan view, the third region 551A has a larger area than the fourth region 551B. The third thickness T3 of the third region 551A is still larger than the fourth thickness T4 of the fourth portion 55B.

[0081] In this configuration, for example, by making the third thickness T3 of the third region 551A smaller than that in the first embodiment, the function of alleviating electric field concentration at the end of the source-side extension portion 34 can be improved. In addition, by having the third portion 55A have a plurality of different thicknesses (the third thickness T3 and the thickness T3A), the average thickness of the third portion 55A can be increased. This can reduce the gate-source capacitance.

[0082] In the second embodiment, the boundary 56 between the third portion 55A and the fourth portion 55B is located closer to the source opening 50A than the end of the source-side extension portion 34. In this way, the boundary 56 does not necessarily need to exactly coincide with the position of the end of the source-side extension portion 34 in a plan view, and may be slightly deviated.

[0083] The nitride semiconductor device 10 of the second embodiment has the following advantages in addition to the advantages of the first embodiment. (2-1) The first portion 52A has a plurality of different thicknesses (first thickness T1 and thickness T1A), so that the average thickness of the first portion 52A can be increased to reduce the gate-source capacitance. In addition, the first thickness T1 of the first region 521A is made smaller than that of the first embodiment, so that the function of alleviating electric field concentration at the end of the drain-side extension 36 can be improved.

[0084] (2-2) By having the third portion 55A have a plurality of different thicknesses (the third thickness T3 and the thickness T3A), the average thickness of the third portion 55A can be increased to reduce the gate-source capacitance. In addition, by making the third thickness T3 of the third region 551A smaller than that of the first embodiment, the function of alleviating electric field concentration at the end of the source-side extension portion 34 can be improved.

[0085] [Third embodiment] 14 is a schematic plan view of an exemplary nitride semiconductor device 10 according to the third embodiment. The third embodiment differs from the second embodiment in that the field plate electrode 60 of the second embodiment is replaced with a field plate electrode 60A. Other configurations are similar to those of the first and second embodiments, and therefore detailed descriptions of similar configurations will be omitted.

[0086] As shown in FIG. 14, in the third embodiment, the field plate electrode 60A is provided separately from the source electrode 42. Although not shown, the field plate electrode 60A is electrically connected to the source electrode 42. The field plate electrode 60A is provided across the first portion 52A, the first step portion 54, and the second portion 52B so as to cover at least a portion (end portion) of the drain side extension portion 36 in a plan view. In the example of FIG. 14, the field plate electrode 60A overlaps a portion of the drain side extension portion 36 in a plan view, but does not overlap the entire drain side extension portion 36. In this configuration, the area where the field plate electrode 60A and the drain side extension portion 36 overlap in a plan view is reduced, thereby reducing the gate-source capacitance.

[0087] Further, the source electrode 42 is provided across the third portion 55A, the second step portion 57, and the fourth portion 55B so as to cover at least a portion (end portion) of the source side extension portion 34 in a plan view. In the example of Fig. 14, the source electrode 42 overlaps a portion of the source side extension portion 34 in a plan view, but does not overlap the entire source side extension portion 34. With this configuration, the area where the source electrode 42 and the source side extension portion 34 overlap in a plan view is reduced, thereby making it possible to reduce the gate-source capacitance.

[0088] The nitride semiconductor device 10 of the third embodiment has the following advantages in addition to the advantages of the first and second embodiments. (3-1) The area where the field plate electrode 60A and the drain-side extension 36 overlap is small in plan view. Also, the area where the source electrode 42 and the source-side extension 34 overlap is small in plan view. This reduces the gate-source capacitance.

[0089] [Example of change] The above-described embodiments may be modified as follows: The above-described embodiments and the following modifications may be combined with each other to the extent that no technical contradiction occurs.

[0090] The gate layer 30 is not limited to a structure including both the source side extension portion 34 and the drain side extension portion 36. For example, the gate layer 30 may have a structure including the gate layer main body portion 32 and the drain side extension portion 36, but not including the source side extension portion 34.

[0091] In the first embodiment, the boundary 53 does not necessarily have to exactly match the position of the end of the drain-side extension portion 36 in a plan view, and may be slightly offset as in the second and third embodiments. Similarly, the boundary 56 does not necessarily have to exactly match the position of the end of the source-side extension portion 34 in a plan view, and may be slightly offset as in the second and third embodiments.

[0092] The first thickness T1 is not limited to being greater than the thickness of the drain side extension portion 36, and may be the same thickness as the drain side extension portion 36. In addition, the third thickness T3 is not limited to being greater than the thickness of the source side extension portion 34, and may be the same thickness as the source side extension portion 34.

[0093] The sum of the first thickness T1 and the thickness of the drain-side extension portion 36 may be equal to or less than the thickness of the gate layer main body 32. In addition, the sum of the third thickness T3 and the thickness of the source-side extension portion 34 may be equal to or less than the thickness of the gate layer main body 32.

[0094] The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the phrase "a first element is mounted on a second element" is intended to mean that in some embodiments, the first element may be directly disposed on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0095] The Z-axis direction used in this disclosure does not necessarily have to be vertical, and does not have to be completely vertical. Therefore, the various structures according to this disclosure are not limited to the "up" and "down" of the Z-axis direction described in this specification being "up" and "down" of the vertical direction. For example, the X-axis direction may be vertical, or the Y-axis direction may be vertical.

[0096] [Note] The technical ideas that can be understood from the above-mentioned embodiments and each modified example are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid in understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0097] (Appendix 1) an electron transit layer (26) made of a first nitride semiconductor; an electron supply layer (28) provided on the electron transit layer (26) and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor; a gate layer (30) made of a third nitride semiconductor and provided on a portion of the electron supply layer (28); a gate electrode (40) provided on the gate layer (30); a passivation layer (50) covering the electron supply layer (28), the gate layer (30), and the gate electrode (40) and including a source opening (50A) and a drain opening (50B); a source electrode (42) in contact with the electron supply layer (28) through the source opening (50A); a drain electrode (44) in contact with the electron supply layer (28) through the drain opening (50B); a field plate electrode (60; 60A) provided on the passivation layer (50) and electrically connected to the source electrode (42); the gate layer (30) includes a gate layer body portion (32) and a drain side extension portion (36) extending from the gate layer body portion (32) toward the drain opening (50B); The passivation layer (50) is a first portion (52A) overlapping both the drain side extension portion (36) and the field plate electrode (60; 60A) in a plan view; a second portion (52B) continuous with the first portion (52A) and positioned between the drain side extension portion (36) and the drain opening (50B); a first step portion (54) located in a region including a boundary (53) between the first portion (52A) and the second portion (52B), The first step portion (54) has a step upper surface (54A), a step lower surface (54B) that is lower than the step upper surface (54A), and a step wall (54C) that connects the step upper surface (54A) and the step lower surface (54B), the first portion (52A) has a first thickness (T1) from the step upper surface (54A) to an upper surface of the drain-side extension portion (36); the second portion (52B) has a second thickness (T2) from the step lower surface (54B) to the upper surface of the electron supply layer (28); The first thickness (T1) is greater than the second thickness (T2).

[0098] (Appendix 2) 2. The nitride semiconductor device (10) according to claim 1, wherein a ratio of the first thickness (T1) to the second thickness (T2) is greater than 1 and is not greater than 3.

[0099] (Appendix 3) the first portion (52A) predominantly includes a region having the first thickness (T1); The nitride semiconductor device (10) according to claim 1 or 2, wherein the second portion (52B) predominantly includes a region having the second thickness (T2).

[0100] (Appendix 4) The nitride semiconductor device (10) according to any one of appendix 1 to 3, wherein the first thickness (T1) is not less than 100 nm and not more than 200 nm.

[0101] (Appendix 5) The nitride semiconductor device (10) according to any one of appendices 1 to 4, wherein the second thickness (T2) is not less than 50 nm and not more than 150 nm.

[0102] (Appendix 6) The first portion (52A) is A first region (521A) having the first thickness (T1); a second region (521B) located closer to the gate layer body portion (32) than the first region (521A) and having a thickness (T1A) greater than the first thickness (T1); A nitride semiconductor device (10) according to any one of appendices 1 to 5, comprising:

[0103] (Appendix 7) 7. The nitride semiconductor device (10) according to claim 6, wherein the first region (521A) has a larger area than the second region (521B) in a plan view.

[0104] (Appendix 8) The nitride semiconductor device (10) according to any one of claims 1 to 7, wherein the first thickness (T1) is greater than a thickness of the drain-side extension portion (36).

[0105] (Appendix 9) The nitride semiconductor device (10) according to any one of Appendices 1 to 8, wherein a total thickness of the first thickness (T1) and a thickness of the drain-side extension portion (36) is greater than a thickness of the gate layer main body (32) and is smaller than a total thickness of the gate layer main body (32) and a thickness of the gate electrode (40).

[0106] (Appendix 10) The gate layer (30) further includes a source side extension portion (34) extending from the gate layer body portion (32) toward the source opening (50A), The passivation layer (50) is a third portion (55A) overlapping both the source side extension portion (34) and the field plate electrode (60; 60A) in a plan view; a fourth portion (55B) continuous with the third portion (55A) and positioned between the source side extension portion (34) and the source opening portion (50A); and a second step portion (57) located in a region including a boundary (56) between the third portion (55A) and the fourth portion (55B), the second step portion (57) has a step upper surface (57A), a step lower surface (57B) that is lower than the step upper surface (57A) of the second step portion (57), and a step wall (57C) that connects the step upper surface (57A) and the step lower surface (57B) of the second step portion (57); the third portion (55A) has a third thickness (T3) from the step upper surface (57A) of the second step portion (57) to an upper surface of the source side extension portion (34), the fourth portion (55B) has a fourth thickness (T4) from the step lower surface (57B) of the second step portion (57) to the upper surface of the electron supply layer (28); The nitride semiconductor device (10) according to any one of appendices 1 to 9, wherein the third thickness (T3) is greater than the fourth thickness (T4).

[0107] (Appendix 11) The nitride semiconductor device (10) according to claim 10, wherein a ratio of the third thickness (T3) to the fourth thickness (T4) is greater than 1 and is not greater than 3.

[0108] (Appendix 12) The nitride semiconductor device (10) according to claim 10 or 11, wherein the third thickness (T3) is not less than 100 nm and not more than 200 nm.

[0109] (Appendix 13) The nitride semiconductor device (10) according to any one of Appendices 10 to 12, wherein the fourth thickness (T4) is not less than 50 nm and not more than 150 nm.

[0110] (Appendix 14) The third portion (55A) is a third region (551A) having the third thickness (T3); a fourth region (551B) located closer to the gate layer body portion (32) than the third region (551A) and having a thickness (T3A) greater than the third thickness (T3); A nitride semiconductor device (10) according to any one of appendices 10 to 13, comprising:

[0111] (Appendix 15) The nitride semiconductor device (10) according to any one of Appendices 10 to 14, wherein the third thickness (T3) is greater than a thickness of the source-side extension portion (34).

[0112] (Appendix 16) The nitride semiconductor device (10) according to any one of Appendices 10 to 15, wherein a total thickness of the third thickness (T3) and a thickness of the source-side extension portion (34) is greater than a thickness of the gate layer main body (32) and is smaller than a total thickness of the gate layer main body (32) and a thickness of the gate electrode (40).

[0113] (Appendix 17) 17. The nitride semiconductor device (10) according to any one of Appendices 1 to 16, wherein the field plate electrode (60) is formed integrally with the source electrode (42) and extends from the source electrode (42) toward the drain electrode (44) so ​​as to cover the source side extension portion (34), the gate layer main body portion (32), and the drain side extension portion (36) in a planar view.

[0114] (Appendix 18) 17. The nitride semiconductor device (10) according to any one of Appendices 1 to 16, wherein the field plate electrode (60A) is provided separately from the source electrode (42) and is provided across the first portion (52A), the first step portion (54), and the second portion (52B) so as to cover at least a portion of the drain-side extension portion (36) in a planar view.

[0115] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0116] 10...Nitride semiconductor device 20...Semiconductor substrate 26...Electron transport layer 28…electron supply layer 30…Gate layer 32...Gate layer main body 34…Source side extension part 36...Drain side extension 40...Gate electrode 42...Source electrode 44...Drain electrode 50…passivation layer 50A…Source opening 50B…Drain opening 52A…First part 521A…First area 521B…Second area 52B…Second part 53…boundary 54…First step 54A…Top of step 54B… Bottom surface of step 54C…Step wall 55A…3rd part 551A…Third area 551B…4th area 55B…4th part 56…boundary 57…Second step 57A…Top of step 57B…Bottom surface of step 57C…Step wall 60,60A…Field plate electrode T1…First thickness T1A…Thickness T2: Second thickness T3…Third thickness T3A…Thickness T4…Fourth thickness

Claims

1. an electron transit layer made of a first nitride semiconductor; an electron supply layer provided on the electron transit layer and made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; a gate layer formed on a portion of the electron supply layer and made of a third nitride semiconductor; a gate electrode provided on the gate layer; a passivation layer covering the electron supply layer, the gate layer, and the gate electrode, and including a source opening and a drain opening; a source electrode in contact with the electron supply layer through the source opening; a drain electrode in contact with the electron supply layer through the drain opening; a field plate electrode provided on the passivation layer and electrically connected to the source electrode; the gate layer includes a gate layer main body portion and a drain side extension portion extending from the gate layer main body portion toward the drain opening, The passivation layer comprises: a first portion overlapping both the drain side extension and the field plate electrode in a plan view; a second portion continuous with the first portion and located between the drain side extension and the drain opening; a first step portion located in a region including a boundary between the first portion and the second portion, the first step portion has a step upper surface, a step lower surface that is lower than the step upper surface, and a step wall that connects the step upper surface and the step lower surface, the first portion has a first thickness from the step top surface to the top surface of the drain-side extension portion; the second portion has a second thickness from a lower surface of the step to an upper surface of the electron supply layer; The first thickness is greater than the second thickness.

2. The nitride semiconductor device according to claim 1 , wherein a ratio of said first thickness to said second thickness is greater than 1 and is equal to or less than 3.

3. the first portion predominantly includes a region having the first thickness; The nitride semiconductor device according to claim 1 , wherein said second portion predominantly includes a region having said second thickness.

4. 4. The nitride semiconductor device according to claim 1, wherein said first thickness is not less than 100 nm and not more than 200 nm.

5. 5. The nitride semiconductor device according to claim 1, wherein the second thickness is not less than 50 nm and not more than 150 nm.

6. The first portion is a first region having the first thickness; a second region located closer to the gate layer body than the first region and having a thickness greater than the first thickness; 6. The nitride semiconductor device according to claim 1, comprising:

7. The nitride semiconductor device according to claim 6 , wherein said first region has a larger area than said second region in a plan view.

8. 8. The nitride semiconductor device according to claim 1, wherein said first thickness is greater than a thickness of said drain-side extension portion.

9. 9. The nitride semiconductor device according to claim 1, wherein a total thickness of the first thickness and a thickness of the drain-side extension portion is greater than a thickness of the gate layer main body portion and is smaller than a total thickness of the gate layer main body portion and a thickness of the gate electrode.

10. the gate layer further includes a source side extension portion extending from the gate layer body portion toward the source opening, The passivation layer comprises: a third portion overlapping both the source side extension and the field plate electrode in a plan view; a fourth portion continuous with the third portion and located between the source side extension and the source opening; a second step portion located in a region including a boundary between the third portion and the fourth portion, the second step portion has a step upper surface, a step lower surface that is lower than the step upper surface of the second step portion, and a step wall that connects the step upper surface and the step lower surface of the second step portion, the third portion has a third thickness from the step upper surface of the second step portion to an upper surface of the source-side extension portion; the fourth portion has a fourth thickness from the step lower surface of the second step portion to the upper surface of the electron supply layer, The nitride semiconductor device according to claim 1, wherein said third thickness is greater than said fourth thickness.

11. The nitride semiconductor device according to claim 10 , wherein a ratio of said third thickness to said fourth thickness is greater than 1 and is equal to or less than 3.

12. The nitride semiconductor device according to claim 10 , wherein the third thickness is not less than 100 nm and not more than 200 nm.

13. The nitride semiconductor device according to claim 10, wherein the fourth thickness is not less than 50 nm and not more than 150 nm.

14. The third portion is a third region having the third thickness; and a fourth region located closer to the gate layer body than the third region and having a thickness greater than the third thickness; The nitride semiconductor device according to claim 10, comprising:

15. The nitride semiconductor device according to claim 10, wherein the third thickness is greater than a thickness of the source-side extension portion.

16. The nitride semiconductor device according to any one of claims 10 to 15, wherein a total thickness of the third thickness and a thickness of the source-side extension portion is greater than a thickness of the gate layer main body portion and is smaller than a total thickness of the gate layer main body portion and a thickness of the gate electrode.

17. The nitride semiconductor device according to any one of claims 1 to 16, wherein the field plate electrode is formed integrally with the source electrode and extends from the source electrode toward the drain electrode so as to cover the gate layer main body and the drain side extension in a planar view.

18. The nitride semiconductor device according to any one of claims 1 to 16, wherein the field plate electrode is provided separately from the source electrode and is provided across the first portion, the first step portion, and the second portion so as to cover at least a portion of the drain side extension portion in a planar view.

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