FMCW chirp bandwidth control

Abstract

In the described example, a frequency modulated continuous wave (FMCW) synthesizer (208) includes a control engine (304) and a phase locked loop (302) (PLL), which includes a frequency divider (310), a control voltage generator (CVG), and a voltage controlled oscillator VCO (330). The frequency divider varies the VCO output frequency based on a control input (340). The CVG generates a control voltage (328) based on the frequency reference (308) and the divider output. The VCO outputs an FMCW output (336) having a VCO output frequency in response to the control voltage (328). The control engine (304) generates the control input (340) such that the VCO output frequency is at a first frequency from a first time to a second time, changes at a first rate from the second time to a third time, changes at a second rate different from the first rate from the third time to a fourth time, and is at the second frequency from the fourth time to a fifth time.

Description

[Technical field]

[0001] This application relates generally to frequency modulated continuous wave (FMCW) radar, and more particularly to the precise generation of FMCW chirp waveforms. [Background technology]

[0002] Prior art high speed FMCW radar systems include an FMCW synthesizer that generates chirp signals that are processed (e.g., phase shifted, amplified) and transmitted. When the FMCW radar system receives reflections of the transmitted chirp signals from an object, it can process these signals and determine the range, velocity, and distance to the object. Each chirp signal slews up and down in frequency over a period of time.

[0003] FIG. 1 shows an example diagram of a prior art FMCW signal 100 generated by a prior art FMCW synthesizer, with the vertical axis being frequency and the horizontal axis being time. FIG. 1 also shows a corresponding control timing diagram 102, with the vertical axis being control signals and the horizontal axis being time. The control timing diagram 102 shows a number of control signals 104 (sometimes referred to as control words) with initiation pulses occurring at various times (t 0 , t 1 1. Each control signal 104 initiates an action on a corresponding control signal 104, represented as a vertical line occurring at a start frequency (F 0 ) and the subsequent chirp frequency (0 or s in the example control signal 104 in FIG. 1 ). 1 ) and a slope to generate the frequency. The slope corresponds to the change in frequency per unit time, e.g., ΔHz / s.

[0004] Interval t 0 ~t 1 is the idle time 106 during which no FMCW chirps are transmitted. This idle time is controlled by the control signal 104 (F 0,0) is fed to the FMCW synthesizer at a frequency F 0 and generate a frequency F 0 A constant tone having a time t 0 Starting at time t 1 ~t 2 corresponds to the generation and transmission of the FMCW chirp 108. 1 In the control signal 104 (F 0 , s 1 ) is fed to the FMCW synthesizer 108 at the frequency F 0 and set the output frequency 112 to a slope of s 1 and generates the FMCW chirp 108 at time t 2 In the FMCW chirp 108, the frequency F 1 (The maximum frequency of FMCW Chirp 108 is 114.) 1 The maximum frequency of 114 is the starting frequency F 0 plus the slope of the FMCW chirp 108 multiplied by the duration of the FMCW chirp 108, which corresponds to F 1 =F 0 +s 1 ×(t 2 -t 1 )

[0005] Interval t 2 ~t 3 corresponds to the idle time 106. 2 The control signal 104 (F 0 , 0) instructs the FMCW synthesizer to synthesize its output at a frequency F with an intended waveform 116 that may have a conventional sawtooth pattern. 0 However, the result of this change in frequency separation is a new targeted onset frequency F 0The settling time may result in an actual waveform 118 that includes an unintended overshoot 120 of more than 100 ms. Such overshoots may result in additional restalling time before the FMCW signal 100 stabilizes and allows the next FMCW chirp 108 to be generated. The reduced FMCW chirp 108 rate reduces the number of data samples that can be collected, reducing the accuracy of the FMCW radar system. Some FMCW radars do not collect radar data samples during the settling time, or do not use data samples collected during the settling time, to determine the presence, range, and velocity of a target.

[0006] In some examples, the FMCW radar system operates within an allocated bandwidth and frequency overshoot 120 can cause the FMCW signal to exceed the allocated bandwidth. In some examples, the FMCW radar system operates within an allocated bandwidth and frequency overshoot 120 can cause the FMCW signal to exceed the allocated bandwidth. 0 and F 1 is selected. However, this may reduce the accuracy of the FMCW radar system since the accuracy of the FMCW radar system is proportional to the bandwidth of the transmitted FMCW chirp 108. In some examples, the radar system power amplifier is turned off to prevent transmission during the idle time 106. However, this may result in additional resettling time in the FMCW radar system receiver as it transitions between not receiving a signal and receiving a signal, and the receiver accuracy may be reduced during the resettling. Turning the FMCW radar system power amplifier 118 off and on may also result in additional resettling time in the FMCW synthesizer since the power amplifier state transitions pull the frequency generated by the FMCW synthesizer. Summary of the Invention

[0007] In the described example, a frequency modulated continuous wave (FMCW) synthesizer includes a control engine and a phase-locked loop (PLL), the PLL including a frequency divider, a control voltage generator (CVG), and a voltage controlled oscillator (VCO). The frequency divider varies a VCO output frequency based on a control input. The CVG generates a control voltage based on a frequency reference and the frequency divider output. The VCO outputs an FMCW output having a VCO output frequency in response to the control voltage. The control engine generates the control input such that the VCO output frequency is a first frequency from a first time to a second time, changes at a first rate from a second time to a third time, changes at a second rate different from the first rate from a third time to a fourth time, and is at the second frequency from a fourth time to a fifth time. [Brief description of the drawings]

[0008] [Figure 1] 1 shows an example FMCW signal generated by a prior art FMCW synthesizer and a corresponding control timing diagram;

[0009] [Diagram 2] 1 illustrates an example functional block layout of an FMCW radar system.

[0010] [Diagram 3] 3 illustrates an example functional block layout of the FMCW synthesizer of FIG. 2.

[0011] [Figure 4] 4 shows an example diagram of an FMCW signal generated by the FMCW synthesizer of FIG. 3 and a corresponding control timing diagram.

[0012] [Diagram 5] 4 shows an example diagram of an FMCW signal generated by the FMCW synthesizer of FIG. 3 and a corresponding control timing diagram.

[0013] [Figure 6] 1 illustrates an example process for generating an FMCW signal.

[0014] [Figure 7] 7 shows an example process 700 for operating the FMCW radar system 200 of FIG. 2, including the FMCW synthesizer 208 of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] 2 shows an example functional block layout of a prior art FMCW radar system 200, which has certain characteristics known in the art, but which is further improved by the teachings herein. The system 200 includes a receiver (RX) 202, which receives a signal and outputs to a low noise amplifier (LNA) 204. The receiver 202 may include multiple receiver sensors to enable determination of information such as distance, speed, and range. The LNA 204 outputs to a mixer 206. An FMCW synthesizer 208 generates an FMCW chirp to be transmitted (e.g., for object detection and ranging). The FMCW synthesizer 208 outputs the FMCW chirp to the mixer 206 and to a phase shift block 210. The mixer 206 mixes the amplified receive signal from the LNA 204 with the chirp from the FMCW synthesizer 208 and outputs to a bandpass filter / variable gain amplifier (BPF / VGA) 212. The BPF / VGA 212 outputs to an analog-to-digital converter (ADC) 214, which outputs to a digital signal processor (DSP) 216 or other analysis component. The phase shift block 210 outputs the phase shifted FMCW chirp to the power amplifier (PA) 118, which outputs to the transmitter (TX) 220.

[0016] 2, transmitter 220 transmits an amplified, phase-shifted FMCW chirp 222 that may be reflected from objects within range 224 of the transmitted FMCW chirp 222. (The range of an FMCW radar such as FMCW radar system 200 depends, for example, on the modulation frequency of the transmitted signal, the frequency change per unit time of the chirp in the transmitted signal, i.e., the "slope" or "slew" of the chirp in the transmitted signal, the bandwidth of the BPF, and the ADC sampling rate.) The reflected FMCW signal 224 is received by receiver 202. DSP 216 may be used to determine information about objects within range 224, such as distance, direction, and velocity.

[0017] 3 shows an example functional block layout of the FMCW synthesizer 208 of FIG. 2. The FMCW synthesizer 208 includes a phase-locked loop (PLL) 302 and a timing and control engine 304. In the PLL 302, a phase frequency detector (PFD) 306 tunes a frequency reference 308 to a reference frequency F ref and also receives as an input the output of divider 310. The PFD 306 outputs UP and DN (down) control signals to a charge pump (CP) 312. The CP 312 outputs a control signal to a filter 314 which generates a filtered control signal VCTRL 328.

[0018] The filter 314 includes a first resistor R F and a second resistor R z and a third resistor R F and a third resistor 320 having a first capacitance C z and a first capacitor 322 having a second capacitance C F and a second capacitor 324 having a third capacitance C Fand a third capacitor 326 having a first pole and a second pole of the second resistor 318. The output of the charge pump 312 is connected to a first pole of the first resistor 316 and a first pole of the second resistor 318. The second pole of the second resistor 318 is connected to a first plate of the first capacitor 322. The second pole of the first resistor 316 is connected to a first pole of the third resistor 320 and a first plate of the second capacitor 324. The second pole of the third resistor is connected to output a filtered control signal VCTRL 328 from the filter 314 to a voltage controlled oscillator (VCO) 330 and is also connected to the first plate of the third capacitor 326. A reference node 332 of a reference voltage GRND, such as a ground voltage, is connected to the second plate of the first capacitor 322, the second plate of the second capacitor 324, and the second plate of the third capacitor 326.

[0019] The VCO 330 outputs to a buffer (BUF) 334, which receives the frequency F from the FMCW synthesizer 208. 0 The buffer 334 also outputs the FMCW output signal 336 to the divider 310, which outputs to the PFD 306 (as described above) and to the digital ramp generator 338. The digital ramp generator 338 is connected to receive timing and control signals 340 from the timing and control engine 304. The timing and control engine 304 may include, for example, a start frequency, a slope, and a start pulse (to begin execution based on the start frequency and slope). The timing and control engine 304 may be a slow timing and control engine. The timing and control engine 304 also outputs a reference frequency F ref For example, the timing and control engine 304 may be clocked by a 40 MHz clock, and F ref is equal to 900MHz.

[0020] The digital ramp generator 338 is connected to the divider 310, the CP 312, and the filter 314. The connections from the digital ramp generator 338 to the CP 312 and the filter 314 are shown as single lines for clarity, but can correspond to separate signals transmitted over separate lines.

[0021] The frequency divider 310 divides the FMCW output signal 336 by a number N to produce a frequency F 0 / N signal. The PFD306 outputs the reference frequency F ref and the divider output frequency F 0 / N and outputs the UP and DN control signals to make these two frequencies equal. Therefore, F 0 = N × F ref Digital ramp generator 338 outputs a signal to frequency divider 310, which controls the value of N and thereby the frequency of FMCW output signal 336. The control signals output by frequency divider 310 to charge pump 312 and filter 314 are further described with respect to FIGS.

[0022] 4 shows an example diagram of an FMCW signal generated by the FMCW synthesizer 208 of FIG. 3, as well as a corresponding control timing diagram 402. The control timing diagram 402 shows a number of control signals 404 (sometimes referred to as control words) that are applied at various times (t 0 , t 1 3. The control signals 404 include an initiation pulse for initiating an action on a corresponding control signal 404, represented as a vertical line appearing on the input of the digital ramp generator 338 (e.g., F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31, F32, F33, F34, F35, F36, F37, F38, F39, F40, F41, F42, F43, F44, F45, F46, F47, F48, F50, F51, F52, F53, F54, F55, F56, F57, F58, F59, F60, F61, F62, F63, F64, F65, F66, F67, F68, F69, F70, F71, F72, F73, F74, F75, F76, F77, F78, F79, F80, F81, F82, F83, F84, F85, F86, F87, F88, F89, F90, F91, F92, F93, F94, F95, F96, F97, F98, F99, F100, F101, F102, F103, F104, F105, F106, F107, F108, F109, F110, F110, F120, F130, F ref Each control signal 404 is equal to a starting frequency (F 0 or F 1 ) and the subsequent chirp frequency (0, s1 , or s 2 ) and a slope to generate the frequency. The slope corresponds to the change in frequency per unit time, e.g., ΔHz / s.

[0023] Interval t 0 ~t 1 is the idle time 406 during which no FMCW chirps are transmitted. 0 In the control signal 404 (F 0 ,0) is the frequency F with zero slope in the FMCW synthesizer 208. 0 and generate a frequency F 0 Generate a constant tone at 410 for time t 1 ~t 2 corresponds to the generation and transmission of the FMCW chirp 408. 1 In the control signal 404 (F 0 , s 1 ) is fed to the FMCW synthesizer 208 at the frequency F 0 and the gradient s 1 At time t 2 In the FMCW chirp 408, the frequency F 1 (FMCW Chirp 408's maximum frequency of 414 has been reached. FMCW Chirp 408F 1 The maximum frequency 414 of the FMCW chirp 408 is the slope of the FMCW chirp 408 multiplied by the duration of the FMCW chirp 408, which is the starting frequency F 0 This corresponds to the addition of F 1 =F 0 +s 1 ×(t 2 -t 1 )

[0024] The timing and control engine 304 is shown as F 1 We can calculate F 1 , F 0 , and the ramp-down period T down Based on 420s 2 where Tdown The FMCW chirp 408 has a maximum frequency of 414 to F 0 is the time period to slew downward to T down 420 can be selected. For example, T down 420 may be selected, F 0 , F 1 , and T down Based on s 2 can be calculated, and the cycle slip: s 2 =(F 0 -F 1 ) / T down A cycle slip is a slip of a cycle relative to the frequency reference 308 and corresponds to a loss of phase lock in the PLL 302. A cycle slip is a slip of a cycle relative to the frequency reference 308 and corresponds to a loss of phase lock in the PLL 302. A cycle slip is a slip of a higher slope s than the PLL 302 can tolerate. 2 can be caused by.

[0025] The interval t2 to t4 corresponds to the idle time 406. The ideal sawtooth pattern has a chirp start frequency F 0 However, the chirp start frequency F 0 To avoid overshoot when returning to t 2 The control signal 404 (F 1 , s 2 ) synthesizes the FMCW synthesizer 208 at a frequency of F 1 and the output frequency 418 is increased by a linear slope s 2 This allows the t 2 From 3 A controlled time period T down Over 420 Hz, the output frequency is the chirp start frequency F 0 Return to s 1 can be 100MHz / microsecond, and s 2t may be 1000 MHz / microsecond, allowing for a higher FMCW chirp 408 repetition frequency and therefore a shorter period for the repetition of the FMCW chirp waveform. The FMCW chirp waveform corresponds to the idle time 406 plus the FMCW chirp 408. Thus, the repetition period of the FMCW chirp waveform is t 0 From 2 Period until, and t 2 From 5 to 100 Hz (corresponding to the periods of two separate FMCW chirps 408, respectively). The repetition frequency is the inverse of the repetition period.

[0026] The FMCW signal 400 of Figure 4 illustrates a sawtooth signal. It is contemplated that a reverse sawtooth FMCW signal may also be used and such a reverse sawtooth signal may correspond to the FMCW signal 400, but with the time order of the control signals 404 reversed. Thus, the FMCW signal 400 may be generated as shown in Figure 4, with the time interval corresponding to the signal generated in response to the control signal being t 0 ~t 1 , t 1 ~t 2 , t 2 ~t 3 , t 3 ~t 4 , t 4 ~t 5 , and t 5 ~t6, or vice versa, and t 6 ~t 5 , t 5 ~t 4 , t 4 ~t 3 , t 3 ~t2, t2~t 1 , and t 1 ~t 0 corresponds to a time period of

[0027] The digital ramp generator 338 of FIG. s2 The time interval t corresponding to increasing the absolute value of the steepness of 2 ~t 3To shorten , the CP 312 can be controlled to supply increased current to the filter 314. For example, the current supplied to the filter 314 can be increased by increasing the current supplied to the charge pump 312 over a time interval t 1 ~t 2 3. The VCO 330 and PLL 302 can be increased by increasing the frequency of the output of the PLL 302 more quickly and accurately without losing lock and therefore without introducing cycle slips.

[0028] Time interval t 2 ~t 3 To shorten R, the digital ramp generator 338 may also control one or more of the resistors 316, 318, 320 or capacitors 322, 324, 326 of the filter 314 to increase the bandwidth of the filter 314 to increase the reaction rate of the filter 314 and increase the rate of change of the VCTRL 328. The bandwidth of the filter 314 may be increased, for example, by ten times the bandwidth used during the generation of the FMCW chirp 408. Thus, the digital ramp generator 338 may control R to vary the bandwidth of the filter 314. F , R Z , C F , and Cz (some or all of which may be programmable). Increasing the bandwidth of filter 314 increases the phase noise at FMCW synthesizer output 336, but reduces the chirp start frequency F 0 t . Conversely, lowering the bandwidth of filter 314 reduces the phase noise at FMCW synthesizer output 336. Thus, the bandwidth of filter 314 is adjusted to reduce the phase noise during the frequency ramp-down periods (the interval t 2 ~t 3 , and interval t 5 ~t 6 T corresponding to down420). The bandwidth of the filter 314 may be reduced during the remainder of the idle time 406 and during the FMCW chirp 408 to reduce phase noise at the FMCW synthesizer output 336.

[0029] In some examples, the idle time 406 can be considered "wasted" time when the ADC 214 of FIG. 2 is not sampling data for analysis. The ADC 214 of FIG. 2 samples data during the FMCW chirp 408 (so that data is received by the receiver 202). The increased filter noise from the increased filter 314 bandwidth increases the T down During 420, idle time 406 may be permitted to be reduced.

[0030] s 2 , the increased current of CP 312, and the increased bandwidth of filter 314, down During idle times 406, including during 420, the PLL 302 is selected to remain in lock to increase the accuracy of the frequency control of the VCO 330 and to avoid frequency overshoot. 2 , the increased current of CP 312 and the increased bandwidth of filter 314 are 2 ~t 3 , and therefore the frequency F 1 from frequency F 0 The time required for the transition to

[0031] 5 shows an example diagram of an FMCW signal 500 generated by FMCW synthesizer 208 of FIG. 3 and a corresponding control timing diagram 502. FMCW signal 500 is generated similarly to FMCW signal 400 of FIG. 4. However, FMCW signal 500 of FIG. 5 differs from FMCW signal 400 in that FMCW synthesizer 208 of FIG. 3 in that it generates a plurality of different frequencies (e.g., F 0 , F 2 ) and then several different frequencies (e.g., F 1 , F 3), and showing that it is possible to generate an FMCW output signal 336 without overshoot that includes FMCW chirps 508a, 508b that end with a slope of s between the FMCW chirps 508a, 508b. 1 and s 3 , and the ramp-down period T down1 516 and T down2 Between 528 s 2 and s 4 ).

[0032] Interval t 0 ~t 1 is the first idle time 506a. 0 In the timing and control engine 304, the timing and control engine 304 sends a control signal 504 to the PLL 302 to set a constant frequency 510F 0 (starting frequency F 0 , zero slope).

[0033] Interval t 1 ~t 2 is the first FMCW chirp 508a. Time t 1 In FIG. 3, the PLL 302 operates at a frequency F 0 Starting with a gradient of s 1 The output frequency 512 is instructed to slew increasing at time t 2 In, the FMCW chirp 508a has a maximum frequency of 514, F 1 As described above with respect to FIG. 0 , t 1、 and t 2 Using F 1 can be calculated.

[0034] Interval t 2 ~t 4 is the second idle time 506b. 2 ~t 3 is the ramp-down period T down1 516. The first ramp down 518 over the interval t 2 ~t 3During this time, the FMCW synthesizer output frequency is at frequency F 1 from frequency F 2 4, the timing and control engine 304 controls the CP 312 to increase its output current and the filter 314 to increase its bandwidth, resulting in a slope s 2 The gradient s 1 It can be made steeper, and T down1 516. Also, the slope s 2 is F 1 , F 2 , T down1 516:s2=(F 2 -F 1 ) / T down1 It can be calculated based on the time t 3 At , the FMCW synthesizer output 336 has a constant frequency of 520F 2 Therefore, the frequency F 2 has zero gradient.

[0035] Interval t 4 ~t 5 is the second FMCW chirp 508b. 4 In this case, the PLL 302 operates at a frequency F 2 Starting with a gradient of s 3 The output frequency 522 is commanded to slew increasing at time t 5 In the FMCW chirp 508b, the maximum frequency is 524, F 3 As described above with respect to FIG. 2 , t 4 , and t 5 Using F 3 can be calculated.

[0036] Time t 5 is the start of the third idle period 506c (the end of the third idle period 506c, which corresponds to the start of the third FMCW chirp, is not shown). 5 ~t 6 is the duration T down2The second ramp down 526 over the interval t 5 ~t 6 During this time, the FMCW synthesizer output frequency is at frequency F 3 from frequency F 4 to, gradient s 4 4, the timing and control engine 304 controls the CP 312 to increase its output current and the filter 314 to increase its bandwidth, resulting in a slope s 4 The gradient s 3 It can be made steeper, and T down2 528. Also, the slope s 4 is F 3 , F 4 , T down2 516:s 4 =(F 4 -F 3 ) / T down2 It can be calculated based on the time t 6 At , the FMCW synthesizer output 336 has a constant frequency of 530F 4 Therefore, the frequency F 4 has zero gradient.

[0037] 6 shows an example process 600 for operating the FMCW radar system 200 of FIG. 2. In step 602, the transmitter 220 transmits an FMCW synthesizer signal. In step 604, the receiver 202 receives the FMCW chirp return signal 226. In step 606, the FMCW synthesizer 208 generates an FMCW synthesizer signal at an FMCW synthesizer output frequency, where the FMCW synthesizer output frequency: between a first time and a second time, is a first FMCW idle frequency, between a second time and a third time, varies at a specified first rate, between a third time and a fourth time, varies at a specified second rate, the first rate being different from the second rate, and between a fourth time and a fifth time, is a second FMCW idle frequency. In step 608, the mixer 206 mixes the FMCW chirp reflected signal with the FMCW synthesizer signal to generate a mixer output. In step 610, the ADC 214 samples the mixer output.

[0038] 7 shows an example process 700 for operating the FMCW radar system 200 of FIG. 2 including the FMCW synthesizer 208 of FIG. 3. To generate the FMCW chirp 408, a digital state machine (not shown) controls the ADC 214, the TX 202, the RX 220, and the FMCW synthesizer 208 to operate synchronously as follows: In step 702, the bandwidth of the filter 314 is changed to a relatively low value by changing the impedance of the filter 314. In step 704, the current supplied to the CP 312 is changed to a relatively low value. In step 706, the output frequency of the VCO 330 is ramped up to generate the FMCW chirp 408, which is transmitted using the transmitter 220. In step 708, the FMCW chirp return signal 226 is received using the receiver 202. In step 710, data is sampled using the ADC 214.

[0039] During the time between FMCW chirps 408, the digital state machine controls the ADC 214 and the FMCW synthesizer 208 as follows: At step 712, the ADC 214 stops sampling data; At step 714, the bandwidth of the filter 314 is increased to a relatively high value by changing the impedance of the filter 314; At step 716, the current supplied to the CP 312 is increased to a relatively high value; At step 718, the output frequency of the VCO 330 is ramped down with a slope having a higher absolute value than the slope of the FMCW chirp 408 by setting the slope such that the ramp down begins at the ending frequency of the FMCW chirp 408 and ends at the starting frequency of the next FMCW chirp 408, avoiding cycle slips. The process 700 can then be repeated from step 702.

[0040] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

[0041] In some embodiments, the filter is T down In some embodiments, the filter is set to a high bandwidth during idle times.

[0042] In some embodiments, an ADC samples the signal emitted from the receiver over a period corresponding to an FMCW synthesizer that generates the FMCW chirp.

[0043] In some embodiments, the input of the divider connected to the output of the buffer may be referred to as the tone input, and the input of the divider connected to the digital ramp generator may be referred to as the control input.

[0044] In some embodiments, a control voltage generator may be used in the phase-locked loop to generate a control voltage (VCTRL) for the VCO in response to a reference frequency and fed back in response to the VCO output signal. In some embodiments, the control voltage generator includes a PFD, a charge pump, and a filter, as described with respect to FIG.

[0045] In some embodiments, the FMCW chirp corresponds to a decreasing frequency and the ramp down corresponds to an increasing frequency.

[0046] In some embodiments, during the initial portion of the FMCW chirp, such as the first 10% of the FMCW chirp, the FMCW synthesizer continues to settle towards the correct frequency ramp. This time can be considered "wasted" time when the ADC is not sampling data for analysis.

[0047] In some embodiments, the time between FMCW chirps (idle time) may be referred to as inter-chirp time.

[0048] In some embodiments, a ramp down occurs before the FMCW chirp, producing a signal that resembles an inverse sawtooth. Thus, starting at an idle frequency, the frequency is changed with a specified slope for a specified duration to reach the FMCW chirp start frequency, while the charge pump output current and filter bandwidth are relatively increased. Then, starting at the FMCW chirp start frequency, the frequency is changed with a specified slope for a specified duration to produce the FMCW chirp, while the charge pump output current and filter bandwidth are relatively decreased.

[0049] In some embodiments for 76-81 GHz commercial automotive radar, the idle time, FMCW chirp, and ramp-down period durations are 5 μs, 30 μs, and 2 μs, respectively. In some embodiments, the FMCW chirp duration is 15 μs to facilitate accurate detection of object presence, range, and velocity at very high velocities.

[0050] In some embodiments, a processor (e.g., a DSP) processes data sampled (e.g., by an ADC) during the FMCW chirp to determine one or more of the presence, distance, or velocity of a target object. In some embodiments, the processor does not process data sampled during ramp-down or during idle times (or both) to determine the presence, distance, or velocity of a target object.

[0051] 2-6, it is intended to suggest that in certain embodiments, the frequency of the output signal is controlled to have a particular value between a first time and a second time (for example), and a particular slope beginning at a particular value between a second time and a third time, and that the frequency of the output signal avoids other unintended values ​​or slopes for the described time periods. However, in certain embodiments, the actual signal frequency may not exhibit perfectly linear behavior, and normal frequency variations common to smooth transitions in the controlled characteristics of a signal (e.g., as opposed to relatively prime frequency control, which results in overshoot, as described herein) are intended to be considered within the described signal performance with respect to the specified behavior during the specified intervals.

Claims

1. 1. A frequency modulated continuous wave (FMCW) synthesizer, comprising: A phase-locked loop (PLL), a frequency divider including a control input, a frequency divider input, and a frequency divider output; a control voltage generator (CVG) including a CVG input coupled to the divider output, the CVG being configured to generate a control voltage in response to the CVG input; a voltage controlled oscillator (VCO) including a VCO input coupled to the CVG and a VCO output coupled to the divider input, the VCO being configured to output an FMCW output signal having an FMCW output frequency in response to the VCO input; the PLL including a control engine including a first control output coupled to a control input of the frequency divider, the FMCW output frequency being determined by: a first idle frequency from a first time to a second time; varies at a specified first rate from the second time to a third time; varying from the third time to a fourth time at a specified second rate different from the specified first rate; a second idle frequency different from the first idle frequency from the fourth time to the fifth time; the control engine configured to control the PLL such that An FMCW synthesizer including:

2. 2. The FMCW synthesizer of claim 1, a receiver adapted to receive the reflected FMCW chirp, the receiver including a receiver output; an analog-to-digital converter (ADC) including an ADC input coupled to the receiver output and an ADC output, the ADC configured to sample a signal received by the ADC input and to output the sampled signal; a processor including a processor input coupled to the ADC output, the processor configured to determine at least one of a presence, a distance, and a velocity of a target object in response to the sampled signal being sampled between the second time and the third time, and configured to perform no determination operation between the third time and the fourth time; a transmitter including a transmitter input coupled to the VCO output, the transmitter being configured to transmit a signal received by the transmitter input; The FMCW synthesizer further comprises:

3. 3. The FMCW synthesizer of claim 2, An FMCW synthesizer, wherein the absolute value of the specified second rate is greater than the absolute value of the specified first rate.

4. 2. The FMCW synthesizer of claim 1, the control engine further includes a second control output and a third control output; The CVG is a charge pump (CP) including a charge pump (CP) control input coupled to the second control output and a CP output, the CP being configured such that a current of the CP output varies in response to the CP control input; a filter including a filter signal input coupled to the CP output, a filter control input coupled to the third control output, and a filter output, the filter being configured to vary a bandwidth of the filter in response to the filter control input; The FMCW synthesizer further comprises:

5. 5. An FMCW synthesizer as claimed in claim 4, comprising: The control engine: controlling a bandwidth of the filter to be relatively low between the second time and the third time; controlling the bandwidth of the filter to be relatively high between the third time and the fourth time; The FMCW synthesizer further configured as follows:

6. 6. An FMCW synthesizer as claimed in claim 5, comprising: An FMCW synthesizer, wherein the filter is configured to vary a bandwidth of the filter by varying one or more impedances of the filter.

7. 5. An FMCW synthesizer as claimed in claim 4, comprising: The control engine: controlling the current of the CP output to be relatively low between the second time and the third time; controlling the current of the CP output to be relatively high between the third time and the fourth time; The FMCW synthesizer further configured as follows:

8. 2. The FMCW synthesizer of claim 1, An FMCW synthesizer, wherein the specified first rate is constant and the specified second rate is constant.

9. 2. The FMCW synthesizer of claim 1, the control engine further includes a second control output; the CVG further comprising a CVG control input coupled to the second control output, the CVG further configured to vary a current of the control voltage output in response to the CVG control input; The control engine: controlling the current of the control voltage output to be relatively low between the second time and the third time; controlling the current of the control voltage output to be relatively high between the third time and the fourth time; The FMCW synthesizer further configured as follows:

10. 2. The FMCW synthesizer of claim 1, The control engine: The output frequency of the FMCW is changing from the fifth time to the sixth time, or vice versa, at a specified third rate; changing from the sixth time to a seventh time, or vice versa, at a specified fourth rate different from the specified third rate; a third idle frequency from the seventh time to the eighth time, or vice versa; The FMCW synthesizer is further configured to control the PLL so that

11. 2. The FMCW synthesizer of claim 1, The control engine is further configured to control the PLL to maintain phase lock both when generating FMCW chirps and during idle times between generating FMCW chirps.

12. 2. The FMCW synthesizer of claim 1, An FMCW synthesizer in which the time sequence starts with the first time, then the second time, then the third time, then the fourth time, then the fifth time, or starts with the fifth time, then the fourth time, then the third time, then the second time, then the first time.

13. 2. The FMCW synthesizer of claim 1, An FMCW synthesizer, wherein the control engine further includes the feedback input coupled to the divider output, the control engine further configured to control the PLL in response to the feedback input.

14. 1. A frequency modulated continuous wave (FMCW) data system comprising: a receiver adapted to receive the reflected FMCW chirp, the receiver including a receiver output; 1. An FMCW synthesizer, comprising: FMCW synthesizer output; a phase locked loop (PLL) including a control input and a phase locked loop (PLL) output coupled to the FMCW synthesizer output, the PLL being configured to output an FMCW signal having an FMCW output frequency in response to the control input; a control engine including a feedback input coupled to the FMCW synthesizer output and a control output coupled to the control input, the FMCW output frequency being determined by: a first FMCW idle frequency from a first time to a second time; varies at a specified first rate from the second time to a third time; varying from the third time to a fourth time at a specified second rate different from the specified first rate; a second FMCW idle frequency different from the first FMCW idle frequency from the fourth time to the fifth time; the control engine configured to control the PLL in response to the feedback input such that the FMCW synthesizer, a mixer including a first mixer input coupled to the receiver output, a second mixer input coupled to the frequency synthesizer output, and a mixer output, the mixer being configured to generate a mixer output signal in response to the first mixer input and the second mixer input; an analog-to-digital converter (ADC) including an ADC input coupled to the mixer output and an ADC output, the ADC configured to sample a signal received by the ADC input and to output the sampled signal; a processor including a processor input coupled to the ADC output, the processor configured to determine at least one of a presence, a distance, and a velocity of a target object in response to the sampled signal sampled between the second time and the third time, the processor configured to perform no determination operation between the third time and the fourth time; a transmitter including a transmitter input coupled to the FMCW synthesizer output, the transmitter configured to transmit a signal received by the transmitter input; An FMCW data system.

15. 15. The FMCW radar system of claim 14, An FMCW radar system, wherein the absolute value of the determined second rate is greater than the absolute value of the determined first rate.

16. 15. The FMCW radar system of claim 14, 11. The FMCW radar system of claim 10, wherein the control engine is further configured to control the PLL to maintain phase lock both when generating FMCW chirps and during idle times between generation of FMCW chirps.

17. 15. The FMCW radar system of claim 14, The control engine: increasing a filter bandwidth of a filter of said PLL during idle times between generation of an FMCW chirp; Lowering the filter bandwidth of the filter of the PLL during generation of the FMCW chirp; increasing the current of a control voltage of a voltage controlled oscillator (VCO) of said PLL during idle times between generation of FMCW chirps; reducing the current of the control voltage of the VCO of the PLL during generation of the FMCW chirp; The FMCW radar system is further configured to control the PLL so as to

18. 1. A method for operating a frequency modulated continuous wave (FMCW) radar, comprising: receiving an FMCW chirp reflected signal with a receiver; generating an FMCW synthesizer signal at an FMCW synthesizer output frequency using an FMCW synthesizer, the FMCW synthesizer output frequency being: a first FMCW idle frequency from a first time to a second time; varies at a specified first rate from the second time to a third time; varying from the third time to a fourth time at a specified second rate different from the specified first rate; a second FMCW idle frequency different from the first FMCW idle frequency from the fourth time to the fifth time; generating said FMCW synthesizer signal; mixing the FMCW chirp reflected signal with the FMCW synthesizer signal using a mixer to generate a mixer output; sampling the mixer output with an analog-to-digital converter (ADC); transmitting the FMCW synthesizer signal using a transmitter; A method comprising:

19. 20. The method of claim 18, relatively lowering a filter bandwidth of a phase-locked loop (PLL) of the FMCW synthesizer between the second time and the third time; making the bandwidth of a filter of a PLL of the FMCW synthesizer relatively high during the third time and the fourth time; The method further comprises:

20. 20. The method of claim 18, maintaining a relatively low current at an output of a charge pump of a phase-locked loop (PLL) of the FMCW synthesizer during the second and third times; making the current of the output of the charge pump of the PLL of the FMCW synthesizer relatively high between the third time and the fourth time; The method further comprises:

21. 20. The method of claim 18, generating the FMCW synthesised signal using the FMCW synthesiser, The FMCW synthesizer output frequency is at a third rate specified between the fifth and sixth times; at a specified fourth rate different from the specified third rate between the sixth and seventh times; a third FMCW idle frequency between the seventh and eighth times; The method further comprising generating the FFMCW synthesizer signal.

22. 20. The method of claim 18, The method further includes maintaining phase synchronization with a phase-locked loop (PLL) of the FMCW synthesizer both when generating the FCMW chirp and during idle times between generation of FMCW chirps.

23. 20. The method of claim 18, A method in which the time sequence starts with the first time, then the second time, then the third time, then the fourth time, then the fifth time, or starts with the fifth time, then the fourth time, then the third time, then the second time, then the first time.

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