Compensated Digital-to-Analog Converter (DAC)

Abstract

The circuit includes a digital-to-analog converter (DAC) (200) and a compensation circuit (210). The DAC (200) has a first terminal (VA) and a second terminal (VB). The compensation circuit (210) has a third terminal (211) and a fourth terminal (212). The third terminal (211) is coupled to the first terminal (VA) and the fourth terminal (212) is coupled to the second terminal (VB). The compensation circuit (210) is configured to source a current to the first terminal (VA) in response to an increase in a voltage on the second terminal (VB) and to sink a current from the first terminal (VA) in response to a decrease in a voltage on the second terminal (VB).

Description

[Technical field]

[0001] A digital-to-analog converter (DAC) converts a digital signal to an analog signal. A current-steering DAC is a type of DAC that includes a current source and two or more transistors. The control terminals of the transistors (e.g., their gates) are controlled by a digital input signal or its logical inverse. In response to one state of the digital input signal to the DAC, a first transistor is turned on to direct current from the current source to one output terminal of the current-steering DAC. In response to another state of the digital input signal, another transistor is turned on to direct current from the current source to another output terminal of the current-steering DAC. Current-steering DACs may be used, for example, in sigma-delta modulators used in analog-to-digital converters (ADCs). Summary of the Invention

[0002] In one example, a circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has a first terminal and a second terminal. The compensation circuit has a third terminal and a fourth terminal. The third terminal is coupled to the first terminal and the fourth terminal is coupled to the second terminal. The compensation circuit is configured to source a current to the first terminal in response to an increase in a voltage on the second terminal and to sink a current from the first terminal in response to a decrease in the voltage on the second terminal. [Brief description of the drawings]

[0003] [Figure 1] 1 illustrates an example implementation of a current steering DAC.

[0004] [Diagram 2] 1 illustrates an example implementation of a compensated current steering DAC that includes p-type metal oxide semiconductor field effect transistors.

[0005] [Diagram 3] 3 illustrates an example implementation of the current steering DAC of FIG. 2 with additional details.

[0006] [Figure 4] 2, 3, and 5 show an example of a second-order delta-sigma modulator including multiple compensated current-steering DACs.

[0007] [Diagram 5] 1 illustrates an example implementation of a compensated current steering DAC that includes n-type metal oxide semiconductor field effect transistors. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] As mentioned above, a current steering DAC has transistors that "steer" current to one output terminal of the DAC or another output terminal of the DAC. Threshold voltage mismatch between the transistors and feedback effects from a delta-sigma modulator in which a current steering DAC may be used can undesirably introduce harmonics and noise. Such harmonics and noise can degrade the signal-to-noise ratio (SNR) and distort the output signal from, for example, a sigma-delta analog-to-digital converter (ADC) in which the sigma-delta modulator is used. Figure 1 is used to explain the problem of harmonics and noise.

[0009] FIG. 1 is an example of a current steering DAC 100. In this example, the current steering DAC 100 includes transistors MP0, MP1, PCAS, and PBIAS. The transistor PBIAS is a p-type metal oxide semiconductor field effect transistor (PMOS transistor). A bias voltage BIAS1 is provided to the gate of the PBIAS transistor, thereby causing the transistor PBIAS to generate a fixed reference current IREF1. The transistor PBIAS operates as a current source. The drain of the transistor PBIAS is connected to the source of the transistor PCAS, which operates as a cascode transistor to increase the output resistance of the current source (transistor PBIAS). A bias voltage BIAS2 is provided to the gate of the PCAS transistor.

[0010] The drain of transistor PCAS is coupled to the sources of PMOS transistors MP0 and MP1 at a terminal labeled VA. Current steering DAC 100 is a single-bit DAC whose single-bit digital inputs are digital input signal Q and its logical inverse QZ. Digital input signal Q is coupled to the gate of transistor MP0, and QZ is coupled to the gate of transistor MP1. Terminals VP and VM are the output terminals of the current steering DAC. The drain of transistor MP0 is coupled to terminal VP, and the drain of transistor MP1 is coupled to terminal VM. Depending on the state of the digital input signal, the IREF1 reference current flows through transistor MP0 to terminal VP or through transistor MP1 to terminal VM. When signal Q is low (and thus QZ is high), the IREF1 reference current flows through transistor MP0 to terminal VP. Conversely, when signal QZ is low (and thus Q is high), the IREF1 reference current flows through transistor MP1 to terminal VM. Terminals VP and VM are coupled to other components in the system, such as a delta-sigma modulator in which the current-steering DAC 100 may be used. An example of a delta-sigma modulator using a current-steering DAC is provided in FIG. 4 and described below.

[0011] Capacitor Cpar is shown coupled between terminal VA and ground. Capacitor Cpar represents the parasitic capacitances of transistors MP0, MP1, PCAS, and the layout trace capacitance between terminal VA. For transistors MP0 and MP1, capacitor Cpar represents the gate-source capacitance (CGS), source-body capacitance (CSB), and drain-source capacitance (CDS) of MP1 and MP0. For transistor PCAS, capacitor Cpar represents the gate-drain capacitance (CGD), drain-body capacitance (CDB), and CDS.

[0012] In an ideal case (i.e., without the parasitic capacitor Cpar), the total IREF1 current flows through either the VP or VM terminal through the respective transistor MP0 or MP1. The voltage on the terminal VA may increase or decrease with each digital input transition (e.g., Q changing from low to high or high to low). In some cases, the transistors MP0 and MP1 operate in the saturation region. If the threshold voltage of the transistor MP0 is equal to the threshold voltage of the transistor MP1, the voltage on the terminal VA remains at a fixed voltage and does not change during a digital input change of the state of the signals Q and QZ. However, due to manufacturing tolerances, there may be a difference in the threshold voltages of the transistors MP0 and MP1. The threshold voltage difference causes a change in the voltage on the terminal VA during a digital input change. For example, the voltage on the terminal VA may increase or decrease by the amount of the threshold voltage difference between the transistors MP0 and MP1, depending on which transistor has a higher or lower threshold voltage than the other transistor.

[0013] In some implementations, transistors MP0 and MP1 operate in their linear regions. In such implementations, during a data transition of Q and QZ (e.g., Q changes from "0" to "1" and QZ changes from "1" to "0"), the voltage on terminal VA increases to VP+VDS (where VDS is the drain-source voltage of transistor MP0 or MP1 that is on). In some implementations, the magnitude of VDS may be on the order of 2-3 mV. The voltage between terminals VP and VM has a signal swing with some offset voltage. The offset voltage may be on the order of 10-20 mV in some implementations.

[0014] Due to the presence of the parasitic capacitor Cpar in response to a sudden increase in the voltage at the terminal VA, the voltage across the capacitor Cpar increases, so that a current flows from the terminal VA to the capacitor Cpar, as shown by arrow 110. Conversely, in response to a decrease in the voltage at the terminal VA, the voltage across the capacitor Cpar decreases, so that a current flows from the capacitor Cpar to the terminal VA, as shown by arrow 111. In a scenario in which the capacitor Cpar is being charged (due to an increase in the voltage on the terminal VA), a portion of the IREF1 current is provided to the capacitor Cpar. Thus, when the capacitor Cpar receives current from the terminal VA, less than the full IREF1 current flows through whichever transistor MP0 or MP1 is on. In a scenario in which the capacitor Cpar is being discharged (due to a decrease in the voltage on the terminal VA), the current provided by the capacitor Cpar is provided to the terminal VA and is added to the IREF1 current from the transistor PBIAS. Thus, when the capacitor Cpar provides current to the terminal VA, more than the full IREF1 current flows through whichever transistor MP0 or MP1 is on. In either case, during the transitions of the digital signals Q and QZ at the gates of transistors MP0 and MP1, the current through MP0 or MP1 (whichever transistor is on) will momentarily deviate from the magnitude of IREF1. When the parasitic capacitor Cpar is fully charged or discharged, the (110) or (111) current into or out of capacitor Cpar drops to 0A and the drain current through MP0 or MP1 returns to IREF1. The above data transition-induced deviations in IREF1 above and below unfortunately introduce harmonics into the output current from the current steering DAC (the current through transistors MP0, MP1) and increase the noise floor due to aliasing.

[0015] FIG. 2 shows an example of a compensated current steering DAC 200 that reduces or eliminates the harmonic and noise floor issues mentioned above by using a compensation circuit 210. The compensation circuit 210 ensures that the current through MP0 or MP1 is approximately equal to IREF1 despite the extra current flow to or from the capacitor Cpar. The compensation circuit 210 includes a transistor M21, a compensation capacitor Ccomp, and a bias current circuit Ibias ("Ibias" refers to both the bias current circuit and the current it generates). In this example, the transistor M21 is an n-type metal oxide semiconductor field effect transistor (NMOS transistor). The drain of the transistor M21 is coupled to a supply voltage terminal, and the source of the transistor M21 is coupled to the compensation capacitor Ccomp and to the bias current source circuit Ibias at the terminal VC. The drain current through the transistor M21 is denoted as I_M21. The current through the compensation capacitor Ccomp is denoted as I_comp. The current through the parasitic capacitor Cpar is denoted as I_cpar. Currents I_cpar and I_comp are shown as solid arrows in one direction and dashed arrows in the opposite direction. The solid arrows represent the direction of currents I_cpar and I_comp in response to an increase in voltage on terminal VA (and capacitor Cpar charging), while the dashed arrows represent the direction of currents I_cpar and I_comp in response to a decrease in voltage on terminal VA (and capacitor Cpar discharging).

[0016] The gate of transistor M21 provides a first terminal 211 of compensation circuit 210. A compensation capacitor Ccomp provides a second terminal 212 of compensation circuit 210 (opposite the capacitor terminal coupled to the source of transistor M21). Compensation circuit terminal 211 is coupled to terminal VA. Compensation circuit compensation capacitor Ccomp (and thus terminal 212) is coupled to the junction between transistors PBIAS and PCAS (terminal labeled VB in FIG. 2).

[0017] When the voltage on the terminal VA increases, a current I_cpar flows from the terminal VA to the parasitic capacitor Cpar, thereby charging the parasitic capacitor. The direction of current flow of I_cpar to the parasitic capacitor Cpar is represented as a solid arrow. The increase in the voltage on the terminal VA also increases the gate-source voltage (Vgs) of transistor M21. The increase in Vgs of transistor M21 causes an increase in the drain current (I_M21) through transistor Ml. Because Ibias is a fixed current, as the current I_M21 increases, that portion of the current I_M21 that exceeds Ibias flows as I_comp (solid arrow) through the compensation capacitor Ccomp to the terminal VB. Thus, when the voltage on the terminal VA increases, a current I_cpar flows from the terminal VA to the parasitic capacitor Cpar, and a current of approximately equal magnitude I_comp flows from the compensation capacitor Ccomp to the terminal VB. The net effect of the current I_cpar leaving terminal VA and the approximately equal magnitude current I_comp entering terminal VB is that the current through either transistor MP0 or MP1 is approximately equal to Iref1, even during transitions of the digital input signals Q and QZ to the compensated current steering DAC 200.

[0018] When the voltage on the terminal VA decreases, a current I_cpar (dashed arrow) flows from the parasitic capacitor Cpar to the terminal VA, thereby discharging the parasitic capacitor. The decrease in the voltage on the terminal VA also decreases the Vgs of the transistor M21. The decrease in Vgs of the transistor M21 causes a decrease in the current I_M21 through the transistor. When the current I_M21 decreases below the magnitude of the fixed current Ibas, the I_comp current (dashed arrow) flows from the terminal VB through the capacitor Comp to the terminal VC, such that the sum of I_M21 and I_comp is approximately equal to Ibias. Thus, when the voltage on the terminal VA decreases, a current I_cpar flows from the parasitic capacitor Cpar to the terminal VA, and an approximately equal current I_comp flows from the terminal VB to the compensation capacitor Ccomp. The net effect of the current I_cpar flowing into terminal VA and the approximately equal magnitude current I_comp flowing from terminal VB is that the current through either transistor MP0 or MP1 that is on is approximately equal to Iref1, even during transitions of the digital input signals Q and QZ to the compensated current steering DAC 200.

[0019] The compensation circuit 210 has a common-drain type configuration. The voltage gain of this configuration is ideally unity, but in practice can be slightly less than unity (e.g., unity less by an amount α). The current I_comp is made approximately equal to the current I_cpar, taking into account the value α, by making the capacitance of the capacitor Ccomp equal to the capacitance of the capacitor Cpar (i.e., α×Ccomp=Cpar). The current value of Ibias is selected so that the amplifier has sufficient bandwidth. Thus, the voltage at the terminal VC can track the voltage at the terminal VA.

[0020] As described above, compensation circuit 210 responds to changes in the voltage on terminal VA by sourcing or sinking current to or from terminal VB. The current into or out of terminal VB by compensation circuit 210 is approximately equal in magnitude to the current that charges or discharges parasitic capacitor Cpar, thereby making the current through MP0 (or MP1) approximately equal to Iref1.

[0021] FIG. 3 shows a compensated current steering DAC 300 that is similar to compensated current steering DAC 200 but with additional details. The additional details include the implementation of an enable switch P_EN and a bias current source circuit Ibias. The enable switch P_EN is a PMOS transistor in this example, and couples between VDD and the PBIAS transistor. The signal to the gate of the enable switch P_EN is a signal called EN. The EN signal turns P_EN on and off. When P_EN is in the off state, the compensated current steering DAC 300 is disabled, and when P_EN is in the on state, the compensated current steering DAC 300 is enabled.

[0022] The bias current source circuit Ibias includes a current source 306 coupled to a current mirror formed by NMOS transistors M2 and M3. The current source 306 generates a current Ibias that flows through transistor M2. In one example, the current ratio of the current mirror is 1:1, so that the current through transistor M3 is also approximately Ibias, as shown in FIG.

[0023] The compensated current steering DAC described herein can be used as a standalone DAC or as part of a larger system such as an ADC. Examples of ADCs that may use the compensated current steering DAC described herein include sigma-delta ADCs, successive approximation register (SAR) ADCs, and pipeline ADCs. The current steering DAC described herein can also be used as part of a charge pump.

[0024] FIG. 4 shows an example implementation of a second-order (although the ADC can be of any order) sigma-delta modulator-based ADC 400. In the example of FIG. 4, the sigma-delta modulator-based ADC includes integrators 415 and 419, a comparator 420, and compensated current steering DACs 402 and 412. In one example, each of the compensated current steering DACs 402 and 412 is implemented as shown for the compensated current steering DACs 200 or 300 of FIG. 2 and FIG. 3. The compensated current steering DAC 412 includes PBIAS1 and PCAS1 transistors, which represent the transistors PBIAS and PCAS described above. Transistors MP0 and MP1 from FIG. 2 are also shown. A compensation circuit 410 within the current steering DAC 412 connects to terminals VA and VB as described above. In one example, the compensation circuit 410 is implemented as shown for the compensation circuit 210 of FIG. 2 or FIG. 3. Similarly, the compensated current steering DAC 402 includes transistors PBIAS2 and PCAS2 (connected together at terminal VB1), which represent the transistors PBIAS and PCAS described above. Transistors MP0 and MP1 of Figures 2 and 3 are shown as transistors MP2 and MP3, respectively, in DAC 402, with their sources connected together at terminal VA1. A compensation circuit 411 in the current steering DAC 402 connects to terminals VA1 and VB1 as described above. In one example, compensation circuit 411 is implemented as shown for compensation circuit 210 of Figures 2 or 3.

[0025] The analog input signal to the sigma-delta modulator-based ADC 400 is encoded as the voltage difference between the input voltages VINP and VTNM. The integrator 415 includes two resistor-capacitor pairs R41 / C41 and R42 / C42. The voltage VINP is provided to its respective resistor R41, and the voltage VINM is provided to its respective resistor R42. The resistors R41 are connected to their respective capacitors C41 at terminals 216 as shown, and the resistors R42 are connected to their respective capacitors C42 at terminals 417. The voltage on terminal 416 is labeled VAP (note that terminal 416 is also referred to as VAP terminal 416), and the voltage on terminal 417 is labeled VAM (note that terminal 417 is also referred to as VAM terminal 417). The drain of transistor MP2 of the compensated current steering DAC 402 is coupled to terminal VAP, and the drain of transistor MP3 of the compensated current steering DAC 402 is coupled to terminal VAM. In the case of compensated current steering DAC 402, the VAP terminal 416 and the VAM terminal 417 are the VP and VM terminals, respectively, of FIG.

[0026] The integrator 419 includes a transconductance amplifier (Gm) 418 and capacitors C43 and C44. The positive input of Gm 418 is coupled to resistor R41 and capacitor C41 at VAP terminal 416. The negative input of Gm 418 is coupled to resistor R42 and capacitor C42 at VAM terminal 417. In this example, resistors R41 and R42 have the same resistance and capacitors C41 and C42 have the same capacitance. Thus, the voltage on VAP terminal 416 is provided to the positive input of Gm 418 and the voltage on VAM terminal 417 is provided to the negative input of Gm 418. The positive output of Gm 418 is coupled to the positive input of comparator 420 at terminal 421 and the negative output of Gm 418 is coupled to the negative input of comparator 420 at terminal 422.

[0027] Capacitor C43 is coupled between terminal 422 and ground as shown. Similarly, capacitor C44 is coupled between terminal 421 and ground. In this example, capacitors C43 and C44 have the same capacitance. Current from Gm 418 and current from compensated current steering DAC 402 charge capacitors C44 and C43, thereby forming a differential voltage between VP terminal 421 and VM terminal 422. Comparator 420 outputs the digital signal Q and its logical inverse QZ mentioned above. Q is asserted high (and QZ is asserted low) by comparator 420 in response to the voltage on VP terminal 421 being higher than the voltage on VM terminal 422. Q is forced low (and QZ is forced high) by comparator 420 in response to the voltage on VP terminal 421 being lower than the voltage on VM terminal 422. 2. The Q signal is connected to the gates of transistors MP0 and MP2, and the QZ signal is connected to the gates of transistors MP1 and MP3. A clock signal (CLK) is used to cause comparator 420 to sample the inputs on VP terminal 421 and VM terminal 422. The drain of transistor MP0 of compensated current steering DAC 412 is connected to VP terminal 421, and the drain of transistor MP1 is connected to VM terminal 422. For compensated current steering DAC 412, VP terminal 421 and VM terminal 422 are the VP terminal and VM terminal of FIG. 2, respectively.

[0028] In response to the Q signal being low, the compensated current steering DACs 402 and 412 inject current into the VAP terminal 416 and the VP terminal 421, respectively, turning on transistors MP2 and MP0. Conversely, in response to the QZ signal being low, the compensated current steering DACs 402 and 412 inject current into the VAM terminal 417 and the VM terminal 422, respectively, turning on transistors MP3 and MP1. The compensation circuit 411 sources current to or sinks current from terminal VB1 in response to changes in the voltage on terminal VA1, as described above. Similarly, the compensation circuit 410 sources current to or sinks current from terminal VB in response to changes in the voltage on terminal VA.

[0029] The signal-to-noise ratio (SNR) of a current-steering DAC can be increased by including a compensation circuit (e.g., compensation circuit 210). Table 1 below shows the SNR of a sigma-delta ADC with a current-steering DAC without the compensation circuit described (e.g., current-steering DAC 100 of FIG. 1) and with the compensation circuit described (e.g., compensated current-steering DAC 200 (FIG. 2)). SNR values ​​are provided for various offset voltages. The offset voltage represents the change in voltage on the VA terminal during a data transition. At an offset of 0 mV, there is little or no difference in SNR between the two types of current-steering DACs. However, the SNR of the sigma-delta ADC with a compensated current-steering DAC is higher than that of the sigma-delta ADC with an uncompensated current-steering DAC for offset voltages of 20 mV, 40 mV, and 60 mV. For example, the SNR of a current steering DAC without compensation is 58 dB in the absence of an offset voltage, but decreases to 43.2 dB in the presence of a 40 mV offset, whereas by using a compensation circuit as described herein, the SNR is 55.5 dB at a 40 mV offset. JPEG2024511397000002.jpg58168

[0030] While the compensated current steering DACs of Figures 2 and 3 include PMOS transistors, the compensation circuits described herein can be used with NMOS transistor-based current steering DACs. Figure 5 shows a compensated current steering DAC 500 including NMOS transistors. The compensated current steering DAC 500 includes NMOS transistors MN0, MN1, NCAS, and NBIAS, and a compensation circuit 510. The compensation circuit 510 includes a transistor M51, a compensation capacitor Ccomp51, and a bias current circuit Ibias51 ("Ibias51" refers to both the bias current circuit and the current it generates). In this example, the transistor M51 is a PMOS transistor. The drain of the transistor M51 is coupled to ground, and the source of the transistor M51 is coupled to the compensation capacitor Ccomp51 and to the bias current source circuit Ibias51 at the terminal VC51. The drain current through the transistor M51 is designated as I_M51. The current through the compensation capacitor Ccomp is designated as I_comp51. The current through the parasitic capacitor Cpar is denoted as I_cpar51.

[0031] The gate of transistor M51 provides a first terminal 511 of compensation circuit 510. Compensation capacitor Ccomp51 provides a second terminal 512 of compensation circuit 210 (opposite the capacitor terminal coupled to the source of transistor M51). Compensation circuit terminal 511 is coupled to terminal VA51. Compensation circuit compensation capacitor Ccomp51 (and therefore terminal 512) is coupled to the junction between transistors NBIAS and NCAS (the terminal labeled VB51 in FIG. 5).

[0032] When the voltage on terminal VA51 increases, a current I_cpar51 (solid arrow) flows from terminal VA51 to parasitic capacitor Cpar, thereby charging parasitic capacitor Cpar. The increase in voltage on terminal VA51 also decreases Vgs of transistor M51. The decrease in Vgs of transistor M51 causes a decrease in the drain current (I_M51) through transistor M51. Because Ibias51 is a fixed current, as the current I_M51 decreases, the portion of Ibias51 that exceeds I_M51 flows through compensation capacitor Ccomp to terminal VB51 as current I_comp51 (solid arrow). Thus, when the voltage on terminal VA51 increases, current I_cpar51 flows from terminal VA51 to parasitic capacitor Cpar, and a current I_comp51 of approximately equal magnitude flows from compensation capacitor Ccomp to terminal VB51.

[0033] When the voltage on the terminal VA51 decreases, a current I_cpar flows (dashed arrow) from the parasitic capacitor Cpar to the terminal VA, thereby discharging the parasitic capacitor Cpar. The decrease in the voltage on the terminal VA51 also increases the Vgs of the transistor M51. The increase in the Vgs of the transistor M51 causes an increase in the current I_M51 through the transistor M51. When the current I_M51 increases beyond the magnitude of the fixed current Ibias51, the I_comp51 current (dashed arrow) flows from the terminal VB51 through the capacitor Ccomp51 to the terminal VC51 such that the sum of I_M51 and I_comp51 is approximately equal to Ibias51. Thus, when the voltage on the terminal VA51 decreases, a current I_cpar51 flows from the parasitic capacitor Cpar to the terminal VA51, and an approximately equal current I_comp51 flows from the terminal VB51 to the compensation capacitor Ccomp51.

[0034] As used herein, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A controls device B to generate signals to perform an action, (A) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via control signals generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0035] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. 1. A circuit comprising: a digital-to-analog converter (DAC) having a first terminal and a second terminal; a compensation circuit having a third terminal coupled to the first terminal and a fourth terminal coupled to the second terminal, providing a current to the first terminal in response to an increase in voltage on the second terminal; sinking current from said first terminal in response to a decrease in voltage on said second terminal; The compensation circuit is configured as follows: The circuit includes:

2. 2. The circuit of claim 1, The compensation circuit, a transistor having a gate coupled to the fourth terminal, a drain, and a source; a capacitor having a first terminal coupled to the source and a second terminal coupled to the third terminal; The circuit includes:

3. 3. The circuit of claim 2, The compensation circuit further comprises a current source circuit coupled to the source.

4. 4. A circuit as claimed in claim 3, The current source circuit is coupled between the source and one of a ground terminal or a supply voltage terminal.

5. 2. The circuit of claim 1, The circuit wherein the DAC is a current steering DAC.

6. 2. The circuit of claim 1, The circuit wherein the DAC is a current steering single bit DAC.

7. 7. A circuit according to claim 6, comprising: The DAC is A first transistor; a second transistor coupled to the first transistor at the second terminal; a third transistor configured to provide a bias current; a fourth transistor coupled at the first terminal to the third transistor and coupled at the second terminal to the first and second transistors; The circuit includes:

8. 1. A current steering digital to analog converter, comprising: A first transistor; A second transistor; and a bias current transistor having a first terminal; a third transistor coupled to the first terminal, the third transistor having a second terminal coupled to the first and second transistors; a compensation circuit having a third terminal coupled to the first terminal and a fourth terminal coupled to the second terminal, providing a current to the first terminal in response to an increase in voltage on the second terminal; sinking current from said first terminal in response to a decrease in voltage on said second terminal; The compensation circuit is configured as follows:

1. A current steering digital-to-analog converter comprising:

9. 9. A current steering digital-to-analog converter as claimed in claim 8, comprising: The compensation circuit, a metal-oxide-semiconductor field effect transistor (MOSFET) having a gate, a drain, and a source coupled to the fourth terminal; a capacitor having a first terminal coupled to the source and a second terminal coupled to the third terminal; 1. A current steering digital-to-analog converter comprising:

10. 10. A current steering digital to analog converter as claimed in claim 9, comprising: The compensation circuit further comprises a current circuit coupled to the source.

11. 11. A current steering digital to analog converter as claimed in claim 10, comprising: A current steering digital-to-analog converter, wherein the current source circuit is coupled between the source and one of a ground terminal or a supply voltage terminal.

12. 9. A current steering digital-to-analog converter as claimed in claim 8, comprising: The compensation circuit, A current source circuit; a capacitor having a first terminal coupled to the current source circuit and a second terminal coupled to the third terminal; 1. A current steering digital-to-analog converter comprising:

13. 9. A current steering digital-to-analog converter as claimed in claim 8, comprising: The current steering digital-to-analog converter, wherein the third transistor is a cascode transistor.

14. 1. A circuit comprising: a sigma-delta modulator based analog-to-digital converter (ADC) having a first ADC terminal and a second ADC terminal; a first digital-to-analog converter (DAC) having a first DAC terminal coupled to the first ADC terminal, a second DAC terminal coupled to the second ADC terminal, a third DAC terminal, and a fourth DAC terminal; a first compensation circuit having a first compensation circuit terminal coupled to the third DAC terminal and a second compensation circuit terminal coupled to the fourth DAC terminal, providing a current to the third DAC terminal in response to an increase in voltage on the fourth DAC terminal; sinking current from the third DAC terminal in response to a decrease in voltage on the fourth DAC terminal; The first compensation circuit is configured as follows: The circuit includes:

15. 15. The circuit of claim 14, The first compensation circuit comprises: a transistor having a gate coupled to the second compensation circuit terminal, a drain, and a source; a capacitor having a first terminal coupled to the source and a second terminal coupled to the first compensation network terminal; The circuit includes:

16. 15. The circuit of claim 14, The circuit, wherein the first compensation circuit further includes a current circuit coupled to the source.

17. 15. The circuit of claim 14, The circuit wherein the first DAC is a current steering DAC.

18. 15. The circuit of claim 14, The circuit wherein the first DAC is a current steering single bit DAC.

19. 15. The circuit of claim 14, a second DAC having a fifth DAC terminal coupled to a third ADC terminal of the sigma-delta modulator based ADC, a sixth DAC terminal coupled to a fourth ADC terminal of the sigma-delta modulator based ADC, a seventh DAC terminal, and an eighth DAC terminal; a second compensation circuit having a third compensation circuit terminal coupled to the seventh DAC terminal and a fourth compensation circuit terminal coupled to the eighth DAC terminal; The circuit further comprises:

20. 20. The circuit of claim 19, The second compensation circuit comprises: providing a current to the seventh DAC terminal in response to an increase in voltage on the eighth DAC terminal; sinking current from the seventh DAC terminal in response to a decrease in voltage on the eighth DAC terminal; The circuit is configured as follows.

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