Apparatus and method for implementing a scalable digital infrastructure for measuring ring oscillators - Patents.com

Abstract

An apparatus has a collection of ring oscillators. An instruction register block is configured to sequentially address and drive each ring oscillator in the collection of ring oscillators. A multiplexer has an input line connected to each ring oscillator in the collection of ring oscillators and an output line. A pulse counter is connected to the output line of the multiplexer for counting the number of oscillations of a selected ring oscillator within a selected time period and forming a multiple bit frequency count output signal. A data shift register receives the multiple bit frequency count output signal and generates a serial frequency count output signal.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 215,044, filed June 25, 2021, the contents of which are incorporated herein by reference.

[0002] The present invention relates generally to semiconductor wafer inspection, and more particularly to techniques for implementing a scalable digital infrastructure for measuring ring oscillators in a wafer scribe line. [Background technology]

[0003]

[0003] FIG. 1 shows a known semiconductor wafer test system including a test instrument 100 connected to a probe card 102 that makes connections to pads on a wafer 104. FIG. 2 shows a semiconductor wafer 104 having individual chips 200. The individual chips 200 form rows and columns of chips separated by scribe lines 202. Within the scribe lines 202 are test circuits 204. The test circuits 204 are used during wafer level testing. When testing is completed, a saw is used to cut the areas of the scribe lines to separate the individual chips for subsequent packaging. This cutting process destroys the test circuits 204 within the scribe lines. FIG. 3 shows a simple test circuit having a gate pad 300, a source pad 302, and a drain pad 304. A probe card needle 306 is connected to the drain pad 304.

[0004]

[0004] Figure 4 shows a prior art ring oscillator 400. The ring oscillator 400 has a logic NAND gate 402 operable as an enable stage followed by an odd number of inverters, in this case 404_1, 404_2, and 404_3, to generate an output Q. A feedback loop 406 returns the output signal to the enable stage 402. The output signal oscillates between a digital signal 1 (high) and a digital signal 0 (low). The frequency of the oscillation depends on the time delays of all the stages. The frequency of the ring oscillator is captured by the number of toggles between a digital signal high and a digital signal low during a predefined time frame.

[0005]

[0005] Ring oscillators are test circuits placed in the scribe lines 202 of a wafer 104 and / or in individual chips 200 of the wafer 104. Ring oscillators are used to gain insight into the power, performance, area, and yield of a manufacturing process. Performance correlates to the measured frequency. Power correlates to the measured current. Yield is evaluated by the statistical variation of many sampled ring oscillators. Summary of the Invention [Problem to be solved by the invention]

[0006]

[0006] A single ring oscillator cannot cover all process variation sources, nor can it be possible to isolate the variation sources from a single ring oscillator, or even from a small set of ring oscillators. Instead, dozens of ring oscillators are required that vary incrementally over a large set of dimensions. Such an infrastructure needs to be fast, robust to extreme process variations, and generate reliable data. The disclosure herein addresses these issues. [Means for solving the problem]

[0007]

[0007] An apparatus has a collection of ring oscillators. An instruction register block is configured to sequentially address and drive each ring oscillator in the collection of ring oscillators. A multiplexer has an input line connected to each ring oscillator in the collection of ring oscillators and an output line. A pulse counter is connected to the output line of the multiplexer and counts the number of oscillations of a selected ring oscillator within a selected time period and forms a multiple bit frequency count output signal. A data shift register receives the multiple bit frequency count output signal and generates a serial frequency count output signal.

[0008]

[0008] The present invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 illustrates a semiconductor wafer testing system as known in the prior art. [Diagram 2]

[0010] FIG. 1 illustrates a prior art semiconductor wafer having scribe lines that host test circuitry. [Diagram 3]

[0011] FIG. 1 illustrates a prior art test circuit and associated probe card needle. [Figure 4]

[0012] FIG. 1 illustrates a prior art ring oscillator. [Diagram 5]

[0013] FIG. 2 illustrates a ring oscillator strand constructed in accordance with one embodiment of the present invention. [Figure 6]

[0014] This is a simplified characterization of the strand. [Figure 7]

[0015] FIG. 2 illustrates a hierarchy of strands configured in accordance with one embodiment of the present invention. [Figure 8]

[0016] FIG. 2 illustrates processing operations associated with a strand configured in accordance with one embodiment of the present invention. [Figure 9]

[0017] FIG. 2 illustrates signals associated with one embodiment of a synchronization strand. [Figure 10]

[0018] FIG. 2 illustrates a synchronous strand chain configured in accordance with one embodiment of the present invention. [Figure 11]

[0019] FIG. 2 illustrates a synchronization strand configured in accordance with one embodiment of the present invention. [Figure 12]

[0020] FIG. 2 illustrates a synchronous instruction register configured in accordance with one embodiment of the present invention. [Figure 13]

[0021] FIG. 2 illustrates a bank of synchronous ring oscillators configured in accordance with one embodiment of the present invention. [Figure 14]

[0022] FIG. 14 illustrates waveforms associated with the circuit of FIG. 13. [Figure 15]

[0023] FIG. 2 illustrates a synchronous balanced AND (BAND) tree multiplexer configured in accordance with one embodiment of the present invention. [Figure 16]

[0024] FIG. 2 illustrates a BAND cell configured in accordance with one embodiment of the present invention. [Figure 17]

[0025] FIG. 2 illustrates a balanced input tree configured in accordance with one embodiment of the present invention. [Figure 18]

[0026] FIG. 2 illustrates a pulse counter constructed in accordance with one embodiment of the present invention. [Figure 19]

[0027] FIG. 2 illustrates a division by two circuits used in accordance with one embodiment of the present invention. [Figure 20]

[0028] FIG. 13 illustrates another division by two circuits used in accordance with one embodiment of the present invention. [Figure 21]

[0029] FIG. 2 illustrates a sticky bit circuit used in accordance with one embodiment of the present invention. [Figure 22]

[0030] FIG. 2 illustrates a synchronous data register used in accordance with one embodiment of the present invention. [Figure 23]

[0031] FIG. 2 illustrates an asynchronous strand configured in accordance with one embodiment of the present invention. [Figure 24]

[0032] FIG. 2 illustrates an asynchronous chain used in accordance with one embodiment of the present invention. [Diagram 25]

[0033] FIG. 2 is an asynchronous chain timing diagram characterizing the operation of one embodiment of the present invention. [Figure 26]

[0034] FIG. 2 illustrates an asynchronous processing operation used in accordance with one embodiment of the present invention. [Figure 27]

[0035] FIG. 2 illustrates an asynchronous ring oscillator bank configured in accordance with one embodiment of the present invention. [Figure 28]

[0036] FIG. 1 is an asynchronous ring oscillator bank timing diagram. [Figure 29]

[0037] FIG. 2 illustrates an asynchronous AND tree constructed in accordance with one embodiment of the present invention. [Diagram 30]

[0038] FIG. 2 illustrates an asynchronous instruction register used in accordance with one embodiment of the present invention. [Diagram 31]

[0039] 1 is an asynchronous pulse counter constructed in accordance with one embodiment of the present invention. [Diagram 32]

[0040] 3 is a delay chain used in accordance with one embodiment of the present invention. [Diagram 33]

[0041] 1 is a Muller-C module circuit used in accordance with one embodiment of the present invention. [Diagram 34]

[0042] 2 is an asynchronous data register used in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010]

[0043] Like reference numerals refer to corresponding parts throughout the several views of the drawings.

[0011]

[0044] 5 shows the basic architecture for what is referred to herein as a strand. Both asynchronous and synchronous embodiments of the invention have the same functional blocks that form a strand 500.

[0012]

[0045] Block 502 is S A is an instruction register that serves to configure the system for testing by selecting the ring oscillator (RO) or input of interest via N is the total number of all selectable options.

[0013]

[0046] Block 504 is a bank of ROs. The bank of ROs may include other reference inputs, such as a reference oscillator (REF_OSC), which is selected via a select line S.

[0014]

[0047] Block 506 is a multiplexer (or MUX) that combines the output signals from each RO into a single output. Since only one RO is driven and vibrating at a time, that vibration is the only vibration that appears on the output line (right side) of block 506, which is then provided to block 508.

[0015]

[0048] Block 508 is a pulse counter (or frequency counter). This block counts the number of oscillations that occur within a fixed period of time called the integration window. This count is therefore proportional to the frequency (or speed of the driven RO).

[0016]

[0049] Block 510 is a data shift register that manages the flow of measurement data to a computer located off-chip, such as test instrument 100 .

[0017]

[0050] FIG. 6 is a simplified characterization of a strand 500 having m inputs and m outputs. FIG. 7 shows a hierarchy of strands 500_1-500_N. A chain of strands in FIG. 7 is possible because inputs and outputs of a strand width m can be connected through physical design (PD) as well as when strands are tiled together logically. In the case where there are multiple strands connected to create a strand chain, the chain has operation similar to a single strand but allows for simultaneous operation and measurement. The operation is similar except that the ROs in each of the strands can be measured simultaneously. The functional behavior change to the instruction register initialization step is to shift in a logic "1" into the first RO position in each strand. The remainder of the operation is the same as a single strand as the ROs in each strand are selected, operated on, and measured, but this occurs in parallel within the chain. Data is then serially shifted out for all selected test structures.

[0018]

[0051] 8 illustrates a standard RO data acquisition operation. First, the system is reset (800). Then, a digital signal "1" is shifted into the first bit of the command register of block 502 to select the first RO (802). A pulse signal Φ is applied to the command shift register of block 502 to start the oscillation on the selected RO (804). The same signal is toggled to stop the RO oscillation (806). Data is latched (808). For example, data from the pulse counter of block 508 is latched into the shift register of block 510. Then, the D OUTN bits of data are shifted out (810) to form a signal. The pulse counter of block 508 is then reset (812). A zero is shifted into the instruction register of block 502 (814). It is then determined whether to test another RO (816). If so (816-Yes), a digital signal 0 is shifted into the shift register (820). This causes the next RO to be addressed as the initial digital signal 1 propagates. Blocks 804-816 are repeated until testing is completed (816-No).

[0019]

[0052] 9 illustrates signals associated with one embodiment of a synchronous strand. A synchronous strand is a self-contained block for selecting, executing, and measuring the frequency of any number of ROs. As shown in FIG. 5, synchronous strand 500 includes an instruction register in block 502 and test structures RO0-RO1 in block 504. N-1 The method comprises a bank of ROs, a counter in block 508, and a data register in block 510. One RO is measured at a time and data control integrity is achieved through non-overlapping clocks. The non-overlapping clocks in the shift registers improve robustness to handle variations. Scalability is achieved through a serial interface that allows tiling one or many devices. The approach also includes methods for ensuring data integrity and validity, such as scan integrity, for the command and data registers and reference oscillators used to test and verify the counter circuits at speed and the selection circuits.

[0020]

[0053] Figure 10 shows a chain of synchronous strands. A chain or a single strand is a fully functioning complex for selecting and measuring ROs, either of which is suitable for top-level design, and therefore any number of homogeneous or heterogeneous strands can be connected together to form a chain. If M strands are connected together, the resulting chain can measure M ROs simultaneously. From the point of view of the physical interface, the strands and the chain have identical input and output signals, which allows tiling.

[0021]

[0054] The advantage of this architecture is that the physical implementation can be arranged as tiles and the architecture scales linearly with the number of ROs.

[0022]

[0055] Figure 11 maps the signals of Figures 9 and 10 to the different strand blocks of one strand. The instruction register block 1102 is a clocked FIFO that implements a 1-to-N deserializer. The instruction register block shift registers use the non-overlapping clocks iclk0 and iclk1. INSTR is a 1-bit serial data input, and INSTR is a 1-bit serial data input. out is a 1-bit serial data output. The SEL bus is an N-bit wide output representing the total number of ROs and test structures (equivalent to the FIFO depth).

[0023]

[0056] The RO bank block 1104 contains ROs and possibly other test and validation structures. The SEL bus is an N-bit wide input representing the total number of ROs and test structures (equivalent to the FIFO depth). The signal Φ is a rising trigger event that alternates control between starting and stopping the RO oscillation to create an integration time window. ref is an input signal from an optional external reference oscillator. The OSC signal is a selected RO output, either from an explicit RO or a reference oscillator signal. Φ out and ref outare the buffered outputs of Φ and ref, respectively.

[0024]

[0057] The balanced AND (BAND) tree block 1106 selects the OSC for input into the COUNTER block 508. i Signal OSC OUT This structure is logically just an AND, but the optimal architecture would be one with a BAND structure, or ideally a balanced input tree (bit) structure.

[0025]

[0058] The counter block 1108 is an asynchronous counter designed from DIV2 cells. This counter is an (M-1) bit counter that increments every OSC pulse, where bit M is the last data bit and is a sticky bit for overflow detection. The DONE signal indicates that the counter has finished counting. The RST signal is an event returned from the data register indicating that data has been captured and telling the counter to reset.

[0026]

[0059] The data shift register block 1110 receives the DATA M It takes a signal and creates a means to shift data out through a shift register. The data shift register has non-overlapping clocks dclk0 and dclk1. This block is a synchronous FIFO that implements an M-to-1 serializer. DATA is the input data, and DATA OUT is the output data that allows this block to be chained.

[0027]

[0060] Figure 12 shows the synchronization command register 1200. The purpose of the command register is to select the RO of interest by taking the serial stream, making it parallel, and implementing a serial-to-parallel deserializer. This register can be implemented with any selection of latch blocks L. The total number of bits is N+1 bits to select between N ROs and the reference oscillator input.

[0028]

[0061] FIG. 13 illustrates a synchronous RO bank according to one embodiment of the present invention. FIG. 14 illustrates a signal timing example that demonstrates the operation of the circuit of FIG. 13. The signal Φ represents the integration time window over time (τ0 and τ in FIG. 14). θ Φ is a rising edge trigger event that alternates control between starting the RO oscillation and stopping the RO oscillation to create a selection control line S for the structure of interest i. i Therefore, OSC0 passes the oscillatory output to the OSC line based on τ0 and τ θ , and OSC1 is shown oscillating during another cycle while S1 is enabled. The rising edge of signal Φ turns the oscillation on, and the later rising edge of Φ turns it off. This dual rising behavior ensures a consistent oscillation time window even in the presence of uncertain on-chip delays, because this latency is present in the turn-on and turn-off rising signals and is therefore cancelled out.

[0029]

[0062] FIG. 15 shows a balanced AND (BAND) tree operating with matching rise and fall delays. As the number of ROs increases, the oscillator signal must pass through more BAND cells. If the rise and fall delays of the oscillator signal are unbalanced, the signal may be corrupted. Balancing the rise and fall delays in the BAND cells avoids this signal corruption.

[0030]

[0063] This BAND tree MUX differs from the asynchronous implementation in that it does not include an event signal path to monitor the propagation delay through the BAND tree. The Balanced Input Tree (BIT) of Figure 17 can be used for a balanced AND tree, but a select line must also be passed. A balanced AND tree, when created from a BAND block, requires the disable RO to have a logic "1" output; the BIT structure does not require this behavior since a select line is also included.

[0031]

[0064] 16 illustrates a balanced AND cell that can be used in accordance with one embodiment of the present invention. The output F is the logical AND function of inputs A and B. Unlike conventional AND cells, this circuit has symmetric rise and fall times.

[0032]

[0065] The Balanced Input Tree (BIT) of Figure 17 is an improved version of the BAND of Figure 15. The BAND structure balances any offsets in the strengths of the NMOS and PMOS transistors in the AND cells, but does not balance any offsets in the wire interconnects. The BIT of Figure 17 balances both wire-induced and transistor-induced offsets.

[0033]

[0066] Figure 18 shows a pulse counter. The pulse counter is built from a ripple counter of "divide-by-2" (DIV2) cells along with a sticky bit cell to mark the overflow condition. In this counter, there is no clock in the state machine, so the counter is self-clocked. IN With each pulse above the value of D[0:N-1] is incremented and the bits in D[N] implement overflow detection.

[0034]

[0067] Figures 19 and 20 show two possible implementations of a divide-by-2 circuit. These circuits implement the divide-by-2 with D flip-flops. OUT toggles every other IN toggle, so that the OUT frequency is exactly half the IN frequency.

[0035]

[0068] Figure 21 shows a possible implementation of the sticky bit module of Figure 18. This module retains its state until it is reset via the RST signal. A feature of this circuit is that when S goes high, Q remains high at logic "1" until it is reset by the RST signal, which clears the state. Upon reset, the Q signal returns to a low state at logic "0".

[0036]

[0069] Figure 22 shows a synchronous data register that implements a serializer that takes parallel counter data and forms a serial bit stream. The register is built from transparent latches L, two consecutive latches with alternating non-overlapping clocks dclk0 and dclk1 form a flip-flop. The flip-flop chain is M bits long to form a shift register that is the width of the asynchronous counter data. Each bit of the shift register also contains a MUX to switch the shift register from sample mode to shift mode, and data from the counter is loaded into the shift register.

[0037]

[0070] FIG. 23 shows an embodiment of an asynchronous strand. The asynchronous strand is an independent block for selecting, executing, and measuring the frequency of any number of ROs. The asynchronous strand comprises an instruction register block 2302, a bank of test structures block 2304, an AND tree block 2306, a counter block 2308, and a data register block 2310. The advantage of the asynchronous implementation is that one or more ROs are measured simultaneously. The asynchronous control circuitry improves reliability and reduces test time, especially under extreme process and voltage variations. Scalability is achieved through a serial interface that allows tiling one or many devices. The approach also includes a method for ensuring data accuracy, such as scan integrity, for the instruction and data registers and reference oscillators used to test and verify the high-speed counter and selection circuits.

[0038]

[0071] The command register block 2304 is an asynchronous first-in-first-out (FIFO) that implements a 1-to-N deserializer. For the input boundaries, R0, I0, and A0 are the input request signal, the input data signal, and the input acknowledge signal, respectively. For the output boundaries, R N , I N , A Nare the output request signal, the output data signal, and the input confirm signal, respectively. The SEL bus is an N-bit wide output that represents the total number of ROs and test structures (which is equivalent to the depth of the FIFO).

[0039]

[0072] The RO bank block 2304 contains ROs and possibly other test and validation structures. The SEL bus is an N-bit wide input representing the total number of ROs and test structures (equivalent to the FIFO depth). The signal Φ is a rising edge trigger event that alternates control between starting and stopping the RO oscillation to create an integration time window. ref is the input signal from an external reference oscillator. The OSC signal is the selected RO output, either from an explicit RO or a reference oscillator signal. Φ out and ref out are the buffered outputs of Φ and ref, respectively. C is an event timing signal that reflects the oscillation time window and is shifted with a delay, thereby ultimately used to signal the counter that no more pulses are coming from the selected RO.

[0040]

[0073] The AND tree block 2306 compares the selected OSC for input into the COUNTER block 2308. i Signal OSC OUT This structure is a logical AND, but the optimal architecture would involve a BAND structure, or ideally a BIT. This block also contains an event signal path to capture the worst case delay of the AND tree, which is passed to the counter block as R.

[0041]

[0074] The counter block 2308 is an asynchronous counter. It is an (M-1) bit counter that increments every OSC pulse, with bit M being the last data bit and a sticky bit for overflow detection. R is an input event signal whose delay is longer than the OSC path. The DONE signal indicates that the counter has finished counting. The RST signal is an event returned from the data register indicating that data has been captured and telling the counter to reset.

[0042]

[0075] The data shift register block 2310 receives the DATA M It creates a means to take the signal and shift out the data through the asynchronous shift register. This block is an asynchronous FIFO that implements an M-to-1 serializer. For the input boundaries, S0, D0, and B0 are the input request signal, the input data signal, and the input acknowledge signal, respectively. For the output boundaries, S M , D M , B M are an output request signal, an output data signal, and an input confirmation signal, respectively.

[0043]

[0076] FIG. 24 shows a chain of asynchronous strands. FIG. 25 shows the signal timing associated with the circuit of FIG. 24. Chains and single strands are fully functional blocks for selecting and measuring ROs. Both are suitable for top-level design, so any number of homogeneous or heterogeneous strands can be connected together to form a chain. If M strands are connected together, the resulting chain can measure M ROs simultaneously. From a physical interface point of view, strands and chains have identical input and output signals, which allows tiling.

[0044]

[0077] Figure 25 is an example of asynchronous timing for four bits. Lines 11, 12, 19, 21, 23, 25, 29, 36, 38, 40, and 42 are externally controlled signals, while lines 10, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30, 31, 32, 33, 34, 35, 37, 39, 41, and 43 are internally generated control signals. The circuit is driven by edge trigger events. The timing diagram is referenced from the boundary, so that the address "1" on I0 is explicit for the initial shift, but internal for the following shifts, so that a logic "0" should be presented on I0 for each RO after the first one. A flow chart for the test behavior is presented in Figure 26. The test is performed by shifting a single logic "1" into the instruction register to select the first RO. The signal Φ is then toggled and then toggled again. The time difference between the rising edges of Φ is the integration window. DONE is an event signal that is guaranteed to be slower than the settling time of the counter to indicate that data is ready to be latched into the data register. After DONE is asserted, S M The above event is asserted and D M The data bits on the B M D M Indicates that the above data is valid. S M and B. M Cycling, all data is D M This continues until the instruction register is read via .The instruction register is then clocked to select the next RO.

[0045]

[0078] 26 illustrates the processing operations associated with an asynchronous chain configured in accordance with one embodiment of the present invention. Initially, I0 is set to a digital signal "1" (2600). Then, an event is set on R0 for the instruction register (2602). An acknowledge signal A0 from the instruction register is waited for (2604). Decision block 2606 loops back to block 2604 until the signal is received. Then, Φ is pulsed to a digital signal "1" (2608). An integration window occurs (2610) until Φ is pulsed again (2612). Then, there is a wait for the event DONE signal (2614). Decision block 2616 loops back to block 2614 until the signal is received. Then, the event S M Set above (2618). B M Blocks 2620 and 2622 operate as a loop until an even is received. Then, the bit is D M When all bits are read, the event is M If additional ROs need to be tested (2620--YES), control returns to block 2602.

[0046]

[0079] Figure 27 shows an asynchronous RO bank. Figure 28 is a timing diagram for the signals associated with the circuit of Figure 27. Signal Φ is a rising edge trigger event that alternates control between starting and stopping the RO oscillation to create an integration time window. The Φ signal causes the RO or reference oscillator to select control line S for structure i of interest. iBased on the OSC signal, the RO passes an oscillation output to the OSC line. The rising edge of the Φ signal enables the RO oscillation, and the later rising edge of the Φ signal turns it off. This double rising edge behavior ensures a consistent oscillation time window even assuming uncertain on-chip delays, since this latency is present in the turn-on and turn-off rising edges and is therefore cancelled out. The delay cell needs to be longer than the longest loop time of any RO to generate a signal C, which is used to determine when the counter has stabilized. Alternatively, C can be generated by a delay from each OSC output.

[0047]

[0080] Figure 28 shows the relationship between τ0 and τ θ The timing diagram shows the integration time window between the time when the RO passes the oscillatory output to the OSC line, as shown on OSC0 and OSC1. The Φ signal causes RO to pass the oscillatory output to the OSC line, as shown on OSC0 and OSC1. The delay signal C represents the delay of the signal Φ through the delay line. This delay is shown as C in the timing diagram. t is shown as:

[0048]

[0081] Figure 29 shows an asynchronous logic AND tree. A balanced AND tree works by having matching delay paths between oscillators. This tree also requires a completion element. The characteristic of this component is that the delay element between C and R is equal to the delay from any OSC to OSC OUT The main requirement is that the delay must be longer than the worst-case propagation delay to the OSC. The overall structure is an N+1 input AND tree implemented as a distributed hierarchy of 2-input BAND gates. This structure performs the function of passively multiplexing the RO outputs. Only the selected RO will propagate an oscillation signal to one of the inputs of the AND tree, and this oscillation will be propagated to the OSC. OUTThe unselected RO asserts a logic level high so as not to block the oscillation of the selected RO. BIT can be used for balanced AND trees, but the select line must be passed. Balanced AND trees, when created from BAND blocks, require the disabled RO to have a logic "1" output, and the BIT structure does not require this behavior since the select line is also included.

[0049]

[0082] Figure 30 shows the asynchronous command register. The asynchronous command register is constructed from asynchronous flip-flops (AFFs). The purpose of the command register is to select the RO or reference structure of interest by taking the serial stream, making it parallel, and implementing a serial-to-parallel deserializer. The AFF is a 1-bit basic building block of an asynchronous FIFO, where data is bundled asynchronously by design, using a request signal R and an acknowledge signal A as a method of handshaking. There are N+1 total bits to select between N ROs and the reference oscillator inputs.

[0050]

[0083] Figure 31 shows an asynchronous pulse counter. The asynchronous counter is built from DIV2 cells along with a sticky bit cell to mark the overflow condition. Asynchronous refers to the absence of a clock within the state machine and that the counter is self-clocked. OSC IN Each pulse on increments the value of D[0:N-1], and the bit in D[N] implements the overflow detection. The delay block in Figure 32 implements the event signal generation for the full bundle data asynchronous control protocol of the asynchronous sensor array. When multiple strands are connected together to form a chain, DONE IN is used. All counters should be stable before shifting out data.

[0051]

[0084] 33 shows a Muller-C module represented by an AND cell with a "C". This circuit is used to perform a special AND function on edge event signals as shown in the logic truth table below.

[0052] [Table 1] Unlike a conventional AND cell, the state is preserved when the inputs are different.

[0053]

[0085] Figure 34 shows an asynchronous data register. The data register is built from asynchronous flip-flops AFF. The purpose of the data register is to load data from the pulse counter and create a parallel-to-serial serializer. The AFF is the basic building block of a register with a depth M that matches the width M of the pulse counter. Data is loaded from the counter using a MUX enabled by a load signal L. A bit from counter i is fed to line Db i The data is bundled asynchronously by design for serial output, using a request signal S and a acknowledge signal B as a method of handshaking.

[0054]

[0086] The above description, for purposes of explanation, used specific terms to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that specific details are not required to practice the present invention. Thus, the above description of specific embodiments of the present invention is presented for purposes of illustration and description. The above description is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, so that others skilled in the art can best utilize the invention and various embodiments as adapted to the particular use contemplated. It is intended that the following claims and their equivalents define the scope of the invention.

Claims

1. A set of ring oscillators, an input line configured to input serialized data, and a plurality of output lines connected to respective ring oscillators, configured to output an address as a parallel output signal configured to drive one ring oscillator within the set of ring oscillators, a command register block comprising: a multiplexer comprising a plurality of input lines respectively connected to output lines of each ring oscillator within the set of ring oscillators, the multiplexer configured to connect any one of the ring oscillators to an output line of the multiplexer; a pulse counter connected to the output line of the multiplexer, configured to count the frequency of a selected ring oscillator within a predetermined time frame and form a plurality of bit frequency count output signals; a data shift register configured to receive the plurality of bit frequency count output signals and generate a serial frequency count output signal An apparatus comprising.

2. The apparatus according to claim 1, having a uniform set of input nodes and output nodes forming a ring oscillator strand.

3. The apparatus according to claim 2, connected to a plurality of equally configured ring oscillator strands.

4. The apparatus according to claim 2, wherein the input nodes include an instruction clock node, an instruction signal node, a rising trigger signal node, a reference signal node, a reset signal node, a data clock signal node, a latch signal node, and a data signal node.

5. The apparatus according to claim 2, wherein the output nodes include an instruction clock node, an instruction signal node, a rising trigger signal node, a reference signal node, a reset signal node, a data clock signal node, a latch signal node, and a data signal node.

6. The apparatus according to claim 2, wherein the input nodes include an input request signal node, an input data signal node, an input confirmation signal node, an instruction signal node, a rising trigger signal node, a reference signal node, a done signal node, and a reset signal node.

7. The apparatus according to claim 2, wherein the output nodes include an input request signal node, an input data signal node, an input confirmation signal node, an instruction signal node, a rising trigger signal node, a reference signal node, a done signal node, and a reset signal node.

8. The apparatus according to claim 1, wherein the command register block implements a serial-to-parallel deserializator in response to a clock signal.

9. The apparatus according to claim 1, wherein the set of ring oscillators responds to a rising trigger signal that establishes each selected time frame.

10. The apparatus according to claim 1, wherein the multiplexer is a synchronous balanced logic AND tree.

11. The apparatus according to claim 1, wherein the multiplexer is a balanced input tree.

12. A set of ring oscillators, A command register block configured to sequentially address and drive each ring oscillator within the set of ring oscillators, A multiplexer having input lines and output lines connected to each ring oscillator within the set of ring oscillators, A pulse counter connected to the output line of the multiplexer, counting the frequency of a selected ring oscillator within a selected time frame and forming a plurality of bit frequency count output signals, A data shift register that receives the plurality of bit frequency count output signals and generates a serial frequency count output signal comprising The apparatus, wherein the pulse counter comprises clocked divide-by-2 cells serially connected with sticky bit cells to identify overflow conditions.

13. The apparatus according to claim 1, wherein the data shift register comprises serially connected latches responsive to alternating and non-overlapping clock signals.

14. The apparatus according to claim 1, wherein the command register block implements a serial-to-parallel deserializator in response to an input request signal, an input data signal, and an input confirmation signal.

15. The apparatus according to claim 1, wherein the data shift register responds to an input request signal, an input data signal, and an input confirmation signal.

16. The apparatus according to claim 1, wherein the command register block implements a serial-to-parallel deserializator using asynchronous flip-flops.

17. A set of ring oscillators, A command register block configured to sequentially address and drive each ring oscillator within the set of ring oscillators, A multiplexer having input lines and output lines connected to each ring oscillator within the set of ring oscillators, A pulse counter connected to the output line of the multiplexer, counting the frequency of the selected ring oscillator within the selected time frame and forming a plurality of bit frequency count output signals; A data shift register receiving the plurality of bit frequency count output signals and generating a serial frequency count output signal; Comprising; The apparatus, wherein the pulse counter comprises a self-clocked divide-by-2 cell serially connected with a sticky bit cell to identify an overflow condition.

18. The apparatus according to claim 1, wherein the data shift register comprises an asynchronously connected flip-flop connected serially.

19. The apparatus according to claim 12, having a uniform set of output nodes and input nodes forming a ring oscillator strand.

20. The apparatus according to claim 17, having a uniform set of output nodes and input nodes forming a ring oscillator strand.

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