Apparatus and method for setting a precise voltage on a test circuit - Patents.com

Abstract

The apparatus has a semiconductor wafer hosting rows and columns of chips, the rows and columns of chips being separated by scribe lines. Selection circuits are disposed within the scribe lines. The selection circuits are connected to test circuits within the scribe lines. The selection circuits operate to enable voltage control at a single test circuit while disabling all other test circuits.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 215,050, filed June 25, 2021, the contents of which are incorporated herein by reference.

[0002]

[0002] The present invention relates generally to testing semiconductor wafers, and more particularly to setting precise voltages on test circuits. [Background technology]

[0003] FIG. 1 shows a known semiconductor wafer testing system that includes a test instrument 100 connected to a probe card 102 that makes connections to pads on a wafer 104. FIG. 2 shows a semiconductor wafer 104 with individual chips 200. The individual chips 200 form rows and columns of chips that are separated by scribe lines 202. Within the scribe lines 202 are test circuits 204. The test circuits 204 are used during wafer level testing. When testing is complete, a saw is used at the scribe lines to separate the individual chips for subsequent packaging. This cutting process destroys the test circuits 204 within the scribe lines. FIG. 3 shows a simple test circuit with a gate pad 300, a source pad 302, and a drain pad 304. A probe card needle 306 is connected to the drain pad 304.

[0004] 4 shows a test instrument 100 with source measurement units SMU1 and SMU2. The SMU voltage is connected through wire connections from the instrument cable, the probe tip, the probe pad, and the on-chip metal route to the intended circuit, shown here as resistor R9. It should be understood that the test circuit can be of any complexity.

[0005]

[0005] Current flows from the SMU to the test circuit, which means that the voltage at resistor R9 drops from the SMU voltage. Resistors R1-R8 are not well controlled. Resistors R1, R2, R3, R4, R5, and R6 represent parasitic resistances in the cable, probe card, probe tip, and / or probe pad. Resistors R7 and R8 represent parasitic resistances from on-chip wire routes.

[0006]

[0006] Each SMU includes two connections, a "force" connection and a "sense" connection. In this case, a target voltage is applied through the force terminal of the SMU. Current from the force terminal flows through R1, which creates a voltage drop (called the "IR voltage" drop) equal to the resistance of R1 multiplied by the value of the current. Due to the IR voltage drop, the voltage at node N1 is different from the voltage applied at the SMU. The sense terminal of the SMU measures the voltage. The current through the sense terminal is designed to be very low so that the IR voltage drop through R2 is negligible. The SMU compares the sense voltage with the intended target voltage and raises the force voltage to obtain the target voltage at the "Kelvin node" N1. The Kelvin nodes N1 and N2, where the force and sense terminals meet, may typically be located on a cable bond, or a probe card, or a probe pad, or a chip 104.

[0007]

[0007] Figure 5 shows a prior art system having a test instrument 100 and a wafer 104 having multiple test circuits 1-N. All of the test circuits in the array share a common Vdd and / or Vss for efficient pad utilization. Each test circuit is digitally addressable, whereby only one circuit is enabled and the remaining circuits are disabled. The current drawn from the common Vdd and Vss pads is several orders of magnitude higher for the enabled circuits compared to any of the disabled circuits. This means that the current measured with the SMU is nearly identical to the current drawn for the enabled circuits. This has two problems.

[0008]

[0008] First, when the array of test circuits is large, the leakage current from disabled circuits may be large enough to cause significant errors in the current measurements for enabled circuits. Second, it is desirable to measure the leakage current on individual test circuits. In this case, all circuits are disabled and the current measurement is the combined leakage for all of the test circuits. There is no ability to measure the leakage current on each test circuit. Summary of the Invention [Problem to be solved by the invention]

[0009]

[0009] Therefore, there is a need for improved power management of test circuits in wafer scribe lines. [Means for solving the problem]

[0010]

[0010] An apparatus has a semiconductor wafer hosting rows and columns of chips, the rows and columns of chips being separated by scribe lines. Selection circuits are disposed within the scribe lines. The selection circuits are connected to test circuits within the scribe lines. The selection circuits operate to enable voltage control at a single test circuit while disabling all other test circuits.

[0011]

[0011] The present invention will be more fully understood in conjunction with the following detailed description taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 illustrates a semiconductor wafer testing system as known in the prior art. [Diagram 2]

[0013] FIG. 1 illustrates a prior art semiconductor wafer having scribe lines that host test circuitry. [Diagram 3]

[0014] FIG. 1 illustrates a prior art test circuit and associated probe card needle. [Figure 4]

[0015] FIG. 1 illustrates a prior art resistor network associated with a test circuit. [Diagram 5]

[0016] FIG. 1 shows prior art test equipment and test circuits on a wafer. [Figure 6]

[0017] FIG. 2 illustrates a wafer having test circuit selection circuitry in accordance with one embodiment of the present invention. [Figure 7]

[0018] FIG. 2 illustrates a wafer having header switch selection circuitry in accordance with one embodiment of the present invention. [Figure 8]

[0019] FIG. 2 illustrates a wafer having a footer switch selection circuit, according to one embodiment of the present invention. [Figure 9]

[0020] FIG. 2 illustrates a selection circuit used in accordance with one embodiment of the present invention. [Figure 10]

[0021] FIG. 2 illustrates a selection circuit used in accordance with one embodiment of the present invention. [Figure 11]

[0022] FIG. 2 illustrates a selection circuit used in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013]

[0023] Like reference numerals refer to corresponding parts throughout the several views of the drawings.

[0014]

[0024] 6 shows a header switch 600 inserted between the SMU power supply and each test circuit. In the case where the test circuit is a digital circuit such as a ring oscillator, the header switch controls the Vdd power supply and the footer switch 602 controls the Vss power supply.

[0015]

[0025] Each test circuit in the addressable array has its own header switch and its own footer switch. A digital select line 604 is connected from the external pad connection to each header and footer switch. The digital addressing is such that only one circuit can be selected at a time (value "1"). The digital select values ​​for all remaining test circuits are set to "0". As an example, a digital select signal can be initiated on the test instrument 100 and then applied by a probe pin to a digital select pad.

[0016]

[0026] The SMU connections for the power supplies are common across all header and footer switches, as indicated by the node labeling in the diagram. In this example, there are four SMUs, SMU1, SMU2, SMU3, and SMU4, with force and sense lines N1F, N1S, N2F, N2S, N3F, N3S, N4F, and N4S, respectively. These force and sense line nodes have connections to a header switch 600 and a footer switch 602, as shown in Figure 6. In this embodiment, the header switch 600 is connected to nodes N1F, N1S, N2F, N2S, and the footer switch 602 is connected to nodes N3F, N3S, N4F, NFS.

[0017]

[0027] The use of both header and footer switches allows the elimination or reduction of IR voltage drops on both power rails.

[0018]

[0028] One embodiment of the present invention uses only a header switch 600, as shown in FIG.

[0019]

[0029] The Kelvin node 700 for Vss (where force and sense for SMU3 meet) is shown in this figure as being on chip 104. This Kelvin node could occur elsewhere along the SMU power line (e.g., off-chip). An advantage of the implementation of Figure 7 is reduced complexity.

[0020]

[0030] FIG. 8 illustrates one embodiment of the present invention that uses only the footer switch 602.

[0021]

[0031] The Kelvin node 800 for Vdd (where the force and sense for SMU1 contact) is shown in this diagram as being on chip. This Kelvin node could occur elsewhere along the SMU power line (e.g., off chip). The advantage of this implementation is reduced complexity.

[0022]

[0032] FIG. 9 shows one implementation of the header switch 600 and footer switch 602. The header and footer switches for each test circuit are controlled by digital selects S1, S2, ... SN for N instances of the test circuit (the bars above the selects indicate that the select signals are inverted). For the N instances, only one select can have a value "1" at a time, and all of the remaining selects are "0". For example, if S1 has a logic value "1", then the S2 through SN selects must be "0". When S1 is "1", transistors MNa1, MNb1, MPa1, MPb1 are turned on and power for test circuit 1 is connected to the force and sense of SMU1 (nodes N1F, N1S) and the force and sense of SMU3 (nodes N3F, N3S). The Kelvin nodes for the force and sense of SMU1 are node 900, and for SMU3 are node 902. These nodes are immediately adjacent (both physically and diagrammatically) to test circuit 1. Transistor gates MNc1, MNd1, MPc1, and MPd1 are disconnected from SMU2 and SMU4 (nodes N2F, N2S, N4F, N4S). Because S2 through SN are "0," all of these test circuits are disconnected from SMU1 and SMU3, but connected to SMU2 and SMU4.

[0023]

[0033] The voltage applied to SMU3 is set to be the same as the voltage applied to SMU1 so that there is no voltage drop across the "off" transistors in the header and footer switches. Thus, for the selected transistor, all of the current from the selected test circuit is diverted to SMU1 and SMU3, and all of the current for the unselected test circuits is diverted to SMU2 and SMU4.

[0024]

[0034] 10 shows another implementation of the header switch 600 and footer switch 602 where the Kelvin node points for unselected test circuits are placed before the switches, thus reducing circuit complexity and wire routing complexity.

[0025]

[0035] This implementation can result in significant IR voltage drops if the leakage currents for unselected test circuits (i.e., for the legs of SMU2 and SMU4) are large enough. If the array of test circuits is large enough, the leakage currents for unselected test circuits can add up and become significant. Thus, this implementation has limitations on the number of test circuits that can be placed in the array.

[0026]

[0036] FIG. 11 shows another implementation that allows the Kelvin nodes of SMU2 and SMU4 (i.e., the connection between force and sense for each SMU) to be located outside (e.g., perhaps off-chip) of the header and footer switches. When S1 is set to “1”, S2-SN are set to “0”, and transistors MPa1, MPb1, MPd1, and MPe1 are turned on, connecting SMU1 (nodes N1F and N1S) to the top side of test circuit 1. Similarly, MNa1, MNb1, MNd1, and MNe1 are turned on, connecting the bottom side of test circuit 1 to SMU3. Transistors MPc1, MPf1, MNc1, and MNf1 are turned off, disconnecting SMU2 and SMU4 from test circuit 1.

[0027]

[0037] While S1 is still at "1", the opposite set of transistors is turned on / off in the header and footer switches of Test Circuit 2 through Test Circuit N. With the header switches in Test Circuit 2, SMU2 is not directly connected to the top of the test circuits as in the previous circuits. In this case, the connections of SMU2 to nodes Na2 and Nb2 are isolated from the test circuits by MPa2 and MPb2 which are turned off.

[0028]

[0038] The above description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that specific details are not required to practice the present invention. Thus, the above description of specific embodiments of the present invention is presented for purposes of illustration and description. The above description is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, so that those skilled in the art can best utilize the invention and its various embodiments, with various modifications as suited to the particular use contemplated. It is intended that the following claims and their equivalents define the scope of the invention.

Claims

1. A semiconductor wafer that hosts rows and columns of chips, wherein the rows and columns of chips are separated by scribe lines, and the semiconductor wafer; A selection circuit disposed within the scribe line, connected to a plurality of test circuits within the scribe line, and operative to enable voltage control in a single test circuit while rendering all other test circuits inoperative; Comprising: The selection circuit includes at least one of a header switch and a footer switch for each test circuit, and the at least one of the header switch and the footer switch A first switch having a first terminal configured to be connected to a force pad of a source measurement unit and a second terminal connected to a first terminal of the test circuit; A second switch having a first terminal configured to be connected to a footer terminal of the source measurement unit and a second terminal connected to a second terminal of the test circuit; An apparatus including.

2. The apparatus according to claim 1, wherein the selection circuit includes the header switch for each test circuit.

3. The apparatus according to claim 1, wherein the selection circuit includes the footer switch for each test circuit.

4. The apparatus according to claim 1, further comprising the source measurement unit.

5. The apparatus according to claim 1, further comprising a digital selection pad for receiving a control signal for the selection circuit that is operative to enable voltage control in the single test circuit while rendering all other test circuits inoperative.

6. The apparatus according to claim 1, wherein the first switch includes a first transistor and the second switch includes a second transistor of the same type as the first transistor.

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