Process for manufacturing a composite structure comprising a thin layer made of monocrystalline SiC on a carrier substrate made of polycrystalline SiC

Abstract

The invention relates to a process for producing a composite structure comprising a thin layer of monocrystalline silicon carbide (c-SiC) arranged on a carrier substrate of polycrystalline silicon carbide (p-SiC), the process comprising the steps of: a) providing an initial substrate of c-SiC; b) a first step of forming a first layer of p-SiC on the front side of the initial substrate; c) forming a buried brittle plane in the initial substrate; and d) a second step of deposition at a temperature below 900° C. to form a second layer of amorphous and / or polycrystalline SiC on the first layer, the second layer having a thickness of 10 μm or more and a thickness of 10 μm or more. 19 / cm 3 a) a third step of deposition at a temperature higher than 1000°C to form a third layer of p-SiC on the second layer, the first to third layers forming a carrier substrate and separation along the buried brittle plane occurring.

Description

[Technical field]

[0001] The present invention relates to the field of semiconductors for microelectronic components, in particular to a process for fabricating a composite structure comprising a thin layer made of monocrystalline silicon carbide on a carrier substrate made of polycrystalline silicon carbide, the composite structure conducting electricity vertically between the thin layer and the carrier substrate. [Background technology]

[0002] Power devices and integrated power systems based on single crystal silicon carbide can manage much higher power densities than their conventional silicon counterparts, and do so using smaller sized active areas. To further limit the size of SiC power devices, it is advantageous to fabricate vertical components rather than lateral components. To do so, the structure must allow vertical electrical conduction between electrodes located on the front and rear surfaces of the SiC structure.

[0003] Monocrystalline SiC substrates intended for the microelectronics industry remain expensive and difficult to mass produce, making it advantageous to use thin layer transfer solutions to manufacture composite structures, which usually comprise a thin layer made of a cheaper carrier substrate monocrystalline SiC. One well-known thin layer transfer solution is the Smart Cut™ process, based on implantation of light ions and direct bonding. Such a process makes it possible to fabricate composite structures, for example, with a thin layer made of monocrystalline SiC (c-SiC), which is split off from a donor substrate made of c-SiC, which is in direct contact with a carrier substrate made of polycrystalline SiC (p-SiC), allowing vertical electrical conduction. Nevertheless, it remains difficult to achieve good direct bonding between two c-SiC and p-SiC substrates by molecular adhesion, because the control of the surface finish and roughness of the substrates is complex, and c-SiC and p-SiC tend to have different polytypes.

[0004] Various methods derived from this process are also known in the prior art. For example, F. Mu et al. (ECS Transactions, 86 (5) 3-21, 2018) carry out direct bonding after activation of the surface, which becomes bonded by bombardment with argon (SAB: "surface activated bonding"), and such a treatment before bonding creates a very high density of dangling bonds, which promotes the formation of covalent bonds at the joint and therefore high bonding energy. Nevertheless, this method has the drawback of creating an amorphous layer on the surface of the donor substrate made of monocrystalline SiC, which has an unfavorable effect on the vertical electrical conduction between the thin layer made of c-SiC and the carrier substrate made of p-SiC.

[0005] Solutions have been proposed to solve this problem, notably in document EP 3168862, which uses the implantation of dopant elemental species into the amorphous layer in order to restore its electrical properties. The drawback of this approach is its complexity and therefore its cost.

[0006] Furthermore, document WO 2021 / 019137 is known, which describes a process for producing a composite structure comprising a thin layer made of monocrystalline silicon carbide, arranged on a carrier substrate made of polycrystalline silicon carbide, the process comprising: Providing an initial substrate made from single crystal silicon carbide; a first step of deposition, at a temperature higher than 1000° C., of the initial substrate to form an intermediate layer made of polycrystalline silicon carbide, the intermediate layer having a thickness of at least 1.5 microns; - a step of ion implantation of light element species through the intermediate layer to form a buried brittle plane in the initial substrate, the ion implantation defining a thin layer between said buried brittle plane and the intermediate layer; and a second step of deposition at a temperature higher than 1000° C. to form an additional layer made of polycrystalline silicon carbide on the intermediate layer, said intermediate layer and said additional layer forming a carrier substrate. During the second deposition step, separation occurs along the buried brittle plane, leading to the obtaining of a composite structure.

[0007] However, ion implantation through thick intermediate layers made of p-SiC remains relatively complex and expensive, as non-standard implant doses and energies are involved. Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention relates to an alternative solution to the prior art, aiming at overcoming all or some of the above mentioned drawbacks.The invention particularly relates to a process for manufacturing a composite structure comprising a thin layer made of c-SiC arranged on a carrier substrate made of p-SiC, the composite structure having a very good electrical conduction vertically between the thin layer and the carrier substrate. [Means for solving the problem]

[0009] The invention relates to a process for manufacturing a composite structure comprising a thin layer made of monocrystalline silicon carbide arranged on a carrier substrate made of polycrystalline silicon carbide, the process comprising: a) providing an initial substrate made of single crystal silicon carbide; b) a first step of deposition at a temperature higher than 1100° C. to form a first layer made of polycrystalline silicon carbide on the front side of the initial substrate, the first layer having a thickness of less than 1 μm and a thickness of less than 10 μm; 19 / cm 3 a first step of deposition having a dopant concentration greater than c) a step of ion implantation of light elemental species through the first layer to form a buried brittle plane in the initial substrate, the ion implantation defining a thin layer between said buried brittle plane and the front surface of the initial substrate; d) a second step of deposition at a temperature lower than 900° C. to form on the first layer a second layer made of amorphous and / or polycrystalline silicon carbide, the second layer having a thickness of at least 10 μm and a thickness of at least 10 μm; 19 / cm 3 a second step of deposition having a concentration of dopant of the same type as the first layer, higher than e) a third step of deposition at a temperature higher than 1000° C. to form a third layer made of polycrystalline silicon carbide on the second layer, the first layer, the second layer and the third layer forming a carrier substrate, and in the third deposition step separation occurs along a buried brittle plane. Includes.

[0010] According to other advantageous and non-limiting features of the present invention, applicable individually or in any technically possible combination, the first and third deposition steps are carried out by chemical vapor deposition at a temperature between 1100° C. and 1600° C., preferably between 1200° C. and 1600° C., more preferably between 1200° C. and 1400° C.; The first layer is 5×10 19 / cm 3 has a dopant concentration greater than At the end of the first deposition step, the first layer has a thickness of 50 nm to 500 nm, or even 50 nm to 200 nm, The fabrication process comprises, before the first deposition step, a step of pretreatment of the initial substrate, comprising at least one deoxidation of the front surface of said initial substrate, The manufacturing process comprises, before step b), a step a') of the formation of an intermediate layer on the front side of the initial substrate, the intermediate layer having the purpose of promoting electrical conduction, then in step b) a first layer is formed on said intermediate layer, The middle layer is made of silicone. The third layer formed in step e) has a thickness of 100 μm or more and a thickness of 10 μm or more in at least the first 100 microns of the thickness of the third layer. 19 / cm 3 and a dopant concentration higher than [Brief description of the drawings]

[0011] Further features and advantages of the present invention will become apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings. [Figure 1] 1 illustrates a composite structure manufactured using a fabrication process according to the present invention; [Figure 2a] 1 illustrates steps of a fabrication process according to the present invention; [Figure 2b] 1 illustrates steps of a fabrication process according to the present invention; [Figure 2c] 1 illustrates steps of a fabrication process according to the present invention; [Figure 2d] 1 illustrates steps of a fabrication process according to the present invention; [Figure 2e] 2e and 2e' respectively show steps of the fabrication process according to the present invention. [Figure 2f] 1 illustrates steps of a fabrication process according to the present invention;

[0012] The figures are schematic representations that are not drawn to scale for ease of reading, in particular the thicknesses of the layers along the z-axis are not drawn to scale with respect to the lateral dimensions along the x- and y-axes, and the relative thicknesses of the layers with respect to one another are not respected in the figures. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The invention relates to a process for producing a composite structure 1 comprising a thin layer 10 made of monocrystalline silicon carbide arranged on a carrier substrate 20 made of polycrystalline silicon carbide (FIG. 1).

[0014] The process first comprises a step a) of providing an initial substrate 11 made from monocrystalline silicon carbide (c-SiC) (FIG. 2a).

[0015] The initial substrate 11 preferably takes the form of a wafer with a diameter of 100 mm, 150 mm, 200 mm or even 300 mm and a thickness typically between 300 and 800 microns. It has a front face 11a and a rear face 11b. The surface roughness of the front face 11a is advantageously chosen to be lower than 1 nm Ra (average roughness), according to measurements by atomic force microscopy (AFM) on a 20 μm×20 μm scan.

[0016] At the end of the process of the invention, the initial substrate 11 from which the thin c-SiC layer 10 of the composite structure 1 is to be formed, the crystal orientation, crystal quality and doping level of which are therefore selected to meet the required specifications of the vertical components that are to be manufactured in the thin layer 10. For example, the initial c-SiC substrate 11 may be of 4H or 6H polytype, with an offcut angle of about 4.0° relative to the crystallographic axis <11-20>±0.5° and a doping angle of 5 / cm. 2 Below that, even 1 / cm 2 It has a micropipe density of less than 1500 / cm. It is preferably n-doped (with nitrogen) and has a resistivity of 0.015 Ω.cm to 0.030 Ω.cm. It has a low density of basal plane dislocations (BDPs) and a resistivity of typically 1500 / cm. 2 It may be advantageous to select an initial substrate 11 having a density of BPDs of:

[0017] Alternatively, the initial substrate 11 can be provided with a surface layer on its front surface 11a, produced, for example by epitaxy, and having the necessary properties for the future thin layer 10 to be formed from said surface layer at the end of the process of the invention.

[0018] The process then comprises a step b), called a first deposition step, for forming, on the front surface 11a of the initial substrate 11, a first layer 21 made of polycrystalline silicon carbide (p-SiC) (FIG. 2b). In the context of this description, it is noted that the first layer 21 can be formed directly on the front surface 11a of the initial substrate 11 or indirectly, i.e. through an intermediate layer that will then be inserted between the initial substrate 11 and the first layer 21. Variants involving such intermediate layers are described below.

[0019] The first layer 21 has a thickness of less than 1 μm. The thickness of the first layer 21 is advantageously 500 nm or less, and typically 50 nm to 200 nm.

[0020] The first layer 21 further comprises 10 19 / cm 3 The dopant concentration of the first layer 21 is usually desired to be of the same type as the dopant of the future thin layer 10 and therefore in this case of the initial substrate 11; in composite SiC structures intended for power applications, the dopant is most often chosen to be of n-type (doping with nitrogen). The doping concentration of the first layer 21 is 10 19 / cm 3 ~Number 10 21 / cm 3 In particular, the dopant concentration is selected between 5×10 19 / cm 3 Or more, for example, 3×10 20 / cm 3 Above all, 4×10 20 / cm 3 ~6×10 20 / cm 3 Doping the polycrystalline silicon carbide to such a level promotes obtaining good electrical conduction between the thin layer 10 (which will subsequently be transferred from the initial substrate 11) and the carrier substrate 20 (which includes, among other things, the first layer 21).

[0021] The p-SiC deposition in step b) is carried out at a temperature higher than 1100° C. It is advantageously carried out using a chemical vapour deposition (CVD) technique, for example one based on chlorine-containing precursors, at a temperature between 1100° C. and 1600° C. It is even more advantageous for the deposition temperature to be between 1200° C. and 1600° C., in particular between 1200° C. and 1400° C. The parameters of the first deposition are such that the first layer 21 has, apart from a good electrical conductivity due to being highly doped and uniform in terms of polytype (advantageously 3C), a high thermal conductivity (typically 200 W.m -1 .K -1 or more) and a similar thermal expansion coefficient to the future thin layer 10 (typically 3.8 at room temperature). E -6 / K~4.2 E −6 / K).

[0022] The first deposition step b) is carried out at high, even very high, temperatures, thus promoting the formation of SiC polycrystals of good quality, with low stress levels and with structural properties adapted to the targeted electrical, thermal and mechanical properties.

[0023] As an example, in some cases, the first layer 21 has 3C SiC grains with 111 orientation and an average size of 1 to 10 μm, and has a size of about 5×10 20 / cm 3 (equivalent to a resistivity of about 2 mΩ.cm).

[0024] The fabrication process advantageously includes, before step b), a step of pretreatment of the initial substrate 11, comprising at least one sequence of deoxidation of said front surface 11a of said initial substrate 11. This sequence may for example possibly involve immersion in a bath of hydrofluoric acid (HF), exposure to HF vapor or even annealing under hydrogen as a preliminary step to the first deposition of p-SiC. The pretreatment step may also include a cleaning sequence to remove all or part of particulate contamination, metallic or organic, potentially present on the faces 11a, 11b of the initial substrate 11.

[0025] According to one variant, the process may comprise, before step b), a step a') of the formation of an intermediate layer on the front surface 11a of the initial substrate 11, with the purpose of promoting electrical conduction, then the first layer 21 is formed on said intermediate layer in step b).

[0026] Such an intermediate layer may for example be made from amorphous silicon or polysilicon, optionally highly doped with the same type as the initial substrate 11. Other materials may also be envisaged, such as titanium, nickel, aluminium, molybdenum, niobium, tantalum, cobalt or copper, capable of forming a good electrical contact between the first layer 21 and the initial substrate 11. The thickness of the intermediate layer is kept small, typically less than 20 nm, or even less than 10 nm.

[0027] Returning to the general description, the fabrication process according to the invention further comprises a step c) of ion implantation of light element species to a given depth in the initial substrate 11, through the first layer 21. This implantation creates a buried brittle plane 12 in the initial substrate 11 (FIG. 2c).

[0028] The light element species implanted are preferably hydrogen, helium or a combination of these two species implanted simultaneously. As is well known (see the Smart Cut™ process), these light element species will form, around a given depth, microcavities distributed in a thin layer parallel to the free surface of the first layer 21, i.e. parallel to the plane (x,y) of the drawing. This thin layer will be called, for simplicity, the buried brittle plane.

[0029] A buried brittle plane 12 defines the future thin layer 10 with the front surface of the initial substrate 11. The energies of the implantation of the light element species are selected so that they penetrate the first layer 21 and reach a given depth in the initial substrate 11, said depth corresponding to the targeted thickness for the thin layer 10. Due to the small thickness of the first layer 21, this remains within the conventional implantation energy range.

[0030] Typically, hydrogen ions are introduced with energies between 50 keV and 210 keV, so as to pass through the first layer 21 of 50 nm to 1 μm and define a thin layer 10 of about 100 to 1500 nm. E 16 / cm 2 ~1 E 17 / cm 2 is injected at a dose of 100 mM NaCl.

[0031] It is noted that optionally a protective layer is deposited on the free face of the first layer 21 before the ion implantation step, to be removed before step d), i.e. the subsequent steps of the process. This protective layer may be made, for example, from a material such as silicon oxide or silicon nitride.

[0032] The fabrication process then includes a step d), called the second deposition step, for forming a second layer 22 on the first layer 21 (FIG. 2d), this second layer 22 being made of amorphous silicon carbide (a-SiC), or of polycrystalline silicon carbide (p-SiC), or of a mixture of a-SiC and p-SiC.

[0033] The second deposition of a-SiC or p-SiC is carried out at a temperature below 900° C., preferably below 800° C. The thermal budget of the second deposition is selected to remain below the thermal budget of blistering or splitting at the level of the buried brittle plane 12. In other words, the temperature and deposition time used for the deposition of step d) prevent the cavities and microcracks of the buried brittle plane 12 from thermally growing to a point where local deformation (blistering) of the stack of layers (lamina 10, first layer 21, second layer 22) occurs or where they cause partial delamination or separation with complete splitting over the entire length of the buried brittle plane 12.

[0034] Typically, the second deposition is carried out at 750-800° C., making it possible to obtain a thickness of about 10-15 μm for the second layer 22. Conventional chemical vapor deposition (CVD) techniques may optionally be used.

[0035] The second layer 22 has a thickness of 10 μm or more, this minimum thickness being specified to ensure that in subsequent steps of the process, the second layer 22 can act as a hardener to enable the application of higher thermal budgets in order to induce thermal growth of voids and microcracks in the embedded brittle plane 12, as described below.

[0036] The second layer 22 is 10 19 / cm 3 The second layer 22 further has a concentration of the same type of dopant as the first layer 21, which is higher than 5×10 19 / cm 3 From the number 10 20 / cm 3Up to and including tens 21 / cm 3 It is advantageous to select a temperature range up to about 10000 .mu.m. The purpose is to ensure a certain continuity in electrical conductivity between the first layer 21 and the second layer 22, even if the second layer 22 is of lower quality due to the relatively low deposition temperature of the second layer 22.

[0037] The manufacturing process according to the invention finally comprises a step e), called a third deposition step, for forming on the second layer 22 a third layer 23 made of polycrystalline silicon carbide (FIG. 2e).

[0038] The third deposition is carried out at a temperature above 1000° C. to ensure a sufficient deposition rate. As in the first deposition (step b)), this third deposition is advantageously carried out using chemical vapour deposition (CVD) techniques at a temperature between 1100° C. and 1600° C., preferably between 1200° C. and 1600° C. The parameters of the third deposition are also determined so that the third layer 23 has good electrical conductivity and high thermal conductivity (200 W.m -1 .K -1 or more) and a thermal expansion coefficient similar to that of thin layer 10.

[0039] The temperature and conditions of the third deposition will optionally be the same as or different from those of the first deposition in step b).

[0040] It is noted that if the second layer 22 deposited in the second deposition step, step d), is made wholly or partly of amorphous silicon carbide, the high temperature step, step e), will crystallize the amorphous silicon carbide into polycrystalline form.

[0041] Typically, the third layer 23 formed in step e) has a thickness of 100 μm or more, even 200 μm or more. The assembly made of the first layer 21, the second layer 22 and the third layer 23 forms the p-SiC carrier substrate 20 of the composite structure 1. It is mainly the third layer 23 that gives the carrier substrate 20 its thickness and therefore its mechanical properties. The thickness of the third layer 23 is therefore adjusted to the specifications required for the carrier substrate 20.

[0042] The third layer 23 has a thickness of at least 100 microns. 19 / cm 3 It is advantageous to have a dopant concentration higher than 100 μm. The doping can be uniform over the thickness of the third layer 23, or can be gradually decreased, or can be abruptly decreased beyond a certain thickness (e.g., 100 μm, 150 μm, 200 μm or more) to limit stress in the layer and to simplify deposition.

[0043] The dopant type is selected to be the same as that of the first layer 21 and that of the second layer 22 .

[0044] In the third deposition step, step e), due to the thermal budget applied to the structure formed by the initial substrate 11, the first and second layers 21, 22 and the growing additional third layer 23, a separation occurs along the buried brittle plane 12 (FIG. 2e'). In particular, the microcavities present in the buried brittle plane 12 grow until a splitting wave is initiated, which propagates over the entire extent of the buried brittle plane 12 and causes the assembly formed by the thin layer 10 and the first, second and third layers 21, 22, 23 to separate from the remainder 11' of the initial substrate 11.

[0045] Separation generally occurs before the third layer 23 reaches its target thickness, due to the thermal budget of the third deposition, which is much higher than the thermal budget required for splitting to occur. When splitting occurs, the splitting wave will propagate over the entire extent of the embedded brittle plane 12, since only the second layer 22 is thick enough to guarantee the reinforcing effect, regardless of the thickness of said layer 23, so that cavities do not bulge the layer. Also, the thickness of the second layer 22 alone allows the integrity of the intermediate composite structure 1' (figure e') to be maintained, avoiding delamination or degradation of said structure until the third layer 23 is completed.

[0046] Thus, the third deposition may continue until the target thickness of the third layer 23 is reached, resulting in the final composite structure 1 (Figure 2f).

[0047] Although not mentioned in connection with deposition steps b), d), and e) of the fabrication process, conventional surface pretreatment steps may advantageously be carried out prior to the formation of the first layer 21, the second layer 22, and / or the third layer 23, as the case may be.

[0048] According to one advantageous embodiment, the manufacturing process includes finishing steps applied to the final composite structure 1 obtained at the end of step e). These finishing steps are aimed in particular at improving the roughness of the free surface of the thin layer 10 (the front surface of the final composite structure 1) and optionally of the free surface of the third layer 23 (the rear surface of the final composite structure 1).

[0049] In particular, after detachment, the free surface of the thin layer 10 typically has a roughness of 3 nm to 6 nm Ra (AFM - 20 μm x 20 μm scan). For the subsequent fabrication of the components, the aim is to obtain a roughness lower than 1 nm Ra. For the rear surface of the final composite structure 1, the roughness at the end of the third deposition is typically higher than 10 nm Ra, or even higher than 100 nm Ra, the target aim being typically to reduce the roughness to less than 3 nm Ra.

[0050] The finishing step can in particular use known mechanical and / or chemical-mechanical polishing techniques and is applied to the front side of the final composite structure 1, to its rear side, or to both sides simultaneously using a double-sided polishing device. The polishing process applied to the front side will possibly be different from the one applied to the rear side, and will usually require different consumables to smooth the c-SiC and p-SiC surfaces.

[0051] The finishing step may also include a heat treatment at high or very high temperatures, typically between 1500°C and 1900°C, with the aim of restoring the crystalline quality and electrical properties of the thin layer 10 and improving the uniformity of the structural properties of the various layers 21, 22, 23 of the carrier substrate 20.

[0052] The composite structure 1 according to the invention provides excellent electrical conductivity between the thin layer 10 and the carrier substrate 20 and, in particular, a thickness of 5×10 -5 Ω.cm 2 Lower than 10 -5 Ω.cm 2 It has the advantage of having an interface resistivity of:

[0053] (Example) According to one non-limiting example of implementation, the initial substrate 11 provided in the first step of the fabrication process is a c-SiC wafer of 4H polytype having an orientation of 4.0° relative to the axis <11-20>±0.5° and having a diameter of 150 mm, a thickness of 350 μm and an average resistivity of 20 mΩ.cm.

[0054] A conventional cleaning sequence consisting of an RCA cleaning step (Standard Clean 1 + Standard Clean 2), followed by a cleaning step with Caro's acid (a mixture of sulfuric acid and hydrogen peroxide) and then a cleaning step with HF (hydrofluoric acid) is performed on the initial substrate 11 before the first deposition step. A CVD deposition based on a chlorine-containing precursor is performed on the front side 11a of the initial substrate 11 at a temperature of 1300 °C, with a thickness of 500 nm, and a deposition of 5 × 10 20 / cm 3The p-SiC first layer 21 has a concentration of n-type dopant (nitrogen) of 10 -5 Ω.cm 2 That's about it.

[0055] The hydrogen ions are implanted through the free surface of the first layer 21 with an energy of 200 keV and a velocity of 6 E 16H + / cm 2 Thus, a buried brittle plane 12 is created at a depth of about 1.2 μm in the initial substrate 11.

[0056] A cleaning sequence consisting of an RCA+Caro's Acid cleaning step is performed on the structure to remove potential contaminants from the free surface of the first layer 21.

[0057] A second CVD deposition of polycrystalline SiC or amorphous SiC or a mixed p-SiC / a-SiC structure is performed on the first layer 21 at a temperature of 800° C. to achieve a thickness of 10 μm for the second layer 22. 20 / cm 3 A concentration of n-type dopant (nitrogen) is incorporated into the second layer 22 during deposition.

[0058] A new cleaning sequence consisting of an RCA+Caro's acid cleaning step is performed on the resulting structure to remove potential contaminants from the free surface of the second layer 22.

[0059] A third CVD deposition is performed on the second layer 22 at a temperature of 1300° C. to achieve a thickness of 350 μm for the third layer 23. The initial 100 μm of the third layer 23 is approximately 5×10 20 / cm 3 The layer is then n-doped (doped with nitrogen) at a concentration of 5×10 18 / cm 3 As the doping is reached, the doping is decreased.

[0060] The thermal budget of the third CVD deposition causes the second layer 22 to crystallize into polycrystalline form.

[0061] Separation occurs during the third deposition at the level of the buried brittle plane 12. At the end of the third deposition, the composite structure 1, formed from the thin layer 10 and from the carrier substrate 20, separates from the remainder 11' of the initial substrate 11.

[0062] Mechanical, then chemical-mechanical polishing is performed to recover the surface roughness of the p-SiC rear surface of the carrier substrate 20 (free surface of the third layer 23), typically resulting in a thickness of p-SiC of about several microns to several tens of microns being removed as the case may be. Chemical-mechanical polishing is performed to recover the surface roughness of the thin layer 10, where about several tens to several hundreds of nanometers are removed.

[0063] A heat treatment at 1700° C. for 30 minutes is applied to the composite structure 1 before and after the above-mentioned chemical-mechanical polishing carried out on the sides of the thin layer 10 .

[0064] Of course, the invention is not limited to the described embodiments and examples, and variants may be added without departing from the scope of the invention as defined by the claims.

[0065] In particular, according to one possible variant, the thermal budget of the third CVD deposition is not high enough to crystallize the second layer 22 (wholly or partially amorphous during the second deposition) into polycrystalline form throughout the entire second layer 22. In this case, additional heat treatments may be performed before and after the third deposition in order to induce this crystallization.

Claims

1. A process for fabricating a composite structure (1) comprising a thin layer (10) made of single-crystalline silicon carbide, disposed on a carrier substrate (20) made of polycrystalline silicon carbide, comprising: a) providing an initial substrate (11) made of single-crystalline silicon carbide; b) A first step of deposition at a temperature higher than 1100 °C for forming a first layer (21) made of polycrystalline silicon carbide on the front surface (11a) of the initial substrate (11), wherein the first layer (21) has a thickness of less than 1 µm and a dopant concentration higher than 10 １９ / cm ３ and a first step of deposition; c) implanting ions of a light element species through the first layer (21) to form an embedded brittle plane (12) in the initial substrate (11), the ion implantation step defining the thin layer (10) between the embedded brittle plane (12) and the front surface of the initial substrate (11); d) A second step of deposition at a temperature lower than 900 °C for forming a second layer (22) made of amorphous and / or polycrystalline silicon carbide on the first layer (21), the second layer (22) having a thickness of 10 μm or more and a concentration of dopants of the same type as the first layer (21) that is higher than 10 １９ / cm ３ , a second step of deposition. e) a third step of deposition at a temperature higher than 1000 °C to form a third layer (23) made of polycrystalline silicon carbide on the second layer (22), the first layer (21), the second layer (22), and the third layer (23) forming the carrier substrate (20), and separation occurring along the embedded brittle plane (12) during the third deposition step; A process comprising the above steps.

2. The manufacturing process according to claim 1, wherein the first deposition step and the third deposition step are carried out by chemical vapor deposition at a temperature of 1100 °C to 1600 °C, preferably 1200 °C to 1600 °C, more preferably 1200 °C to 1400 °C.

3. The production process according to claim 1, wherein the first layer (21) has a dopant concentration higher than 5×10 １９ / cm ３ .

4. At the end of the first deposition step, the first layer (21) has a thickness of 50 nm to 500 nm, further preferably 50 nm to 200 nm, according to the manufacturing process of claim 1.

5. The manufacturing process according to claim 1, including a pre-treatment step of the initial substrate (11) including at least one deoxidation of the front surface of the initial substrate (11) before the first deposition step.

6. Before step b), including a step a') of forming an intermediate layer on the front surface of the initial substrate (11) for the purpose of promoting electrical conduction, and then in step b) the first layer (21) is formed on the intermediate layer, according to the manufacturing process of claim 1.

7. The manufacturing process according to claim 6, wherein the intermediate layer is made of silicon.

8. The third layer (23) formed in step e) has a thickness of 100 μm or more and a dopant concentration higher than 10 １９ / cm ３ in at least the first 100 microns of the thickness of the third layer (23). The manufacturing process according to any one of claims 1 to 7

Images