Voltage level shifting with reduced timing degradation - Patents.com
Patent Information
- Application Number
- JP2024521296
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2021-11-08
- Filing Date
- 2022-10-07
- Publication Date
- 2025-09-25
AI Technical Summary
Voltage level shifters experience significant timing degradation and occupy a large IC footprint due to the use of numerous devices, leading to duty cycle distortion and timing uncertainty, especially when converting signals between different voltage domains.
The implementation of edge matching circuits, which utilize a series connection of field effect transistors and inverters, to align the timing of signals across different voltage domains, reducing the number of devices required and minimizing IC footprint.
Edge matching circuits achieve substantial time alignment of signals, reducing timing degradation and IC footprint, while maintaining signal integrity and efficiency in voltage level shifting processes.
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Abstract
Description
[Technical field]
[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This patent application claims priority to pending U.S. Non-provisional Application No. 17 / 521,651, filed November 8, 2021, and assigned to the assignee of this application, which is expressly incorporated by reference herein as if fully set forth below and for all applicable purposes.
[0002] Aspects of the present disclosure relate generally to voltage level shifters, and more particularly to voltage level shifters with substantially no or reduced timing degradation. [Background technology]
[0003] A voltage level shifter is typically employed to convert an input signal in a first voltage domain to generate an output signal in a second voltage domain. A voltage domain is defined by the voltage levels of the high and low logic states of the signal. The voltage level shifter may receive an input signal from a circuit configured to process a signal in the first voltage domain. The voltage level shifter may provide an output signal to a circuit configured to process a signal in the second voltage domain. The voltage level shift may be upward if the second voltage domain has at least one logic voltage level that is higher than at least one corresponding logic voltage level of the first voltage domain. The voltage level shift may be downward if the second voltage domain has at least one logic voltage level that is lower than at least one corresponding logic voltage level of the first voltage domain. Summary of the Invention
[0004] SUMMARY OF THE DISCLOSURE The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.
[0005] One aspect of the disclosure relates to an apparatus including a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies according to a first voltage domain, a first input configured to receive a second input signal that varies according to a second voltage domain, and a first output configured to generate a first output signal that varies according to the second voltage domain, the first output signal being based on the first input signal and the second input signal, the first FET and the first inverter being coupled in series between a first voltage rail and a second voltage rail.
[0006] Another aspect of the disclosure relates to a method including receiving at a first input a first input signal that varies according to a first voltage region according to a first mode of operation and receiving at a second input a second input signal that varies according to a second voltage region according to the first mode of operation, where the first voltage region is different from the second voltage region, and generating at an output a first output signal that varies according to the second voltage region according to the first mode of operation, where the first output signal is based on the first input signal and the second input signal.
[0007] Another aspect of the disclosure relates to an apparatus including an input configured to receive a first signal in a first voltage domain, a first output configured to generate a second signal in a second voltage domain, and a second output configured to generate a third signal in a third voltage domain, the second signal and the third signal being based on the first signal, a first edge alignment circuit configured to generate a fourth signal in the third voltage domain based on the second signal and the complement of the third signal, and a second edge alignment circuit configured to generate a fifth signal in the third voltage domain based on the complement of the second signal and the third signal.
[0008] Another aspect of the disclosure relates to an apparatus including an input configured to receive a first signal in a first voltage domain, a first output configured to generate a second signal in a second voltage domain, and a second output configured to generate a third signal in a third voltage domain, the second signal and the third signal being based on the first signal, a first edge alignment circuit configured to generate a fourth signal in the third voltage domain based on the second signal and the complement of the third signal, and a second edge alignment circuit configured to generate a fifth signal in the third voltage domain based on the complement of the second signal and the third signal.
[0009] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of only a few of the various ways in which the principles of the various implementations may be employed and the implementations described herein are intended to include all such aspects and their equivalents. [Brief description of the drawings]
[0010] [Figure 1A]1 illustrates a block diagram of an exemplary signal processing system according to one aspect of the present disclosure. [Figure 1B] 1B illustrates a timing diagram of an exemplary operation of the signal processing system of FIG. 1A according to another aspect of the disclosure. [Diagram 2] 2 shows a block diagram of another exemplary signal processing system according to another aspect of the present disclosure. [Diagram 3] 4 shows a schematic diagram of an exemplary edge matching circuit according to another aspect of the present disclosure. [Figure 4] 4 shows a schematic diagram of another exemplary edge matching circuit according to another aspect of the present disclosure. [Diagram 5] 5 illustrates a timing diagram of an exemplary operation of the edge alignment circuit of FIG. 3 and FIG. 4 according to another embodiment of the present disclosure. [Figure 6] 2 shows a block diagram of another exemplary signal processing system according to another aspect of the present disclosure. [Figure 7] 2 shows a block diagram of another exemplary signal processing system according to another aspect of the present disclosure. [Figure 8] 1 shows a schematic diagram of an exemplary multi-mode edge matching circuit according to another aspect of the present disclosure. [Figure 9] 4 illustrates a flow diagram of an exemplary method for voltage level shifting an input signal to generate an output signal according to another aspect of the disclosure. [Figure 10] 1 illustrates a block diagram of an exemplary wireless communication device according to another aspect of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0011] The detailed description of the present invention, described below in connection with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
[0012] Voltage level shifting is used in many applications. Voltage level shifting involves shifting an input signal that varies according to a first voltage domain to produce an output signal that varies according to a second voltage domain, the first voltage domain being different from the second voltage domain. The voltage domains are defined by the voltage levels of the high and low logic states of the signal. The voltage level shifting can be upward if the second voltage domain of the output signal has at least one logic voltage that is higher than at least one corresponding logic voltage of the first voltage domain of the input signal. The voltage level shifting can also be downward if the second voltage domain of the output signal has at least one logic voltage that is lower than at least one corresponding logic voltage of the first voltage domain of the input signal.
[0013] As an example of an upward voltage level shift, a first voltage domain of the input signal may vary between a low logic voltage of zero (0) volts (V) and a high logic voltage of 0.9V, and a second voltage domain of the output signal may vary between a low logic voltage of 0V and a high logic voltage of 1.8V. Therefore, the high logic voltage of 1.8V of the second voltage domain is higher than the high logic voltage of 0.9V of the first voltage domain. This example may be applicable when the input signal is processed by a high speed digital circuit associated with an integrated circuit (IC) or a system on a chip (SOC), where the high speed of signal processing is advantageous to use relatively small transistors or field effect transistors (FETs) in the digital circuit. Due to the small nature of the transistor, the transistor may have a reliability limit with respect to the voltage that can be applied across the transistor. For this example, the high logic voltage of 0.9V of the first voltage domain may be within the reliability limit of the transistor, but the high logic voltage of the second voltage domain may be outside the reliability limit of the transistor. The second voltage domain of the output signal may be more suitable for transmission of the signal external to the IC or SOC, such as over transmission lines on a printed circuit board (PCB).
[0014] Continuing with the previous embodiment according to the downward voltage level shift, the second voltage domain of the input signal in this case can vary between a low logic voltage of 0V and a high logic voltage of 1.8V, and the first voltage domain of the output signal can vary between a low logic voltage of 0V and a high logic voltage of 0.9V. Therefore, the high logic voltage of the second voltage domain, 0.9V, is lower than the high logic voltage of the first voltage domain, 1.8V. This embodiment may be applicable when the input signal is received by an IC or SOC from a transmission line of a PCB, and the downward voltage translation is performed so that the high speed digital circuit can process the output signal in a lower voltage domain so that the reliability of the transistors is not compromised. The voltage level shifter performing the above-mentioned upward and downward voltage level shifting can be employed by the input / output (I / O) circuit or driver of the IC or SOC to transmit and receive signals to and from the outside of the IC or SOC. Further discussion and examples of voltage level shifting are further provided herein.
[0015] 1A illustrates a block diagram of an exemplary signal processing system 100 according to one embodiment of the present disclosure. The signal processing system 100 receives an input signal VIN in a first voltage domain, which may be referred to herein as the “PX” voltage domain. PX The input signal VIN PX may vary between a low logic voltage VSSX (e.g., 0 V) and a high logic voltage VDDPX (e.g., 1.8 V). As discussed further herein, the signal processing system 100 may be configured to receive an input signal VIN PX is configured to generate signals in different voltage domains for processing based on
[0016] Specifically, the signal processing system 100 includes a voltage domain splitter 110, buffers 115, 125, 130, and 135, and voltage level shifters 120 and 140. Furthermore, the signal processing system 100 includes a low voltage (LV) domain signal processing circuit 150 and a high voltage (HV) domain processing circuit 160.
[0017] The voltage domain splitter 110 divides the input signal VIN PX Receives the input signal VIN PX Based on the first signal V1 HV and the second signal V2 LV According to the above embodiment, the input signal VIN PX may be in the higher PX voltage domain because signal processing system 100 may be receiving signals from outside the IC or SOC via transmission lines on the PCB. Voltage domain splitter 110 may be part of the I / O circuitry or drivers of the IC or SOC and may include transistors (e.g., FETs) or circuits (e.g., stacks of FETs) configured to reliably handle signals in the PX voltage domain (e.g., 0V to 1.8V).
[0018] First signal V1 HV may be in the HV voltage domain, in which case the first signal V1 HV The second signal V2 varies between a low logic voltage VSSIX (e.g., 0.9 V) and a high logic voltage VDDPX (e.g., 1.8 V). LV may be in the LV voltage domain, in which case the second signal V2 LV The voltage domain splitter 110 therefore divides the input signal VIN PXThe voltage domain PX (e.g., 0V to 1.8V) of the LV 140 effectively divides the voltage domain PX (e.g., 0V to 1.8V) into an upper half voltage domain HV (e.g., 0.9V to 1.8V) and a lower half voltage domain LV (e.g., 0V to 0.9V). Note that in this embodiment, the low logic voltage in the HV voltage domain is substantially the same as the high logic voltage in the LV voltage domain. Because the voltage difference between the low and high logic voltages in the HV and LV voltage domains (e.g., ΔV=0.9V) is half that of the PX voltage domain, the circuits that process these signals (e.g., buffers 115, 125, 130, 135, voltage level shifters 120 and 140, and signal processing circuits 150 and 160) can be implemented using smaller transistors or FETs that can reliably process signals in the HV and LV voltage domains.
[0019] The buffer 115 outputs the first signal V1 HV to generate a buffered first signal V1 BHV The buffer 125 is configured to generate a second signal V2 LV to generate a buffered second signal V2 BLV The buffer 135 is configured to generate a first signal V1 HV to generate another buffered first signal V1 BHV The buffer 130 is configured to generate a second signal V2 LV to generate another buffered second signal V2 BLV The voltage level shifter 120 is configured to generate the buffered first signal V1 BHV The first signal V1 is voltage level shifted downward. HV Based on the above, in the LV voltage domain, the signal V1 LV Similarly, the voltage level shifter 140 is configured to generate a buffered second signal V2 BLV The second signal V2 is obtained by voltage level shifting upward. LV Based on the above, but in the HV voltage domain, the signal V2 HVIt is configured to generate V1 LV Signal and V2 BLV The signals are in the LV voltage domain, so the LV domain signal processing circuit 150 is configured to process these signals. BHV Signal and V2 HV Since the signals are in the HV voltage domain, HV domain signal processing circuitry 160 is configured to process these signals.
[0020] 1B illustrates a timing diagram of an exemplary operation of the signal processing system 100 according to another aspect of the disclosure. The horizontal axis of the timing diagram represents time. The vertical axis of the timing diagram represents, from top to bottom, the signal V1 HV , V2 LV , V1 BHV , V1 LV , V2 BLV , and V2 HV represents the logic level of
[0021] As mentioned above, the first signal V1 HV and the second signal V2 LV is the input signal VIN PX Both signals V1 HV and V2 LV The same signal VIN PX Since both signals are derived from V1, they should be logically identical, except that they are in different voltage domains HV and LV. However, in some cases, the first signal V1 HV and the second signal V2 LV and propagate through different data paths, resulting in V1 HV and V2 LV For example, in this example timing diagram, the second signal V2 LV is the first signal V1 HV That is, the second signal V2 has a pulse width or duty cycle that is greater than the pulse width or duty cycle of the first signal V1. LV The pulse width of is from time t1 to time t 10while the first signal V1 HV The pulse width of extends from time t3 to time t8 (e.g., t 10 As a result of this early timing degradation, these signals V1 HV and V2 LV Signals derived from may experience additional timing degradation.
[0022] For example, the first signal V1 HV and the second signal V2 LV The first buffered signal V1 is generated by the buffers 115 / 135 and 130 / 135, respectively, based on BHV and the second buffered signal V2 BLV For example, the second buffered signal V2 has a significantly different pulse width or duty cycle. BLV has a pulse width that extends from time t2 to time t9, and the first buffered signal V1 BHV has a pulse width that ranges from time t4 to time t7, where t9-t2 is significantly greater than t7-t4. This is sometimes referred to as duty cycle distortion.
[0023] Further, according to this embodiment, the buffered signal V1 BHV and V2 BLV The voltage level shifted signals V1 and V2 are generated by the voltage level shifters 120 and 140, respectively, based on the LV and signal V2 HV and may have additional timing degradation and uncertainty. For example, in addition to duty cycle distortion, the voltage level shifted signals V1 and V2 may each have additional timing degradation and uncertainty. LV and signal V2 HV and the timing uncertainties ΔT5 and ΔT6 at the rising edge of the voltage level shifted signal V1 LV and signal V2 HV Timing uncertainty ΔT on the falling edge of 11 and ΔT 12This may be because voltage level shifters 120 and 140 typically have many devices (e.g., 18 or more FETs) and with that many devices, there may be significant process-voltage-temperature (PVT) operating variations.
[0024] Due to all of the above-mentioned timing degradations, the signal V1 provided to the LV domain signal processing circuit 150 and the HV domain signal processing circuit 160, respectively, LV / V2 BLV and signal V1 BHV / V2 HV The timing of the signal V1 may be completely destroyed. Therefore, the LV signal processing circuit 150 and the HV signal processing circuit 160 each process the timing-degraded signal V1. LV / V2 BLV and signal V1 BHV / V2 HV Based on the above, the voltage level shifters 120 and 140 may not be able to perform their intended operations. Another drawback of the voltage level shifters 120 and 140 is that they occupy a substantial IC footprint due to the large number of devices. Furthermore, the delay between the input and output signals of the voltage level shifters 120 and 140 may be very large, e.g., on the order of nanoseconds.
[0025] 2 illustrates a block diagram of another exemplary signal processing system 200 according to another aspect of the present disclosure. The signal processing system 200 may perform the same or similar operations as the signal processing system 100 described above. However, instead of using the voltage level shifters 120 and 140, the signal processing system 200 uses edge matching circuits to reduce or substantially eliminate any timing degradation in the signals provided to the LV and HV signal processing circuits.
[0026] Specifically, signal processing system 200 includes a voltage domain splitter 210, inverters 220 and 230, edge matching circuits 215 and 240, and buffers 225 and 235. Voltage domain splitter 210 may be implemented similarly to voltage domain splitter 110 detailed above. That is, voltage domain splitter 210 splits an input signal VIN in the PX voltage domain (e.g., 0V to 1.8V). PX Receives the input signal VIN PX Based on the above, the first signal V1 in the HV voltage domain (for example, 0.9V to 1.8V) and the LV voltage domain (for example, 0V to 0.9V) HV and the second signal V2 LV Similarly, the buffers 235 and 225 are each configured to generate a first signal V1 HV and the second signal V2 LV Based on the first buffered signal V1 BHV and the second signal V2 BLV is configured to generate
[0027] The inverters 230 and 220 each generate a first signal V1 HV and the second signal V2 LV By inverting the first signal,
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[0028] 3 shows a schematic diagram of an example edge matching circuit 300 according to another aspect of the present disclosure. The edge matching circuit 300 may be an example detailed implementation of the edge matching circuit 215 described above.
[0029] Specifically, the edge matching circuit 300 includes a first field effect transistor (FET) M1, which may be implemented as an n-channel metal oxide semiconductor (NMOS) FET. The edge matching circuit 300 further includes an inverter 310, which includes a second FET M2 and a third FET M3. The second FET M2 may be implemented as a p-channel metal oxide semiconductor (PMOS) FET, and the third FET M3 may be implemented as an NMOS FET. The FET M1 and the inverter 310 are coupled in series between an upper voltage rail VDDIX and a lower voltage rail VSSX.
[0030] For example, the NMOS FET M1 is PXA first signal V1 generated by the voltage domain splitter 210 based on HV As described above, the first signal V1 HV is in the HV voltage domain (e.g., 0.9V to 1.8V). The PMOS FET M2 and the NMOS FET M3 have their respective gates coupled together to form the input of the inverter 310, and are connected to, for example, a second signal V2 LV A complementary second signal generated by an inverter 220 based on
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[0031] PMOS FET M2 and NMOS FET M3 are coupled together to form the output of inverter 310, which outputs output signal V1 LV As previously mentioned, the output signal V1 LV is in the LV voltage domain (e.g., 0V to 0.9V) and can be provided to the LV voltage domain signal processing circuit 250 as described above. The edge matching circuit 300 outputs the output signal V1 LV Optionally, the inverter 310 may include a latch 320 coupled to the output of the inverter 310 to latch the first signal V1 HV and a second signal complementary to
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[0032] 4 shows a schematic diagram of another exemplary edge matching circuit 400 according to another aspect of the present disclosure. The edge matching circuit 400 may be an exemplary detailed implementation of the edge matching circuit 240 described above.
[0033] Specifically, the edge matching circuit 400 includes an inverter 410 including a first FET M4 and a second FET M5. The first FET M4 may be implemented as a PMOS FET, and the second FET M5 may be implemented as an NMOS FET. The edge matching circuit 400 includes a third FET M6, which may be implemented as a PMOS FET. The inverter 410 and the PMOS FET M6 are coupled in series between an upper voltage rail VDDPX and a lower voltage rail VSSIX.
[0034] The PMOS FET M6, for example, PX A second signal V2 generated by the voltage domain splitter 210 based on LV As described above, the second signal V2 LV is in the LV voltage domain (e.g., 0V to 0.9V). PMOS FET M4 and NMOS FET M5 have their respective gates coupled together to form the input of an inverter 410, and are connected to a first signal V1, for example. HV A complementary first signal generated by the inverter 230 based on
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[0035] PMOS FET M4 and NMOS FET M5 are coupled together to form the output of inverter 410, which outputs output signal V2 HV As previously mentioned, the output signal V2 HV is in the HV voltage domain (e.g., 0.9V to 1.8V) and can be provided to the HV voltage domain signal processing circuit 260 as described above. The edge matching circuit 400 outputs the output signal V2 HV Optionally, a latch 420 may be included coupled to the output of the inverter 410 to latch the second signal V2. LV The first signal is complementary to
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[0036] 5 shows a timing diagram of an exemplary operation of edge alignment circuits 300 and 400 according to another embodiment of the disclosure. The timing diagram is similar to that of FIG. 1B, with the horizontal axis representing time and the vertical axis representing, from top to bottom, the signal V1 HV , V2 LV , V1 LV , and V2 HV represents the logic level of
[0037] As mentioned above, for example, the input signal VIN PX When the first signal V1 is generated by the voltage domain splitter 210 based on HV and the second signal V2 LV As an example, there may be some timing degradation in the second signal V2. LV is the first voltage signal V1 HV For example, in this particular embodiment, the second signal V2 may have a pulse width or duty cycle that is greater than the pulse width or duty cycle of the first signal V1. LV The pulse width of the first signal V1 extends from time t1 to time t8. HV The pulse width of the first signal t8 extends from time t2 to time t5, where t8-t1 is greater than t5-t2.
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[0038] With further reference to FIG. 3, considering the operation of the edge matching circuit 300, at time t1, the second signal V2 LV transitions from a low logic level to a high logic level in the LV domain. At substantially the same time, a complementary second signal
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[0039] Then, at time t4, the first signal V1 HV The first signal V1 transitions from a high logic signal to a low logic signal in the HV domain. HV is applied to the gate of NMOS FET M1, turning off FET M1. Then, at time t6, the second signal V2 LV transitions from a high logic level to a low logic level in the LV domain. At substantially the same time, a complementary second signal
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[0040]
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[0041] 4, considering the operation of the edge matching circuit 400, similarly at time t1, the second signal V2 LV The second signal V2 transitions from a low logic level to a high logic level in the LV domain. LV is applied to the gate of the PMOS FET M6, the PMOS FET M6 is turned off. Then, at time t2, the first signal V1 HV transitions from a low logic level to a high logic level in the HV domain. At substantially the same time, the complementary first signal
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[0042] Then, at time t4, the first signal V1 HV transitions from a high logic level to a low logic level in the HV domain. At substantially the same time, the complementary first signal
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[0043] Output signal V1 of edge matching circuit 300 LV and the output signal V2 of the edge matching circuit 400 HV Note that output signal V1 has a rising edge at time t3 and a falling edge at time t7 that are substantially time aligned. LV and V2 HV The rising edge of the first signal V1 HV It is generated in response to the rising edge of the output signal V1 LV and V2 HV The falling edge of the second signal V2 LV Therefore, edge matching circuits 300 and 400 can be used as voltage level shifters for the input signals at the gates of FETs M1 and M6, respectively. In the case of edge matching circuit 300, the first signal V1 HV In the edge matching circuit 400, the second signal V2 operates as a downward voltage level shifter to level shift the second signal V2 from the HV voltage domain to the LV voltage domain. LV from the LV voltage domain to the HV voltage domain.
[0044] Further advantages of the edge matching circuits 300 and 400 come from the fact that they include a small number of devices. For example, without the optional latches 320 and 420, each of the edge matching circuits 300 and 400 includes three devices, compared to at least 18 devices for the exemplary voltage level shifter, as described above. With the optional latches 320 and 420, each of the edge matching circuits 300 and 400 may have nine devices, since each latch may include a cross-coupled inverter. Furthermore, due to the small number of devices, each of the edge matching circuits 300 and 400 may occupy a relatively small IC footprint. Furthermore, the delay associated with each of the edge matching circuits 300 and 400 may be on the order of picoseconds (ps), while the delay associated with the exemplary voltage level shifter, as described above, may be on the order of nanoseconds (ns).
[0045] 6 illustrates a block diagram of another exemplary signal processing system 600 according to another aspect of the present disclosure. In the signal processing system 200, the voltage domain splitter 210 splits the input signal VIN PX from which a signal in the upper half-voltage domain HV and a signal in the lower half-voltage domain LV are generated.
[0046] In the signal processing system 600, an input signal VIN CX is provided to a voltage level shifter 610. In this case, the voltage level shifter 610 receives an input signal VIN CX Based on this, the first signal V1 in the HV voltage region (for example, 0.9V to 1.8V) HV and a complementary first signal
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[0047] 7 illustrates a block diagram of another exemplary signal processing system 700 according to another aspect of the disclosure. To address the timing degradation discussed with respect to signal processing system 600, signal processing system 700 includes edge alignment circuitry that retimes or substantially time aligns signals for further processing by the HV and LV voltage domain signal processing circuits, as previously described.
[0048] Specifically, the signal processing system 700 receives an input signal VIN CX Receive a first signal V1 in the HV voltage domain (for example, 0.9V to 1.8V) HV and a complementary first signal
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[0049] The signal processing system 700 further includes a set of edge matching circuits 720, 730, 740, and 740. The edge matching circuit 720 matches the first signal V1 HV and a complementary second signal
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[0050] The edge matching circuit 740 outputs a complementary first signal
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[0051] 8 shows a schematic diagram of an exemplary multi-mode edge matching circuit 800 according to another embodiment of the present disclosure. In a first mode of operation, the edge matching circuit 800 operates according to the aforementioned edge matching circuit 300. In a second mode of operation, the edge matching circuit 300 operates as a two-input inverter.
[0052] Specifically, the edge matching circuit 800 includes a first FET M7, which may be implemented as a PMOS FET. The edge matching circuit 800 further includes a first inverter 815, which includes an input coupled to a gate of the PMOS FET M7. The first inverter 815 may be coupled to a first programmable voltage rail VDDPX / VDD_1P2 and a second programmable voltage rail VSSIX / VSSX, which are configured to receive a supply voltage according to the HV voltage domain (e.g., 1.8V and 0.9V, respectively) in a first operating mode and to receive a supply voltage in the VDD_1P2 voltage domain (e.g., 1.2V and 0V, respectively) in a second operating mode. The edge matching circuit 800 further includes a second FET M8, which may be implemented as an NMOS FET. The edge matching circuit 800 also includes a second inverter 810, which includes a third FET M9 and a fourth FET M10. The third FET M9 may be implemented as a PMOS FET, and the fourth FET M10 may be implemented as an NMOS FET. The second FET M8 and the second inverter 810 are coupled in series between an upper voltage rail VDD_1P2 and a lower voltage rail VSSX, which are configured to receive a supply voltage according to the VDD_1P2 voltage domain (e.g., 1.2V and 0V, respectively). The PMOS FET M7 is coupled between the upper voltage rail VDD_1P2 and the second inverter 810.
[0053] The PMOS FET M7 includes a gate configured to receive a first input signal V1. According to a first operating mode, the first input signal V1 varies according to an HV voltage domain (e.g., 0.9V to 1.8V). According to a second operating mode, the first input signal V1 varies according to a VDD_1P2 voltage domain (e.g., 0V to 1.2V). The PMOS FET M9 and the NMOS FET M10 are coupled together to form an input of the inverter 810 and include corresponding gates configured to receive a second input signal V2. According to a first operating mode, the second input signal V2 varies according to an LV voltage domain (e.g., 0V to 0.9V). According to a second operating mode, the second input signal V2 varies according to a VDD_1P2 voltage domain (e.g., 0V to 1.2V).
[0054] The PMOS FET M9 and the NMOS FET M10 include corresponding drains coupled together to form an output of the inverter 810 and configured to generate an output signal V3. In a first operating mode, the output signal V3 varies according to an LV voltage domain (e.g., 0V to 0.9V). In a second operating mode, the output signal V3 varies according to a VDD_1P2 voltage domain (e.g., 0V to 1.2V). The edge matching circuit 800 may optionally include a latch 820 coupled to the output of the inverter 810 for latching the output signal V3. This can improve the latching of the correct logic state of the output signal V3 when there is a significant time delay between the first signal V1 and the second signal V2.
[0055] The operation mode is set by the voltage domains of the first input signal V1 and the second input signal V2. For example, when the first input signal V1 and the second input signal V2 change according to the HV voltage domain and the LV voltage domain, respectively, the edge matching circuit 800 operates according to the first operation mode. In this mode, the PMOS FET M7 is effectively disabled, and the inverter 815 and the NMOS FET M8 are enabled. The inverter 815 generates a complementary first voltage V1 at the gate of the NMOS FET M8, which is substantially complementary to the logic level of the second voltage V2 in this embodiment. Therefore, the operation of the edge matching circuit 800 is substantially the same as that of the edge matching circuit 300 described above.
[0056] As discussed, according to the first mode of operation, PMOS FET M7 is effectively disabled because the first signal V1 cannot turn on PMOS FET M7 at a low logic level (e.g., 0.9V) according to the HV voltage domain. For example, if the threshold voltage of PMOS FET M7 is 0.4V, a low logic level of 0.9V will generate a gate-source voltage of 0.3V, which is lower than the threshold voltage of 0.4V. Therefore, PMOS FET M7 will not turn on.
[0057] When the first input signal V1 and the second input signal V2 change according to the VDD_1P2 voltage domain, the edge matching circuit 800 operates according to a second operation mode. In this mode, the PMOS FET M7, the inverter 815, and the NMOS FET M8 are enabled. Therefore, the edge matching circuit 800 operates as a two-input inverter. That is, when the first input signal V1 and the second input signal V2 are at a low logic level (e.g., 0V) according to the VDD_1P2 voltage domain, the FETs M7, M8, and M9 are turned on, and the FET M10 is turned off. Therefore, the output signal V3 is at a high logic level (e.g., 1.2V) according to the VDD_1P2 voltage domain. Conversely, when the first input signal V1 and the second input signal V2 are at a high logic level (e.g., 1.2V) according to the VDD_1P2 voltage domain, the FETs M7, M8, and M9 are turned off, and the FET M10 is turned on. Therefore, the output signal V3 is at a low logic level (eg, 0V) according to the VDD_1P2 voltage domain.
[0058] FIG. 9 illustrates a flow diagram of an example method 900 for voltage level shifting an input signal to generate an output signal according to another aspect of the disclosure.
[0059] Method 900 includes receiving at a first input a first input signal that varies according to a first voltage domain according to a first mode of operation (block 910). Examples of means for receiving at a first input a first input signal that varies according to a first voltage domain according to a first mode of operation include the gate of FET M1 in edge matching circuit 300, the gate of FET M6 in edge matching circuit 400, and the gate of FET M8 of edge matching circuit 800, as well as corresponding first inputs of edge matching circuits 215, 240, 720, 730, 740, and 735.
[0060] Method 900 further includes receiving at a second input a second input signal that varies according to a second voltage region according to the first mode of operation, the first voltage region being different from the second voltage region (block 920). Examples of means for receiving at a second input a second input signal that varies according to a second voltage region according to the first mode of operation, the first voltage region being different from the second voltage region, include the input to inverter 310 in edge matching circuit 300, the input to inverter 410 in edge matching circuit 400, and the input to inverter 810 of edge matching circuit 800, as well as corresponding second inputs of edge matching circuits 215, 240, 720, 730, 740, and 735.
[0061] Further, the method 900 includes generating, at an output, a first output signal that varies according to a second voltage domain according to the first operating mode, the first output signal being based on the first input signal and the second input signal (Block 930). Examples of means for generating, at an output, a first output signal that varies according to a second voltage domain according to the first operating mode, the first output signal being based on the first input signal and the second input signal include inverter 310 of edge matching circuit 300, inverter 410 of edge matching circuit 400, and inverter 810 of edge matching circuit 800, as well as edge matching circuits 215, 240, 720, 730, 740, and 735.
[0062] 10 illustrates a block diagram of an example wireless communication device 1000 according to another aspect of the disclosure. The wireless communication device 1000 includes at least one antenna 1060 (e.g., an antenna array), a transceiver 1050 coupled to the at least one antenna 1060, and an integrated circuit (IC) or system on chip (SOC) 1010. The IC or SOC 1010 includes one or more signal processing cores 1020 and one or more input / output (I / O) drivers or circuits 1030 coupled to the transceiver. The one or more I / O circuits 1030 may include one or more edge matching circuits, implemented as previously described herein.
[0063] According to a signal transmission application, the one or more signal processing cores 1020 can be configured to process a transmit baseband (BB) signal in a first voltage domain (e.g., a CX voltage domain). The one or more I / O circuits 1030 can be configured to voltage level shift the transmit (BB) baseband signal upward to a second voltage domain (e.g., a PX voltage domain). The one or more I / O circuits 1030 can include, for example, one or more edge matching circuits, each implemented by the edge matching circuit 400 to perform the upward voltage level shift. The transmit baseband (BB) signal in the second voltage domain is provided to a transceiver 1050, which is configured to generate a transmit radio frequency (RF) signal based on the transmit baseband (BB) signal. The transmit RF signal is provided to at least one antenna 1060 for wireless transmission to one or more remote wireless devices.
[0064] According to a signal receiving application, the at least one antenna 1060 is configured to wirelessly receive a received RF signal from one or more remote wireless devices. The transceiver 1050 is configured to generate a received baseband (BB) signal in a second voltage domain based on the received RF signal. The one or more I / O circuits 1030 are configured to voltage level shift the received baseband (BB) signal downward to generate a received baseband (BB) signal in a first voltage domain. The one or more I / O circuits 1030 may include one or more edge matching circuits, each implemented by the edge matching circuits 300 or 800, for example, to perform a downward voltage level shift. The one or more signal processing cores 1020 may be configured to process the received baseband (BB) signal in the first voltage domain.
[0065] The following provides a summary of aspects of the present disclosure: Aspect 1: An apparatus comprising: a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies according to a first voltage domain; a first input configured to receive a second input signal that varies according to a second voltage domain; and a first inverter including a first output configured to generate a first output signal that varies according to the second voltage domain, wherein the first output signal is based on the first input signal and the second input signal, and the first FET and the first inverter are coupled in series between a first voltage rail and a second voltage rail.
[0066] Aspect 2: The apparatus of aspect 1, wherein the first voltage rail and the second voltage rail are configured to receive a first supply voltage and a second supply voltage, respectively, according to a second voltage domain.
[0067] Example 3: The device of example 1 or 2, wherein the first FET comprises an n-channel metal-oxide-semiconductor (NMOS) FET.
[0068] Example 4: The apparatus of example 3, wherein the NMOS FET and the first inverter are coupled in series, in that order, between a first voltage rail and a second voltage rail.
[0069] Aspect 5: The apparatus of any one of Aspects 1-4, wherein the second input signal varies between a first low logic voltage and a first high logic voltage according to a second voltage domain, the first supply voltage is substantially the same as the first high logic voltage, and the second supply voltage is substantially the same as the first low logic voltage.
[0070] Aspect 6: The apparatus of aspect 5, wherein the first input signal varies between a second low logic voltage and a second high logic voltage according to a first voltage domain, the second low logic voltage being substantially the same as the first high logic voltage.
[0071] Example 7: The device of example 1 or 2, wherein the first FET comprises a p-channel metal-oxide-semiconductor (PMOS) FET.
[0072] Example 8: The apparatus of Example 7, wherein the first inverter and the PMOS FET are coupled in series, in that order, between a first voltage rail and a second voltage rail.
[0073] Aspect 9: The apparatus of aspect 7 or 8, wherein the second input signal varies between a first low logic voltage and a first high logic voltage according to a second voltage domain, the first supply voltage is substantially the same as the first high logic voltage, and the second supply voltage is substantially the same as the first low logic voltage.
[0074] Example 10: The apparatus of example 9, wherein the first input signal varies between a second low logic voltage and a second high logic voltage according to a first voltage domain, and the second high logic voltage is substantially the same as the first low logic voltage.
[0075] Example 11: The apparatus of any one of Examples 1-10, wherein the first input signal is logically complementary to the second input signal.
[0076] Example 12: The apparatus of any one of Examples 1-11, further comprising a latch coupled to the first output of the first inverter.
[0077] Aspect 13: The apparatus of aspect 1, wherein in accordance with a first mode of operation, a first gate of the first FET is configured to receive a first input signal, and the first inverter is configured to receive a second input signal and generate a first output signal.
[0078] Example 14: The apparatus of example 13, wherein the first voltage rail and the second voltage rail are configured to receive a first supply voltage and a second supply voltage, respectively, according to a third voltage domain.
[0079] Example 15: The apparatus of example 13 or 14, further including: a second FET including a second gate configured to receive a first input signal according to the first mode of operation and to receive a third input signal according to the second mode of operation; and a second inverter including a second input coupled to the second gate of the second FET and a second output coupled to the first gate of the first FET.
[0080] Aspect 16: The apparatus of aspect 15, wherein a second inverter is coupled to a programmable third voltage rail and a fourth voltage rail configured to receive a third supply voltage and a fourth supply voltage according to a first voltage domain and a first operating mode, and to receive the first supply voltage and a second supply voltage according to a second operating mode.
[0081] Example 17: The device of example 15 or 16, wherein the first FET comprises an n-channel metal-oxide-semiconductor (NMOS) FET and the second FET comprises a p-channel metal-oxide-semiconductor (PMOS) FET.
[0082] Example 18: The apparatus of any one of Examples 15-17, wherein the second FET is coupled between the first voltage rail and the first inverter.
[0083] Aspect 19: The apparatus of any one of aspects 15-18, wherein in accordance with the second operating mode, the second gate of the second FET is configured to receive a third input signal that varies according to a third voltage region, and the first inverter is configured to receive a fourth input signal that varies according to the third voltage region and generate a second output signal that varies according to the third voltage region.
[0084] Aspect 20: The apparatus of any one of aspects 15-19, wherein in accordance with a first operating mode, the second FET is effectively disabled and the second inverter and the first FET are enabled, and in accordance with a second operating mode, the second FET, the second inverter, and the first FET are enabled.
[0085] Aspect 21: A method comprising: receiving a first input signal that varies according to a first voltage region according to a first operating mode; receiving a second input signal that varies according to a second voltage region according to the first operating mode, where the first voltage region is different from the second voltage region; and generating a first output signal that varies according to the second voltage region according to the first operating mode, where the first output signal is based on the first input signal and the second input signal.
[0086] Example 22: The method of example 21, wherein the first input signal is logically complementary to the second input signal.
[0087] Aspect 23: The method of aspect 21 or 22, wherein the first input signal varies between a first low logic voltage and a first high logic voltage according to a first voltage domain, the second input signal varies between a second low logic voltage and a second high logic voltage according to a second voltage domain, and the second high logic voltage is substantially the same as the first low logic voltage.
[0088] Example 24: The method of example 21 or 22, wherein the first input signal varies between a first low logic voltage and a first high logic voltage according to a first voltage domain, the second input signal varies between a second low logic voltage and a second high logic voltage according to a second voltage domain, and the first high logic voltage is substantially the same as the second low logic voltage.
[0089] Aspect 25: The method of any one of aspects 21 to 23, further comprising: receiving, at the first input, a third input signal that varies according to a third voltage region in accordance with a second operating mode; receiving, at the second input, a fourth input signal that varies according to the third voltage region in accordance with the second operating mode; and generating, at the output, a second output signal that varies according to the third voltage region in accordance with the second operating mode, wherein the second output signal is based on the third input signal and the fourth input signal.
[0090] Aspect 26: An apparatus including an input configured to receive a first signal in a first voltage domain, a first output configured to generate a second signal in a second voltage domain, and a second output configured to generate a third signal in a third voltage domain, the second signal and the third signal being based on the first signal; a voltage domain splitter configured to generate a fourth signal in the third voltage domain based on the second signal and the complement of the third signal; and a second edge alignment circuit configured to generate a fifth signal in the third voltage domain based on the complement of the second signal and the third signal.
[0091] Aspect 27: The apparatus of aspect 26, wherein the first edge alignment circuit includes an n-channel metal-oxide-semiconductor field effect transistor (NMOS FET) including a gate configured to receive the second signal, and an inverter including an input configured to receive a complementary third signal and an output configured to generate a fourth signal, wherein the NMOS FET and the inverter are coupled in series between a first voltage rail and a second voltage rail associated with a third voltage domain.
[0092] Example 28: The apparatus of example 26 or 27, wherein the second edge matching circuit includes an inverter including an input configured to receive a complementary second signal and an output configured to generate a fifth signal, and a p-channel metal-oxide-semiconductor field effect transistor (PMOS FET) including a gate configured to receive a third signal, wherein the inverter and the PMOS FET are coupled in series between a first voltage rail and a second voltage rail associated with the second voltage domain.
[0093] Aspect 29: An apparatus including an input configured to receive a first signal in a first voltage domain, a first output configured to generate a second signal in a second voltage domain, and a second output configured to generate a third signal in a third voltage domain, the second signal and the third signal being based on the first signal; a voltage level shifter; a first edge alignment circuit configured to generate a fourth signal in the third voltage domain based on the second signal and a complement of the third signal; and a second edge alignment circuit configured to generate a fifth signal in the third voltage domain based on the complement of the second signal and the third signal.
[0094] Example 30: The apparatus of example 29, wherein at least one of the first edge matching circuit or the second edge matching circuit includes a field effect transistor (FET) including a gate configured to receive the second signal or the third signal, and an inverter including an input configured to receive the third signal or the second signal, and an output configured to generate the fourth signal or the fifth signal, wherein the FET and the inverter are coupled in series between the first voltage rail and the second voltage rail.
[0095] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. 1. An apparatus comprising: a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies according to a first voltage domain in a first mode of operation; a first inverter configured to receive a second input signal that varies according to a second voltage domain in the first mode of operation, and a first output configured to generate a first output signal that varies according to the second voltage domain in the first mode of operation, the first output signal being based on the first input signal and the second input signal, the first FET and the first inverter being coupled in series between a first voltage rail and a second voltage rail, the first voltage rail and the second voltage rail being configured to receive a first supply voltage and a second supply voltage according to a third voltage domain, respectively. Device.
2. The apparatus of claim 1 , wherein the first FET comprises an n-channel metal-oxide-semiconductor (NMOS) FET.
3. 3. The apparatus of claim 2, wherein the NMOS FET and the first inverter are coupled in series, in that order, between the first voltage rail and the second voltage rail, the second input signal varies between a first low logic voltage and a first high logic voltage according to the second voltage domain, the first supply voltage is substantially the same as the first high logic voltage, and the first input signal varies between a second low logic voltage and a second high logic voltage according to the first voltage domain, and the second low logic voltage is substantially the same as the first high logic voltage.
4. 2. The apparatus of claim 1, wherein the first input signal is the logical complement of the second input signal.
5. 2. The apparatus of claim 1, further comprising: a latch coupled to the first output of the first inverter.
6. a second FET including a second gate configured to receive a first inverted input signal from a first node in accordance with the first mode of operation and a third input signal from the first node that varies according to the third voltage region in accordance with a second mode of operation; a second inverter including a second input coupled to the second gate of the second FET and a second output coupled to the first gate of the first FET; The apparatus of claim 1 further comprising:
7. 7. The apparatus of claim 6, wherein the second inverter is coupled to programmable third and fourth voltage rails configured to receive a third and fourth supply voltage according to the first voltage domain and the first operating mode, and to receive the first and second supply voltages according to the second operating mode.
8. 7. The apparatus of claim 6, wherein the first FET comprises an n-channel metal oxide semiconductor (NMOS) FET and the second FET comprises a p-channel metal oxide semiconductor (PMOS) FET.
9. 7. The apparatus of claim 6, wherein the second FET is coupled between the first voltage rail and the first inverter.
10. 7. The apparatus of claim 6, wherein according to the second mode of operation, the first inverter is configured to receive a fourth input signal that varies according to the third voltage domain and to generate a second output signal that varies according to the third voltage domain.
11. In accordance with the first mode of operation, the second FET is disabled and the second inverter and the first FET are enabled; the second FET, the second inverter, and the first FET are enabled according to the second mode of operation; 11. The apparatus of claim 10.
12. A method of operating the apparatus of claim 1, comprising: receiving, at a first input, the first input signal varying according to the first voltage domain according to the first operating mode; receiving, at a second input, the second input signal varying according to the second voltage domain according to the first operating mode, the first voltage domain being different from the second voltage domain; and generating, at an output, the first output signal that varies according to the second voltage region according to the first operating mode, the first output signal being based on the first input signal and the second input signal. method.
13. 13. The method of claim 12, wherein the first input signal is the logical complement of the second input signal.
14. the first input signal varies between a first low logic voltage and a first high logic voltage according to the first voltage domain, the second input signal varies between a second low logic voltage and a second high logic voltage according to the second voltage domain; and the second high logic voltage is substantially the same as the first low logic voltage, or the first high logic voltage is substantially the same as the second low logic voltage; The method of claim 12.
15. receiving at the first input a third input signal that varies according to the third voltage domain according to a second mode of operation; receiving at the second input a fourth input signal that varies according to the third voltage domain in accordance with the second mode of operation; generating, at the output, a second output signal that varies according to the third voltage region according to the second operating mode, the second output signal being based on the third input signal and the fourth input signal; The method of claim 12 further comprising: