Method for preparing a support substrate provided with a charge trapping layer - Patents.com

Abstract

The present invention relates to a process for preparing a support substrate (1) carrying a charge trapping layer, comprising the steps of introducing a monocrystalline silicon base substrate (2) into a chamber of a deposition equipment and, without removing the base substrate (2) from the chamber, flushing the chamber with a carrier gas, carrying out the following successive steps: forming a dielectric layer (3) on a base substrate (2) by introducing a reactive gas into a chamber for a first period of time; forming a polycrystalline silicon charge trapping layer (4) directly over the dielectric layer (3) by introducing a silicon-containing precursor gas into the chamber for a second period of time subsequent to the first period of time; The time during which the dielectric layer (3) is exposed only to the carrier gas between the first and second periods is less than 30 seconds, and the formation of the charge trapping layer (4) is carried out at a temperature of 1010°C to 1200°C.

Description

[Technical field]

[0001] FIELD OF THEINVENTION The present invention relates to a process for preparing a support substrate provided with a charge trapping layer. The present invention also relates to a process for transferring a thin layer onto such a support substrate to form a composite substrate. These support substrates and composite substrates have prominent applications in the field of high frequency integrated devices, i.e. electronic devices processing signals with frequencies between about 3 kHz and 300 GHz, for example in the field of telecommunications (telephone, Wi-Fi, Bluetooth, etc.). [Background technology]

[0002] (Technical Background of the Invention) In order to prevent or limit possible electromagnetic coupling between an electronic device and the support substrate of a silicon-on-insulator (SOI) substrate on which said device is formed, it is known to insert a charge trapping layer between the buried dielectric layer and the SOI support, directly below the dielectric layer. This layer may for example consist of a 0.1-10 micron layer of polycrystalline silicon formed on a monocrystalline silicon base substrate, often chosen to be highly resistive (i.e. having a resistivity greater than 500 ohm·cm, or even greater than 1000 ohm·cm). The junctions of the grains forming the polycrystalline then constitute traps for charge carriers, which may come from the trapping layer itself or from the underlying substrate. In this way, the appearance of a conductive surface beneath the insulator is prevented. The production of known SOI substrates of this type is described, for example, in French Patents FR 2 860 341, FR 2 933 233, FR 2 953 640, US 2015 / 115480, US 7 268 060, US 6 544 656 or WO 2020 / 008116.

[0003] In order to facilitate the creation of a charge trapping layer formed on a base substrate of monocrystalline silicon and to avoid recrystallization of the charge trapping layer, it is known to form an amorphous dielectric layer, typically a silicon dioxide layer, on this base substrate before forming the trapping layer by deposition, which makes it possible to maintain the polycrystalline nature of the trapping layer by preventing recrystallization when the temperature of the stack is increased.

[0004] Thus, EP 3136421 proposes to form a polycrystalline silicon trap layer on a base substrate with a resistivity of 700 Ohm-cm. The base substrate is oxidized by simple cleaning or dry oxidation. The trap layer is then formed in two successive deposition steps using trichlorosilane precursor gas. The first step concerns the formation of a seed layer directly on the silicon oxide layer at a relatively low temperature below 1010 °C, while the second step is carried out at a higher temperature than the first step. According to said document, this technique makes it possible to form the trap layer quickly and without excessive deformation of the base substrate that may hinder the assembly of the substrate by molecular adhesion if it is intended to form a support substrate for a silicon-on-insulator substrate.

[0005] EP 3309819 proposes forming a dielectric layer on the exposed surface of a base substrate and forming a charge trapping layer on the dielectric layer over the course of two successive steps carried out on different items of equipment. The charge trapping layer is formed at a temperature of 1050°C to 1200°C.

[0006] For its part, EP 2503592 envisages the in situ manufacture of such a layer, in which the trapping layer is formed on the dielectric layer of a silicon base substrate without removing the base substrate from the equipment used to form this stack, which may be the chamber of an epitaxy frame.

[0007] In this technique, a base substrate is placed in a chamber of the equipment and an oxidizing gas is circulated through said chamber to superficially form a dielectric layer during an oxidation step, which is carried out at a temperature of about 1100° C. Then, without removing the base substrate from the chamber, a carrier gas is circulated to flush out the oxidizing gas and bring the temperature of the chamber and / or substrate to a relatively low deposition temperature, such as 900° C. or less.

[0008] Once the oxidizing atmosphere has been flushed with the carrier gas and the deposition temperature established, a silicon-containing precursor gas is introduced and deposited to gradually form a polycrystalline silicon layer on the dielectric layer. By continuing the introduction of gas into the chamber in this manner, the introduction of precursor gas before the oxidizing gas has been flushed out and before the temperature has been fully established at the target temperature of about 900° C. or less is avoided, preventing premature deposition of polycrystalline silicon that may not have the required quality.

[0009] However, the formation of the polycrystalline silicon layer at relatively low deposition temperatures is particularly slow, being of the order of 0.3 microns / min at 900° C. In particular, it is well known that the deposition rate generally increases with temperature. In order to improve this deposition rate and thus the manufacturing time of the support carrying the trapping layer, it may be envisaged to form only a seed part of the trapping layer at a low temperature, as proposed in EP 3136421, and then to form the remaining part of the layer at a relatively high temperature and therefore more quickly.

[0010] Although such an approach does indeed improve the manufacturing speed of the support substrate, the formation of the seed layer remains a particularly time-consuming step. Of course, it is generally desirable to further increase the manufacturing speed without compromising the quality of the support.

[0011] (Objective of the Invention) One of the goals of the present invention is to propose a process for preparing a support substrate with a charge trapping layer that at least partially addresses this problem. More specifically, one of the goals of the present invention is to propose a process for preparing a support substrate with a charge trapping layer, the implementation time of which is reduced compared to prior art processes with comparable quality. Even more specifically, one of the goals of the present invention is to propose a process for preparing a support substrate with a charge trapping layer that does not require a seed part formed at a relatively low temperature of about 1010° C. or less.

[0012] BRIEF DESCRIPTION OF THE DRAWINGS To achieve this goal, the object of the present invention is to propose a process for preparing a support substrate carrying a charge trapping layer, which process comprises the steps of introducing a monocrystalline silicon base substrate having a resistivity greater than 500 Ohm·cm into the chamber of a deposition equipment and, without removing the base substrate from the chamber and while flushing the chamber with carrier gas, carrying out the following successive steps: forming a dielectric layer on an exposed surface of the base substrate by introducing a reactive gas into the chamber for a first period of time; forming a polycrystalline silicon charge trapping layer directly over the dielectric layer by introducing a silicon-containing precursor gas into the chamber for a second time period subsequent to the first time period. and performing the steps of:

[0013] According to the present invention, the time during which the dielectric layer is exposed only to the carrier gas between the first and second periods is less than 30 seconds. Also, according to the present invention, the step of forming the charge trapping layer is strictly performed at a temperature of 1010°C to 1200°C.

[0014] By limiting the time during which the dielectric layer is exposed only to the carrier gas between the first and second time periods, the surface state of this layer is adjusted or maintained to be particularly suitable for receiving a polycrystalline silicon layer of the same quality as that obtained at much lower temperatures with the prior art techniques. This surprising result makes it possible to grow a trapping layer at a higher growth rate with comparable quality, and thus to form a support substrate at an improved rate compared to the prior art techniques.

[0015] According to other preferred, non-limiting features of the present invention, alone or in any technically feasible combination: The carrier gas comprises or consists of hydrogen; The silicon-containing precursor gas is selected from the list comprising silane, disilane, trichlorosilane, dichlorosilane and silicon tetrachloride; The dielectric layer is made of silicon oxide, and the reactive gas is a mixture of 0.1% to 10% oxygen in a neutral gas such as argon. The step of forming the dielectric layer is carried out at a temperature of 1010° C. to 1150° C. The dielectric layer has a thickness of greater than 0.5 nm. The step of forming the charge trapping layer is carried out at a temperature above 1050° C. or 1100° C. The charge trapping layer and the dielectric layer are formed at the same temperature, within 50° C. The time during which the dielectric layer is exposed to only the carrier gas is less than 20 seconds or less than 15 seconds; The charge trapping layer has a thickness of 0.1 to 10 microns.

[0016] Other features and advantages of the present invention will become apparent from the following detailed description of the invention which proceeds with reference to the accompanying drawings. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a diagram showing a support substrate according to the first embodiment. [Diagram 2]FIG. 2 is a diagram showing a support substrate according to the second embodiment. [Diagram 3] FIG. 3 shows a composite substrate comprising a support substrate according to the present invention. [Figure 4] FIG. 4 shows the sequence of the two main steps of the process according to the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Detailed Description of the Invention Referring to FIG. 1, a support substrate 1 in one embodiment includes a base substrate 2, a dielectric layer 3 disposed on the base substrate 2, and a charge trapping layer 4 disposed on and in contact with the dielectric layer 3.

[0019] The support substrate 1 may be in the form of a circular wafer of standard size, for example 200 mm or 300 mm or even 450 mm in diameter, however the invention is in no way limited to these dimensions or to this form.

[0020] The base substrate 2 consists of monocrystalline silicon and has a thickness of several hundred microns. Preferably, the base substrate 2 has a high resistivity, strictly greater than 500 or 1000 Ohm·cm, and even more preferably greater than 3000 Ohm·cm. This limits the density of charges, holes or electrons that are prone to mobility in the base substrate 2 and thus reduces the RF performance of the final substrate S. It may for example be a CZ substrate with a low interstitial oxygen content, with a resistivity that may be greater than 1000 Ohm·cm, as is known per se.

[0021] However, the present invention is not limited to base substrates 2 having such resistivities and also provides RF performance advantages when the base substrate 2 has a more suitable resistivity of 500 ohm-cm or less, or even 100 ohm-cm or less, which may be a more standard single crystal CZ substrate having a resistivity of less than 500 ohm-cm. This approach is advantageous in that such substrates can be easily and inexpensively procured.

[0022] 2, the support substrate may also comprise an intrinsic monocrystalline silicon layer 5, i.e. a layer that is not intentionally doped and is therefore particularly resistive, arranged between the base substrate 2 and the dielectric layer 3, in particular if the base substrate 2 has a resistivity of less than or equal to 500 ohm·cm. The intrinsic monocrystalline silicon layer 5 preferably has a resistivity of more than 2000 ohm·cm and may even reach a resistivity of more than 20 kOhm·cm. Its thickness may be between 0.5 and 100 microns, preferably between 5 and 20 microns.

[0023] The dielectric layer 3 is for example made of silicon oxide or silicon nitride and has a thickness greater than 0.5 nm, for example between 0.5 nm and 50 nm. This amorphous dielectric layer 3 makes it possible to form the charge trapping layer 4 in polycrystalline form and to avoid or limit recrystallization of this layer when the support substrate 1 is exposed to high temperatures, during the formation of this layer 4 or during subsequent heat treatments to which the support substrate 1 is subjected.

[0024] The support substrate 1 also includes a charge trapping layer 4 made of polycrystalline silicon, disposed directly on and in contact with the dielectric layer 3. The charge trapping layer 4 has a resistivity greater than 500 ohm·cm, preferably greater than 1 kOhm·cm. As mentioned at the beginning of this patent application, the function of the trapping layer is to capture charge carriers that may be present within the support 1 and to limit their movement. The charge trapping layer 4 typically has a thickness of 0.1 microns to 10 microns, or more.

[0025] Due to its non-crystalline nature, the trapping layer 4 has structural defects such as dislocations, grain boundaries, amorphous regions, gaps, inclusions, pores that define the grains of the layer. These structural defects form traps for charges, for example at the level of incomplete or uncompleted chemical bonds, that tend to circulate in the material. This prevents conduction in the trapping layer, so that the support substrate 1 has high high frequency performance. This performance can be established by a "second harmonic distortion" characterization measurement of the support thus prepared. This measurement is typically performed at 900 MHz. It is generally required that the distortion measurement is less than -70 dB so that the support substrate can be considered to have high high frequency performance.

[0026] This characterization measurement, described in detail in a January 2015 document entitled "White paper - RF SOI wafer characterization" published by Soitec and described in U.S. Patent Application Publication No. 2015 / 0168326, is particularly relevant because it is highly representative of the performance of RF integrated devices that may be formed on a composite substrate incorporating the characterized support substrate.

[0027] The grain size of the polycrystalline silicon trapping layer 4 is preferably between 50 nm (below this thermal stability is no longer guaranteed and there is a risk of temperature-induced recrystallization) and 2000 nm (above this the RF performance of the supporting substrate is affected).

[0028] In either case, regardless of the exact characteristics of the grains in the trapping layer 4, the trapping layer 4 will have a high resistivity, greater than 500 ohm-cm. To this end, the trapping layer 4 is not intentionally doped, i.e., it has a charge-carrying dopant concentration of less than 2E13 atoms per cubic centimeter. It may also be nitrogen-rich or carbon-rich to improve resistive properties.

[0029] For the sake of completeness, Figure 3 shows a composite substrate S comprising a support substrate 1 according to the invention. As can be seen very clearly from this figure, the composite substrate comprises, on the support substrate 1, a thin film 6, preferably made of a crystalline material. For example, but not limited to, the thin film 6 can be made of a semiconductor material such as silicon or of lithium tantalate (LiTaO 3 ) or lithium niobate (LiNbO 3 ) can be made from a piezoelectric material.

[0030] The composite substrate S of Fig. 3 can be formed from a support substrate 1 in many ways, but this formation preferably comprises a step of transferring a thin film 6 onto this support substrate. As is known per se, this transfer is usually carried out by assembling the "main" faces of the donor substrate and the support substrate 1. It is generally envisaged to provide at least one of these faces with a dielectric bonding layer 7, typically made of silicon oxide, which may be formed by thermal treatment or deposition. This assembly preferably comprises a molecular adhesive bond.

[0031] After this assembly step, the thickness of the donor substrate is reduced to form a thin film 6. This reduction step may be performed by mechanical or chemical thinning, or it may also be performed by fracture at weakened areas previously introduced in the donor substrate, for example according to the principle of the Smart Cut™ technology.

[0032] A finishing step of the thin film 6, for example a polishing step, a heat treatment in a reducing or neutral atmosphere, or a sacrificial oxidation, may be performed in succession with the thickness reduction step.

[0033] It should be noted that the donor substrate may be a simple substrate, i.e., a substrate that does not contain integrated devices, or alternatively, the donor substrate may be pre-processed to generate integrated devices on its surface.

[0034] Now, a process for preparing the support substrate 1, which was the subject of the previous section of this specification, is disclosed.

[0035] A monocrystalline silicon base substrate 2 is introduced into the chamber of the deposition equipment.

[0036] The equipment may correspond to an epitaxial deposition equipment. The equipment comprises a susceptor arranged in the chamber to receive the base substrate and expose one of its faces to the atmosphere and to the gas streams circulating in the chamber. The susceptor may be mobile, in particular having a rotational movement for angular uniformity of the exposure of the free face of the base substrate 2 to the gas streams. To allow the introduction of these gas streams and the control of the atmosphere contained in the chamber, the chamber is equipped with a number of inlet ports and at least one outlet port. The chamber is also equipped with devices for heating the substrate, the gases and / or the walls of the chamber, for example lamps emitting radiation capable of heating the free surface of the base substrate. A number of tubes fluidly connected to the inlet ports of the chamber allow the introduction at a controlled rate of gases for treating the base substrate 2. The said gases are in particular reactive, oxidizing or nitriding gases, carrier gases, for example mixtures of argon and hydrogen, or hydrogen, and precursor gases containing silicon. The precursor gases are, for example, silane, disilane, trichlorosilane, dichlorosilane, and silicon tetrachloride. The instrument may of course be equipped with other tubes for introducing other gases into the chamber, and the instrument is provided with a control device configured to control all the parameters of the preparation process carried out (flow rates of the various gases, temperature, pressure, etc.).

[0037] The process for preparing a support substrate according to the previous sections of this specification notably comprises two main steps, which are performed without removing the base substrate 2 from the chamber of the instrument, and as a result, the base substrate is not exposed to gases or atmospheres other than those introduced or present in the chamber throughout the preparation process.

[0038] As is known per se, a carrier gas CG is introduced into the chamber through an inlet port at a given flow rate to flush the chamber throughout the process for preparing a donor substrate, and in particular during the two main steps of this process.

[0039] In a first step, as shown in FIG. 4, the dielectric layer 3 is formed on the exposed surface of the base substrate 2 by introducing a reactive gas RG into the chamber at a selected flow rate for a first period T1. The heating device is controlled so that the dielectric layer is formed at a temperature typically between 900° C. and 1150° C., preferably between 950° C. and 1100° C. Depending on the nature of the dielectric layer, for example silicon dioxide or silicon nitride, it is desired to form, this reactive gas may be formed from an oxidizing gas or a nitriding gas. Preferably, the dielectric layer is made of silicon oxide, in which case the reactive gas may comprise, for example, 0.1% to 10% oxygen in a neutral gas such as argon. The oxidizing atmosphere in the chamber is maintained for a time (first period) selected depending on the desired thickness of the dielectric layer 3. Preferably, the dielectric layer 3 has a thickness greater than 0.5 nm.

[0040] Then, in a second step following the first step, a silicon-containing precursor gas PrG is introduced into the chamber at a selected flow rate for a second time period T2 following the first time period T1 to form a charge trapping layer 4 made of polycrystalline silicon directly on the dielectric layer 3. The amorphous nature of the dielectric layer prevents crystallization of the trapping layer formed during this second step, which would occur in the absence of this dielectric layer.

[0041] The sequence of the first and second steps is performed in a controlled manner to avoid intermixing of reactive and precursor gases, which may cause undesired chemical reactions in the chamber and prevent the deposition of a trapping layer of desired quality. In other words, as can be clearly seen in Figure 4, the first step in which reactive gases form the atmosphere of the chamber does not overlap with the second step in which precursor gases form the atmosphere of the chamber.

[0042] At the end of the first step, and during a transition period Tt separating the end of the first period from the beginning of the second period, a carrier gas, which is constantly flushing the chamber throughout the preparation process, flushes the reactive gas from the chamber. This transition period is also used to adjust the temperature of the chamber and / or the substrate if the temperature of the first step is different from that of the second step. In the second stage, after this transition period Tt, a precursor gas is introduced into the chamber. Thus, once this gas is introduced into the chamber, the atmosphere and temperature of this chamber are perfectly suitable for the formation of a high-quality charge trapping layer 4. The carrier gas and the precursor gas flow simultaneously through the chamber for the remainder of this second process step.

[0043] Conventionally, as reported in the introduction to this patent application, the growth of the trapping layer is carried out at relatively low temperatures, below 1010 °C, at least in the seed part in contact with the dielectric layer, in order to obtain a layer of good quality. This quality is notably measured by measuring the second harmonic distortion. It is also measured by the stress in the charge trapping layer 4, which, if too great, may tend to deform the substrate. It is generally sought to limit this deformation (typically "warping" in semiconductor technology) to less than 200 microns, or even less than 100 microns, for a substrate with a diameter of 300 mm.

[0044] Surprisingly, the inventors of the present patent application have observed that by carrying out this second step at a relatively high temperature, precisely above 1010°C, it is possible to obtain a trapping layer 4 of completely similar quality to that of the prior art, as long as the length of the transition period Tt does not exceed 30 seconds. In other words, if the time during which the dielectric layer 3 is exposed only to the carrier gas is less than 30 seconds, the formation of the charge trapping layer 4 can be carried out at temperatures above 1010°C, typically between 1010°C and 1200°C, and at the same time have an acceptable quality of this layer, both in terms of deformation and second harmonic distortion measurements.

[0045] It can therefore be seen that by limiting the time during which the dielectric layer 3 is exposed to only the carrier gas between the first and second time periods, the surface state of this layer 3 is adjusted or maintained so as to be particularly suitable for the direct growth of the trapping layer 4 at temperatures much higher than in the prior art. To this end, it may be expedient to limit the time during which the dielectric layer 3 is exposed to only the carrier gas to 20 seconds, or even to 15 seconds.

[0046] It should also be noted that by limiting this time, possible melting of the dielectric layer 3 during the transition period is avoided or limited. This melting results in a loss of thickness of this dielectric layer, which is proportional to the length of the transition period Tt to the power of n (Tt)^n, where n can range from 2 to 4 depending on the temperature, the initial thickness of the dielectric layer, and the flow rate of the carrier gas. If the length of the transition period is too long, the thickness of the dielectric layer is likely to be insufficient to form a good quality charge trapping layer.

[0047] It is recalled that the relatively high formation temperature of the trapping layer is an important property in that it allows the trapping layer to be formed more quickly with comparable quality. Thus, the growth rates are on the order of 0.8 microns / min at 950°C, 1.25 microns / min at 1000°C, and 2 microns / min at 1100°C, which is significantly higher than the 0.3 microns / min observed at 900°C. This significantly improves the manufacturing speed of the support substrate compared to the rates obtained using the prior art processes. This is particularly true when the trapping layer is relatively thick, exceeding 2 microns.

[0048] Therefore, in order to target a high growth rate of the trapping layer 4, the step of forming this layer 4 is preferably carried out at a temperature strictly above 1010°C, above 1050°C or above 1100°C.

[0049] Regardless of the temperature selected during this step of forming trapping layer 4 , it is performed for a time sufficient to form the target thickness of polycrystalline silicon directly above dielectric layer 3 .

[0050] In order to limit the loss in thickness of the dielectric layer 2 during the transition period Tt, the processing temperature may be reduced during this period, for example by 50° C. relative to the temperature of the first period.

[0051] Preferably, the charge trapping layer 4 and the dielectric layer 3 are formed at the same respective temperatures within 50° C. For example, the two steps may be performed in sequence as presented above, while maintaining the same temperature of 1050° C. or 1100° C. for the first and second steps. Since there is no need to ramp up or down the temperature between the two steps, the length of the transition period can be more easily reduced to less than 30 seconds, for example less than 20 seconds or even less than 15 seconds.

[0052] The dielectric layer 3 may be formed at a temperature higher than or lower than the formation temperature of the charge trapping layer 4, or may be formed at the same temperature.

[0053] Optionally, prior to the first step of forming the dielectric layer 3, the base substrate can be deoxidized annealed at a temperature between 900° C. and 1200° C. in a reducing or weakly reducing atmosphere to remove any native oxide that may be present on the surface of the base substrate 2. This annealing may be performed while only carrier gas is flowing in the chamber for a period of a few seconds to a few minutes depending on the temperature selected in order to remove this native oxide.

[0054] This step is particularly useful when the base substrate 2 has a relatively low resistivity, for example a resistivity below 500 Ohm·cm, and when it is preferred to provide an intrinsic silicon epitaxial layer 5 on the base substrate 2. In such a case, the treatment process comprises forming this intrinsic silicon epitaxial layer 5 on the base substrate 2, between the deoxidation annealing and the first step of forming the dielectric layer 3, at an epitaxial temperature, typically between 900 °C and 1200 °C. To this end, a carrier gas and a silicon-containing precursor gas can be circulated simultaneously in the chamber.

[0055] Needless to say, these steps of deoxidation annealing and / or epitaxial layer formation are also performed in situ, i.e. without removing the base substrate 2 from the chamber of the apparatus and without exposing the free surface of the support 1 being prepared to gases or atmospheres other than those introduced or present in the chamber throughout the process.

[0056] Of course, the invention is not limited to the described embodiments, and variations in implementation may be applied without departing from the scope of the invention as defined by the claims.

Claims

1. A process for preparing a support substrate (1) carrying a charge trapping layer (4), comprising the steps of introducing a monocrystalline silicon base substrate (2) having a resistivity greater than 500 ohm-cm into a chamber of a deposition equipment, and, without removing the base substrate (2) from the chamber, while flushing the chamber with a carrier gas, the following successive steps: forming a dielectric layer (3) on the exposed surface of the base substrate (2) by introducing a reactive gas into the chamber for a first period of time; forming a polycrystalline silicon charge trapping layer (4) directly on the dielectric layer (3) by introducing a silicon-containing precursor gas into the chamber for a second period of time subsequent to the first period of time; and performing the steps of The process is characterized in that the time during which the dielectric layer (3) is exposed to only the carrier gas between the first and second periods is less than 30 seconds, and the step of forming the charge trapping layer (4) is carried out at a temperature of precisely 1010°C to 1200°C.

2. 10. The process of claim 1, wherein the carrier gas comprises or consists of hydrogen.

3. 3. The process of claim 1 or 2, wherein the silicon-containing precursor gas is selected from the list comprising silane, disilane, trichlorosilane, dichlorosilane and silicon tetrachloride.

4. The process of claim 1 or 2, wherein the dielectric layer (3) is made of silicon oxide and the reactive gas comprises 0.1% to 10% oxygen in a neutral gas such as argon.

5. The process according to claim 1 or 2, wherein the step of forming the dielectric layer (3) is carried out at a temperature between 1010°C and 1150°C.

6. 3. The process according to claim 1 or 2, wherein the dielectric layer (3) has a thickness of more than 0.5 nm.

7. 3. The process of claim 1 or 2, wherein the step of forming the charge trapping layer (4) is performed at a temperature above 1050°C or 1100°C.

8. 3. The process of claim 1 or 2, wherein the charge trapping layer (4) and the dielectric layer (3) are formed at the same respective temperatures within 50°C.

9. 3. The process of claim 1 or 2, wherein the time during which the dielectric layer (3) is exposed to the carrier gas alone is less than 20 seconds or less than 15 seconds.

10. The process of claim 1 or 2, wherein the charge trapping layer (4) has a thickness of 0.1 to 10 microns.

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