Configurable PAM level read clock toggle

Abstract

The read clock circuit selectively provides a read clock signal from the memory to the memory controller via the memory bus and includes a pulse amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicative of respective digital values. The digital control circuit is coupled to the PAM driver and is operable to cause the PAM driver to provide a preamble signal prior to the read clock signal, the preamble signal including an initial toggle state in which the PAM driver toggles between two selected levels at a first rate and a final toggle state in which the PAM driver toggles between the two selected levels at a second rate higher than the first rate, the length of the initial toggle state and the length of the final toggle state being based on the value in the mode register.

Description

[Background technology]

[0001] Modern dynamic random-access memory (DRAM) provides high memory bandwidth by increasing the speed of data transmission on a bus that connects the DRAM to one or more data processors, such as a graphics processing unit (GPU) or a central processing unit (CPU). DRAM is typically inexpensive and dense, which allows for a large number of DRAMs to be integrated per device. Most DRAM chips sold today conform to various double data rate (DDR) DRAM standards promoted by the Joint Electron Devices Engineering Council (JEDEC). Typically, several DDR DRAM chips are combined on a single printed circuit board to form a memory module that is relatively fast but also offers scalability. However, while these enhancements have improved the speed of DDR memory used for main memory in computer systems, further improvements are required.

[0002] One type of DDR DRAM, known as graphics double data rate (GDDR) memory, has pushed the boundaries of data transmission rates to accommodate the high bandwidth required for graphics applications. As new GDDR standards are developed, they tend to support higher data rates. One technique used to support higher data rates is a multi-level pulse amplitude modulation (PAM) data transmission and reception mode, instead of the traditional two-level transmission system. With more PAM levels, for a given clock speed, the data transmission bandwidth can be increased. However, continuous data transmission at these high speeds results in relatively high power consumption. [Brief description of the drawings]

[0003] [Figure 1] 1 is a block diagram illustrating a data processing system according to some embodiments. [Diagram 2] 2 is a block diagram showing a GDDR PHY-DRAM link of the data processing system of FIG. 1; [Diagram 3] FIG. 4 is a timing diagram of a read clock signal preamble signal according to some embodiments. [Figure 4] FIG. 11 is a timing diagram of a read clock signal preamble signal according to some additional embodiments. [Diagram 5] 1 is a table containing mode register settings for read clock configuration according to some embodiments. [Figure 6] 2 is a timing diagram illustrating the relationship of various signals in a GDDR memory according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] In the following description, the use of the same reference numbers in different figures indicates similar or identical items. Unless otherwise noted, the word "coupled" and its related verb forms include both direct and indirect electrical connections by means well known in the art, and unless otherwise noted, any description of a direct connection also refers to alternative embodiments using a suitable form of indirect electrical connection.

[0005] A read clock circuit for selectively providing a read clock signal from a memory to a memory controller via a memory bus includes a pulse amplitude modulation (PAM) driver, a mode register, and a digital control circuit. The PAM driver includes an input and an output capable of driving at least three levels representing respective digital values. The digital control circuit is coupled to the input of the PAM driver and is operable to cause the PAM driver to provide a preamble signal prior to the read clock signal. The preamble signal includes an initial toggle state in which the PAM driver toggles between two selected levels at a first rate, and a final toggle state in which the PAM driver toggles between the two selected levels at a second rate that is higher than the first rate. The length of the initial toggle state and the length of the final toggle state are based on the value in the mode register.

[0006] A method selectively provides a read clock signal from a memory to a memory controller via a memory bus. The method includes deactivating a pulse amplitude modulation (PAM) driver capable of driving at least three levels indicative of respective digital values ​​for a read clock signal following a memory read. In response to a new memory read, the method includes activating the PAM driver to provide a preamble signal for the read clock signal, the preamble signal including, in turn, at least one static state, an initial toggle state in which the PAM driver toggles between two selected levels at a first rate, and a final toggle state in which the PAM driver toggles between the two selected levels at a second rate higher than the first rate. The method includes determining lengths of at least the initial and final toggle states based on a value in a mode register, and toggling the PAM driver at the second rate to provide the read clock signal following the preamble.

[0007] The data processing system includes at least one processor, a memory controller coupled to the processor via a memory bus, and a dynamic random access memory (DRAM) coupled to the memory controller via the memory bus, the DRAM including a read clock circuit for selectively providing a read clock signal from the memory to the memory controller via the memory bus. The read clock circuit includes a pulse amplitude modulation (PAM) driver, a mode register, and a digital control circuit. The PAM driver includes an input and an output capable of driving at least three levels representing respective digital values. The digital control circuit is coupled to an input of the PAM driver and is operable to cause the PAM driver to provide a preamble signal prior to the read clock signal. The preamble signal includes an initial toggle state in which the PAM driver toggles between two selected levels at a first rate, and a final toggle state in which the PAM driver toggles between the two selected levels at a second rate higher than the first rate. The length of the initial toggle state and the length of the final toggle state are based on a value in the mode register.

[0008] 1 is a block diagram illustrating a data processing system 100 in accordance with some embodiments. Data processing system 100 generally includes data processors in the form of a graphics processing unit (GPU) 110, a host central processing unit (CPU) 120, double data rate (DDR) memory 130, and graphics DDR (GDDR) memory 140.

[0009] GPU 110 is a discrete graphics processor with very high performance for optimized graphics processing, rendering and display, but requires high memory bandwidth to perform these tasks. GPU 110 generally includes a set of command processors 111, a graphics single instruction, multiple data (SIMD) core 112, a set of caches 113, a memory controller 114, a DDR physical interface circuit (DDR PHY) 117, and a GDDR PHY 118.

[0010] Command processor 111 is used to interpret high-level graphics instructions such as those specified in the OpenGL programming language. Command processor 111 has a bidirectional connection to memory controller 114 for receiving high-level graphics instructions such as OpenGL instructions, a bidirectional connection to cache 113, and a bidirectional connection to graphics SIMD core 112. In response to receiving the high-level instructions, command processor issues low-level instructions for rendering, geometric processing, shading, and rasterization of data such as frame data, using cache 113 as temporary storage. In response to the graphics instructions, graphics SIMD core 112 executes the low-level instructions on large data sets in a massively parallel manner. Command processor 111 and cache 113 are used for temporary storage of input data and output (e.g., rendered and rasterized) data. Cache 113 also has a bidirectional connection to graphics SIMD core 112 and a bidirectional connection to memory controller 114.

[0011] The memory controller 114 has a first upstream port connected to the command processor 111, a second upstream port connected to the cache 113, a first downstream bidirectional port to the DDR PHY 117, and a second downstream bidirectional port to the GDDR PHY 118. As used herein, the "upstream" port is the side of the circuitry towards the data processor and away from the memory, and the "downstream" port is in the direction away from the data processor and towards the memory. The memory controller 114 controls the timing and sequencing of data transfers between the DDR memory 130 and the GDDR memory 140. DDR and GDDR memories have asymmetric access, i.e., access to open pages in the memory is faster than access to closed pages. The memory controller 114 stores memory access commands and processes them out of order for efficiency, for example, by prioritizing access to open pages while adhering to certain quality of service targets.

[0012] The DDR PHY 117 has an upstream port connected to a first downstream port of the memory controller 114 and a downstream port bidirectionally connected to the DDR memory 130. The DDR PHY 117 meets all specified timing parameters of a version of the DDR memory 130, such as DDR version 5 (DDR5), and performs timing calibration operations at the direction of the memory controller 114. Similarly, the GDDR PHY 118 has an upstream port connected to a second downstream port of the memory controller 114 and a downstream port bidirectionally connected to the GDDR memory 140. The GDDR PHY 118 meets all specified timing parameters of a version of the GDDR memory 140, and performs timing calibration operations at the direction of the memory controller 114.

[0013] The GDDR memory 140 includes a set of mode registers 141 programmable on the GDDR PHY 118 to configure the GDDR memory 140 for operation. In particular, as described herein, the read clock (RCK) that the GDDR memory 140 provides to the GDDR PHY 118 can be programmed to operate in certain new and advantageous ways. According to some embodiments, the read clock can be configured to operate in a "read-only" mode on the RCK signal to conserve power by not toggling continuously, but instead to start toggling during the read preamble period prior to the data transmission of a read command and continue toggling at least until the end of the read postamble period following the read command. The read-only mode provides the ability to reduce power consumption during workloads where read operations are or may be infrequent. The read clock RCK can also be programmable to operate in an "always-on" mode where the GDDR memory 140 provides the RCK signal continuously as long as a write clock (WCK) is received from the host (e.g., the memory controller or memory PHY of the host processor chip). The always-on mode provides the ability for the host processor PHY to remain locked and avoid the need for resynchronization during the preamble. Certain techniques for controlling the RCK preamble are provided below in connection with an RCK operable in these two modes, but these techniques are also applicable to the preamble of an RCK circuit that does not have a read-only mode in various embodiments.

[0014] During operation, the data processing system can be used as a graphics card or accelerator due to the high bandwidth graphics processing performed by the graphics SIMD cores 112. The host CPU 120, which runs an operating system or application programs, sends graphics processing commands to the CPU 110 through the DDR memory 130, which serves as a unified memory for the GPU 110 and the host CPU 120. It may send commands to the GPU interface, for example, using OpenGL commands or through any other host CPU. OpenGL is a cross-language, cross-platform application programming interface for rendering 2D and 3D vector graphics developed by the Khronos Group. The host CPU 120 interacts with the GPU 110 using an application programming interface (API) to provide hardware accelerated rendering.

[0015] Data processing system 100 uses two types of memory. The first type of memory is DDR memory 130, which is accessible by both GPU 110 and host CPU 120. As part of the high performance of graphics SIMD core 112, GPU 110 uses high speed graphics double data rate (GDDR) memory.

[0016] 2 is a block diagram of a GDDR PHY-DRAM link 200 of the data processing system 100 of FIG. 1 according to some embodiments. The GDDR PHY-DRAM link 200 includes the GPU 110 and a portion of the GDDR memory 140 communicating via a physical interface 260.

[0017] GPU 110 includes a phase locked loop (PLL) 210, a command and address ("C / A") circuit 220, a read clock circuit 230, a data circuit 240, and a write clock circuit 250. These circuits form part of GDDR PHY 118 of GPU 110.

[0018] The phase-locked loop 210 operates as a reference clock generating circuit and generates a clock signal “CK IN ” and an output.

[0019] C / A circuit 220 includes a delay element 221, a selector 222, and a transmit buffer 223 labeled "TX." Delay element 221 has an input connected to the output of PLL 210, an output, and has a variable delay controlled by an input not specifically shown in FIG. 2. Selector 222 has a first input for receiving a first command / address value, a second input for receiving a second command / address value, and a control input connected to the output of delay element 221. Transmitter 223 has an input connected to the output of selector 222 and an output connected to a corresponding integrated circuit terminal for providing a command / address signal labeled "C / A." C / A circuit 220 includes a set of individual buffers for each signal in the C / A signal group, configured in the same manner as the exemplary selector 222 and buffer 223 shown in FIG. 2, although it should be noted that only the exemplary C / A circuit 220 is shown.

[0020] Read clock circuit 230 includes a receive buffer 231, labeled "RX," and a selector 232. Receive buffer 231 has an input connected to a corresponding integrated circuit terminal for receiving a signal labeled "RCK," and an output. Receive clock selector 232 has a first input connected to the output of PLL 210, a second input connected to the output of receive buffer 231, an output, and a control input for receiving a mode signal, not shown in FIG.

[0021] Data circuit 240 includes a receive buffer 241, a latch 242, delay elements 243 and 244, a serializer 245, and a transmit buffer 246. Receive buffer 241 has a first input connected to an integrated circuit terminal that receives a data signal generally labeled "DQ" and a second input connected to an integrated circuit terminal that receives a data signal generally labeled "V REF Latch 242 is a D-type latch having an input labeled "D" connected to the output of receive buffer 241, a clock input, and an output labeled "Q" for providing an output data signal. The interface between GDDR PHY 118 and GDDR memory 140 implements a four-level Pulse Amplitude Modulation data signaling system known as "PAM-4" which encodes two data bits into one of four nominal voltage levels. Thus, receive buffer 241 identifies which of the four levels is indicated by the input voltage and outputs two data bits representing a state accordingly. For example, receive buffer 241 may have V 100, V 200, V 300 defining four voltage ranges. REF Based on the three slicing levels, three comparators can be used to determine which range the received data signal falls into. Data circuit 240 includes a latch that latches two data bits and is replicated for each bit position. Delay element 243 has an input connected to the output of selector 232 and an output connected to the clock input of latch 242. Delay element 244 has an input connected to the output of PLL 210 and an output. Serializer 245 has an input for receiving a first data value for a given bit position and a second data value for a given bit position corresponding to successive cycles of the burst, a control input connected to the output of delay element 244, and an output connected to a corresponding DR terminal. Each data byte of the data bus has a set of data circuits such as data circuit 240 for each bit of the byte. This replication allows different data bytes with different routing on the printed circuit board to have different delay values.

[0022] Write clock circuit 250 includes a delay element 251, a selector 252, and a transmit buffer 253. Delay element 251 has an input connected to the output of PLL 210 and an output. Selector 252 has a first input for receiving a first clock state signal, a second input for receiving a second clock voltage, a control input connected to the output of delay element 251, and an output. Transmit buffer 253 has an input connected to the output of selector 252, a first output connected to a corresponding integrated circuit terminal for providing a true write clock signal labeled "WCK_t" and a second output connected to a corresponding integrated circuit terminal for providing a complementary write clock signal labeled "WCK_c."

[0023] GDDR memory 140 generally includes write clock receiver 270, command / address receiver 280, and data path transceiver 290. Write clock receiver 270 includes receive buffer 271, buffer 272, divider 273, buffer / tree 274, and divider 275. Receive buffer 271 has a first input connected to an integrated circuit terminal of GDDR memory 140 that receives a WCK_t signal, a second input connected to an integrated circuit terminal of GDDR memory 140 that receives a WCK_c signal, and an output. In the example shown in FIG. 2, the output of receive buffer 271 is a clock signal having a nominal frequency of 8 GHz. Buffer 272 has an input connected to the output of receive buffer 271 and an output. Divider 273 has an input connected to the output of buffer 272 and an output for providing a divided clock having a nominal frequency of 4 GHz. Divider 275 has an input connected to the output of buffer / tree 274, and an output for providing a clock signal labeled "CK4" having a nominal frequency of 2 GHz.

[0024] The command / address receiver 280 includes a receiving buffer 281 and a slicer 282. The receiving buffer 281 has a first input connected to a corresponding integrated circuit terminal of the GDDR memory 140 that receives the C / A signal, and a second input connected to a V REFIt has a second input for receiving and an output. The C / A input signal is received as a normal binary signal having two logic state levels and is regarded as non-return-to-zero (NRZ) signal encoding. The slicer 282 has a set of two data latches, each having a D input connected to the output of the receive buffer 281, a clock input for receiving the corresponding output of the divider 275, and a Q output for providing the corresponding C / A signal.

[0025] The data path transceiver 290 includes a read clock circuit 285, a serializer 293, a transmitter 294, a receive buffer 295, and a slicer 296. The serializer 293 has an input for receiving a first read data value, a second input for receiving a second data value, a select input connected to the output of the buffer / tree 274, and an output connected to the DQ terminal of the GDDR memory 140. The transmitter 294 has an input connected to the output of the serializer 293 and an output connected to the corresponding DQ terminal of the GDDR memory 140. The receive buffer 295 has a first input connected to the corresponding DQ terminal of the GDDR memory 140, a second input for receiving a V REF value, and an output. The slicer 296 has a set of four data latches, each having a D input connected to the output of the receive buffer 295, a clock input connected to the output of the buffer / tree 274, and a Q output for providing the corresponding DQ signal.

[0026] The read clock circuit 285 includes a read clock control circuit 291, a transmitter 292, and a mode register 298. The read clock control circuit 291 has an input connected to the mode register 298, an input connected to the output of the buffer / tree 274, and an output. The transmitter 292 has an input connected to the output of the serializer 291 and an output connected to the RCK terminal of the GDDR memory 140, and provides a read clock signal "RCK", which hereinafter refers to the signal and the illustrated terminal at which it is driven. The transmitter 292 is a PAM driver capable of driving three or more PAM levels. In operation, the read clock control circuit 291 controls the transmitter 292 to provide a preamble signal prior to the read clock signal RCK. As will be further described below, the preamble signal includes an initial toggle state in which the PAM driver toggles between two selected levels at a first rate, and a final toggle state in which the PAM driver toggles between two selected levels at a second rate that is higher than the first rate. The length of the initial toggle state and the length of the final toggle state are based on the value in mode register 298 .

[0027] The interface 260 includes a set of physical connections routed from the bond pads of the GPU 110 die, through the package impedance to the package terminals, through traces on the printed circuit board to the package terminals of the GDDR memory 140, and back through the package impedance to the bond pads of the GDDR memory 140 die.

[0028] 3 is a timing diagram of a read clock signal preamble signal 300 according to some embodiments. The vertical axis shows a signal level selected from among the four illustrated PAM4 levels labeled -3, -1, +1, and +3, which in this embodiment correspond to voltage levels between the signaling voltage supply level and 0 volts. Note that the PAM level labels are simply a convention for referencing the PAM levels, and another common convention uses a binary scheme of 00, 01, 10, 11 to refer to the same levels. The actual levels are typically analog voltage levels that are adjusted by a driver during operation and vary depending on the supply voltage. The horizontal axis shows time. In general, the preamble signal helps the PAM receiver begin to receive the read clock signal so that the receiver on the memory controller PHY can synchronize with the read data signal.

[0029] The preamble signal 300 is transmitted following a period during which the RCK signal is inactivated. In response to a new read command, the RAM (in this example, a GDDR memory, such as the GDDR memory 200 of FIG. 2) activates a PAM driver for RCK and provides the preamble signal 300 for the read clock signal. The preamble signal 300 includes, in order, two static states 302 and 304, an initial toggle state 306, a final toggle state 308, and a clock running state 310.

[0030] In this example preamble signal, two static states 302 and 304 are used, although other preamble signals may include only one static state. In the initial static state 302, the PAM4 driver is held at the highest PAM4 level for a period of two clock cycles relative to the final frequency of the internal memory clock. In this example, the internal memory clock is the GDDR memory's internal "CK4" clock, which is generated from the "WCK" write clock on the memory channel, for example at a frequency ¼ that of WCK. The initial static state 302 lasts for two cycles of the CK4 clock, but can be programmed to be longer or shorter, as described below.

[0031] In the static state 304, the PAM4 driver is driven to its lowest level, typically a 0V level, which is designated as the "-3" level in this embodiment, and the static state 304 lasts for two cycles of the CK4 clock in this example.

[0032] Following the static state 304, the preamble signal 300 includes an initial toggle state 306 in which the PAM4 driver toggles between two selected levels at a first rate. In this example, the toggle rate is twice the CK4 clock rate, i.e., half the MCK clock rate. The preamble signal 300 then transitions to a final toggle state 308 in which the PAM4 driver toggles between two selected levels at a second rate that is higher than the first rate. While in the final toggle state 308, the PAM4 receiver can stabilize reception of the RCK clock signal.

[0033] Following the final toggle state 308, the RCK clock signal transitions from the preamble to an RCK clocked state where the RCK clock signal is provided in a clocked state 310. Preferably, the frequency of the RCK clock signal is the same as the toggle rate used in the final toggle state 308.

[0034] 4 is a timing diagram of a read clock signal preamble signal 400 according to some additional embodiments. The diagram is similarly structured to FIG. 4. The illustrated preamble signal 400 shows an example of some ways in which the preamble signal may be altered by settings in the mode register 141. The preamble signal 400 includes, in order, two static states 402 and 404, an initial toggle state 406, a final toggle state 408, and a clock running state 410.

[0035] In the preamble signal 400, the timing of the various states is similar to that of FIG. 4, but the PAM4 levels used are different. In this example, different values ​​are set for the two selected levels 420 and 430 used while in the toggle state based on the value in the mode register 141. The static state 404 is set to the −1 PAM4 level while the static state 402 is set to the +3 PAM4 level, and in the toggle states 406 and 408, the preamble signal 400 toggles between PAM4 levels −1 and +1 as shown. Finally, in the clock running state, the RCK clock signal toggles between PAM4 levels −1 and +1.

[0036] The two selected levels are based on the value in the mode register 298. In this embodiment, a limited set of levels is configurable for the pairs of PAM levels, as described below with respect to FIG. 5, but in other embodiments, the settings in the mode register 298 can configure any pair of PAM levels to be used in any of the states 402, 404, 406, 408, 410. Different pairs of PAM levels can be used in different states. Preferably, the two selected levels in the final toggle state 408 are the levels used for the read clock signal during a read operation in state 410. The two selected levels during the initial toggle state 406 can be different from those in the final toggle state. In this example preamble signal 400, only the initial and final toggle states are used, but additional toggle states can be used to speed up the toggle rate between the initial toggle state 406 and the final toggle state 408.

[0037] In this embodiment, the PAM driver used (FIG. 2, 292) is a PAM-4 driver capable of driving four levels representing respective 2-bit digital values ​​for a signaling supply voltage of 1.2 volts, making the identified levels of -3, -1, +1, +3 approximately 0V, 0.4V, 0.8V, 1.2V, respectively. Preferably, the signaling levels may be adjusted to conserve power, providing a lower maximum level (+3), with the other levels being reduced accordingly. In other embodiments, other PAM drivers such as PAM-6 or PAM-8 are used. In general, the techniques herein are suitable for use with any PAM driver capable of driving three or more voltage levels.

[0038] Figure 5 shows a table 500 illustrating mode register settings for the read clock mode of the memory of Figure 2. Table 500 shows the values ​​of different bits or bit fields of a 12-bit mode register, the 12 bits corresponding to the address signals into which the mode register is loaded. Table 500 has six columns including an OP code (operation code) column that corresponds to particular bits of the mode register, a function column that identifies the function defined by the corresponding bits, an OP code value column that specifies different values ​​of the OP code, and a description column that identifies the meaning of the different OP code values.

[0039] Mode register bits [1:0] are labeled "RCKMODE" and identify the selected RCK mode. A value of 00b (binary) identifies a disabled mode in which RCK is not provided by memory 200. This mode is the default mode.

[0040] A value of 01b indicates read-only mode. As explained further below, in read-only mode, the RCK is provided during one or more read cycles, with each read cycle including both a preamble and a postamble. When read-only mode is selected, the interamble behavior is such that successive reads are greater than a minimum interval amount, i.e., at least t CCD +1 RCK cycles, where t CCDis the minimum inter-command delay. In general, during read data mode, RCK starts the preamble period before the transfer of data in a read cycle and ends the preamble period after the read cycle. In particular, it starts toggling simultaneously with data transfer for read command (RD), read with auto-precharge command (RDA), and read training (RDTR) commands. It stops on a clear condition. In some embodiments, the clear condition includes receipt of a write command (write command (WR), write with auto-precharge command (WRA), write training (WRTR) command), receipt of an all-banks idle indicator, or entry into a power down state.

[0041] A value of 10b indicates an always-running mode, in which the RCK runs continuously as long as the WCK used to generate the RCK is received by memory 200.

[0042] The value of 11b is reserved (RSVD) but allows the definition of new modes that provide an RCK signal to be added in the future using this mode register structure.

[0043] Mode register bit [2] defines the read clock type (RCKTYPE). A value of 0b indicates that the GDDR memory 200 provides the RCK signal as a single-ended signal, i.e.

[0044]

number

[0045]

number

[0046] Mode register bits [4:3] define the length of the static preamble period. To allow the memory controller to lock onto the preamble, each preamble period has a static period, a slow period, and a fast period. In the example preamble signals of Figures 3 and 4, static states 304 and 404 represent the static period, initial toggle states 306 and 406 represent the slow period, and final toggle states 308 and 408 represent the fast period. During the static period, the read clock signal is driven in its inactive state, i.e., RCK is driven low, and

[0047]

number

[0048] Mode register bit [5] defines the RCK level setting (RCKLEVEL), which in this example provides two possible value pairs for the RCK level during the RCK preamble and RCK operation. A value of 0b defines a value of +3 / -3 for the PAM driver of the RCK signal, and a value of 1b defines a value of +1 / -1. Although these value pairs are shown as examples, in various embodiments, configuration settings can be used to program any desired value pair, including defining different value pairs for each phase of the preamble.

[0049] Mode register bits [7:6] define the length of the fast preamble period. A value of 00b indicates a fast preamble period of 0 clock cycles, i.e. no fast preamble period. Values ​​of 01b, 10b and 11b define static periods of 2, 4 and 6 cycles, respectively.

[0050] Mode register bit [8] is undefined and reserved for future use (RFU).

[0051] Mode register bits [10:9] define the length of the slow preamble period. A value of 00b indicates a slow preamble period of 0 clock cycles, i.e. no slow preamble period. Values ​​of 01b, 10b and 11b define static periods of 1, 2 and 3 cycles. Note that the fast and slow preamble periods are independently programmable, but if the OP code bits [7:6] and [10:9] have the same value, then the fast and slow preambles are the same length of time.

[0052] Mode register bit

[11] is not defined and is marked as RFU.

[0053] It should be apparent that these mode register encodings are just one possible way to encode these values, and that other encodings are possible. For example, instead of using a dedicated mode register, these bits could be distributed among multiple mode registers, e.g., in otherwise unused or reserved bit positions. Furthermore, the selection of available values ​​for the static preamble, slow preamble, and fast preamble is somewhat arbitrary and may vary in different embodiments.

[0054] 6 illustrates a timing diagram 600 showing the relationship of various signals in a GDDR memory, according to some embodiments. Diagram 600 includes a set of data signals including an internal memory clock signal labeled "CK4," a write clock signal labeled "WCK," a command signal labeled "CMD," a read clock signal RCK, and data bus inversion signals labeled "DQ[7:0], DBI." The horizontal axis represents time and the vertical axis represents the amplitude of the various signals in volts.

[0055] Diagram 600 illustrates an exemplary sequence in which a read command 602 is received at a memory having an RCK configured as described above in a read-only mode. The CK4 signal is generated based on the received WCK signal, in a ratio of 4:1 in this embodiment. For example, if WCK is 8 Ghz, then CK4 is 2 Ghz. The dashed lines indicate low-to-high transitions of the CK4 signal, corresponding to various time points labeled T0-T11. Diagram 600 illustrates active command encoding for the COMMAND signal, and no operational cycles are shown.

[0056] In the exemplary scenario shown in timing diagram 600, mode register 300 is programmed for RCKMODE=read only, RCKTYPE=single-ended, RCKPRE_Static=2, RCKPRE_LS=2, RCKPRE_HS=1, and RCKLEVEL=1. Diagram 600 illustrates the issuance of a read command labeled "READm" at time T0. Due to read latency, memory 200 does not provide read data until time T8. During this time, the RCK signal includes a preamble defined by the configuration settings in mode register 298 according to FIG. 5, activating a read clock to provide signal RCK, allowing a receiver in the memory controller to synchronize with the RCK signal in an efficient manner.

[0057] In response to the read command READm received at time T0, the RCK driver must first be enabled. As indicated by the time "tRCKEN", a time of two cycles of CK4 is required to enable the RCK clock driver. During this time, the output of the RCK driver (e.g., 292 in FIG. 2) is undefined, but is typically expected to be high, as indicated by RCK from T0 to T3.

[0058] At time T3, the static period begins with the RCK signal driven at a -1 level. The length of this static period is controlled by the RCKPRE_Static setting in the mode register. In this example, the length is two cycles of CK4.

[0059] At time T5, an initial toggle period begins, with the length controlled by the RCKPRE_LS setting. During this period, RCK toggles between two selected levels, +1 and -1, at twice the rate of CK4 and half the rate of WCK. Although this toggle rate is shown, other toggle rates can be used. Typically, the toggle in the initial toggle period is slower than the final toggle rate to help the PAM receiver lock onto the RCK signal.

[0060] At time T7, a final toggle period begins, with the length controlled by the RCKPRE_HS setting. The toggle rate during this period is preferably the same as the RCK toggle rate following the preamble, which in this example is the rate of the WCK. Other rates, such as half the WCK rate, could be used. Note that in this example the same pair of levels is used in both toggle periods of the preamble, but different levels could be used.

[0061] At time T8, the final toggle period ends and the preamble is completed. At this time, RCK continues to toggle at the rate of WCK, and the PAM of the RCK signal is synchronized to the RCK signal. As seen in the DQ[7:0], DBI signals, the read command is filled with data sent to the memory controller during two cycles of CK4, in this example, from T8 to T10. The PAM receiver for each data line of the data channel used in the read operation is clocked using the received RCK signal. Following T10, RCK may continue to operate for the transmission of data, such as metadata, via the DQE signal, and the receiver in the memory controller for the DQE signal also uses RCK for synchronization. In some embodiments, during the read-only mode, the RCK signal may continue to toggle as a read clock for multiple sequential read commands.

[0062] Other relevant events may also occur on the GDDR memory during the preamble, for example, in embodiments using switchable on-die termination (ODT), the ODT may be switched from enabled to disabled during the slow toggle period.

[0063] Thus, the techniques disclosed herein may be used to improve data transmission bandwidth by transmitting non-binary symbols, i.e., symbols with more than two states per clock edge. It is believed that noise mitigation techniques may enable reception of PAM4 in systems that are otherwise not robust enough to decode the four voltage levels used in PAM4 symbols at existing clock rates. According to the disclosed embodiments, a memory transmits an RCK signal with a preamble having programmable PAM levels and durations, allowing for different system characteristics and greater flexibility in receiver design.

[0064] An integrated circuit or integrated circuits including the reference voltage generating circuit described herein or any portion thereof may be described or represented by a computer-accessible data structure in the form of a database or other data structure that may be read and used by a program to directly or indirectly manufacture the integrated circuit. For example, the data structure may be a behavioral level description or a register-transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that can synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware that includes the integrated circuit. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture the integrated circuit. Alternatively, the database on the computer-accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, if desired.

[0065] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, various PAM driver designs may be used with different numbers of PAM levels. Furthermore, various methods of configuring the read clock driver control circuitry may be used to achieve the desired configurability. The disclosed techniques are applicable to a wide variety of integrated circuits that use high speed data transmission. In one particular example, one integrated circuit may be a data processor, system-on-chip (SOC) or graphics processing unit (GPU), and the other integrated circuit is a DDR or GDDR SDRAM, although the techniques described herein may be used with many other types of integrated circuits. Also, the transmission medium may vary between embodiments and may include printed circuit board traces, bond wires, through-silicon vias (TSV), etc.

[0066] Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. a read clock circuit for selectively providing a read clock signal from a memory to a memory controller via a memory bus, the read clock circuit comprising: a pulse amplitude modulated multilevel (PAM) driver including inputs and outputs capable of driving at least three levels representing respective digital values; A mode register; a digital control circuit coupled to an input of the PAM driver and operable to cause the PAM driver to provide a preamble signal prior to the read clock signal, the preamble signal including an initial toggle state in which the PAM driver toggles between two selected levels at a first rate and a final toggle state in which the PAM driver toggles between the two selected levels at a second rate that is faster than the first rate; the length of the initial toggle state and the length of the final toggle state are based on the value of the mode register. Read clock circuit.

2. the two selected levels being based on one or more values ​​of the mode register; 2. The read clock circuit of claim 1.

3. the digital control circuitry is operable to cause the PAM driver to provide at least one static state in the preamble prior to the initial toggle state.

2. The read clock circuit of claim 1.

4. the two selected levels in the final toggle state are levels to be used for the read clock signal during the read operation.

2. The read clock circuit of claim 1.

5. the two selected levels in the initial toggle state are different from the levels in the final toggle state; 2. The read clock circuit of claim 1.

6. the digital control circuitry is configurable to include a second toggle state between the initial toggle state and the final toggle state, the second toggle state toggling at a rate between the initial toggle state and the final toggle state.

2. The read clock circuit of claim 1.

7. 1. A method for selectively providing a read clock signal from a memory to a memory controller over a memory bus, comprising: deactivating a pulse amplitude modulation (PAM) driver capable of driving at least three levels indicative of respective digital values ​​for a read clock signal following a memory read; activating the PAM driver in response to a new memory read and providing a preamble signal for a read clock signal, the preamble signal including, in sequence, at least one static state, an initial toggle state in which the PAM driver toggles between two selected levels at a first rate, and a final toggle state in which the PAM driver toggles between two selected levels at a second rate that is higher than the first rate; determining a length of at least the initial toggle state and the final toggle state based on a value in a mode register; following the preamble, toggling the PAM driver at the second rate to provide the read clock signal. method.

8. the two selected levels being based on one or more values ​​of the mode register; The method of claim 7.

9. providing at least one static state in the preamble prior to the initial toggle state. The method of claim 7.

10. the two selected levels in the final toggle state are levels to be used for the read clock signal during a read operation. The method of claim 7.

11. the two selected levels in the initial toggle state are different from the levels in the final toggle state; The method of claim 7.

12. providing a second toggle state between the initial toggle state and the final toggle state, the second toggle state toggling at a rate between the initial toggle state and the final toggle state. The method of claim 7.

13. The PAM driver is capable of driving four levels representing respective 2-bit digital values ​​for a signaling supply voltage of 1.2 volts. The method of claim 7.

14. a toggle rate of the read clock is based on a toggle rate of a write clock received at the memory from the memory controller. The method of claim 7.

15. 1. A data processing system comprising: At least one processor; a memory controller coupled to the processor via a memory bus; a dynamic random access memory (DRAM) coupled to said memory controller via a memory bus, said DRAM including a read clock (strobe) circuit for selectively providing a read clock signal from said memory to said memory controller via said memory bus; The DRAM includes: a pulse amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels representing respective digital values; A mode register; a digital control circuit coupled to an input of the PAM driver, the digital control circuit operable to cause the PAM driver to selectively provide the read clock signal during a read operation and to cause the PAM driver to provide a preamble signal prior to the read clock signal, the preamble signal including an initial toggle state where the PAM driver toggles between two selected levels at a first rate and a final toggle state where the PAM driver toggles between the two selected levels at a second rate that is faster than the first rate; the length of the initial toggle state and the length of the final toggle state are based on the value of the mode register. Data processing system.

16. the two selected levels being based on one or more values ​​of the mode register; 16. The data processing system of claim 15.

17. the digital control circuitry is operable to cause the PAM driver to provide at least one static state in the preamble prior to the initial toggle state.

16. The data processing system of claim 15.

18. the two selected levels in the final toggle state are levels to be used for the read clock signal during the read operation.

16. The data processing system of claim 15.

19. the two selected levels in the initial toggle state are different from the levels in the final toggle state; 16. The data processing system of claim 15.

20. the digital control circuitry is configurable to include a second toggle state between the initial toggle state and the final toggle state, the second toggle state toggling at a rate between the initial toggle state and the final toggle state.

16. The data processing system of claim 15.

Images