Fabrication of semiconductor devices including quantum dot structures

Abstract

The present invention relates to a method for manufacturing a semiconductor device. The method comprises providing a cavity structure including a seed region having a seed material. The method further comprises growing a quantum dot structure in the cavity structure in a first growth direction from a seed surface of the seed material and growing a first burying layer in the first growth direction on the first surface of the quantum dot structure. The method further comprises removing the seed material and growing a second burying layer in the cavity structure in a second growth direction on a second surface of the quantum dot structure. The second surface of the quantum dot structure is different from the first surface of the quantum dot structure and the second growth direction is different from the first growth direction. The present invention further relates to a device obtained by such a method.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention generally relate to methods for fabricating semiconductor devices including quantum dot structures, and further to devices obtained by such methods. [Background technology]

[0002] Integrated quantum optics has generated a lot of interest for optical quantum computing, with first proof-of-principle experiments demonstrating qubit operations using photons.

[0003] Key devices in optical computing are single-photon sources and detectors. First devices have been demonstrated, but scalable and highly controlled processes are needed. Single-photon detectors based on superconducting nanowire technology are well established, but there is growing interest in scaled devices that can operate at temperatures higher than ambient, e.g., especially at room temperature.

[0004] Single-photon devices are often based on materials incorporating single quantum dots. To achieve efficient single-photon manipulation and to fabricate more advanced devices, precise alignment of the quantum dots is crucial. Therefore, fabrication techniques are needed that allow precise fabrication of quantum dot structures in semiconductor material systems.

[0005] Quantum dots are semiconductor particles fabricated on the nanoscale that can transport electrons. Quantum dots have different electrical and optical properties than larger particles due to quantum mechanics. Summary of the Invention

[0006] According to a first aspect, the invention is embodied in a method for manufacturing a semiconductor device. The method includes providing a cavity structure, the cavity structure including a seed region including a seed material. The method further includes growing a quantum dot structure in the cavity structure in a first growth direction from a seed surface of the seed material, and growing a first burying layer in the first growth direction on the first surface of the quantum dot structure. The method further includes removing the seed material, and growing a second burying layer in the cavity structure in a second growth direction on a second surface of the quantum dot structure. The second surface of the quantum dot structure is different from the first surface of the quantum dot structure, and the second growth direction is different from the first growth direction.

[0007] According to an embodiment of a further aspect of the present invention there is provided a semiconductor device obtainable by a method according to the first aspect.

[0008] According to an embodiment of a further aspect of the present invention, there is provided a semiconductor device including a quantum dot structure and a first burying layer epitaxially grown on a first surface of the quantum dot structure. The semiconductor device further includes a second burying layer epitaxially grown on a second surface of the quantum dot structure. The first surface of the quantum dot structure and the second surface of the quantum dot structure are disposed opposite each other.

[0009] According to one embodiment of a further aspect of the present invention, the proposed semiconductor structure may be arranged within a resonant structure, such as a photonic crystal lattice, to provide enhanced light emission in a resonant mode.

[0010] According to one embodiment of a further aspect of the invention, the proposed semiconductor structures can be configured to allow for easy input or output coupling of light to waveguides and other passive structures.

[0011] The steps of the first aspect of the invention may be carried out in a different order as appropriate. Importantly, the growth of the QDs may be carried out in a step immediately prior to the growth of the second buried layer. This may reduce the effects of lattice mismatch from the seed layer.

[0012] Moreover, steps may also be combined where appropriate, that is, for example, two or more steps may be performed together.

[0013] Advantages of a feature of one aspect of the invention may be applied to a corresponding feature of another aspect of the invention.

[0014] Embodiments of the invention will now be described in more detail, by way of illustrative and non-limiting examples, with reference to the accompanying drawings, in which:

[0015] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments, which are to be taken in conjunction with the accompanying drawings, in which: Since the illustrations are for clarity in order to facilitate those skilled in the art in understanding the invention together with the detailed description, various features of the drawings are not to scale. [Brief description of the drawings]

[0016] [Figure 1a] 2A-2C are enlarged top views of an initial structure formed during a stage of a manufacturing method according to an embodiment of the present invention. [Figure 1b] 1A-1C are enlarged top views of intermediate structures formed during stages of a manufacturing method according to an embodiment of the present invention. [Figure 1c] 1A-1C are enlarged top views of intermediate structures formed during stages of a manufacturing method according to an embodiment of the present invention. [Figure 1d] 1A-1C are enlarged top views of intermediate structures formed during stages of a manufacturing method according to an embodiment of the present invention. [Figure 1e] 1A-1C are enlarged top views of intermediate structures formed during stages of a manufacturing method according to an embodiment of the present invention. [Figure 1f]1A-1C are enlarged top views of intermediate structures formed during stages of a manufacturing method according to an embodiment of the present invention. [Figure 1g] 1A-1C are enlarged top views of intermediate structures formed during stages of a manufacturing method according to an embodiment of the present invention. [Figure 1h] 1A-1C are enlarged top views of intermediate structures formed during stages of a manufacturing method according to an embodiment of the present invention. [Figure 1i] 1A-1C are enlarged top views of intermediate structures formed during stages of a manufacturing method according to an embodiment of the present invention. [Figure 1j] 1A-1C are enlarged top views of the final structure formed during stages of a manufacturing method according to an embodiment of the present invention. [Figure 2a] 1b is a corresponding enlarged cross-sectional view of a structure corresponding to FIG. 1a. FIG. [Figure 2b] 1b is a corresponding enlarged cross-sectional view of a structure corresponding to FIG. [Figure 2c] 1c , a corresponding enlarged cross-sectional view of the structure; FIG. [Figure 2d] FIG. 1C is a corresponding enlarged cross-sectional view of the structure corresponding to FIG. [Figure 2e] 1c is a corresponding enlarged cross-sectional view of a structure corresponding to FIG. 1e. FIG. [Figure 2f] 1f is a corresponding enlarged cross-sectional view of the structure corresponding to FIG. [Figure 2g] 1g is a corresponding enlarged cross-sectional view of a structure corresponding to FIG. [Figure 2h] 1c is a corresponding enlarged cross-sectional view of the structure corresponding to FIG. [Figure 2i] FIG. 1b is a corresponding enlarged cross-sectional view of the structure corresponding to FIG. [Figure 2j] 1c is a corresponding enlarged cross-sectional view of the structure corresponding to FIG. 1j. [Diagram 3] 3 is a flow diagram of method steps of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] First, some general aspects and terminology of embodiments of the present invention will be described with reference to FIGS.

[0018] In any or all of the figures, dimensions may not be drawn to scale and may be shown in a simplified schematic form to illustrate features and principles of embodiments of the present invention.

[0019] "Cavity" herein refers to a template-covered hollow space in which quantum dots (QDs) and embedding layers can be grown. This should not be confused with the resonant cavities used to fabricate lasers or other resonant devices, although "cavities" may be integrated into such resonant structures.

[0020] The terms "top" and "above" are used in this context, as is customary, to denote an orientation or relative position perpendicular or orthogonal to the surface of the substrate, in particular in the vertical z-direction.

[0021] The terms "lateral" or "laterally" are used in this context, as is conventional, to denote an orientation generally parallel to the plane of the substrate, as opposed to generally perpendicular or outward from the substrate surface.

[0022] The term "disposed on a semiconductor substrate" should be understood in a broad sense, and in particular includes embodiments in which an intermediate layer, e.g., an insulating layer, is disposed between the substrate and the photonic crystal structure. Thus, the term "disposed on a substrate" is intended to include the meaning "above the substrate."

[0023] Methods according to embodiments of the invention allow for the fabrication of quantum dot structures, in particular localized quantum dots, in integrated active semiconductor devices, in particular on silicon or silicon-on-insulator (SOI).

[0024] An embodiment of the present invention performs a two-step epitaxial growth process in a cavity structure, whereby a semiconductor material, particularly a III-V semiconductor material, is grown on opposite sides of a quantum dot structure, allowing the quantum dot structure to be precisely positioned within the embedded material, which may in particular be a semiconductor material, particularly a III-V semiconductor material.

[0025] According to an embodiment, the growth of the quantum dot structure is performed immediately before the growth of the second burying layer, which can reduce the effects of lattice mismatch from the seed layer.

[0026] Methods according to embodiments of the present invention may enable the fabrication of scaled single photon detectors or emitters.

[0027] 1a-1j show enlarged top views of initial, intermediate and final structures formed during stages of a manufacturing method according to an embodiment of the present invention.

[0028] 2a-2j show corresponding enlarged cross-sectional views of structures corresponding to FIGS. 1a-1j.

[0029] FIG. 1a shows a top view of the initial structure 101, and FIG. 2a shows a corresponding cross-sectional view.

[0030] The initial structure 101 includes a substrate 120. The substrate 120 includes a conductive material and may be, for example, a bulk semiconductor substrate. The substrate 120 may be embodied as a crystalline semiconductor or a compound semiconductor wafer with a larger diameter. The substrate may include, for example, a material from group IV of the periodic table as a semiconductor material. Group IV materials include, for example, silicon (Si), germanium (Ge), a mixture of silicon and germanium, a mixture of silicon and carbon (C), a mixture of silicon, germanium and carbon, etc. For example, the substrate 120 may be a crystalline silicon wafer used in the semiconductor industry. In the following exemplary description, it is assumed that the substrate includes silicon (Si), which is indicated by vertical stripes.

[0031] The structure 101 further includes an insulating layer 121 on the substrate 120. The insulating layer 121 may be embodied as, for example, a dielectric layer. The insulating layer 121 can be formed by known methods such as, for example, thermal oxidation, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition, chemical solution deposition, MOCVD, evaporation, sputtering, and other deposition processes. Examples of such dielectric materials include, but are not limited to, SiO 2 , Si 3 N 4 , Al 2 O 3 ,AlON,Ta 2 O 5 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , ZrO 2 , Y 2 O 3 , Gd 2 O 3 , MgO, MgNO, Hf-based materials and combinations thereof including multilayers.

[0032] In the following exemplary description, the insulating layer 121 is a SiO 2 Assume that it contains

[0033] The structure 100 further includes a sacrificial structure 122 on the insulating layer 121. The sacrificial structure 122 includes or is composed of a seed material. The seed material may be a group IV or group III-V material. The seed material may in particular be Si, which is illustratively shown with vertical stripes. According to other embodiments, the seed material may be a group III-V compound material including gallium (Ga) or indium (In).

[0034] The structural substrate 120, the insulating layer 121, and the sacrificial structure 122 may in particular be embodied as a silicon-on-insulator wafer.

[0035] The thickness of the substrate 120, the insulating layer 121, and the sacrificial structure 122 may be any suitable thickness. According to an embodiment, the substrate 120 and the sacrificial structure 122 may be composed of Si. The insulating layer 121 may be composed of SiO 2 It may be composed of:

[0036] According to an embodiment, the structure 101 including the substrate 120, the insulating layer 121, and the sacrificial structure 122 may be embodied as a silicon-on-insulator wafer, in particular a commercially available SOI wafer.

[0037] The sacrificial structure 122 is patterned in a desired manner. It forms the inner part of a subsequently formed cavity structure, which is locally replaced by another semiconductor material, in particular a III-V semiconductor material. The sacrificial structure may be formed by lithography and subsequent etching. The etching may in particular be based on hydrogen bromide (HBr) chemistry, as known in the art and used as a standard technique in Si photonics. This has the advantage of providing smooth sidewalls.

[0038] It should be noted that in the top views 1a-1j, for ease of illustration, the insulating layer 121 and the substrate 120 are not shown.

[0039] FIG. 1b shows a top view of structure 102, and FIG. 2b shows the corresponding cross-sectional view. Structure 102 is formed from structure 101 by encapsulating sacrificial structure 122 with oxide. More specifically, sacrificial structure 122 is covered with a coating layer 123 of a dielectric material. In the exemplary embodiment of FIGS. 1b and 2b, coating layer 123 is SiO 2 , which is indicated by a dot pattern. 2 It is assumed to include.

[0040] Fig. 1c shows a top view of the structure 103, and Fig. 2c shows the corresponding cross-sectional view. The structure 103 is formed from the structure 102 by forming an opening 124 in the coating layer 123 at the expected location of the seed region 126 and the (to be formed) quantum dot structure. The opening 124 may be formed in particular by an etching step. According to an embodiment, the etching may include an under-etching to also form an opening 125 below the sacrificial structure 122. The seed region 126 is located in a central part of the sacrificial structure 122.

[0041] FIG. 1d shows a top view of the structure 104, and FIG. 2d shows a corresponding cross-sectional view. The structure 104 is formed from the structure 103 by performing a controlled oxidation of the seed material of the sacrificial structure 122 in the seed region 126. This performs a controlled reduction of the cross section of the seed region 126 in the lateral Y direction and / or the vertical Z direction. According to such an embodiment, the seed material of the sacrificial structure 122 may in particular be any suitable oxidizing material. According to an embodiment, the seed region 126 is oxidized to a thickness of 100 nm. 2 ~4000nm 2 The cross-sectional area in the yz plane may be:

[0042] Fig. 1e shows a top view of structure 105, and Fig. 2e shows the corresponding cross-sectional view. Structure 105 is formed from structure 104 by opening a first window 127 into sacrificial structure 122. More specifically, the SiO 2 The sacrificial Si material is then etched away, for example by reactive ion etching (RIE), to make it possible to access the sacrificial Si material.

[0043] Figure 1f shows a top view of structure 106, and Figure 2f shows a corresponding cross-sectional view. Structure 106 is formed from structure 105 by performing selective removal of seed material, particularly Si, back to a desired portion of the quantum dot structure, thereby forming a first hollow cavity 128a of cavity structure 128 for a subsequent growth step. The selective removal is performed using, inter alia, a fluorine-containing gas such as TMAH or XeF 2 The first hollow cavity 128a includes a seed surface 129 of the seed material in the seed region 126. The seed surface 129 may be formed of a silicon-based etchant.

[0044] FIG. 1g shows a top view of the structure 107, and FIG. 2g shows a corresponding cross-sectional view. The structure 107 is formed from the structure 106 by growing a quantum dot structure 130 from a seed surface 129 in a cavity structure 128, more particularly in a first cavity 128a. Furthermore, a first burying layer 140 is grown from a first surface 131 of the quantum dot structure 130. The growth of the quantum dot structure 130 and the first burying layer 140 establishes a first growth step. The first growth step includes a nucleation stage, the growth of the quantum dot structure 130, and the growth of the first burying layer 140. The quantum dot structure 130 may in particular be embodied as a single quantum dot. The growth of the first quantum dot structure 130 and the first burying layer 140 is performed in a first growth direction 150. The first growth direction 150 may in particular be lateral.

[0045] The quantum dot structure 130 may in particular comprise a III-V semiconductor material. The first burying layer 140 may also comprise a III-V semiconductor material.

[0046] According to an embodiment, the dimensions of the quantum dot structure 130 may be in the range of 10 nm to 60 nm in all dimensions, ie, the x-direction, the y-direction and the z-direction.

[0047] Fig. 1h shows a top view of the structure 108, and Fig. 2h shows a corresponding cross-sectional view. The structure 108 is formed from the structure 107 by encapsulating the first buried layer 140 by a coating layer 141, in particular an oxide layer. The coating layer 141 may be much thinner than the coating layer 123 of the cavity structure 128.

[0048] Figure 1i shows a top view of structure 109, and Figure 2i shows the corresponding cross-sectional view. Structure 109 is formed from structure 108 by opening a second window 142 into sacrificial structure 122. More specifically, the SiO 2 of coating layer 123 is opened to allow access to the sacrificial Si material. 2 is etched by RIE. Furthermore, selective removal of the seed material, in particular Si, back to the quantum dot structure 130 is performed. This forms a second hollow cavity 128b of the cavity structure 128 for a subsequent growth step. The selective removal may in particular be performed by a selective etching technique. By selective etching, a second surface 132 of the quantum dot structure 130 is formed. In other words, the sacrificial Si material is selectively removed back to the position of the previous nucleation. The first surface 131 and the second surface 132 of the quantum dot structure 130 are arranged opposite each other.

[0049] Figure 1j shows a top view of structure 110, and Figure 2j shows a corresponding cross-sectional view. Structure 110 is formed from structure 110 by growing a second burying layer 143 from a second surface 132 of quantum dot structure 130 within cavity structure 128, more specifically within second cavity 128b. Growing the second burying 143 establishes a second growth step. The second growth step includes a nucleation stage and growth of the second burying layer 143.

[0050] The growth of the second burying layer 143 is performed in a second growth direction 151. The first growth direction 150 and the second growth direction 151 are in particular lateral in the yx-plane. The first growth direction 150 is in particular opposite to the second growth direction 151.

[0051] The second buried layer 143 may in particular comprise a III-V semiconductor material.

[0052] According to an embodiment, the quantum dot structure 130 may comprise a second semiconductor material, in particular a second III-V semiconductor material, while the first buried layer 140 and the second buried layer 143 may comprise a first semiconductor material, in particular a first III-V semiconductor material. The first and second semiconductor materials may have different band gaps to provide quantum confinement. In particular, the first semiconductor material of the first buried layer 140 and the second buried layer 143 has a larger band gap than the second semiconductor material of the quantum dot structure 130. One preferred combination of the first and second III-V semiconductor materials includes InP as the first semiconductor material of the buried layer and InGaAs as the second semiconductor material of the quantum dot structure. Other preferred combinations include the combination of AlGaAs and GaAs, and the combination of GaAs and InGaAs. According to an embodiment, the first buried layer 140 may include a first semiconductor material and the second buried layer 143 may include a third semiconductor material different from the first semiconductor material.

[0053] However, it should be noted that III-V materials in general may be divalent and trivalent or tetravalent materials.

[0054] According to other embodiments, suitable pairs of II-VI semiconductor compounds, mixed II-VI compounds, and IV-VI compounds may be used.

[0055] According to an embodiment, the quantum dot structure 130 may comprise a second semiconductor material, the first buried layer 140 may comprise a doped semiconductor layer of the first semiconductor material, and the second buried layer 143 may comprise a doped semiconductor layer of the first semiconductor material or a third semiconductor material.

[0056] According to an embodiment, the pair first semiconductor material / second semiconductor material may in particular be established by the pairs InP / InGaAs, InP / InAlGaAs, GaAs / AlGaAs, GaAs / InAs, InP / InAsSb, GaN / InGaN or InAs / CdSe.

[0057] The growth of the quantum dot structure 130, the growth of the first burying layer 140, and the growth of the second burying layer 143 may be performed by, for example, metalorganic chemical vapor deposition (MOCVD), atmospheric pressure CVD, low pressure or reduced pressure CVD, ultra-high vacuum CVD, molecular beam epitaxy (MBE), atomic layer deposition (ALD), or hydride vapor phase epitaxy.

[0058] In general, the versatility of methods according to embodiments of the present invention may enable any combination of III-V semiconductor materials within the cavity structure 128, including buried quantum wells, quantum dots, quantum wires, doped or intrinsic semiconductor layers and heterojunctions.

[0059] According to an embodiment, the quantum dot structure 130, the first implant 140 and the second implant 143 may form a gain structure, which is epitaxially grown and extends laterally of the substrate, more specifically in the xy plane, which is arranged parallel to the underlying substrate.

[0060] Thus, the embodied gain structure may include a doping profile that forms a pin structure, which facilitates electrical pumping. A pin structure is a structure having an intrinsic region disposed between p-doped and n-doped regions.

[0061] In this respect, doping shall be understood as the deliberate introduction of impurities into an intrinsic semiconductor with the purpose of adjusting its electrical, optical and structural properties. Doping a semiconductor introduces energy states that are allowed in the band gap but very close to the energy band corresponding to the dopant type. Positive or p-type doping introduces free holes in the valence band, while negative or n-type doping introduces free electrons in the conduction band.

[0062] The introduction of dopants has the effect of shifting the energy band relative to the Fermi level. In n-type semiconductors, the Fermi level is close to the conduction band, or in degenerate n-type semiconductors, it is within the conduction band. For p-type, the Fermi level is close to or within the valence band. Typical doping densities in doped semiconductors range from 5x10 to 10, depending on the material and density of states. 18 cm 3 ~10 20 cm 3 Although semiconductors are rarely perfectly intrinsic, in the electrical sense, intrinsic means that the semiconductor does not conduct electricity. Typically, doping levels range from about 10 15 ~10 16 cm 3 It is.

[0063] FIG. 3 shows a flow diagram of method steps of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0064] A cavity structure is provided at step 310. The cavity structure includes a seed region that includes a seed material.

[0065] In step 320, a quantum dot structure is grown within the cavity structure in a first growth direction from a seed surface of the seed material.

[0066] In step 330, a first burying layer is grown on a first surface of the quantum dot structure in a first growth direction.

[0067] In step 340, the seed material of the sacrificial structure is removed.

[0068] In step 350, a second burying layer is grown within the cavity structure and on a second surface of the quantum dot structure in a second growth direction.

[0069] The second surface of the quantum dot structure may be different from, and in particular opposite to, the first surface of the quantum dot structure, and the second growth direction may be different from, and in particular opposite to, the first growth direction.

[0070] It should be noted that step 350 may be followed, if desired, by further processing steps appropriate to result in a final device structure, which may include, in particular, growing a contact layer over the buried layer.

[0071] Although illustrative examples are provided above, it will be understood that the basic fabrication steps described above can be used to fabricate semiconductor structures of other materials, shapes, and sizes. Materials and processing techniques can be selected as appropriate for a given embodiment, and appropriate choices will be readily apparent to those of skill in the art.

[0072] Although specific examples have been described above, many other embodiments are possible. The seed surface for growing the semiconductor structure may preferably be a crystalline seed surface, but according to other embodiments may be provided by an amorphous surface. If the seed has a well-defined crystal orientation and the crystal structure of the seed reasonably matches the crystal structure of the growing crystal (e.g., a III-V compound semiconductor), the growing crystal can adopt this orientation. If the seed is amorphous or has an undefined crystal orientation, the growing crystal will be single crystalline, but its crystal orientation will be random.

[0073] The disclosed semiconductor structures and circuits can be part of a semiconductor chip. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier or other higher level carrier with leads that are secured to a motherboard) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects or both). In either case, the chips may be integrated with other chips, discrete circuit elements, or other signal processing devices, or a combination thereof, as part of an intermediate product such as a motherboard or an end product. The end product can be any product that includes an integrated circuit chip.

[0074] The following definitions and abbreviations are used in interpreting the claims and this specification. As used herein, the terms "includes," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, product, or apparatus that includes a list of elements is not necessarily limited to only those elements and can include other elements not expressly listed or inherent to such composition, mixture, process, method, product, or apparatus.

[0075] As used herein, the articles "a" and "an" preceding an element or component are intended to be non-restrictive with respect to the number of instances (i.e., occurrences) of the element or component. Thus, "a" or "an" should be read as including one or at least one, and the singular form of an element or component also includes the plural, unless the number is clearly intended to be singular.

[0076] As used herein, the term "quantum dot structure" is a non-limiting term and is intended to refer to quantum well embodiments, quantum dots, particularly single quantum dots, and quantum wires.

[0077] As used herein, the terms "invention" or "present invention" are open-ended terms and are not intended to refer to any single embodiment of a particular invention, but rather encompass all possible embodiments described in the specification and claims.

[0078] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over the technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method for manufacturing a semiconductor device, comprising: providing a cavity structure, the cavity structure comprising a seed region comprising a seed material; growing a quantum dot structure within the cavity structure in a first growth direction from a seed surface of the seed material; growing a first burying layer on a first surface of the quantum dot structure in the first growth direction; removing the seed material; and and growing a second burying layer in the cavity structure on a second surface of the quantum dot structure in a second growth direction, the second surface of the quantum dot structure being different from the first surface of the quantum dot structure and the second growth direction being different from the first growth direction.

2. The method of claim 1 , wherein the quantum dot structure comprises one or more quantum dots.

3. The method of claim 1 , wherein the first growth direction is opposite to the second growth direction.

4. The method of claim 1 , wherein the location of the quantum dot structure is defined by the seed region.

5. The seed region is 100 nm ２ ~4000nm ２ The method of claim 1 , wherein the cross-sectional area is

6. Providing the cavity structure includes: Providing a semiconductor substrate; patterning a sacrificial structure on the semiconductor substrate, the sacrificial structure including the seed material; forming a coating layer comprising a coating material over the semiconductor substrate and the sacrificial structure; The method of claim 1 , further comprising selectively removing a first portion of the seed material, thereby forming the seed surface.

7. 7. The method of claim 6, further comprising selectively removing a second portion of the sacrificial structure, thereby providing the second surface of the quantum dot structure.

8. The method of claim 1 , wherein the seed region is formed within a central portion of the cavity structure.

9. the seed material being an oxidizing material, and the method comprising: forming an opening in the coating layer at the seed region; 7. The method of claim 6, further comprising: performing a controlled oxidation of the seed material in the seed region, thereby performing a controlled reduction in a cross-section of the seed region.

10. The method of claim 1 , wherein the seed material is a group IV material, in particular Si.

11. The method of claim 1, wherein the seed material is a III-V material comprising a material selected from the group consisting of GaAs, InAs, and InP.

12. The method of claim 1 , wherein the quantum dot structure comprises a III-V semiconductor material.

13. The method of claim 1 , wherein the first buried layer and the second buried layer each comprise a III-V semiconductor material.

14. the first buried layer comprises a doped semiconductor layer of a first semiconductor material; the second buried layer comprises a doped semiconductor layer of the first semiconductor material; The method of claim 1 , wherein the quantum dot structure comprises a second semiconductor material.

15. The first semiconductor material and the second semiconductor material are 15. The method of claim 14, wherein the pair is selected from the pair consisting of InP / InGaAs, InP / InAlGaAs, GaAs / AlGaAs, GaAs / InAs, InP / InAsSb, GaN / InGaN, and InAs / CdSe.

16. 2. The method of claim 1, wherein the growth of the quantum dot structure and the growth of the first and second burying layers are performed by one of metal-organic chemical vapor deposition (MOCVD), atmospheric pressure CVD, low pressure or reduced pressure CVD, ultra-high vacuum CVD, molecular beam epitaxy (MBE), atomic layer deposition (ALD), and hydride vapor phase epitaxy.

17. The method of claim 6 , wherein selectively removing the first portion of the seed material comprises performing a selective wet etch.

18. The method of claim 6 , wherein the coating material is a dielectric material.

19. the first buried layer comprises a doped semiconductor layer of a first semiconductor material; the second buried layer comprises a doped semiconductor layer of a third semiconductor material; The method of claim 1 , wherein the quantum dot structure comprises a second semiconductor material.

20. 1. A semiconductor device comprising: A quantum dot structure; a first burying layer epitaxially grown on a first surface of the quantum dot structure; a second burying layer epitaxially grown on the second surface of the quantum dot structure, the first surface of the quantum dot structure and the second surface of the quantum dot structure being disposed opposite one another.

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