Masking agent for high dielectric constant thin film, selective area deposition method using same, semiconductor substrate and semiconductor device manufactured therefrom

Abstract

The present invention relates to a masking agent for a high dielectric constant thin film, a selective area deposition method using the same, and a semiconductor substrate and a semiconductor device manufactured therefrom. The present invention has an effect of providing a masking agent for a high dielectric constant thin film, which can manufacture a patterned thin film by an atomic layer deposition method without a patterning process, and can significantly reduce impurities, a selective area deposition method using the same, and a semiconductor substrate and a semiconductor device manufactured therefrom.

Description

[Technical field]

[0001] The present invention relates to a masking agent for a high dielectric constant thin film, a selective area deposition method using the same, and a semiconductor substrate and a semiconductor device manufactured therefrom. More particularly, the present invention relates to a masking agent for a high dielectric constant thin film that can produce a patterned thin film by an atomic layer deposition method without a patterning process and can significantly reduce impurities, a selective area deposition method using the same, and a semiconductor substrate and a semiconductor device manufactured therefrom. [Background technology]

[0002] 2. Description of the Related Art Semiconductor processes are necessary since metal, semiconductor or insulator thin films are used in various fields such as semiconductor devices, integrated circuits, solar cells, liquid crystal displays, and organic light emitting diodes.

[0003] The semiconductor process repeats an etching-deposition-polishing (CMP) process to selectively deposit a film on a complex surface consisting of a junction of various materials.

[0004] As for the deposition, active research is being conducted on depositing high-quality thin films at relatively low temperatures using atomic layer deposition (ALD), which controls the reaction mechanism.

[0005] In the ALD process, the surface environment of the substrate is adjusted stepwise to form a self-saturating unit atomic film precursor, and a reaction occurs on the surface. The characteristic of forming a self-saturating precursor not only allows for atomic-level thickness control, but also allows for the deposition of a perfectly conformal thin film even when a surface with a very complex shape is formed due to the surface movement of the precursor precursor. The deposited thin film has a high density and the deposition temperature can be reduced.

[0006] Recently, as semiconductor patterns have become finer and more three-dimensional, we have come to encounter structures that are difficult to form using conventional techniques.

[0007] To overcome this, there is a need to develop a 'selective deposition technique' that allows specific components to be selectively deposited only in the required areas.

[0008] Selective deposition can be divided into active types, where precursors go to desired areas, and passive types, such as molecular layer-photoresist, where unwanted areas are blocked.

[0009] Among these, the active type has a drawback of low substrate selectivity, so in order to realize a high step difference, it is necessary to use a passive type.

[0010] Passive type is developed as a permanent molecular layer photoresist method through a wet process. One example is a technique of immersing the substrate in a thiol solution, but it is not suitable for use in deposition processes due to the disadvantage of wet stripping.

[0011]

[0012] [Prior art document]

[0013] [Patent documents]

[0014] (Patent Document 1) Korean Patent Publication No. 2019-0140104 Summary of the Invention [Problem to be solved by the invention]

[0015] In order to solve the above-mentioned problems of the prior art, the present invention aims to provide a masking agent for high dielectric constant thin films, which can provide a selective deposition technique in which a surface on which the masking agent is not grown is passivated by performing dry removal-molecular layer-photoresist for each deposition cycle using the masking agent for high dielectric constant thin films, and a precursor is applied only to the surface on which the masking agent is grown, a selective area deposition method using the masking agent, and a semiconductor substrate and a semiconductor device manufactured therefrom.

[0016] The above and other objects of the present invention can all be achieved by the present invention described below. [Means for solving the problem]

[0017] In order to achieve the above object, the present invention provides a masking agent for high dielectric constant thin films, which is characterized by being capable of selectively adsorbing to a surface having a dielectric constant (k) of 4.0 or more on a composite substrate having one or more surfaces having a dielectric constant of 4.0 or more.

[0018]

[0019] The present invention also relates to

[0020] Providing a composite substrate having at least one surface on a substrate having a dielectric constant (k) of less than 4.0 and at least one surface having a dielectric constant of 4.0 or greater; and

[0021] and then loading the substrate into a chamber, the method comprising the steps of: providing a step pattern or stack in which the ratio of the deposition thickness of the maskant for high dielectric constant thin film on a surface having a dielectric constant (k) of less than 4.0 to the deposition thickness of the maskant for high dielectric constant thin film on a surface having a dielectric constant (k) of 4.0 or more is in the range of 1:2 to 20 using the maskant for high dielectric constant thin film, a precursor compound, and a reaction gas.

[0022]

[0023] The present invention also provides a selective area deposition method, comprising the step of injecting the masking agent for a high dielectric constant thin film into a chamber and onto a surface of a loaded substrate.

[0024]

[0025] The present invention also provides a semiconductor substrate including a step pattern or stack manufactured by the above-described selective area deposition method.

[0026]

[0027] The present invention also provides a semiconductor device including the semiconductor substrate described above.

[0028] The semiconductor substrate may be low resistive metal gate interconnects, high aspect ratio 3D metal-insulator-metal (MIM) capacitors, DRAM trench capacitors, 3D Gate-All-Around (GAA), or 3D NAND. Effect of the Invention

[0029] According to the present invention, a step pattern or stack can be manufactured without a patterning process, and a selective deposition area can be provided on a substrate having a complex structure by controlling a thin film growth rate.

[0030] In addition, during the formation of the thin film, process by-products are more effectively reduced, corrosion and deterioration are prevented, and the crystallinity of the thin film is improved, thereby improving the electrical properties of the thin film.

[0031] In addition, the amount of process by-products during thin film formation can be reduced, improving step coverage and thin film density, and thus providing a selective area deposition method using the same and a semiconductor substrate manufactured therefrom. [Brief description of the drawings]

[0032] [Figure 1] This is a cross-sectional view showing the thickness of a layer of SiO2 deposited when a total of four thin films, SiO2, HfO2, ZrO2, and SiN, are deposited on a pattern portion where two or more types of film are exposed on a wafer using a stage heater at a temperature condition of 300 to 400°C, and then SiO2 is directly deposited on the top of each thin film.

[0033] [Diagram 2] This is a cross-sectional view showing the thickness of a layer of SiO2 deposited when a total of four thin films, SiO2, HfO2, ZrO2, and SiN, are deposited on a pattern portion where two or more types of film are exposed on a wafer using a stage heater at a temperature condition of 300 to 400°C, and then SiO2 is directly deposited on the top of each thin film.

[0034] [Diagram 3] 3 is a graph showing a deposition rate reduction rate for each deposition temperature when the HfO2 of FIG. 2 is deposited using a masking agent for a high dielectric constant thin film.

[0035] [Figure 4] 3 is a graph showing a deposition rate reduction rate for each deposition temperature when the SiO2 of FIG. 2 is deposited using a masking agent for a high dielectric constant thin film. [Diagram 5] 3 is a graph showing a deposition rate reduction rate for each deposition temperature when the SiO2 of FIG. 2 is deposited using a masking agent for a high dielectric constant thin film. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] The masking agent for high dielectric constant thin films described herein, the selective area deposition method using the same, and the semiconductor substrate manufactured therefrom will be described in detail below.

[0037] As used herein, unless otherwise specified, the term "high dielectric constant" refers to a dielectric constant (k) of 4.0 or greater.

[0038] As used herein, unless otherwise specified, the term "composite substrate" refers to a substrate having at least one surface with a dielectric constant (k) of less than 4.0 and at least one surface with a dielectric constant of 4.0 or greater.

[0039]

[0040] In order to achieve the above object, the present invention provides a masking agent for high dielectric constant thin films, which is characterized in that, on a composite substrate having one or more surfaces with a dielectric constant (k) of less than 4.0 and one or more surfaces with a dielectric constant of 4.0 or more, the masking agent is selectively adsorbed to the surfaces with a dielectric constant of 4.0 or more.

[0041] In the composite substrate, the surface having a dielectric constant (k) of less than 4.0 may be one selected from Si and SiO2.

[0042] In the composite substrate, the surface having a dielectric constant (k) of 4.0 or greater may be represented by MO2, M2O3, MN, or M3N4, where M is a metal.

[0043] In the composite substrate, the surface having a dielectric constant (k) of 4.0 or more may be one selected from Al2O3, ZrO2, HfO2, La2O3, Si3N4, TiN, TaN, GaN, AlN, and BN.

[0044] When the adsorption selectivity for a surface having a dielectric constant (k) of less than 4.0 is a and the adsorption selectivity for a surface having a dielectric constant of 4.0 or more is b, the following mathematical formula 1 may be satisfied.

[0045] [Formula 1]

[0046] a <b<2a

[0047] The masking agent for high dielectric constant thin films may be a compound that is deposited on a surface having a dielectric constant (k) of 4.0 or more to a thickness within the range of 0.1 to 0.4 Å per cycle.

[0048] The masking agent for high dielectric constant thin films may be a compound that deposits on a surface having a dielectric constant (k) of less than 4.0 to a thickness within the range of 0.6 to 1.5 Å per cycle.

[0049] The dielectric constant (k) used in the present invention may be based on a value known in the art (measured at 20° C.).

[0050] The masking agent for high dielectric constant thin films that satisfies the above-mentioned deposition thickness may be a compound having a tertiary structure or a linear carbonate structure.

[0051] The masking agent for high dielectric constant thin films may preferably contain one or more compounds selected from linear compounds having three or more elemental species having unshared electron pairs.

[0052] The linear compound having three or more elemental species having an unshared electron pair may be a compound represented by the following Chemical Formula 1.

[0053] [Chemical formula 1]

[0054] [ka]

[0055] (wherein, in the formula 1, R″ is hydrogen, an alkyl group having 1 to 5 carbon atoms, an alkene group having 1 to 5 carbon atoms, or an alkoxy group having 1 to 5 carbon atoms;

[0056] The B is -OH, -OCH3, -OCH2CH3, -CH2CH3, -SH, -SCH3, or -SCH2CH3.

[0057] The masking agent for high dielectric constant thin films may have a refractive index (measured at 20 to 25° C.) of 1.365 to 1.48, 1.366 to 1.47, 1.367 to 1.46, 1.365 to 1.41, or 1.41 to 1.46.

[0058]

[0059] The masking agent for high dielectric constant thin films may include at least one compound selected from the compounds represented by the following formulas 1-1 to 1-3.

[0060] [Chemical Formula 1-1 to 1-3]

[0061] [ka]

[0062] The masking agent for high dielectric constant thin films may be a solid or liquid under conditions of 20° C. and 1 bar.

[0063]

[0064] The present invention also relates to

[0065] Providing a composite substrate having at least one surface on a substrate having a dielectric constant (k) of less than 4.0 and at least one surface having a dielectric constant of 4.0 or greater; and

[0066] and then loading the substrate into a chamber, the method comprising the steps of: providing a step pattern or stack in which the ratio of the deposition thickness of the maskant for high dielectric constant thin film on a surface having a dielectric constant (k) of less than 4.0 to the deposition thickness of the maskant for high dielectric constant thin film on a surface having a dielectric constant (k) of 4.0 or more is in the range of 1:2 to 20 using the maskant for high dielectric constant thin film, a precursor compound, and a reaction gas.

[0067] The deposition thickness of the masking agent for high dielectric constant thin film on a surface having a dielectric constant (k) of less than 4.0 on a surface having a dielectric constant (k) of 4.0 or more may be in the range of 0.1 to 0.4 Å per cycle.

[0068] The deposition thickness of the masking agent for high dielectric constant thin films on a surface having a dielectric constant (k) of less than 4.0 may be in the range of 0.6 to 1.5 Å per cycle.

[0069] The substrate may be formed from a hafnium-based thin film, a silicon-based thin film, an aluminum-based thin film, a copper thin film, or a tungsten thin film.

[0070] The hafnium-based thin film may be hafnium oxide.

[0071] The silicon-based thin film may be silicon nitride or silicon oxide.

[0072] The aluminum-based thin film may be aluminum oxide.

[0073] In this case, the substrate may be selected from titanium nitride, hafnium oxide, silicon oxide or silicon nitride as required.

[0074]

[0075] The area selective deposition method may be performed by ALD, CVD, PEALD or PECVD.

[0076] The precursor compound that provides a surface having a dielectric constant of 4.0 or greater may be a molecule consisting of a central metal that forms Si3N4, Al2O3, TiO2, Ta2O5, HfO2, ZrO2, La2O3, Gd2O3, Er2O3, Nd2O3, PrO2, CeO2, Y2O3, HfSiO2, a-LaAlO3, SrTiO3, etc.

[0077] The lower substrate of the composite substrate may be selected from SiN, SiO2, HfO, Al2O3, Cu and W.

[0078] The reactive gas may include oxygen, nitrogen or sulfur.

[0079] The deposition temperature may be in the range of 50 to 700°C.

[0080]

[0081] The present invention also provides a selective area deposition method, comprising the step of injecting the masking agent for a high dielectric constant thin film into a chamber and onto a surface of a substrate that is loaded thereon.

[0082]

[0083] The selective area deposition method may include the steps of: i) vaporizing the masking agent for the high dielectric constant thin film to form a shielding area on a surface of a substrate loaded into a chamber; ib) primarily purging the interior of the chamber with a purge gas; ii-a) vaporizing a source precursor for a target film and adsorbing it in an area outside the shielding area; ii-b) secondary purging the interior of the chamber with a purge gas; iii-a) vaporizing a source precursor for a non-target film and adsorbing it in an area outside the shielding area; iii-b) tertiary purging the interior of the chamber with a purge gas; iv-a) supplying a reaction gas into the chamber; and iv-b) fourth purging the interior of the chamber with a purge gas.

[0084] Steps iii-a) and iii-b) may be carried out prior to steps ii-a) and ii-b), and steps ii-a) and iii-a), and steps ii-b) and iii-b) may be carried out simultaneously, if necessary.

[0085] In addition, steps iii-a) and iii-b) may be carried out prior to steps ii-a) and ii-b), and then steps ia) and ib) may be carried out. If necessary, steps ii-a) and iii-a), and steps ii-b) and iii-b) may be carried out simultaneously, and then steps ia) and ib) may be carried out.

[0086] The chamber may be an ALD chamber, a CVD chamber, a PEALD chamber, or a PECVD chamber.

[0087] The masking agent or precursor for the high dielectric constant thin film may be vaporized and injected, and then a plasma post-treatment may be performed.

[0088] The amount of the purge gas introduced into the chamber may be 10 to 100,000 times the volume of the introduced high dielectric constant thin film masking agent.

[0089] The reaction gas, the masking agent for the high dielectric constant thin film, and the source precursor may be delivered into the chamber by a VFC method, a DLI method, or an LDS method.

[0090] The substrate loaded into the chamber may be heated to 50 to 400° C., and the ratio of the high dielectric constant thin film masking agent and the raw material precursor input into the chamber (mg / cycle) may be 1:1.5 to 1:20.

[0091] The reactive gas may be a reducing agent, a nitriding agent or an oxidizing agent.

[0092]

[0093] * The selective area deposition method may be performed at a deposition temperature of 50 to 700°C.

[0094] The selective atomic layer deposition thin film may be a low dielectric constant thin film, a high dielectric constant thin film, or a metal film.

[0095]

[0096] The present invention also provides a semiconductor substrate including a step pattern or stack manufactured by the above-described selective area deposition method.

[0097] The step pattern or stack may have a multi-layer structure of two or more layers.

[0098] The step pattern or stack may contain carbon, silicon and halogen compounds at 1% or less, without remaining on the hafnium-based thin film, silicon-based thin film, aluminum-based thin film, copper thin film or tungsten thin film.

[0099] The step pattern or stack may be used as an insulator, a dielectric film, a diffusion barrier or an electrode.

[0100]

[0101] The present invention also provides a semiconductor device including the semiconductor substrate described above.

[0102] The semiconductor substrate may be low resistive metal gate interconnects, high aspect ratio 3D metal-insulator-metal (MIM) capacitors, DRAM trench capacitors, 3D Gate-All-Around (GAA), or 3D NAND.

[0103]

[0104] According to the present invention, a step pattern or stack can be manufactured without a patterning process, and a selective deposition area can be provided on a substrate having a complex structure by controlling a thin film growth rate.

[0105] In addition, during the formation of the thin film, process by-products are more effectively reduced, corrosion and deterioration are prevented, and the crystallinity of the thin film is improved, thereby improving the electrical properties of the thin film.

[0106] In addition, the amount of process by-products during thin film formation can be reduced, improving step coverage and thin film density, and thus providing a selective area deposition method using the same and a semiconductor substrate manufactured therefrom.

[0107]

[0108] In order to aid in the understanding of the present invention, preferred embodiments and drawings are presented below. The following embodiments and drawings are merely illustrative of the present invention, and it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the scope and technical idea of ​​the present invention, and it is natural that such changes and modifications fall within the scope of the attached claims.

[0109]

[0110] [Example]

[0111] Example 1 and Comparative Examples 1 to 2

[0112] The combinations shown in Table 1 below were selected based on the masking agent for high dielectric constant thin films used in the experiment, raw material precursor, reaction gas, deposition temperature, flow rate, purge, deposition conditions, and cycle (masking agent injection-purge-precursor injection-purge-reaction gas injection-purge) conditions.

[0113] [Table 1]

[0114] In the above Table 1, CpHf is an abbreviation for CpHf(NMe2)3, BTBAS is an abbreviation for [Bis(tertiarybutylamino)Silane], and 3DMAS is an abbreviation for Tris(dimethylamino)silane.

[0115] Using the combinations shown in Table 1 above, an experiment was carried out as follows.

[0116] Specifically, a compound represented by the following chemical formula 1-1 was prepared as a high dielectric constant thin film masking agent.

[0117] [Chemical formula 1-1]

[0118] [ka]

[0119] The precursors were CpHf, BTBAS, and 3DMAS, and the reactive gas was ozone (oxygen 1 m 3 Each of the ozone samples was prepared with a concentration of 200 g per sample.

[0120]

[0121] Example 1

[0122] The masking agent for high dielectric constant thin films was placed in a canister and supplied to a vaporizer heated to 150°C at a flow rate of 0.2 g / min using a LMFC (Liquid Mass Flow Controller) at room temperature. The masking agent for high dielectric constant thin films vaporized in the vaporizer was introduced into a deposition chamber loaded with a substrate for 1 second, and then argon gas was supplied at 3000 sccm for 2 seconds to perform argon purging. At this time, the pressure inside the reaction chamber was controlled at 2 Torr.

[0123] Next, the precursor compound CpHf was placed in a canister and injected into the chamber through a VFC (vapor flow controller) for 1 second, and then argon gas was supplied at 3000 sccm for 2 seconds to perform argon purging. At this time, the pressure in the reaction chamber was controlled at 2 Torr.

[0124] Next, 1000 sccm of ozone was introduced as a reactive gas into the reaction chamber for 3 seconds, and then argon purging was performed for 3 seconds. At this time, the substrate on which the thin film was to be formed was heated under the temperature conditions shown in Table 1.

[0125] This process was repeated 200 to 400 times to form a self-limiting atomic layer thin film having a thickness of 10 nm.

[0126]

[0127] Comparative Examples 1 to 5

[0128] The same process as in Example 1 was repeated using the materials and conditions shown in Table 1, except that the masking agent for high dielectric constant thin films in Example 1 was not used.

[0129]

[0130] Experimental Example 1

[0131] For each of the obtained thin films of Example 1 and Comparative Examples 1 to 5, the deposition rate reduction rate (D / R reduction rate), SIMCS impurities, and step coverage were measured in the following manner, and the results are shown in FIGS. 3 to 5 below.

[0132] * Deposition rate reduction rate (D / R (dep. rate) reduction rate): This refers to the ratio of the deposition rate reduction after the introduction of the shielding material compared to the D / R before the introduction of the thin film shielding material to be reacted with the activated surface, and was calculated as a percentage using the measured A / cycle values.

[0133] The deposition rate was calculated by dividing the thickness of the thin film measured by an ellipsometer, which is a device that can measure optical properties such as the thickness and refractive index of a thin film by the number of cycles, to calculate the thickness of the thin film deposited per cycle. Specifically, the deposition rate was calculated using the following Equation 1.

[0134] [Formula 1]

[0135] Deposition rate (D / R) = thickness of deposited thin film / number of cycles of deposition

[0136] * SIMS (Secondary-ion mass spectrometry) C impurity: The C impurity value was confirmed on the SIMS graph, taking into account the C impurity counts, when the sputtering time was 50 seconds, which is the time when the thin film was penetrated axially by ion sputtering and there was little contamination in the substrate surface layer.

[0137] * Step coverage (%): Calculated by measuring TEM of specimens cut horizontally at a position 100 nm below the top of the thin films deposited in Example 1 and Comparative Examples 1 to 5 on a substrate with a complex structure with an aspect ratio of 22:1 (left panel) and at a position 100 nm above the bottom (right panel).

[0138] Specifically, a deposition process was performed using diffusion-improving material application conditions on a substrate with a complex structure with an aspect ratio of 22:1, with an upper diameter of 90 nm, a lower diameter of 65 nm, and a via hole depth of approximately 2000 nm. In order to check the uniformity of the thickness deposited inside the vertically formed via hole and its step coverage, specimens were made by cutting horizontally at a position 100 nm down from the top and at a position 100 nm up from the bottom, and then measured using a transmission electron microscope (TEM).

[0139]

[0140] Additional Example 1

[0141] The same processes as in Example 1 and Comparative Example 1 were carried out on the Si substrate in separate regions, and thin films were obtained by depositing HfO2 depending on whether or not a masking agent for high dielectric constant thin films was used.

[0142] The deposition rate reduction rate for each deposition temperature between the application area of ​​the thin film in Example 1 and the application area of ​​Comparative Example 1 was calculated and is shown in FIG.

[0143] As can be seen from FIG. 3 below, in Example 1 in which the masking agent for high dielectric constant thin films selected in the present invention was applied to a surface having a dielectric constant (k) of 4.0 or more, it was confirmed that the deposition rate (D / R) was significantly improved compared to Comparative Example 1 in which the masking agent for high dielectric constant thin films was not used.

[0144]

[0145] Additional Comparative Example 1

[0146] The same method as in Additional Example 1 was performed. The same process as in Additional Example 1 was repeated, except that the same process as in Comparative Example 2 was performed instead of Example 1, and the same process as in Comparative Example 3 was performed instead of Comparative Example 1, to obtain a thin film in which SiO2 was deposited depending on whether or not a masking agent for a high dielectric constant thin film was used.

[0147] The deposition rate reduction rate for each deposition temperature between the application area of ​​Comparative Example 2 and the application area of ​​Comparative Example 3 of the thin film was calculated and is shown in FIG.

[0148] As can be seen from FIG. 4 below, in Comparative Example 2 in which the masking agent for high dielectric constant thin films selected in the present invention was applied to a surface having a dielectric constant (k) of less than 4.0, no improvement in the reduction rate in deposition rate (D / R) was observed compared to Comparative Example 3 in which the masking agent for high dielectric constant thin films was not applied.

[0149]

[0150] Additional Comparative Example 2

[0151] The same method as in Additional Example 1 was performed. The same process as in Additional Example 1 was repeated, except that the same process as in Comparative Example 4 was performed instead of Example 1, and the same process as in Comparative Example 5 was performed instead of Comparative Example 1, to obtain a thin film in which SiO2 was deposited depending on whether or not a masking agent for a high dielectric constant thin film was used.

[0152] The deposition rate reduction rate for each deposition temperature between the application area of ​​Comparative Example 4 and the application area of ​​Comparative Example 5 of the thin film was calculated and is shown in FIG.

[0153] As can be seen from FIG. 5 below, in Comparative Example 4, in which the masking agent for high dielectric constant thin films selected in the present invention was applied to a surface having a dielectric constant (k) of less than 4.0, no improvement in the reduction rate in deposition rate (D / R) was observed compared to Comparative Example 5, in which the masking agent for high dielectric constant thin films was not applied.

[0154]

[0155] <Experimental Example 2>

[0156] Among the graphs of deposition rate reduction rates according to deposition temperatures in the above-mentioned FIGS. 3 to 5, the deposition rate reduction rates at a deposition temperature of 400° C. are summarized in Table 2 below.

[0157] [Table 2]

[0158] As can be seen from Additional Example 1 in Table 2, it was confirmed that the deposition rate reduction rate between Example 1, in which the masking agent for high dielectric constant thin films according to the present invention was applied to a surface having a dielectric constant (k) of 4.0 or more, and Comparative Example 1, in which the masking agent for high dielectric constant thin films was not applied to the surface, reached 88%.

[0159] Meanwhile, as can be seen from Additional Comparative Example 2 in Table 2, the deposition rate reduction rate between Comparative Example 2, in which the masking agent for high dielectric constant thin films according to the present invention was applied to a surface having a dielectric constant (k) of less than 4.0, and Comparative Example 3, in which the masking agent for high dielectric constant thin films was not applied to the same surface, was only 1%.

[0160] In addition, as can be seen from Additional Comparative Example 3 in Table 2, the deposition rate reduction rate between Comparative Example 4, in which the masking agent for high dielectric constant thin films according to the present invention was applied to a surface having a dielectric constant (k) of less than 4.0 or other surface, and Comparative Example 5, in which the masking agent for high dielectric constant thin films was not applied to the surface, was only 2%.

[0161]

[0162] Therefore, by using a masking agent for a high dielectric constant thin film, the present invention can effectively perform a selective deposition technique in which a precursor is applied only to a surface on which the masking agent is to be grown by performing a dry removal-molecular layer-photoresist for each deposition cycle to passivate the surface on which the masking agent is not grown, and thus is suitable for providing various semiconductor substrates and semiconductor devices.

Claims

1. A masking agent for high dielectric constant thin films, characterized in that on a composite substrate having one or more surfaces with a dielectric constant (k) of less than 4.0 and one or more surfaces with a dielectric constant of 4.0 or more, the masking agent is selectively adsorbed to the surfaces with a dielectric constant of 4.0 or more.

2. In the composite substrate, the surface having a dielectric constant (k) of less than 4.0 is made of Si and SiO ２ 2. The masking agent for high dielectric constant thin films according to claim 1, which is one or more selected from the following:

3. In the composite substrate, the surface having a dielectric constant (k) of 4.0 or more is ２ , M. ２ O ３ , M.N. or M. ３ N ４ 2. The masking agent for high dielectric constant thin films according to claim 1, characterized in that it is represented by the formula: (wherein M is a metal).

4. In the composite substrate, the surface having a dielectric constant (k) of 4.0 or more is made of Al ２ O ３ , ZrO ２ , HfO ２ , La ２ O ３ , Si ３ N ４ 4. The masking agent for high dielectric constant thin films according to claim 3, characterized in that it is at least one selected from the group consisting of TiN, TaN, GaN, AlN, and BN.

5. 2. The masking agent for high dielectric constant thin films according to claim 1, which satisfies the following mathematical formula 1, where a is the adsorption selectivity for a surface having a dielectric constant (k) of less than 4.0 and b is the adsorption selectivity for a surface having a dielectric constant of 4.0 or more. [Formula 1] a<b<2a

6. 2. The masking agent for a high dielectric constant thin film according to claim 1, wherein the masking agent for a high dielectric constant thin film is a compound having a t-alkyl structure or a linear carbonate structure.

7. 2. The masking agent for a high dielectric constant thin film according to claim 1, which is a compound represented by the following Chemical Formula 1: [Chemical formula 1] 【Chemistry 1】 (In the above formula 1, R″ is hydrogen, an alkyl group having 1 to 5 carbon atoms, an alkene group having 1 to 5 carbon atoms, or an alkoxy group having 1 to 5 carbon atoms; The B is —OH, —OCH ３ , -OCH ２ CH ３ , -CH ２ CH ３ , -SH, -SCH ３ , or -SCH ２ CH ３ It is.)

8. Providing a composite substrate having at least one surface on a substrate having a dielectric constant (k) of less than 4.0 and at least one surface having a dielectric constant of 4.0 or greater; and After loading the substrate into a chamber, a masking agent for a high dielectric constant thin film of claim 1, a precursor compound and a reaction gas are used to form a step pattern or stack in which the deposition thickness of the masking agent for a high dielectric constant thin film on a surface having a dielectric constant (k) of less than 4.0 and the deposition thickness of the masking agent for a high dielectric constant thin film on a surface having a dielectric constant (k) of 4.0 or more are in the range of 1:2 to 20.

9. 9. The method of claim 8, wherein the selective area deposition method is performed by ALD, CVD, PEALD or PECVD.

10. 9. The method of claim 8, wherein the precursor compounds are independently selected from a Ti-based compound, a Hf-based compound, and a Si-based compound.

11. 9. The method of claim 8, wherein the deposition temperature is within a range of 50 to 700[deg.] C.

12. A semiconductor substrate comprising a step pattern or stack produced by the selective area deposition method of claim 8.

13. The semiconductor substrate according to claim 12 , wherein the step pattern or stack has a multi-layer structure of two or more layers.

14. A semiconductor device comprising the semiconductor substrate of claim 12.

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