Multi-type integrated passive device (IPD) components and devices and processes for implementing same - Patents.com

Abstract

The transistor device includes a metal submount, a transistor die disposed on the metal submount, a first integrated passive device (IPD) component including a first substrate disposed on the metal submount, and a second integrated passive device (IPD) component including a second substrate disposed on the metal submount, wherein the first substrate is a different material than the second substrate.

Description

[Technical field]

[0001] The present disclosure relates to multiple-type integrated passive device (IPD) components, devices implementing multiple-type IPD components, processes for implementing multiple-type IPD components, and processes for implementing devices having multiple-type IPD components. [Background technology]

[0002] Transistor packages, such as radio frequency (RF) power amplifier transistor products, embody IPD components, which are typically mounted on printed circuit board (PCB)-based substrates, silicon (Si)-based substrates, and / or the like.

[0003] However, PCB-based substrates, Si-based substrates, and / or the like have many drawbacks. In particular, these components can only implement a limited number of components. This increases manufacturing costs, manufacturing complexity, and limits functionality. Furthermore, the configuration and arrangement of these components is very limited. This in turn increases manufacturing costs, manufacturing complexity, and limits functionality. Furthermore, these components can be very large and consume substantial real estate or space within the transistor package. This limits the functionality of the components.

[0004] Therefore, what is needed is an IPD component, an RF product implementing the IPD component, and / or one configured for utilization of multiple components, increased functionality, and efficient utilization of space. Summary of the Invention

[0005] One general embodiment includes a transistor device including a metal submount; a transistor die disposed on the metal submount; a first integrated passive device (IPD) component including a first substrate disposed on the metal submount; and a second integrated passive device (IPD) component including a second substrate disposed on the metal submount, where the first substrate is a different material than the second substrate.

[0006] One general aspect includes a method of implementing a transistor device including providing a metal submount, disposing a transistor die on the metal submount, disposing a first integrated passive device (IPD) component including a first substrate on the metal submount, and disposing a second integrated passive device (IPD) component including a second substrate on the metal submount, where the first substrate is a different material than the second substrate.

[0007] Additional features, advantages, and aspects of the present disclosure can be set forth or become apparent from consideration of the following detailed description, drawings, and claims. Moreover, it is to be understood that both the foregoing summary of the disclosure and the following detailed description are exemplary and intended to provide further explanation without limiting the scope of the present disclosure, as set forth in the claims.

[0008] The accompanying drawings are included to provide a further understanding of the present disclosure, are incorporated in and constitute a part of this specification, illustrate aspects of the disclosure, and together with the detailed description serve to explain the principles of the disclosure. No attempt is made to show structural details of the disclosure more than may be necessary for a fundamental understanding of the disclosure and an understanding of the various ways in which it can be practiced. [Brief description of the drawings]

[0009] [Figure 1] 1 shows a perspective view of a package according to the present disclosure.

[0010] [Diagram 2] 1 shows a cross-sectional view of a package according to the present disclosure.

[0011] [Diagram 3] 1 shows a partial top view of a package according to certain aspects of the present disclosure.

[0012] [Figure 4] 1 shows a partial top view of a package according to another particular embodiment of the present disclosure.

[0013] [Diagram 5] 1 shows a perspective view of a package according to the present disclosure.

[0014] [Figure 6] 6 shows a cross-sectional view of the package according to FIG. 5.

[0015] [Figure 7] 1 shows a partial top view of a package according to another particular embodiment of the present disclosure.

[0016] [Figure 8] 1 shows a partial top view of a package according to another particular embodiment of the present disclosure.

[0017] [Figure 9] 1 shows a partial top view of a package according to another particular embodiment of the present disclosure.

[0018] [Figure 10] 1 shows a partial top view of a package according to another particular embodiment of the present disclosure.

[0019] [Figure 11] 1 shows a partial top view of a package according to another particular embodiment of the present disclosure.

[0020] [Figure 12] 1 shows a partial top view of a package according to another particular embodiment of the present disclosure.

[0021] [Figure 13] 1 illustrates a top view of an IPD component according to the present disclosure.

[0022] [Figure 14A] 14 shows a side view of the IPD components according to FIG. 13. [Figure 14B] 14 shows a side view of the IPD components according to FIG. 13.

[0023] [Figure 15] 14 shows a partial top view of the IPD components according to FIG. 13.

[0024] [Figure 16] 1 illustrates a top view of an IPD component according to the present disclosure.

[0025] [Figure 17A] 17 shows a side view of the IPD components according to FIG. 16. [Figure 17B] 17 shows a side view of the IPD components according to FIG. 16.

[0026] [Figure 18] 1 shows a side view of an IPD component according to the present disclosure.

[0027] [Figure 19] 19 shows a bottom view of the IPD components according to FIG. 18.

[0028] [Figure 20] 19 shows a side view of the IPD components according to FIG. 18.

[0029] [Figure 21] 1 shows a side view of an IPD component according to the present disclosure.

[0030] [Figure 22] 1 shows a side view of an IPD component according to the present disclosure.

[0031] [Figure 23]1 illustrates a manufacturing process for an IPD component according to the present disclosure.

[0032] [Figure 24] FIG. 1 illustrates a process for making a package according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] The aspects of the present disclosure and various features and advantageous details thereof will be more fully explained with reference to the non-limiting aspects and examples described and / or illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale, and that features of one aspect may be employed with other aspects, even if not explicitly described herein, as will be recognized by those skilled in the art. Descriptions of well-known components and processing techniques may be omitted so as not to unnecessarily obscure aspects of the present disclosure. The examples used herein are merely intended to facilitate an understanding of the aspects in which the present disclosure may be implemented, and to further enable those skilled in the art to implement aspects of the present disclosure. Thus, the examples and aspects herein should not be construed as limiting the scope of the present disclosure, which is defined solely by the appended claims and applicable law. Furthermore, it should be noted that like reference numerals represent like components throughout the several views of the drawings and in the different embodiments disclosed.

[0034] In this specification, terms such as first, second, etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] When an element, such as a layer, region, or substrate, is referred to as being "on" or "extending" onto another element, it will be understood that it may be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly" on or extending "directly" onto another element, there are no intervening elements. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another element, it will be understood that it may be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. Also, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0036] Relative terms such as "lower" or "upper" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as depicted in the figures. It will be understood that these terms, and those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0037] The terms used herein are for the purpose of describing particular aspects only and are not intended to limit the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that as used herein, the terms "comprises", "comprises", "includes" and / or "comprises" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with the meaning in the context of the present specification and related art, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such in this specification.

[0039] The present disclosure relates to composite IPD components, devices implementing composite IPD components, processes for implementing composite IPD components, processes for implementing devices having composite IPD components. The present disclosure further relates to hybrid IPD components, devices implementing hybrid IPD components, processes for implementing hybrid IPD components, and processes for implementing devices having hybrid IPD components.

[0040] The present disclosure further relates to a radio frequency (RF) package implementing a radio frequency (RF) device having a hybrid / composite implementation of IPD components. The present disclosure further relates to a radio frequency (RF) power amplifier transistor package implementing an RF device having a hybrid / composite implementation of IPD components. The present disclosure further relates to a process for manufacturing a hybrid / composite implementation of IPD components. The present disclosure further relates to a process for manufacturing a package implementing a hybrid / composite implementation of IPD components. The present disclosure further relates to a process for manufacturing an RF package implementing an RF device having a hybrid / composite implementation of IPD components. The present disclosure further relates to a process for manufacturing a radio frequency (RF) power amplifier transistor package implementing a hybrid / composite implementation of IPD components.

[0041] The present disclosure further relates to a radio frequency (RF) package implementing a radio frequency (RF) device having multiple type IPD components. The present disclosure further relates to a radio frequency (RF) power amplifier transistor package implementing an RF device having multiple type IPD components. The present disclosure further relates to a process for manufacturing a multi-type IPD component. The present disclosure further relates to a process for manufacturing a package implementing a multi-type IPD component. The present disclosure further relates to a process for manufacturing an RF package implementing an RF device having multiple type IPD components. The present disclosure further relates to a process for manufacturing a radio frequency (RF) power amplifier transistor package with multiple type IPD components implemented.

[0042] The present disclosure is directed to IPD components, particularly IPD components that may implement a strategic combination of silicon carbide (SiC) IPDs and PCB-based IPDs for RF pre-matching, baseband decoupling, and / or the like in RF power products, other products, and / or other applications.

[0043] Additionally, the present disclosure is directed to IPD components that may implement a smaller form factor capacitor IPD in combination with a larger size PCB-IPD. The smaller form factor SiC capacitor IPD may reduce cost and / or provide high capacitor density. The larger size PCB-IPD may provide greater coverage and allow thicker metallization on the traces.

[0044] In some embodiments, the SiC capacitor IPD can be directly attached to the package flange through cutout holes or routed corners of the PCB-IPD. In some embodiments, the SiC IPD can be directly attached to the flange, with the PCB-IPD mounted thereon forming the wiring layers, interconnects, and / or the like to other PCB bond pads, PCB ground pads, and / or the like.

[0045] In aspects, the IPD components can be used for matching networks, pre-matching, bias decoupling, thermal grounding, and / or the like in RF power products and / or the like. The IPD components may be placed in a package, such as an open cavity package or an overmolded package, together with transistor dies, such as gallium nitride (GaN) transistor dies, and other capacitors, IPDs, and the like, and connected to each other and to the package leads by wire bonding. Metal metallization can be applied to the top and bottom of the substrate, with vias through the substrate, to form bond pads, inductive strips, inductive coils, capacitive stubs, and the like. Additionally, surface mount device (SMD) elements, such as capacitors, resistors, inductors, and the like, can be attached, for example, by soldering, to the top of the IPD components.

[0046] In aspects, the IPD components may implement small form factor SiC capacitor IPDs that may reduce overall cost compared to fabricating the entire IPD on a SiC substrate. Additionally, the IPD components may take advantage of the high capacitor density, high Q, underside height profile, better thermal performance, and / or similar advantages of SiC capacitors compared to implementing SMD capacitors on a PCB substrate. Furthermore, the IPD components may in some aspects take advantage of PCB technology that has thicker metal traces (e.g., traces with 17-35 microns of copper) compared to SiC traces (e.g., traces with 3-6 microns of Au), which works well for high power handling.

[0047] In aspects, the IPD components can have high volume resistivity and low leakage of both the SiC substrate and the PCB substrate, which can contribute to a high-Q and low-loss IPD. Additionally, IPD components implementing capacitor IPDs can have much better thermal performance, handling of SMD components, and / or the like. Additionally, the IPD components can be configured to directly attach the SiC IPD to a package flange, which can provide a low thermal resistance path for heat transfer. Additionally, the IPD components can include cutouts, routed corners, holes, cutout pockets, and / or the like in the PCB IPD that can place the SiC IPD close to the transistor die, minimize trace losses, minimize inductance, and / or the like. Additionally, the IPD components can include printed low-profile traces on the PCB-IPD implementation, which can provide better inductance control (for low values) than wire bond loops.

[0048] FIG. 1 shows a perspective view of a package according to the present disclosure.

[0049] FIG. 2 shows a cross-sectional view of a package according to the present disclosure.

[0050] FIG. 3 shows a partial top view of a package according to certain embodiments of the present disclosure.

[0051] FIG. 4 shows a partial top view of a package according to another specific embodiment of the present disclosure.

[0052] The embodiments of Figures 1, 2, 3, and 4 may include any one or more features as described herein. In particular, Figures 1, 2, 3, and 4 illustrate an example implementation of a package 100 that may include any one or more other features, components, arrangements, etc. described herein. In particular, Figures 1, 2, 3, and 4 illustrate a package 100 that may be implemented as an RF package, an RF amplifier package, an RF power amplifier package, an RF power transistor package, an RF power amplifier transistor package, and / or as described herein.

[0053] Package 100 may include one or more semiconductor devices 400, support 102, at least one or more of first IPD component 200, second IPD component 300, and third IPD component 800. In embodiments, package 100 may include multiple first IPD components 200, second IPD components 300, and / or third IPD components 800, and in embodiments, package 100 may include one or more single implementations of first IPD component 200, second IPD component 300, and / or third IPD component 800.

[0054] In an embodiment, the first IPD component 200 can be implemented as a PCB IPD component, an IPD component having a PCB substrate, and / or the like. In an embodiment, the second IPD component 300 can be implemented as a SiC IPD component, an IPD component having a SiC substrate, and / or the like. In an embodiment, the third IPD component 800 can be implemented as a PCB IPD component, an IPD component having a PCB substrate, and / or the like. In an embodiment, the first IPD component 200 can utilize a substrate material that is different from the substrate material of the second IPD component 300. In an embodiment, the first IPD component 200 can utilize a substrate material that is the same as the substrate material of the third IPD component 800.

[0055] The first IPD component 200, the second IPD component 300, and / or the third IPD component 800 may be implemented as at least a portion of an RF device described herein. The first IPD component 200, the second IPD component 300, and / or the third IPD component 800 may implement a matching network, a harmonic termination circuit, an integrated passive device (IPD), a capacitor, a resistor, an inductor, and / or the like.

[0056] In an aspect, the second IPD component 300 can be implemented as a smaller form factor SiC capacitor IPD combined with the first IPD component 200 implemented as a larger size PCB-IPD. Implementing the second IPD component 300 as a smaller form factor SiC capacitor IPD can reduce cost, provide high capacitor density, and / or the like. Implementing the first IPD component 200 as a larger size PCB-IPD can provide greater coverage, thicker metallization on traces, and / or the like.

[0057] In some aspects, the second IPD component 300 may be implemented as a capacitor IPD that may be attached directly to a support 102, such as a package flange, through a cutout hole or routed corner of the first IPD component 200 implemented as a PCB-IPD. In some aspects, the second IPD component 300 may be implemented as a SiC IPD and may be attached directly to a support 102, such as a flange, with the first IPD component 200 implemented as a PCB-IPD mounted on top of the second IPD component 300, which forms the wiring layer, interconnects, and / or to other PCB bond pads, PCB ground pads, and the like.

[0058] In aspects, the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 can be used for matching networks, pre-matching, bias decoupling, thermal grounding, and / or the like in RF power products and / or the like. The first IPD component 200, the second IPD component 300, and / or the third IPD component 800 can be placed in a package, such as an open cavity package or an overmolded package, together with transistor dies, such as gallium nitride (GaN) transistor dies, and other capacitors, IPDs, and the like, and wire bonded together and connected to package leads. Metal metallization can be applied to the top and bottom of the substrate, with vias through the substrate, to form bond pads, inductive strips, inductive coils, capacitive stubs, and the like. Additionally, surface mounted device (SMD) elements, such as capacitors, resistors, inductors, and the like, can be attached, for example, by soldering, on the IPD components.

[0059] In an embodiment, the second IPD component 300 can be implemented as a small form factor SiC capacitor IPD, which may reduce overall cost compared to fabricating the entire IPD on a SiC substrate. Additionally, the second IPD component 300 can take advantage of the high capacitor density, high Q, underside height profile, better thermal performance, and / or similar advantages of SiC capacitors compared to implementing SMD capacitors on a SiC substrate. Furthermore, the first IPD component 200 and / or the third IPD component 800 can, in an embodiment, take advantage of PCB technology with thicker metal traces (e.g., traces with 17-35 microns of copper) compared to SiC traces (e.g., traces with 3-6 microns of Au), which works well for high power handling.

[0060] In an aspect, the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 can have high volume resistivity and low leakage of both the SiC substrate and the PCB substrate, which can contribute to a high-Q and low-loss IPD. Furthermore, the second IPD component 300 implemented as a SiC capacitor IPD can have much better thermal performance, handling of SMD components, and / or the like. Furthermore, the first IPD component 200 can be configured to directly attach the second IPD component 300 implemented as a SiC IPD to a support 102, such as a package flange, providing a low thermal resistance path for heat transfer. Furthermore, the first IPD component 200 can include cutouts, routed corners, holes, cutout pockets, and / or the like that can position the second IPD component 300 implemented as a SiC IPD close to one or more semiconductor devices 400, such as transistor dies, to minimize trace losses, minimize inductance, and / or the like. Additionally, the first IPD component 200 and / or the third IPD component 800 may include printed low profile traces on a PCB-IPD implementation that may provide better inductance control (to low values) than wire bond loops.

[0061] The one or more semiconductor devices 400 may be implemented as one or more of a wide bandgap semiconductor device, an ultra-wide band device, a GaN-based device, a metal semiconductor field effect transistor (MESFET), a metal oxide field effect transistor (MOSFET), a junction field effect transistor (JFET), a bipolar junction transistor (BJT), an insulated gate bipolar effect transistor (IGBT), a high electron mobility transistor (HEMT), a wide bandgap (WBG) semiconductor, a power module, a gate driver, a general broadband component, a telecom component, an L-band component, an S-band component, an X-band component, a C-band component, a Ku-band component, a satellite communications component, a Doherty configuration, or the like.

[0062] The package 100 can be implemented to include an open cavity configuration suitable for use with the first IPD component 200, the second IPD component 300, and the third IPD component 800 of the present disclosure. In particular, the open cavity configuration can utilize an open cavity package design. In some embodiments, the open cavity configuration can include interconnects, circuit components, the first IPD component 200, the second IPD component 300, the third IPD component 800, one or more semiconductor devices 400, and / or a lid or other housing for protecting the same. The package 100 can include a ceramic body 402 and one or more metal contacts 404. In other aspects, the package 100 may include a plurality of one or more metal contacts 404, and in aspects, the package 100 may include a plurality of parallel implementations of one or more metal contacts 404 and one or more semiconductor devices 400, first IPD components 200, second IPD components 300, third IPD components 800, and / or parallel implementations thereof.

[0063] Within the package 100, one or more semiconductor devices 400 may be attached to the support 102 via a die attach material 422. One or more interconnects 104 may couple the one or more semiconductor devices 400 to a first one of the one or more metal contacts 404, a second one of the one or more metal contacts 404, a first IPD component 200, a second IPD component 300, and a third IPD component 800, and / or the like. Further, within the package 100, the first IPD component 200, the second IPD component 300, and the third IPD component 800 may be disposed on the support 102 via a die attach material 422 with one or more interconnects 104 shown in an exemplary configuration that may connect between the package 100, the first IPD component 200, and / or the one or more semiconductor devices 400. The support 102 can dissipate heat generated by the one or more semiconductor devices 400, the first IPD component 200, the second IPD component 300, and the third IPD component 800 while isolating and protecting the one or more semiconductor devices 400 and the first IPD component 200, the second IPD component 300, and the third IPD component 800 from the external environment. In embodiments, the die attach material 422 can utilize adhesive bonding, soldering, sintering, eutectic bonding, thermocompression bonding, ultrasonic bonding / welding, clip components, and / or as described herein.

[0064] The one or more interconnects 104 may utilize ball bonds, wedge bonds, compliant bonds, ribbon bonds, metal clip attachments, and / or the like. In one aspect, the one or more interconnects 104 may utilize the same type of connection. In one aspect, the one or more interconnects 104 may utilize different types of connections.

[0065] The one or more interconnects 104 may comprise a variety of metallic materials, including one or more of aluminum, copper, silver, gold, and / or the like. In one embodiment, the one or more interconnects 104 may utilize the same type of metal. In one embodiment, the one or more interconnects 104 may utilize different types of metals. The one or more interconnects 104 may be connected to the plurality of interconnect pads 206 by adhesives, soldering, sintering, eutectic bonding, thermocompression bonding, ultrasonic bonding / welding, clip components, and / or the like, as described herein.

[0066] The support 102 may be implemented as a metal submount, or may be implemented as a support, surface, package support, package surface, package support surface, flange, metal flange, heat sink, common source support, common source surface, common source package support, common source package surface, common source package support surface, common source flange, common source heat sink, lead frame, metal lead frame, and / or the like. The support 102 may include an insulating material, a dielectric material, and / or the like.

[0067] 3, in one aspect, the first IPD component 200 may include an output PCB IPD implementation 292, the first IPD component 200 may include an input PCB IPD implementation 294, the second IPD component 300 may include an output IPD implementation 392, the second IPD component 300 may include an input IPD implementation 394, and the third IPD component 800 may include a baseband PCB IPD implementation. In one aspect, the output IPD implementation 392 may be implemented as a SiC IPD. In one aspect, the input IPD implementation 394 may be implemented as a SiC IPD. However, the first IPD component 200, the second IPD component 300, and the third IPD component 800 may be implemented for other functions.

[0068] In one embodiment, the second IPD component 300 can be configured to be mounted to the support 102. In one embodiment, the second IPD component 300 may be configured to be mounted directly to the support 102. In this regard, mounting the second IPD component 300 to the support 102 may provide thermal advantages over having an SMD implementation of the capacitor mounted on a PCB-IPD.

[0069] Additionally, the first IPD component 200 can be configured to be attached to the support 102. In one aspect, the first IPD component 200 can be configured to be attached directly to the support 102.

[0070] 3, the second IPD component 300 may be disposed on either side of the first IPD component 200 on the support 102. In particular, the input IPD implementation 394 of the second IPD component 300 may be disposed on either side of the input PCB IPD implementation 294 of the first IPD component 200. Further, the output IPD implementation 392 of the second IPD component 300 may be disposed on either side of the output PCB IPD implementation 292 of the first IPD component 200.

[0071] In one aspect, the third IPD component 800 can be configured to be mounted to the support 102. In one aspect, the third IPD component 800 can be configured to be mounted directly to the support 102. As shown in FIG. 3 , the third IPD component 800 can be disposed between the input IPD implementation 394 of the second IPD component 300 and the output IPD implementation 392 of the second IPD component 300.

[0072] 4, the second IPD component 300 can be disposed on the first IPD component 200 as illustrated in and described in connection with FIGS. 14A and 14B. In one aspect, the second IPD component 300 can be disposed directly on the first IPD component 200. In particular, the second IPD component 300 can be disposed on a top surface and on either side of the first IPD component 200. More specifically, the input IPD implementation 394 of the second IPD component 300 can be disposed on the top surface and on either side of the input PCB IPD implementation 294 of the first IPD component 200.

[0073] Additionally, the output IPD implementation 392 of the second IPD component 300 can be disposed on a top surface and on either side of the output PCB IPD implementation 292 of the first IPD component 200. Additionally, the first IPD component 200 can include electrical connections, such as vias, for connecting the first IPD component 200 to the support 102 and / or ground, as shown in and described in connection with Figures 14A and 14B.

[0074] FIG. 5 shows a perspective view of a package according to the present disclosure.

[0075] FIG. 6 shows a cross-sectional view of the package according to FIG.

[0076] In particular, Figures 5 and 6 illustrate another exemplary implementation of package 100, which may include any one or more other features, components, arrangements, etc. described herein. In particular, Figures 5 and 6 illustrate that package 100 may be implemented as an RF package, an RF amplifier package, an RF power amplifier package, an RF power transistor package, an RF power amplifier transistor package, and / or as described herein. Package 100 may include one or more semiconductor devices 400, a first IPD component 200, a second IPD component 300, a third IPD component 800, and / or the like. As further described herein, first IPD component 200, second IPD component 300, and third IPD component 800 may be implemented with thermal conductivity, thermal management, and / or the like to enhance efficiency, performance, and reliability.

[0077] Further, within the package 100, the first IPD component 200 can be disposed on the support 102 as described herein with one or more interconnects 104 shown in an exemplary configuration. Further, within the package 100, the second IPD component 300 and the third IPD component 800 can be disposed on the support 102 and / or the first IPD component 200 as described herein with one or more interconnects 104 shown in an exemplary configuration. The package 100 can include an overmold 530, one or more input / output pins 532, and the support 102. The overmold 530 can substantially surround one or more semiconductor devices 400 mounted on the support 102 with a die attach material 538. The overmold 530 may be formed of a plastic or flexible polymer compound and may be injection molded around the support 102, the one or more semiconductor devices 400, the first IPD component 200, the second IPD component 300, the third IPD component 800, and / or the like, thereby providing protection from the external environment. The one or more semiconductor devices 400, the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 may be coupled to one or more input / output pins 532 via one or more interconnects 104.

[0078] One or more interconnects 104 may be connected to multiple interconnect pads 206. One or more interconnects 104 may be embodied as one or more wires, wire bonds, leads, vias, edge plating, circuit traces, tracks, clips, and / or the like. In one aspect, one or more interconnects 104 may utilize the same type of connection. In one aspect, one or more interconnects 104 may utilize different types of connections.

[0079] In one aspect, the overmolded configuration can substantially surround one or more of the semiconductor devices 400, the first IPD component 200, the second IPD component 300, the third IPD component 800, and / or the like. The overmolded configuration can be formed from plastic, molding compound, flexible plastic compound, polymer, polymer compound, flexible polymer compound, and / or the like. The overmolded configuration can be injection molded, transfer molded, and / or compression molded around the one or more of the semiconductor devices 400, the first IPD component 200, the second IPD component 300, the third IPD component 800, and / or the like, thereby protecting the first IPD component 200, the one or more of the semiconductor devices 400, the second IPD component 300, the third IPD component 800, and other components of the package 100 from the external environment.

[0080] FIG. 7 shows a partial top view of a package according to another specific embodiment of the present disclosure.

[0081] In particular, Figure 7 illustrates another exemplary implementation of package 100, which may include any one or more other features, components, arrangements, etc. described herein. With reference to Figure 7, first IPD component 200 and second IPD component 300 may be disposed on support 102. Additionally, first IPD component 200 may include one or more openings, holes, cutouts, and / or the like, hereinafter referred to as cutouts 298. In an aspect, second IPD component 300 may be disposed in cutout 298 of first IPD component 200, and / or the like, as illustrated in and described in conjunction with Figure 16.

[0082] FIG. 8 shows a partial top view of a package according to another specific embodiment of the present disclosure.

[0083] In particular, FIG. 8 illustrates another exemplary implementation of the package 100, which may include any one or more other features, components, arrangements, etc. described herein. As shown in FIG. 8, the second IPD component 300 may be attached to the support 102. In one aspect, the second IPD component 300 may be directly attached to the support 102. Additionally, one or more implementations of the one or more interconnects 104 may be directly bonded to one or more metal contacts 404 from the one or more semiconductor devices 400. In one aspect, one or more implementations of the one or more interconnects 104 may be directly bonded to one or more metal contacts 404 from the drains of the one or more semiconductor devices 400.

[0084] 8, the first IPD component 200 may be implemented in a continuous bar implementation of one of the interconnect pads 206. Additionally, one or more interconnects 104 may be connected on an output PCB IPD implementation 292 of the first IPD component 200 and to an output IPD implementation 392 of the second IPD component 300. In this regard, the embodiment illustrated in FIG. 8 implements a beneficial configuration such that the one or more interconnects 104 may be shorter, which may result in less inductance, and results in a shorter implementation of the one or more interconnects 104 for shunt tuning wire or series drain wire implementation.

[0085] FIG. 9 shows a partial top view of a package according to another specific embodiment of the present disclosure.

[0086] In particular, Figure 9 illustrates another example implementation of package 100, which may include any one or more other features, components, arrangements, etc. described herein. As shown in Figure 9, an output bar implementation of the plurality of interconnect pads 206 on the output PCB IPD implementation 292 of the first IPD component 200 is divided into two segments. It is further contemplated that the output bar on the output PCB IPD implementation 292 of the first IPD component 200 may be divided into any number of segments.

[0087] FIG. 10 shows a partial top view of a package according to another specific embodiment of the present disclosure.

[0088] In particular, Figure 10 illustrates another example implementation of package 100, which may include any one or more other features, components, arrangements, etc. described herein. In particular, Figure 10 illustrates that at least one device 202 may be disposed on first IPD component 200. In one aspect, at least one device 202 may be disposed directly on first IPD component 200. In one aspect, at least one device 202 may be disposed on output PCB IPD implementation 292 of first IPD component 200.

[0089] In one aspect, the at least one device 202 may be implemented as a baseband decoupling SMD capacitor that may be mounted on the output PCB IPD implementation 292 of the first IPD component 200. In one aspect, the at least one device 202 may be implemented as a baseband decoupling SMD capacitor that may be mounted directly on the output PCB IPD implementation 292 of the first IPD component 200.

[0090] 10 further illustrates that the second IPD component 300 can be connected to the output PCB IPD implementation 292 of the first IPD component 200 by one or more interconnects 104. In one embodiment, the second IPD component 300 can connect to the output PCB IPD implementation 292 of the first IPD component 200 by one or more of the one or more interconnects 104 implemented as wire bonds to form an RF cold spot at the landing point on the support 102. In this regard, the embodiment of FIG. 10 can advantageously have a wide video bandwidth due to the low inductance from the baseband gap (SMD) implementation of at least one device 202 to the output PCB IPD implementation 292 of the first IPD component 200.

[0091] In other embodiments, a separate implementation of a PCB with SMDs may be implemented and may be separate from the output PCB IPD implementation 292 of the first IPD component 200, such as an implementation of a third IPD component 800 implementing at least one device 202.

[0092] The at least one device 202 may be one or more of a surface mount device (SMD) component, a surface mount device (SMD) capacitor, a ceramic capacitor, a surface mount device (SMD) oscillator, a surface mount device (SMD) ceramic capacitor, an inductor, a surface mount device (SMD) inductor, a resistor, a surface mount device (SMD) resistor, a power divider, a surface mount device (SMD) power divider, a power splitter, a surface mount device (SMD) power splitter, an amplifier, a balanced amplifier, a surface mount device (SMD) amplifier, a surface mount device (SMD) balanced amplifier, a combiner, a surface mount device (SMD) combiner, and / or the like. The at least one device 202 may be embodied as a radio frequency device, a radio frequency circuit device, a radio frequency component device, or the like. At least one device 202 may be embodied as a radio frequency device, a radio frequency circuit device, a radio frequency component device, or the like, and may be one or more of a surface mounted device (SMD) radio frequency component, a surface mounted device (SMD) radio frequency capacitor, a radio frequency ceramic capacitor, a surface mounted device (SMD) oscillator, a surface mounted device (SMD) radio frequency ceramic capacitor, a radio frequency inductor, a surface mounted device (SMD) radio frequency inductor, a radio frequency resistor, a surface mounted device (SMD) radio frequency resistor, a radio frequency power divider, a surface mounted device (SMD) radio frequency power divider, a radio frequency power splitter, a surface mounted device (SMD) radio frequency power splitter, a radio frequency amplifier, a balanced radio frequency amplifier, a surface mounted device (SMD) radio frequency amplifier, a surface mounted device (SMD) radio frequency balanced amplifier, a radio frequency combiner, a surface mounted device (SMD) radio frequency combiner, a surface mounted device (SMD) resistor, a surface mounted device (SMD) resistor providing tuning, stability, baseband impedance, and / or the like.

[0093] The package 100 may be implemented as an RF package, and the at least one device 202 may be implemented as a radio frequency device that includes, connects to, supports, or includes a transmitter, transmitter function, a receiver, receiver function, a transceiver, transceiver function, a matching network function, a harmonic termination circuit, an integrated passive device (IPD), etc. The at least one device 202 implemented as a radio frequency device may be configured to, supports, or can be configured to transmit radio waves and modulate the radio waves to transmit data with allowable transmitter power, harmonic, and / or band edge requirements. The at least one device 202 implemented as a radio frequency device may be configured to, supports, or can be configured to receive radio waves and demodulate the radio waves, or the like. At least one device 202 embodied as a radio frequency device may be configured to, support, or the like to transmit radio waves and modulate the radio waves to carry data within allowable transmitter power, harmonics, and / or band edge requirements, and may be configured to, support, or the like to demodulate the radio waves.

[0094] FIG. 11 shows a partial top view of a package according to another specific embodiment of the present disclosure.

[0095] In particular, FIG. 11 illustrates another exemplary implementation of the package 100, which may include any one or more other features, components, arrangements, etc. described herein. With reference to FIG. 11, this implementation may be similar to FIG. 10. Furthermore, the conductive bar of the output PCB IPD implementation 292 of the first IPD component 200 may not be continuous. In particular, as illustrated in FIG. 11, the output bar implementation of the plurality of interconnect pads 206 on the output PCB IPD implementation 292 of the first IPD component 200 is divided into two segments. It is further contemplated that the output bar implementation of the plurality of interconnect pads 206 on the output PCB IPD implementation 292 of the first IPD component 200 may be divided into any number of segments. In this regard, the implementation of the package 100 as illustrated in FIG. 11 may address and reduce stability and odd mode oscillation issues, and / or the like.

[0096] FIG. 12 shows a partial top view of a package according to another specific embodiment of the present disclosure.

[0097] In particular, Figure 12 illustrates another example implementation of package 100, which may include any one or more of the other features, components, arrangements, etc. described herein. As shown in Figure 12, output PCB IPD implementation 292 of first IPD component 200 is divided into two segments. It is further contemplated that output PCB IPD implementation 292 of first IPD component 200 may be divided into any number of segments. Similarly, it is further contemplated that input PCB IPD implementation 294 of first IPD component 200 may be divided into any number of segments.

[0098] FIG. 13 shows a top view of an IPD component according to the present disclosure.

[0099] 14A and 14B show side views of the IPD components according to FIG.

[0100] FIG. 15 shows a partial top view of the IPD components according to FIG.

[0101] In particular, Figures 13, 14A, 14B, and 15 illustrate example implementations of a first IPD component 200 and a second IPD component 300, which may include any one or more other features, components, arrangements, etc. described herein. As illustrated in Figures 13, 14A, and 14B, the first IPD component 200 may be implemented with one or more implementations of the second IPD component 300 disposed thereon. In one aspect, the second IPD component 300 may be disposed directly on the first IPD component 200. With reference to Figure 15, the first IPD component 200 is illustrated without the second IPD component 300 disposed thereon.

[0102] 13, 14A, 14B, and 15 further illustrate that the first IPD component 200 may include a plurality of interconnect pads 206, one or more of which may be configured as an interconnect bond pad. With reference to FIG. 14A, the first IPD component 200 may include a substrate 204. In some aspects, the first IPD component 200 may include a second IPD component 300 as shown. With reference to FIG. 14B, the first IPD component 200 may include a second IPD component 300 disposed on an upper side of the first IPD component 200. In particular, the first IPD component 200 may be connected to the second IPD component 300 by a connecting portion 270. The connecting portion 270 may electrically connect the second IPD component 300 to the first IPD component 200. In certain embodiments, the connection 270 may connect the metallization layer 340 of the second IPD component 300 to the plurality of interconnect pads 206 of the first IPD component 200 by electrical connections 270. In embodiments, the connection 270 may be a die attach material. The connection 270 may be adhesively bonded, soldered, sintered, eutectic bonded, ultrasonically bonded, or as described herein. In one embodiment, the connection 270 comprises a solder. In one embodiment, the connection 270 comprises an epoxy layer. In one embodiment, the connection 270 comprises a gold sinter. In embodiments, the connection 170 or thickness of the die attach material (BLT-bond line thickness) is configured, arranged, structured, and / or can be such as to exceed a minimum height to accommodate CTE (coefficient of thermal expansion) mismatch between the first IPD component 200, the second IPD component 300, and / or the support 102.

[0103] The substrate 204 can be a printed circuit board (PCB) component, a ceramic component, a glass component, a low temperature co-fired ceramic (LTCC) component, a high temperature co-fired ceramic (HTCC) component, a thick film substrate component, and / or the like. In one or more embodiments, the substrate 204 can include Teflon and / or a hydrocarbon material. In one or more embodiments, the substrate 204 can include Teflon and / or a hydrocarbon material mixed with a ceramic filler. In one or more embodiments, the substrate 204 can include Teflon and / or a hydrocarbon material mixed with a ceramic filler implemented as a radio frequency (RF) material.

[0104] 14A, the substrate 204 may include an upper surface 222. The upper surface 222 may lie in a plane generally parallel to the x-axis or a plane generally parallel to the upper surface of the support 102. In this regard, it may be generally defined to be in the range of 0°-15°, 0°-2°, 2°-4°, 4°-6°, 6°-8°, 8°-10°, 10°-12°, or 12°-15°. The upper surface 222 may support a plurality of interconnect pads 206. The plurality of interconnect pads 206 may include a plurality of bond pad areas. The plurality of interconnect pads 206 may be formed by a metal surface on the upper surface 222 of the substrate 204, and may include metallic materials such as copper, gold, nickel, palladium, silver, and combinations thereof.

[0105] Additionally, the first IPD component 200 may include vias 228. The vias 228 may extend from the plurality of interconnect pads 206 to the metallization layer 240. Thus, the terminals of the second IPD component 300 may connect to the first terminal bond pads through the first connections and to the metallization layer 240 through at least the vias 228 to provide electrical connection and / or contact with the support 102. The vias 228 may also extend through the metallization layer 240 to the support 102 to provide electrical connection and / or contact with the support 102. In other aspects, the vias 228 may be implemented only as partial vias. The vias 228 may be metal plated or metal filled holes that may function as electrical tunnels through the substrate 204. The vias 228 may include metallic materials such as copper, gold, nickel, palladium, silver, and combinations thereof. The via 228 can have an axis that can lie in a plane generally perpendicular to the x-axis, a plane generally parallel to the x-axis, and / or a plane generally perpendicular to the upper surface 222 .

[0106] The first IPD component 200 can include a metallization layer 240 located on a lower surface of the substrate 204 opposite the upper surface 222. The metallization layer 240 can be located in a plane generally parallel to the x-axis or a plane generally parallel to the upper surface 222. In one aspect, the metallization layer 240 can be implemented as a full-face metal layer on the lower surface of the substrate 204 opposite the upper surface 222. Additionally or alternatively, the first IPD component 200 can be single-sided having one metal layer; the first IPD component 200 can be double-sided having two metal layers on either side of one substrate layer of the substrate 204; and / or the first IPD component 200 can be multi-layered having outer and inner layers of aluminum, copper, silver, gold, and / or the like alternating with layers of substrate. The first IPD component 200 can include features such as separate conductive lines, tracks, circuit traces, connecting pads, vias for routing connections between layers of aluminum, copper, silver, gold, and / or the like, and solid conductive areas for EM shielding or other purposes. Additionally, the first IPD component 200 can include a circuit structure 260.

[0107] In some embodiments, the first IPD component 200 can include at least one device 202, as illustrated in Figure 10. Accordingly, the present disclosure utilizes a substrate 204 of the first IPD component 200 to support the at least one device 202.

[0108] The substrate 204 can be mounted on the top side of the support 102. The substrate 204 can be mounted on the top surface of the support 102 by adhesive bonding, soldering, sintering, eutectic bonding, ultrasonic bonding, and / or the like, as described herein. In one embodiment, the substrate 204 can be directly attached to the top surface of the support 102. In one embodiment, the substrate 204 can be mounted on the top surface of the support 102 with an intervening structure, component, and / or the like. The top surface of the support 102 can be parallel to the x-axis, and the substrate 204 can be vertically disposed above the support 102 along the y-axis. More specifically, the substrate 204 can at least partially insulate the at least one device 202 from the support 102.

[0109] One or more of the plurality of interconnect pads 206 may be a surface for bonding to one or more interconnects 104. Accordingly, it may be beneficial to ensure that the surfaces of the plurality of interconnect pads 206 are kept clean. In particular, when the at least one device 202 is attached to the plurality of interconnect pads 206, solder may migrate to other surfaces of the plurality of interconnect pads 206. Accordingly, the plurality of interconnect pads 206 may include solder barriers disposed between various bonding areas of the one or more interconnects 104 to the plurality of interconnect pads 206 and bonding areas of the at least one device 202 to the plurality of interconnect pads 206.

[0110] The upper surface 222 may further implement the plurality of interconnect pads 206 as first terminal bond pads. The first terminal bond pads may be disposed in a plane generally parallel to the x-axis or a plane generally parallel to the upper surface 222. The first terminal bond pads may be bonded to a first terminal of at least one device 202. In this regard, a first bonding area may be formed between the first terminal bond pad and the first terminal. The first connection may include adhesive bonding, soldering, sintering, eutectic bonding, ultrasonic welding, and / or as described herein. The first terminal bond pads may be formed by a metal surface on the upper surface 222 of the substrate 204, and may include metallic materials such as copper, gold, nickel, palladium, silver, and combinations thereof.

[0111] In some embodiments, the at least one device 202 may include terminals disposed on a bottom surface. Thus, mounting a device such as the at least one device 202 directly to the support 102 of the package 100 will result in a short circuit. For example, the at least one device 202 implemented as a surface mount device (SMD) component, such as a surface mount device (SMD) ceramic capacitor, may include one or more terminals disposed on a bottom surface of the surface mount device (SMD) component. Thus, mounting the at least one device 202 configured as a surface mount device (SMD) component to the support 102 of the package 100 will result in a short circuit.

[0112] FIG. 16 shows a top view of an IPD component according to the present disclosure.

[0113] 17A and 17B show side views of the IPD components according to FIG.

[0114] In particular, Figures 16, 17A, and 17B show example implementations of the first IPD component 200 and the second IPD component 300, which may include any one or more other features, components, arrangements, etc. described herein. As shown, the first IPD component 200 may include cutouts 298, which may be implemented as routed corners, holes, cutout pockets, and / or the like. Referring to Figure 17B, the first IPD component 200 and the second IPD component 300 may be disposed on the upper side of the support 102. In particular, the first IPD component 200 and / or the second IPD component 300 may be connected to the support 102 by a connecting portion 170. The connecting portion 170 may electrically connect the second IPD component 300 and / or the first IPD component 200 to the support 102. In certain embodiments, the connection 170 may electrically connect the metallization layer 340 of the second IPD component 300 to the support 102. In certain embodiments, the connection 170 may electrically connect the metallization layer 240 of the first IPD component 200 to the support 102. In embodiments, the connection 170 may be a die attach material. The connection 170 may be adhesively bonded, soldered, sintered, eutectic bonded, ultrasonically bonded, or as described herein. In one embodiment, the connection 270 comprises a solder. In one embodiment, the connection 270 comprises an epoxy layer. In one embodiment, the connection 270 comprises a gold sinter. In an embodiment, the connection portion 270 or thickness of the die attach material (BLT - bond line thickness) may be configured, arranged, structured, and / or the like to exceed a minimum height to accommodate CTE (coefficient of thermal expansion) mismatch between the first IPD component 200, the second IPD component 300, and / or the support 102.

[0115] In particular, the cutouts 298 can be formed as cutouts in the first IPD component 200 and / or substrate 204, cutout areas and / or portions of the first IPD component 200 and / or substrate 204, areas where the first IPD component 200 and / or substrate 204 are modified, cut, sawn, wired, drilled, etc. Thus, the first IPD component 200 can implement the cutouts 298 to structurally form shapes that can be configured to increase efficient use of space within the package 100 and to improve performance, reliability, and / or the like. In particular, the first IPD component 200 and the second IPD component 300 can fit together like a jigsaw puzzle to efficiently use space.

[0116] Disposed within the cutout 298 of the first IPD component 200 may be one or more implementations of a second IPD component 300. In one aspect, the first IPD component 200 and the second IPD component 300 may be mounted directly to the support 102. Additionally, one or more interconnects 104 may connect between the first IPD component 200 and the second IPD component 300, as shown in FIG.

[0117] FIG. 18 shows a side view of an IPD component according to the present disclosure.

[0118] FIG. 19 shows a bottom view of the IPD components according to FIG.

[0119] FIG. 20 shows a side view of the IPD components according to FIG.

[0120] In particular, Figures 18, 19, and 20 depict example implementations of a first IPD component 200 and a second IPD component 300, which may include any one or more other features, components, arrangements, etc. described herein. As shown, the second IPD component 300 may be attached to the support 102. In one embodiment, the second IPD component 300 may be directly attached to the support 102. In one embodiment, the first IPD component 200 may be disposed on the second IPD component 300. In one embodiment, the first IPD component 200 may be directly disposed on the second IPD component 300. Additionally, the first IPD component 200 may be electrically attached to the second IPD component 300.

[0121] The first IPD component 200 may have pads on a bottom surface that may be implemented by a metallization layer 240, and the second IPD component 300 may have pads on a top surface that may be implemented by a plurality of interconnect pads 306. The pads of the first IPD component 200 and the pads of the second IPD component 300 may be matching pads. Thus, the first IPD component 200 may be attached to the second IPD component 300 by the matching pads. This attachment may include adhesive bonding, soldering, sintering, eutectic bonding, ultrasonic welding, and / or the like, as described herein. In an aspect, the first IPD component 200 may include wiring and interconnecting through one or more layers within the first IPD component 200.

[0122] FIG. 21 shows a side view of an IPD component according to the present disclosure.

[0123] 21 illustrates an example implementation of a second IPD component 300, which may include any one or more other features, components, arrangements, etc. described herein. The second IPD component 300 may include a substrate 304, a dielectric layer 362, a top metal 364, a bottom metal 366, a metallization layer 340, and / or the like. In particular, the second IPD component 300 may form a capacitor having the top metal 364 and the bottom metal 366 with the dielectric layer 362 therebetween.

[0124] The top metal 364 may be disposed parallel to the x-axis as shown, and the top metal 364 may be contiguous and disposed parallel to the bottom metal 366. Additionally, the top metal 364 may be disposed vertically above the bottom metal 366 along the y-axis as shown.

[0125] The substrate 304 may include silicon carbide (SiC). The substrate 304 may be made of silicon carbide (SiC). In some embodiments, the substrate 304 may be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, and / or the like. In one embodiment, the substrate 304 may be very lightly doped. In one embodiment, the substrate 304 may be formed of SiC selected from the group consisting of 6H, 4H, 15R, 3C SiC, or the like. In one embodiment, the substrate 304 may be formed of SiC, which may be semi-insulating and doped with vanadium or any other suitable dopant, or may be high purity undoped with defects that provide semi-insulation. In other embodiments, the substrate 304 may include silicon, alumina, aluminum nitride (AlN), beryllium oxide (BeO), titanium oxide (TiO), metal oxide substrates, high dielectric metal oxide substrates, high dielectric substrates, thermally conductive high dielectric materials / substrates, and / or other similar thermally conductive performance dielectric materials. The substrate 304 may include an upper surface 322. The upper surface 322 may support a bottom metal 366.

[0126] The bottom metal 366 may be disposed on the upper surface 322 of the substrate 304. In particular, there may be one or more intervening layers or structures (not shown) between the upper surface 322 of the substrate 304 and the bottom metal 366.

[0127] The bottom metal 366 may be formed as a metallic surface on the upper surface 322 of the substrate 304 and may include metallic materials such as copper, gold, nickel, palladium, silver, tin, gold-tin alloys, and the like, as well as combinations thereof. In one embodiment, the bottom metal 366 may have a thickness along the y-axis of 0.1 microns to 0.6 microns, 0.1 microns to 0.2 microns, 0.2 microns to 0.3 microns, 0.3 microns to 0.4 microns, 0.4 microns to 0.5 microns, or 0.5 microns to 0.6 microns.

[0128] The dielectric layer 362 may be disposed on the bottom metal 366 and / or the substrate 304. Notably, there may be one or more intervening layers or structures (not shown) between the dielectric layer 362 and the bottom metal 366. In other embodiments, the dielectric layer 362 may be disposed directly on the bottom metal 366. In one embodiment, the dielectric layer 362 may be continuous. The dielectric layer 362 may include SiN, AlO, SiO, SiO2, AlN, or the like, or combinations thereof, along with other intervening layers. The dielectric layer 362 may have any thickness along the y-axis to provide a desired capacitance density, capacitance, standoff voltage, and / or the like. In some embodiments, the dielectric layer 362 can have a thickness along the y-axis of 100 Å to 11000 Å, 100 Å to 1000 Å, 1000 Å to 2000 Å, 2000 Å to 3000 Å, 3000 Å to 4000 Å, 4000 Å to 5000 Å, 5000 Å to 6000 Å, 6000 Å to 7000 Å, 7000 Å to 8000 Å, 8000 Å to 9000 Å, 9000 Å to 10000 Å, or 10000 Å to 11000 Å. In some embodiments, the dielectric layer 362 can have a thickness along the y-axis of greater than 10000 Å.

[0129] The top metal 364 may be disposed on the dielectric layer 362. Notably, there may be one or more intervening layers or structures (not shown) between the top metal 364 and the dielectric layer 362. In other embodiments, the top metal 364 may be disposed directly on the dielectric layer 362. The top metal 364 may be formed as a metallic surface on the upper surface of the dielectric layer 362 and may include metallic materials such as copper, gold, nickel, palladium, silver, tin, gold-tin alloys, and combinations thereof. In some embodiments, the top metal 364 may include a laminated layer. In one embodiment, the top metal 364 can have a thickness along the Y-axis of 0.1 microns to 7 microns, 0.1 microns to 0.2 microns, 0.2 microns to 0.3 microns, 0.3 microns to 0.4 microns, 0.4 microns to 0.5 microns, 0.5 microns to 0.6 microns, 0.6 microns to 0.7 microns, 0.7 microns to 1 micron, 1 micron to 2 microns, 2 microns to 3 microns, 3 microns to 4 microns, 4 microns to 5 microns, 5 microns to 6 microns, or 6 microns to 7 microns.

[0130] The substrate 304 can include a lower surface 324. The second IPD component 300 can include a metallization layer 340 located on the lower surface 324 of the substrate 304 opposite the upper surface 322. The metallization layer 340 can be located in a plane generally parallel to the x-axis or a plane generally parallel to the upper surface 322. The metallization layer 340 can include metallic materials such as copper, gold, nickel, palladium, silver, tin, gold-tin alloys, and combinations thereof. In one embodiment, the metallization layer 340 can have a thickness along the y-axis of 1 micron to 9 microns, 1 micron to 2 microns, 2 microns to 3 microns, 3 microns to 4 microns, 4 microns to 5 microns, 5 microns to 6 microns, 6 microns to 7 microns, 7 microns to 8 microns, or 8 microns to 9 microns.

[0131] Additionally, the second IPD component 300 may include electrical connections, such as vias 328. However, any type of electrical connections are contemplated. In certain embodiments, the substrate 304 of the second IPD component 300 may include vias 328 that extend along the Y-axis through the substrate 304. One or more of the vias 328 may be electrically connected to the metallization layer 340. Additionally, one or more of the vias 328 may be electrically connected to the bottom metal 366.

[0132] The vias 328 may be metal plated or metal filled holes that may act as electrical tunnels through the substrate 304. The vias 328 may include metallic materials such as copper, gold, nickel, palladium, silver, tin, gold-tin alloys, and combinations thereof. The vias 328 may have an axis that may lie in a plane generally perpendicular to the x-axis, a plane generally parallel to the x-axis, and / or a plane generally perpendicular to the upper surface 322.

[0133] The metallization layer 340 may form a first connection, node, and / or port for the second IPD component 300, and the top metal 364 and / or the plurality of interconnect pads 306 may form a second connection, node, and / or port for the second IPD component 300.

[0134] The upper surface 322 of the top metal 364 can support a number of interconnect pads 306. The number of interconnect pads 306 can include a number of bond pad areas. The number of interconnect pads 306 can be formed by a metal surface on the dielectric layer 362 and / or the top metal 364 and can include metallic materials such as copper, gold, nickel, palladium, silver, and combinations thereof.

[0135] Thus, the second IPD component 300 can form a capacitor, whose capacitance is defined by the area of ​​the bottom metal 366, the top metal 364, and the thickness and dielectric constant of the dielectric layer 362, and can have a separate insulating area on the backside of the substrate 304 for electrical connection by the metallization layer 340.

[0136] FIG. 22 shows a side view of an IPD component according to the present disclosure.

[0137] In particular, Figure 22 illustrates an example implementation of a third IPD component 800, which may include any one or more other features, components, arrangements, etc. described herein. With reference to Figure 22, the third IPD component 800 may include a substrate 804, at least one device 202, and / or the like.

[0138] The substrate 804 may be a printed circuit board (PCB) component, a ceramic component, a glass component, a low temperature co-fired ceramic (LTCC) component, a high temperature co-fired ceramic (HTCC) component, a thick film substrate component, and / or the like. In one or more embodiments, the substrate 804 may include Teflon and / or a hydrocarbon material. In one or more embodiments, the substrate 804 may include Teflon and / or a hydrocarbon material mixed with a ceramic filler. In one or more embodiments, the substrate 804 may include Teflon and / or a hydrocarbon material mixed with a ceramic filler implemented as a radio frequency (RF) material.

[0139] 22, the substrate 804 may include an upper surface 822. The upper surface 822 may lie in a plane generally parallel to the x-axis or a plane generally parallel to the upper surface of the support 102. In this regard, it may be generally defined to be in the range of 0°-15°, 0°-2°, 2°-4°, 4°-6°, 6°-8°, 8°-10°, 10°-12°, or 12°-15°. The upper surface 822 may support a plurality of interconnect pads 806. The plurality of interconnect pads 806 may include a plurality of bond pad regions. The plurality of interconnect pads 806 may be formed by a metal surface on the upper surface 822 of the substrate 804 and may include metallic materials such as copper, gold, nickel, palladium, silver, and combinations thereof.

[0140] In some embodiments, the at least one device 202 may include terminals disposed on a bottom surface. Thus, mounting a device such as the at least one device 202 directly to the support 102 of the package 100 will result in a short. For example, the at least one device 202 implemented as a surface mount device (SMD) component, such as a surface mount device (SMD) ceramic capacitor, may include one or more terminals disposed on a bottom surface of the surface mount device (SMD) component. Thus, mounting the at least one device 202 configured as a surface mount device (SMD) component to the support 102 of the package 100 will result in a short.

[0141] Thus, the present disclosure utilizes a substrate 804 of the third IPD component 800 to support at least one device 202. The substrate 804 may be mounted to an upper surface of the support 102. The substrate 804 may be mounted to the upper surface of the support 102 by adhesive bonding, soldering, sintering, eutectic bonding, ultrasonic bonding, and / or the like, as described herein. In one embodiment, the substrate 804 may be directly mounted to the upper surface of the support 102. In one embodiment, the substrate 804 may be mounted to the upper surface of the support 102 with an intervening structure, component, and / or the like. The upper surface of the support 102 may be parallel to the x-axis, and the substrate 804 may be vertically disposed above the support 102 along the y-axis, as shown in FIG. 22. In one embodiment, the substrate 804 may be at least partially insulating. More specifically, the substrate 804 may at least partially insulate the at least one device 202 from the support 102.

[0142] In one embodiment, one or more of the plurality of interconnect pads 806 may be a surface for bonding to one or more interconnects 104. Accordingly, it may be beneficial to ensure that the surfaces of the plurality of interconnect pads 806 are kept clean. In particular, when the at least one device 202 is attached to the plurality of interconnect pads 806, solder may migrate to other surfaces of the plurality of interconnect pads 806. Accordingly, the plurality of interconnect pads 806 may include solder barriers disposed between various bonding areas of the one or more interconnects 104 to the plurality of interconnect pads 806 and bonding areas of the at least one device 202 to the plurality of interconnect pads 806.

[0143] The upper surface 822 may further implement the plurality of interconnect pads 806 as first terminal bond pads. The first terminal bond pads may be disposed in a plane generally parallel to the x-axis or a plane generally parallel to the upper surface 822. The first terminal bond pads may be bonded to a first terminal of at least one device 202. In this regard, a first connection 820 may be formed between the first terminal bond pad and the first terminal. The first connection 820 may include adhesive bonding, soldering, sintering, eutectic bonding, ultrasonic welding, and / or the like, as described herein. The first terminal bond pads may be formed by a metal surface on the upper surface 822 of the substrate 804, and may include metallic materials such as copper, gold, nickel, palladium, silver, and combinations thereof.

[0144] The upper surface 822 may further implement another one of the plurality of interconnect pads 806 as a second terminal bond pad. The second terminal bond pad may be disposed in a plane generally parallel to the x-axis or a plane generally parallel to the upper surface 822. The second terminal bond pad may be bonded to a second terminal of at least one device 202. In this regard, a second connection 818 may be formed between the second terminal bond pad and the second terminal. The second terminal bond pad may be electrically connected in part to the plurality of interconnect pads 806. The second connection 818 may include adhesive bonding, soldering, sintering, eutectic bonding, ultrasonic welding, and / or the like, as described herein. The second terminal bond pad may be formed by a metal surface on the upper surface 822 of the substrate 804, and may include metallic materials such as copper, gold, nickel, palladium, silver, and combinations thereof. Additionally, the upper surface 822 of the substrate 804 may include additional terminals for at least one device 202, if desired.

[0145] The third IPD component 800 can include a metallization layer 840 located on a lower surface of the substrate 804 opposite the upper surface 822. The metallization layer 840 can be located in a plane generally parallel to the x-axis or a plane generally parallel to the upper surface 822. In one aspect, the metallization layer 840 can be implemented as a full-face metal layer on the lower surface of the substrate 804 opposite the upper surface 822. Additionally or alternatively, the third IPD component 800 can be single-sided having one metal layer; the third IPD component 800 can be double-sided having two metal layers on either side of one substrate layer of the substrate 804; and / or the third IPD component 800 can be multi-layered having outer and inner layers of aluminum, copper, silver, gold, and / or the like alternating with layers of substrate. The third IPD component 800 may include features such as separate conductive lines, tracks, circuit traces, connecting pads, vias for routing connections between layers of aluminum, copper, silver, gold, and / or the like, and solid conductive areas for EM shielding or other purposes.

[0146] Additionally, the third IPD component 800 may include vias 828. The vias 828 may extend from the plurality of interconnect pads 806 to the metallization layer 840. Thus, the terminal of at least one device 202 may connect to the first terminal bond pad through the first connection 820 and to the metallization layer 840 through at least the vias 828 to provide electrical connection and / or contact with the support 102. The vias 828 may also extend through the metallization layer 840 to the support 102 to provide electrical connection and / or contact with the support 102. In other aspects, the vias 828 may be implemented only as partial vias. The vias 828 may be metal plated or metal filled holes that may function as electrical tunnels through the substrate 804. The vias 828 may comprise metallic materials such as copper, gold, nickel, palladium, silver, and combinations thereof. The via 828 can have an axis that can lie in a plane generally perpendicular to the x-axis, a plane generally parallel to the x-axis, and / or a plane generally perpendicular to the upper surface 822.

[0147] Additionally or alternatively, the first IPD component 200 and / or the third IPD component 800 can include conductors on different layers that can be connected with vias, which can be copper-, aluminum-, silver-, gold-, and / or such metal-plated holes that can act as electrical tunnels through a dielectric substrate. The first IPD component 200 and / or the third IPD component 800 can include "through-hole" components that can be mounted by passing their wire leads through a substrate and being lead-soldered to traces on the other side. The first IPD component 200 and / or the third IPD component 800 can include "surface-mount" components that are attached by their leads and / or terminals.

[0148] The first IPD component 200, metallization layer 240, third IPD component 800 and / or metallization layer 840 can be manufactured using one or more manufacturing techniques including print screening or dispensing on solder paste, print screening or dispensing on epoxy, silk screen printing process, photolithography process, printing on transparency film process, photomask process, photo-sensitized substrate process, laser resist ablation process, milling process, laser etching process, and / or the like. In one or more embodiments, the first IPD component 200 and / or the third IPD component 800 can be configured to mechanically support at least one device 202 and electrically connect to the first IPD component 200 and / or the third IPD component 800 and other electronic components.

[0149] In aspects, RF devices may be configured and implemented in the first IPD component 200, the second IPD component 300, and / or the third IPD component 800. In particular, RF devices may be configured and implemented in the first IPD component 200, the second IPD component 300, and / or the third IPD component 800. RF devices may include matching networks, harmonic termination circuits, integrated passive devices (IPDs), etc.

[0150] In particular, RF devices may be configured and implemented in the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 as matching networks, harmonic termination circuits, integrated passive devices (IPDs), and the like, utilizing less expensive ceramic-based surface passive devices (SMDs) that are typically mounted directly to traces on the first IPD component 200 to replace more expensive silicon-based capacitors. In various aspects, the present disclosure is directed to mounting surface mounted discrete devices (SMDs) to the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 implemented as a submount that may be mounted to a support 102, such as a metal flange, metal lead frame, base, and the like. The submount may be wire bonded, and the like, to an RF device, such as a die, by input and / or output leads of the RF package, which may be metal-based.

[0151] Additionally or alternatively, the first IPD component 200 and / or the third IPD component 800 can include conductors on different layers that can be connected with vias, which can be metal plated holes such as copper plated holes, aluminum plated holes, silver plated holes, gold plated holes and / or the like that can act as electrical tunnels through a dielectric substrate. The first IPD component 200 and / or the third IPD component 800 can include "through hole" components that can be mounted by passing their wire leads through a substrate and being lead soldered to traces on the other side. The first IPD component 200 and / or the third IPD component 800 can include "surface mount" components that can be attached by their leads and / or terminals.

[0152] The first IPD component 200 and / or the metallization layer 240 can be manufactured using one or more manufacturing techniques including print screening or dispensing on solder paste, print screening or dispensing on epoxy, silk screen printing process, photolithography process, printing on transparency film process, photomask process, photo-sensitized substrate process, laser resist ablation process, milling process, laser etching process, and / or the like. In one or more embodiments, the first IPD component 200 can be configured to mechanically support at least one device 202 and electrically connect to the first IPD component 200 and other electronic components.

[0153] Further, the first IPD component 200 and / or the third IPD component 800 may include a circuit structure, such as the circuit structure 260 illustrated in FIG. 13 of the first IPD component 200. In particular, the circuit structure may be disposed adjacent to at least one device 202 and may be configured to provide inductance, capacitance, resistance, and / or the like. In one aspect, the circuit structure may be a metal surface disposed on the top side and may form a capacitor together with a metallization layer. Furthermore, the circuit structure may be configured as an inductive strip, an inductive coil, a capacitive stub, and / or the like. In one aspect, the circuit structure may implement a resistor, such as a thin film resistor, a thick film resistor, a printed thin film resistor, a printed thick film resistor, and / or the like, that is disposed on the first IPD component 200 and / or the third IPD component 800 and printed on the first IPD component 200 and / or the third IPD component 800.

[0154] In one aspect, the circuit structure may be implemented as an open-ended shunt stub. In this regard, the circuit structure may be constructed using a top metallization on the upper surface 222 on the substrate 204, with a bottom metallization implemented by the dielectric layer and metallization layer 240 of the substrate 204 forming the capacitance. A plurality of interconnect pads 206 implementing the open-ended shunt stub may be spaced between at least one device 202 to form a low value capacitance suitable for second harmonic or third harmonic optimization of one or more semiconductor devices 400. A plurality of interconnect pads 206 implementing harmonic shunt stubs may be arranged on the first IPD component 200 such that there is one stub available for each of the one or more semiconductor devices 400. Additional capacitive areas may be created using a large continuous rectangular area implementation of the circuit structure connected to the shunt stub and located behind the row of vias 228.

[0155] The adhesives of the present disclosure can be utilized in adhesive bonding processes that can include applying an intermediate layer to connect the surfaces to be connected. The adhesives can be organic or inorganic, and the adhesives can be deposited on one or both surfaces of the surfaces to be connected. The adhesives can be utilized in adhesive bonding processes that can include applying the adhesive material at a specific coating thickness, at a specific bonding temperature, for a specific processing time, under an environment that can include applying a specific tool pressure. In one aspect, the adhesive is a conductive adhesive, an epoxy adhesive, a conductive epoxy adhesive, and / or the like.

[0156] The solders of the present disclosure can be utilized to form a solder interface that can include and / or be formed from solder. The solder can be any fusible metal alloy that can be used to form a bond between surfaces to be joined. The solder can be lead-free solder, lead solder, eutectic solder, etc. Lead-free solder can include traces of tin, copper, silver, bismuth, indium, zinc, antimony, or other metals, etc. Lead solder can include other metals such as lead, tin, silver, and / or the like. The solder can further include a flux, if desired.

[0157] Sintering of the present disclosure may utilize a process of compressing and forming a conductive mass of material with heat and / or pressure. The sintering process may operate without melting the material to the point of liquefying. The sintering process may include sintering of metal nanopowder or hybrid powder in paste or epoxy. The sintering process may include sintering in a vacuum. The sintering process may include sintering using a protective gas.

[0158] The eutectic bonding of the present disclosure may utilize a eutectic soldering process that may form a eutectic system. The eutectic system may be used between the surfaces to be connected. The eutectic bonding may utilize metals that are alloys and / or intermetallic compounds that transition from a solid state to a liquid state or from a liquid state to a solid state at a particular composition and temperature. The eutectic alloy may be deposited by methods such as sputtering, evaporation, electroplating, and / or the like.

[0159] Ultrasonic welding of the present disclosure can utilize a process in which high frequency ultrasonic acoustic vibrations are applied locally to components that are held together under pressure. Ultrasonic welding can form a solid weld between the surfaces being joined. In one aspect, ultrasonic welding involves the application of an ultrasonic force.

[0160] The package 100 can be implemented in any number of different applications. In this regard, the package 100 may be implemented in applications implementing high video bandwidth power amplifier transistors, single pass radio frequency power transistors, single stage radio frequency power transistors, multi-pass radio frequency power transistors, Doherty configured multi-stage radio frequency power transistors, GaN based radio frequency power amplifier modules, laterally diffused metal oxide semiconductor (LDMOS) devices, LDMOS radio frequency power amplifier modules, radio frequency power devices, ultra-wideband devices, GaN based devices, components such as metal-semiconductor field effect transistors (MESFETs), metal-oxide field effect transistors (MOSFETs), junction field effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), wide band gap (WBG) semiconductors, power modules, gate drivers, general purpose broadband components, telecom components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components, and / or the like. Package 100 may be implemented as a power package. Package 100 may be implemented as a power package and may implement the applications and components described herein.

[0161] The package 100 may be implemented as a radio frequency package. The package 100 may be implemented as a radio frequency package and may implement the applications and components described herein. The package 100 implemented as a radio frequency package may include, connect to, support, or be a transmitter, transmitter functionality, a receiver, receiver functionality, a transceiver, transceiver functionality, and the like. The package 100 implemented as a radio frequency package may be configured to, support, or be such as to transmit radio waves and modulate the radio waves to transmit data at allowed transmitter power, harmonics, and / or band edge requirements. The package 100 implemented as a radio frequency package may be configured to, support, or be such as to receive radio waves and demodulate the radio waves. The package 100 implemented as a radio frequency package may be configured to, support, or be configured to transmit radio waves and modulate the radio waves to transmit data at allowed transmitter power, harmonics, and / or band edge requirements, and may be configured to, support, or be such as to receive radio waves and demodulate the radio waves, or the like.

[0162] The first IPD component 200, the second IPD component 300, and / or the third IPD component 800 may be active devices, passive devices, IPDs, transistor devices, etc. The first IPD component 200, the second IPD component 300, and / or the third IPD component 800 may include any electrical component for any application. In this regard, the first IPD component 200 may be a component such as a high video bandwidth power amplifier transistor, a single pass radio frequency power transistor, a single stage radio frequency power transistor, a multipass radio frequency power transistor, a multistage radio frequency power transistor, a GaN based radio frequency power amplifier module, a laterally diffused metal oxide semiconductor (LDMOS) device, an LDMOS radio frequency power amplifier module, a radio frequency power device, an ultra wideband device, a GaN based device, a metal-semiconductor field effect transistor (MESFET), a metal-oxide field effect transistor (MOSFET), a junction field effect transistor (JFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), a wide band gap (WBG) semiconductor, a power module, a gate driver, a general purpose broadband component, a telecom component, an L-band component, an S-band component, an X-band component, a C-band component, a Ku-band component, a satellite communication component, and / or the like. The first IPD component 200, the second IPD component 300, and / or the third IPD component 800 may be implemented as radio frequency devices and may be configured to, support, or the like to transmit radio waves and modulate them to carry data at the allowable transmitter power, harmonics, and / or band edge requirements. The first IPD component 200 implemented as a radio frequency device may be configured to, support, or the like to receive radio waves and demodulate the radio waves.The first IPD component 200, the second IPD component 300, and / or the third IPD component 800 may be implemented as radio frequency devices and may be configured to, support, or the like to transmit radio waves and carry data with allowable transmitter power, harmonics, and / or band edge requirements.

[0163] FIG. 23 illustrates a manufacturing process for an IPD component according to the present disclosure.

[0164] In particular, FIG. 23 illustrates a process 600 for forming an IPD component associated with the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 described herein. It should be noted that aspects of the process 600 for forming an IPD component may be performed in a different order consistent with the aspects described herein. Additionally, it should be noted that portions of the process 600 for forming an IPD component may be performed in a different order consistent with the aspects described herein. Additionally, the process 600 for forming an IPD component may be modified to include one or more processes consistent with various aspects disclosed herein. Additionally, the process 600 for forming an IPD component may include any other aspects of the disclosure described herein.

[0165] Initially, process 600 for forming an IPD component may include process 602 for forming a substrate. More specifically, substrate 204, substrate 304, and / or substrate 804 may be constructed, arranged, and / or configured as described herein. Additionally, via 228 may be formed in substrate 204, via 328 may be formed in substrate 304, and / or via 828 may be formed in substrate 804.

[0166] Additionally, the process 600 of forming an IPD component may include forming a metallization layer 604. More specifically, the metallization layer 240 may be constructed, configured, and / or disposed as described herein on at least a portion of the substrate 204, the metallization layer 340 may be constructed, configured, and / or disposed as described herein on at least a portion of the substrate 304, and the metallization layer 840 may be constructed, configured, and / or disposed as described herein on at least a portion of the substrate 804. The process 604 of forming a metallization layer may include utilizing one or more manufacturing techniques including print screening for solder paste, print screening for epoxy, silk screen printing process, photolithography process, print process on transparent film, photomask process combined with etching process, photo intensified substrate process, laser resist ablation process, milling process, laser etching process, direct process, and / or the like.

[0167] Further, forming 604 the metallization layer may include forming interconnect pads. More specifically, the plurality of interconnect pads 206 may be constructed, configured, and / or arranged as described herein on the substrate 204. And, the plurality of interconnect pads 306 may be constructed, configured, and / or arranged as described herein on the substrate 304. Further, the plurality of interconnect pads 806 may be constructed, configured, and / or arranged as described herein on the substrate 804. The process of forming the interconnect pads may include utilizing one or more manufacturing techniques including using print screening for solder paste, print screening for epoxy, silk screen printing process, photolithography process, printing process on transparent film, photomask process combined with etching process, photo intensified substrate process, laser resist ablation process, milling process, laser etching process, direct metal printing process, and / or similar processes.

[0168] Additionally, forming 604 the metallization layer may include forming the bottom metal 366 with the dielectric layer 362. The process of forming the bottom metal 366 may include utilizing one or more manufacturing techniques including using print screening for solder paste, print screening for epoxy, silk screen printing process, photolithography process, printing process on transparent film, photomask process combined with etching process, photo intensified substrate process, laser resist ablation process, milling process, laser etching process, direct metal printing process, and / or such processes. Additionally, the process 600 of forming the IPD component may include forming a cutout 298 in the first IPD component 200. The cutout 298 may be formed using a drill, laser cut, router, saw, and / or the like.

[0169] Additionally, the process 600 of forming an IPD component can include disposing at least one device on a substrate 606. More specifically, the at least one device 202 can be constructed, configured, and / or disposed as described herein on the substrate 204 of the first IPD component 200 and / or the substrate 804 of the third IPD component 800. In one aspect, the at least one device 202 can be disposed as described herein on the substrate 204 using adhesives, soldering, sintering, eutectic bonding, ultrasonic welding, and / or the like, as described herein. In one aspect, the at least one device 202 can be disposed as described herein on the substrate 804 using adhesives, soldering, sintering, eutectic bonding, ultrasonic welding, and / or the like, as described herein.

[0170] More specifically, the process 600 of forming the IPD components may include manufacturing steps of forming the first IPD component 200, the second IPD component 300 and / or the third IPD component 800 on a panel, a wafer, and / or the like. The process 600 of forming the IPD components may include performing a pick-and-place assembly to place at least one device 202 on the first IPD component 200 and / or the third IPD component 800 on the panel. The process 600 of forming the IPD components may include performing a reflow process on the panel. The process 600 of forming the IPD components may include cutting the panel and / or wafer using a cutting device such as a wafer, circuit board, or package sawing device to singulate the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 from the panel or wafer, which may have the advantage that the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 are placed on a dicing tape on a ring frame and can be loaded directly into a die attach device for subsequent assembly into the package 100.

[0171] In one aspect, the process 600 for forming the IPD components can include processing utilizing a surface mount technology (SMT) line. The surface mount technology (SMT) line can utilize a number of processes including solder printing, component placement, solder reflow, and / or the like. Additional processes can include a flux cleaning step to remove any flux residue, wire bonding, dicing, attaching to a dicing tape, dicing, either mechanical sawing or laser cutting, or a combination of both, and component testing. Additionally, the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 can be placed on a dicing tape to serve as an input for a die attach machine.

[0172] FIG. 24 illustrates a manufacturing process for a package according to the present disclosure.

[0173] In particular, FIG. 24 illustrates a process 700 for forming a package related to the package 100 described herein. It should be noted that aspects of the process 700 for forming a package may be performed in a different order consistent with the aspects described herein. Additionally, it should be noted that aspects of the process 700 for forming a package may be performed in a different order consistent with the aspects described herein. Additionally, the process 700 for forming a package can be modified to have more or fewer processes consistent with various aspects disclosed herein. Additionally, the process 700 for forming a package can include other aspects of the present disclosure as described herein.

[0174] Initially, the process 700 of forming a package can include a process 702 of forming a support. More specifically, the support 102 can be configured, arranged, and / or positioned as described herein. In one aspect, the process 702 of forming a support can include forming the support 102 as a support, a surface, a package support, a package surface, a package support surface, a flange, a heat sink, a source-grounded heat sink, and / or the like.

[0175] The process 700 of forming the package may include the process 600 of forming the IPD components. More specifically, the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 may be configured, arranged, and / or positioned as described herein with reference to FIG. 23 and its associated description. Thereafter, the process 600 of forming the IPD components may further include attaching the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 to the support 102. In this regard, the first IPD component 200, the second IPD component 300, and / or the third IPD component 800 may be mounted to the support 102 and / or the upper surface of the first IPD component 200 by adhesive, soldering, sintering, eutectic bonding, ultrasonic bonding, etc., as described herein.

[0176] The process 700 of forming the package can include a process 704 of forming one or more interconnects. More specifically, the one or more interconnects 104 can be configured, arranged, and / or positioned as described herein. In one aspect, the process 704 of forming one or more interconnects can include forming the one or more interconnects 104 by forming one or more wires, leads, vias, edge plating, circuit traces, tracks, and / or the like. In one aspect, the process 704 of forming one or more interconnects can include connecting the one or more interconnects 104 by adhesives, soldering, sintering, eutectic bonding, ultrasonic bonding, clip components, and / or the like, as described herein.

[0177] The process 700 of forming the package can include a process 706 of encapsulating the package. More specifically, the package 100 can be constructed, configured, and / or arranged as described herein. In one aspect, the process of encapsulating the package 706 can include forming an open cavity configuration, an overmolded configuration, or the like.

[0178] Thus, the present disclosure provides a number of different IPD components, RF products implementing a number of different types of IPD components, and / or the like configured for utilization of multiple components, increased functionality, and efficient utilization of space.

[0179] The following are a number of non-limiting examples of aspects of the present disclosure. Examples include Example 1. A transistor device comprising: a metal submount; a transistor die disposed on the metal submount; a first integrated passive device (IPD) component including a first substrate disposed on the metal submount; and a second integrated passive device (IPD) component including a second substrate disposed on the metal submount, the first substrate being a different material than the second substrate.

[0180] The above embodiments may further include any one or a combination of two or more of the following embodiments: 2. A transistor device as described in any of the embodiments herein, wherein the first integrated passive device (IPD) component comprises a printed circuit board (PCB) substrate; and the second integrated passive device (IPD) component comprises a silicon carbide (SiC) substrate. 3. A transistor device as described in any of the embodiments herein, wherein the first integrated passive device (IPD) component comprises a printed circuit board (PCB) integrated passive device (IPD) and the second integrated passive device (IPD) component comprises a silicon carbide (SiC) integrated passive device (IPD). 4. A transistor device as described in any of the embodiments herein, wherein the second integrated passive device (IPD) component includes a cutout portion configured to receive the second integrated passive device (IPD) component. 5. 5. A transistor device as described in any embodiment herein, wherein the first integrated passive device (IPD) component comprises a surface mounted device mounted on a top surface of the first integrated passive device (IPD) component. 6. A transistor device as described in any of the embodiments herein, wherein the first substrate includes at least one via configured to provide an electrical connection between the surface mounted device and the metal submount. 7. The transistor device of any of the embodiments herein, wherein a first integrated passive device (IPD) component is disposed between a second integrated passive device (IPD) component and a metal submount. 8. The transistor device of any of the embodiments herein, wherein a second integrated passive device (IPD) component is disposed between the first integrated passive device (IPD) component and the metal submount. 9. A transistor device as described in any embodiment herein, comprising a third IPD component comprising a third substrate, wherein the first substrate is the same material as the third substrate. 10. A transistor device as described in any embodiment herein, wherein the third IPD component comprises a surface mounted device mounted on a top surface of the third IPD component. 11. A transistor device as described in any of the embodiments herein, wherein the third substrate includes at least one via configured to provide an electrical connection between the surface mounted device and the metal submount. 12. The transistor device of any of the embodiments herein, wherein the third IPD component comprises a printed circuit board (PCB) integrated passive device (IPD). 13. The transistor device of any of the embodiments herein, wherein the third IPD component comprises a printed circuit board (PCB) substrate. 14. The transistor device of any of the embodiments herein, wherein the transistor die comprises one or more LDMOS transistor dies. 15. The transistor device of any of the embodiments herein, wherein the transistor die includes one or more GaN-based HEMTs. 16. The transistor device of any of the embodiments herein, wherein the transistor device comprises a plurality of transistor dies. 17. The transistor device of any of the embodiments herein, wherein the multiple transistor dies are in a Doherty configuration.

[0181] One embodiment includes Example 18. A method of implementing a transistor device, the method including: providing a metal submount, disposing a transistor die on the metal submount, disposing a first integrated passive device (IPD) component including a first substrate on the metal submount, and disposing a second integrated passive device (IPD) component including a second substrate on the metal submount, where the first substrate is a different material than the second substrate.

[0182] The above embodiments may further include any one or a combination of two or more of the following embodiments. 19. A method of implementing a transistor device as described in any embodiment herein, wherein a first integrated passive device (IPD) component comprises a printed circuit board (PCB) substrate; and a second integrated passive device (IPD) component comprises a silicon carbide (SiC) substrate. 20. A method of implementing a transistor device as described in any embodiment herein, wherein the first integrated passive device (IPD) component comprises a printed circuit board (PCB) integrated passive device (IPD) and the second integrated passive device (IPD) component comprises a silicon carbide (SiC) integrated passive device (IPD). 21. A method of implementing a transistor device as described in any embodiment herein, comprising forming a cutout portion in a second integrated passive device (IPD) component configured to receive the second integrated passive device (IPD) component. 22. A method of implementing a transistor device as described in any embodiment herein, comprising mounting a surface mount device to an upper surface of a first integrated passive device (IPD) component. 23. A method of implementing a transistor device as described in any embodiment herein, comprising forming at least one via in a first substrate configured to provide an electrical connection between the surface mounted device and a metal submount. 24. A method of implementing a transistor device as described in any embodiment herein, comprising disposing a first integrated passive device (IPD) component between a second integrated passive device (IPD) component and a metal submount. 25. A method of implementing a transistor device as described in any embodiment herein, comprising disposing a second integrated passive device (IPD) component between the first integrated passive device (IPD) component and a metal submount. 26. A method of implementing a transistor device as described in any embodiment herein, further comprising providing a third IPD component having a third substrate, the first substrate being the same material as the third substrate. 27. A method of implementing a transistor device as described in any embodiment herein, comprising mounting a surface mounted device to an upper surface of a third IPD component. 28. A method of implementing a transistor device as described in any embodiment herein, comprising forming at least one via in a third substrate configured to provide an electrical connection between the surface mounted device and a metal submount. 29. A method of implementing a transistor device as described in any embodiment herein, wherein the third IPD component comprises a printed circuit board (PCB) integrated passive device (IPD). 30. A method of implementing a transistor device as described in any embodiment herein, wherein the third IPD component includes a printed circuit board (PCB) substrate. 31. A method of implementing a transistor device as described in any embodiment herein, wherein the transistor die includes one or more LDMOS transistor dies. 32. A method of implementing a transistor device as described in any embodiment herein, wherein the transistor die includes one or more GaN-based HEMTs. 33. A method of implementing a transistor device according to any embodiment herein, wherein the transistor device comprises multiple transistor dies. 34. A method of implementing a transistor device as described in any embodiment herein, wherein the plurality of transistor dies are in a Doherty configuration.

[0183] While the present disclosure has exemplary embodiments, those skilled in the art will recognize that the present disclosure can be practiced with modification within the spirit and scope of the appended claims. The examples given above are merely illustrative and are not intended to be an exhaustive listing of all possible designs, embodiments, applications or modifications of the present disclosure.

[0184] 100 packages 102 Support 402 Ceramic Body 404 Metal Contact

Claims

1. 1. A transistor device comprising: A metal submount; a transistor die disposed on the metal submount; a first integrated passive device (IPD) component including a first substrate disposed on the metal submount; a second integrated passive device (IPD) component including a second substrate disposed on the metal submount; wherein the first substrate is a different material than the second substrate.

2. 10. The transistor device of claim 1, wherein the first integrated passive device (IPD) component comprises a printed circuit board (PCB) and the second integrated passive device (IPD) component comprises a silicon carbide (SiC) substrate.

3. 10. The transistor device of claim 1 , wherein the first integrated passive device (IPD) component comprises a printed circuit board (PCB) integrated passive device (IPD) and the second integrated passive device (IPD) component comprises a silicon carbide (SiC) integrated passive device (IPD).

4. The transistor device of claim 1 , wherein the second integrated passive device (IPD) component comprises a cutout portion configured to receive the second integrated passive device (IPD) component.

5. The transistor device of claim 1 , wherein the first integrated passive device (IPD) component comprises a surface mount device mounted on a top surface of the first integrated passive device (IPD) component.

6. The transistor device of claim 5 , wherein the first substrate comprises at least one via configured to provide an electrical connection between the surface mount device and the metal submount.

7. The transistor device of claim 1 , wherein the first integrated passive device (IPD) component is disposed between the second integrated passive device (IPD) component and the metal submount.

8. The transistor device of claim 1 , wherein the second integrated passive device (IPD) component is disposed between the first integrated passive device (IPD) component and the metal submount.

9. 10. The transistor device of claim 1, further comprising a third integrated passive device (IPD) component including a third substrate, the first substrate being the same material as the third substrate.

10. The transistor device of claim 9 , wherein the third IPD component comprises a surface mount device mounted to a top surface of the third IPD component.

11. The transistor device of claim 10 , wherein the third substrate comprises at least one via configured to provide an electrical connection between the surface mount device and the metal submount.

12. The transistor device of claim 9 , wherein the third IPD component comprises a printed circuit board (PCB) integrated passive device (IPD).

13. The transistor device of claim 9 , wherein the third IPD component comprises a printed circuit board (PCB).

14. The transistor device of claim 1 , wherein the transistor die comprises one or more LDMOS transistor dies.

15. The transistor device of claim 1 , wherein the transistor die comprises one or more GaN-based HEMTs.

16. The transistor device of claim 1 , wherein the transistor device comprises a plurality of transistor dies.

17. 20. The transistor device of claim 16, wherein the plurality of transistor dies are in a Doherty configuration.

18. 1. A method of implementing a transistor device, comprising: Providing a metal submount; disposing a transistor die on the metal submount; disposing a first integrated passive device (IPD) component including a first substrate on the metal submount; disposing a second integrated passive device (IPD) component including a second substrate on the metal submount; wherein the first substrate is a different material than the second substrate.

19. 20. The method of implementing a transistor device as recited in claim 18, wherein the first integrated passive device (IPD) component comprises a printed circuit board (PCB) and the second integrated passive device (IPD) component comprises a silicon carbide (SiC) substrate.

20. 20. The method of implementing a transistor device as recited in claim 18, wherein the first integrated passive device (IPD) component comprises a printed circuit board (PCB) integrated passive device (IPD) and the second integrated passive device (IPD) component comprises a silicon carbide (SiC) integrated passive device (IPD).

21. 20. The method of implementing a transistor device as recited in claim 18, further comprising forming a cutout portion in the second integrated passive device (IPD) component configured to receive the second integrated passive device (IPD) component.

22. 20. The method of implementing a transistor device as recited in claim 18, further comprising mounting a surface mount device on a top surface of the first integrated passive device (IPD) component.

23. 23. The method of implementing a transistor device as recited in claim 22, further comprising forming at least one via in the first substrate configured to provide an electrical connection between the surface mount device and the metal submount.

24. 20. The method of implementing a transistor device as recited in claim 18, further comprising disposing the first integrated passive device (IPD) component between the second integrated passive device (IPD) component and the metal submount.

25. 20. The method of implementing a transistor device as recited in claim 18, further comprising disposing the second integrated passive device (IPD) component between the first integrated passive device (IPD) component and the metal submount.

26. 20. The method of implementing a transistor device as recited in claim 18, further comprising providing a third integrated passive device (IPD) component with a third substrate, the first substrate being the same material as the third substrate.

27. 27. The method of implementing a transistor device as recited in claim 26, further comprising mounting a surface mount device to a top surface of the third IPD component.

28. 30. The method of implementing a transistor device as recited in claim 27, further comprising forming at least one via in the third substrate configured to provide an electrical connection between the surface mount device and the metal submount.

29. 27. The method of implementing a transistor device of claim 26, wherein the third IPD component comprises a printed circuit board (PCB) integrated passive device (IPD).

30. 27. The method of implementing a transistor device as recited in claim 26, wherein the third IPD component comprises a printed circuit board (PCB).

31. 20. The method of implementing a transistor device as recited in claim 18, wherein the transistor die comprises one or more LDMOS transistor dies.

32. 20. The method of implementing a transistor device as recited in claim 18, wherein the transistor die comprises one or more GaN-based HEMTs.

33. 20. The method of implementing a transistor device as recited in claim 18, wherein the transistor device comprises a plurality of transistor dies.

34. 34. The method of implementing a transistor device as recited in claim 33, wherein the plurality of transistor dies are in a Doherty configuration.

Images