Voltage Reference Circuit

Abstract

The invention relates to a voltage reference circuit comprising a trailing transistor (M2) with its source and gate connected to the terminals of a dipole (R1), a linked quadrupole (10) with a first terminal (Q1) connected to the gate of the leading transistor (M1), a second terminal (Q2) connected to the source of the leading transistor, a third terminal (Q3) connected to the source of the trailing transistor and a fourth terminal (Q4) connected to the drain of the trailing transistor, a reference voltage being supplied to the source of the leading transistor, and a base transistor (M3) with its source connected to ground, its gate connected to its drain, said drain connected to a terminal of a second dipole (15) and its other terminal connected to the first dipole.

Description

[Technical field]

[0001] The present invention relates to the field of voltage reference circuits used in integrated circuits.

[0002] In particular, the invention relates to a voltage reference circuit having a structure that makes it possible to limit the energy consumption of the circuit while providing a constant voltage reference even when the power supply, temperature or parameters of the components vary. [Background technology]

[0003] Conventionally, a voltage reference circuit is a circuit that provides a constant reference voltage that is stable over time. Moreover, it is desirable to obtain a reference voltage that is insensitive to variations in several parameters.

[0004] By way of example, these parameters are for example supply voltage, temperature, manufacturing variations or even component aging.

[0005] In particular, transistors are often found in voltage reference circuits. However, the parameters of a given transistor can vary greatly depending on the manufacturing process they undergo. Moreover, two transistors that have undergone the same manufacturing process can differ greatly according to the positioning they had on the semiconductor plate that contributed to their manufacture.

[0006] One of these parameters is the voltage threshold, from which a channel is formed between the drain and source of a given transistor. This minimum value is the value to apply between the gate and source to conduct a current between the drain and source of said given transistor. This parameter can vary by up to 50% between transistors, which can lead to a loss of stability of the voltage reference of the circuit.

[0007] A voltage reference circuit generally contains two types of transistors: depletion mode transistors and enhancement mode transistors.

[0008] As shown in Prior Art Figure 1, the depletion-mode transistor 2005 is generally represented by a solid line connecting the drain, source and base. The enhancement-mode transistor 2025 is generally represented by a dotted line connecting the drain, source and base.

[0009] As an example, as shown in FIG. 1 taken from document US 9,647,476 B2, a voltage reference circuit 2000 generally includes a depletion mode transistor 2005, the drain of which is connected to a voltage source V+ and the source of which is connected to eight enhancement mode transistors 2025 in series. Each enhancement mode transistor 2025 has its gate connected to its drain, and the last enhancement mode transistor in the series has its source connected to ground. The gate of the depletion mode transistor 2005 is also connected to ground. A reference voltage Vref is measured at a point located between the capacitor 2015 and the source of the enhancement mode transistor 2055, the gate of which is connected between the sixth and seventh depletion mode transistors in the series.

[0010] In this configuration, the voltage reference circuit 2000 makes it possible to obtain a low current consumption, typically less than 1 μA. However, such a circuit does not make it possible to reach high reference voltage values. In addition, this type of implementation is susceptible to variations in the parameters of the transistors. Therefore, the reference voltage has instabilities. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] US9,647,476B2 Summary of the Invention [Problem to be solved by the invention]

[0012] The technical problem which the invention proposes to solve is that of obtaining a voltage reference circuit that is stable, in particular with respect to the variations in the method for manufacturing transistors while limiting the consumption of the circuit. [Means for solving the problem]

[0013] In order to solve this problem, the applicant a so-called "leading" depletion mode transistor, the drain of which is connected to a voltage source; a so-called “trailing” depletion mode transistor, the source of which is connected to a terminal of the first dipole and the gate of which is connected to a second terminal of the first dipole; a coupled quadrupole having a first terminal connected to the gate of the leading transistor, a second terminal connected to the source of the leading transistor, a third terminal connected to the source of the trailing transistor, and a fourth terminal connected to the drain of the trailing transistor, a reference voltage being provided to the source of the leading transistor; - developed a voltage reference circuit comprising a so-called "base" enhancement mode transistor having a source connected to ground, a gate connected to its drain, said drain connected to a second terminal of a second dipole, and a first terminal connected to the second terminal of the first dipole.

[0014] The voltage reference circuit therefore contains exactly twice as many depletion mode transistors as enhancement mode transistors, which makes it possible to compensate for the variations in the thresholds defined above. Indeed, for N-channel transistors, the depletion mode transistors have a negative threshold, while the enhancement mode transistors have a positive threshold. Moreover, the absolute value of the threshold of the enhancement mode transistors is practically equal to twice the threshold of the depletion mode transistors. The enhancement mode transistors therefore make it possible to compensate a pair of depletion mode transistors. The thresholds are compensated or even eliminated, which makes it possible to limit the negative effects on the value of the reference voltage.

[0015] Moreover, such a circuit has very few components compared to the prior art and is therefore easier to integrate in an integrated circuit having reduced dimensions. In addition, due to the limited number of components, the interference appearing on the voltage reference signal, which is related to the interaction of the components with each other, is reduced.

[0016] According to a first embodiment, the linking quadrupole consists of two short circuits connecting the first and third terminals and the second and fourth terminals respectively.

[0017] Advantageously, the second dipole is therefore a short circuit.

[0018] This embodiment is the simplest. The circuit contains only four components: two depletion mode transistors, one enhancement mode transistor, and one dipole. Therefore, such a circuit is easy to implement and integrate in an integrated circuit, especially with reduced dimensions.

[0019] According to a second embodiment, the coupled quadrupole includes two depletion mode transistors, an upper transistor and a lower transistor, the source of the upper transistor is connected to the drain of the lower transistor and to a first terminal of the coupled quadrupole, the drain of the upper transistor is connected to a second terminal of the coupled quadrupole, the gate of the lower transistor is connected to a third terminal of the coupled quadrupole, and the gate of the upper transistor and the sources of the lower transistor are connected to a fourth terminal of the coupled quadrupole.

[0020] Thus, advantageously, the second dipole comprises an enhancement-mode transistor, the source of which is connected to the second terminal of the second dipole and the gate of which is connected to the drain of which, said drain is connected to the first terminal of the second dipole.

[0021] In this embodiment, the circuit therefore includes two enhancement-mode transistors, the thresholds of which are compensated using two pairs of depletion-mode transistors.

[0022] According to a third embodiment, the coupled quadrupole consists of n elementary quadrupoles, n>1, each of which includes two depletion mode transistors, an upper transistor and a lower transistor, the source of the upper transistor being connected to the drain of the lower transistor and to the first terminal of the elementary quadrupole, the drain of the upper transistor being connected to the second terminal of the elementary quadrupole, the gate of the lower transistor being connected to the third terminal of the elementary quadrupole, and the gate of the upper transistor and the source of the lower transistor being connected to the fourth terminal of the elementary quadrupole. These elementary quadrupoles are connected in series with two successive elementary quadrupoles connected in such a way that the first terminal of the elementary quadrupole is connected to the third terminal of the elementary quadrupole and the second terminal of the elementary quadrupole is connected to the fourth terminal of the elementary quadrupole. The first and second terminals of the elementary quadrupole form the first and second terminals of the coupled quadrupole, and the third and fourth terminals of the elementary quadrupole form the third and fourth terminals of the coupled quadrupole.

[0023] Thus, advantageously, the second dipole comprises n enhancement-mode transistors, each of said transistors having its gate connected to its drain, said transistors being connected in series, two successive transistors being connected by the source of one and the drain of the other, the drain of the first transistor forming a first terminal of the second dipole and the source of the last transistor forming a second terminal of the second dipole.

[0024] The number of enhancement mode transistors and the number of depletion mode transistors are selected according to the voltage reference value that is sought to be obtained: the greater the number of enhancement mode transistors (and the number of depletion mode transistors), the more the voltage value at the input of the circuit and the value of the reference voltage can be increased.

[0025] According to an embodiment, the first dipole may be, for example, an enhancement mode transistor, whose gate is connected to its drain. The transistor is therefore configured like a diode. Preferably, the first dipole is a resistor, which allows to best compensate for fluctuations in the circuit. The dimensions of the transistor or the value of the resistor do not in principle have a significant effect on the value of the voltage reference. However, the dimensions of these components can be adapted to limit the energy consumption of the voltage reference circuit.

[0026] In fact, the depletion mode and enhancement mode transistors can be GaN transistors or MOS transistors without altering the present invention.

[0027] The manner of achieving the invention, as well as the advantages obtained from the invention, will become apparent from the following description of embodiments with the aid of the accompanying drawings. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 is an electrical schematic diagram of a prior art voltage reference circuit. [Diagram 2] 1 is an electrical circuit diagram of a voltage reference circuit according to a first embodiment of the present invention; [Diagram 3] 3 is an electrical schematic diagram of a voltage reference circuit according to an alternative embodiment of the first embodiment of FIG. 2. [Figure 4] FIG. 5 is an electrical circuit diagram of a voltage reference circuit according to a second embodiment of the present invention. [Diagram 5] FIG. 11 is an electrical circuit diagram of a voltage reference circuit according to a fourth embodiment of the present invention. [Figure 6] FIG. 5 is an electrical circuit diagram of a voltage reference circuit according to a third embodiment of the present invention. [Figure 7] 4 is a graph comparing the progression of reference voltage with temperature for a circuit of the present invention and a prior art circuit. [Figure 8]1 is a graph comparing the progression of reference voltage with supply voltage for theoretically equivalent transistors, but whose intrinsic parameters differ due to manufacturing tolerances, for a circuit of the present invention and a circuit of the prior art. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] As shown in Figures 2 to 6, the voltage reference circuit of the present invention includes leading transistors M1, M11, M21, M31, the drains of which are connected to a voltage source Vcc. The voltage source Vcc preferably provides a DC voltage between 0V and 12V. However, this DC voltage may have variations around a target voltage. Typically, the voltage may vary from 0.1% to 0.5% with respect to its target value.

[0030] The voltage reference circuit of the present invention also includes trailing transistors M2, M14, M26 and M36.

[0031] Two transistors, a leading transistor M1, M11, M21, M31 and a trailing transistor M2, M14, M26, M36, are connected to each other by coupling quadrupoles 10, 20, 30, 40.

[0032] 2 and 3, the coupled quadrupole 10 corresponds to two short circuits: a first short circuit connects the terminals Q1 and Q3 of the coupled quadrupole 10, and a second short circuit connects the terminals Q2 and Q4 of the coupled quadrupole 10.

[0033] Thus, leading transistors M1, M11, M21, M31 are connected by their sources to the drains of trailing transistors M2, M14, M26, M36 via the short circuit connecting terminals Q2 and Q4, and in addition, the sources of trailing transistors M2, M14, M26, M36 are connected to the gates of leading transistors M1, M11, M21, M31 via the short circuit connecting terminals Q1 and Q3.

[0034] In the embodiment of FIG. 4, the coupled quadrupole 20 includes two depletion mode transistors M12, M13 in series, an upper transistor M12 and a lower transistor M13. The source of the upper transistor M12 is connected to the drain of the lower transistor M13 and to a first terminal Q1 of the coupled quadrupole 20. The first terminal Q1 is also connected to the gate of the leading transistor M11. The drain of the upper transistor M12 is connected to a second terminal Q2 of the coupled quadrupole 20. The second terminal Q2 is also connected to the source of the leading transistor M11. The gate of the lower transistor M13 is connected to a third terminal Q3 of the coupled quadrupole 20. The third terminal Q3 is also connected to the source of the trailing transistor M14. Finally, the gate of the upper transistor M12 and the source of the lower transistor M13 are connected to a fourth terminal Q4 of the coupled quadrupole 20, which is also connected to the drain of the trailing transistor M14.

[0035] In the embodiment of Fig. 5, the coupled quadrupole 30 consists of two elementary quadrupoles QEi, QEi+1 connected in series, i.e., the third terminal QEi-3 of the first elementary quadrupole QEi is connected to the first terminal QEi+1-1 of the second elementary quadrupole QEi+1, and the fourth terminal QEi-4 of the first elementary quadrupole QEi is connected to the second terminal QEi+1-2 of the second elementary quadrupole QEi+1. Each elementary quadrupole QEi, QEi+1 includes two depletion mode transistors M22-M26, which are upper transistors M22, M24 and lower transistors M23, M25. The source of each upper transistor M22, M24 is connected to the drain of each lower transistor M23, M25 and to the first terminal QEi-1, QEi+1-1 of each elementary quadrupole QEi, QEi+1. The drains of the upper transistors M22, M24 are connected to the second terminals QEi-2, QEi+1-2 of the respective elementary quadrupoles QEi, QEi+1, the gates of the lower transistors M23, M25 are connected to the third terminals QEi-3, QEi+1-3 of the respective elementary quadrupoles QEi, QEi+1, and the gates of the upper transistors M22, M24 and the sources of the lower transistors M23, M25 are connected to the fourth terminals QEi-4, QEi+1-4 of the respective elementary quadrupoles QEi, QEi+1. The terminals QEi-1, QEi-2 form the terminals Q1 and Q2 of the coupled quadrupole 30, respectively, and the terminals QEi+1-3 and QEi+1-4 form the terminals Q3 and Q4 of the coupled quadrupole 30, respectively.

[0036] In the embodiment of Fig. 6, the coupled quadrupole 40 consists of n elementary quadrupoles QE1 to QEn, where n>1. Each elementary quadrupole comprises two depletion mode transistors, upper transistors M32, M34 and lower transistors M33, M35, connected in the same manner as for the elementary quadrupoles QEi, QEi+1 described with reference to Fig. 5. The elementary quadrupoles QE1 to QEn are connected in series, and two successive elementary quadrupoles QEi, QEi+1 are connected such that the first terminal QEi+1-1 of the elementary quadrupole QEi+1 is connected to the third terminal QEi-3 of the elementary quadrupole QEi, and the second terminal QEi+1-2 of the elementary quadrupole QEi+1 is connected to the fourth terminal QEi-4 of the elementary quadrupole QEi. The first and second terminals QE1-1, QE1-2 of the elementary quadrupole QE1 form the first and second terminals Q1, Q2 of the coupled quadrupole 40, and the third and fourth terminals QEn-3, QEn-4 of the elementary quadrupole QEn form the third and fourth terminals Q3, Q4 of the coupled quadrupole 40.

[0037] The leading and trailing transistors are depletion mode transistors. They can belong to the category of GaN transistors or MOS transistors.

[0038] The trailing transistors M2, M14, M26, M36 are connected by their sources to a terminal of the first dipole. The gates of the trailing transistors M2, M14, M26, M36 are connected to a second terminal of the first dipole. For example, the first dipole can be resistors R1, R11, R21, R31 as shown in Figures 2 and 4-6, or it can also be a diode. For example, the first dipole is the enhancement mode transistor M4 mounted in a diode, i.e., its gate is connected to its drain, as shown in Figure 3.

[0039] The second terminal of the first dipole is connected in series with the second dipole 15 , 25 , 35 , 45 .

[0040] In the embodiment of figures 2 and 3, the second dipole 15 corresponds to a short circuit.

[0041] 4, the second dipole 25 includes an enhancement-mode transistor M15 having a source connected to the second terminal of the second dipole 25 and a gate connected to its drain, which is also connected to the first terminal of the second dipole 25.

[0042] In the embodiment of Fig. 5, the second dipole 35 includes two enhancement mode transistors M27, M28. Each transistor M27, M28 has its gate connected to its drain. The transistors M27, M28 are connected in series, i.e. the source of the first transistor M27 is connected to the drain of the second transistor M28. Thus, the drain of the first transistor M27 forms a first terminal D1 of the second dipole 45, and the source of the second transistor M28 forms a second terminal D2 of the second dipole 45.

[0043] In the embodiment of Fig. 6, the second dipole 45 includes n enhancement mode transistors M37, M38. Each transistor M37, M38 has its gate connected to its drain. The transistors M37, M38 are connected in series, i.e. two successive transistors M37, M38 are connected by the source of one and the drain of the other. Thus, the drain of the first transistor M37 forms the first terminal D1 of the second dipole 45, and the source of the last transistor M38 forms the second terminal D2 of the second dipole 45.

[0044] The second terminals of the second dipoles 15, 25, 35, 45 are connected to a nonlinear component. In practice, the nonlinear component is a base transistor M3, M29, M39. The base transistor M3, M29, M39 is advantageously an enhancement mode transistor, the gate of which is connected to its drain. The base transistor M3, M29, M39 is connected by its source to ground.

[0045] A voltage reference value Vref is measured at the sources of the leading transistors M1, M11, M21, M31.

[0046] The upper part of the circuit formed by the depletion mode transistors M1, M2, M11-M14, M21-M26, M31-M36 taken individually is configured as a current source when a current less than the saturation current passes through it. The voltage Vgs measured between the gate and source of the depletion mode transistors M1, M2, M11-M14, M21-M26, M31-M36 actually extends to a voltage threshold by which a channel forms between the drain and source of a given transistor. The voltage Vds measured between the drain and source of the first depletion mode transistor M1, M2, M11-M14, M21-M26, M31-M36 is therefore constant and the current supplied by the current source is substantially constant.

[0047] If the purpose of the circuit is to obtain a voltage reference rather than a current reference, then this circuit is not sufficient in itself, as the voltage thresholds defined above may be subject to variations of up to 50% depending on the transistor manufacturing method.

[0048] The lower part of the circuit formed by the enhancement-mode transistors M3, M15, M16, M27, M28, M29, M37, M38, and M39 effectively provides a voltage that can vary depending on the current passing therethrough.

[0049] Thus, by limiting the current provided by the current source at the top of the circuit, it is possible to limit the voltage fluctuations at the bottom of the circuit. It is therefore the association of the top and bottom of the circuit that makes it possible to obtain a substantially constant voltage reference.

[0050] Furthermore, the depletion mode transistors have a negative threshold, while the enhancement mode transistors have a positive threshold. In addition, the absolute value of the threshold of the enhancement mode transistors is equal to twice the threshold of the depletion mode transistors. Thus, the enhancement mode transistors make it possible to compensate a pair of depletion mode transistors when the lower and upper parts of the circuit are combined. Due to this, it is advantageous that the transistors are N-channel gallium nitride (GaN) based transistors, and that the number of depletion mode transistors in the upper part of the circuit is equal to twice the number of enhancement mode transistors in the lower part of the circuit.

[0051] For example, in the circuit shown in Fig. 2, the role of the leading transistor M1 is to provide a voltage difference between the terminal connected to Vcc and the terminal connected to Vref, so that a reference voltage Vref, referenced to ground, is stable at the output of the circuit. This leading transistor M1 is particularly sized to provide a sufficient current level for the charge connected to the terminal Vref, while the trailing transistor M2 and the base transistor M3 are sized to fix the polarization current and the gate voltage required to control the leading transistor M1. In fact, to limit the influence of the current consumed by this charge on the value of the reference voltage Vref, the leading transistor M1 is selected to have an active surface larger than those of the trailing transistor M2 and the base transistor M3, in order to reduce the total electrical consumption of the circuit.

[0052] The polarization current regulated through the trailing transistor M2 is reduced and through the first dipole, and therefore improved by the value of resistor R1 in the case of Fig. 2. Indeed, with the polarization current smaller than the saturation current of transistor M2, the voltage at the terminals of resistor R1 (corresponding to the gate-source voltage of transistor M2) is close to the threshold voltage of depletion mode transistor M2. The current is therefore determined by the threshold voltage of depletion mode transistor M2 and the resistance value of R1.

[0053] The value of the threshold voltage of the depletion mode transistor M2 and the value of the resistor R1 change under the influence of process induced variations and / or temperature variations during operation, resulting in variations in the polarization current. However, the use of an integrated resistor R1 for the first dipole is more advantageous over the use of enhancement mode transistors, which are more sensitive to process variations. The resistor R1 thus makes it possible to reduce the influence of process induced variations on the reference voltage Vref at the output of the circuit with a ratio close to 10.

[0054] Base transistor M3 is configured to offset the output voltage to compensate for changes due to process and / or temperature variations in depletion mode transistors M1 and M2. In practice, this transistor M3 needs to be large enough to compensate for these variations without making it more sensitive to process variations.

[0055] Therefore, the resulting voltage reference circuit is less sensitive to supply voltage, temperature fluctuations, and variations in transistor manufacturing methods. Another advantageous feature of the circuit of the present invention is that it consumes little energy, typically about 3 μA to 10 μA.

[0056] Finally, the voltage reference circuit can manage up to 10V of charge with only a 6% voltage variation.

[0057] Measurements have been carried out by the applicant to compare the performance obtained between the circuit of the present invention and a prior art circuit.

[0058] As shown in FIG. 7, for the circuit 1000 of the present invention, it was observed that the reference voltage Vref fluctuates between 2.86V and 3.02V when the temperature varies between +20° C. and +150° C., a variation of 0.16V.

[0059] For the prior art circuit 2000, it was observed that when the temperature varied between +20° C. and +150° C., the reference voltage Vref varied between 2.47 V and 2.7 V, a variation of 0.23 V which is 50% greater than the circuit of the present invention.

[0060] The invention therefore effectively makes it possible to limit the variations of the reference voltage Vref with temperature compared to prior art circuits.

[0061] Similarly, Figure 8 compares the variation of the reference voltage Vref for theoretically identical transistors, but whose intrinsic parameters differ due to manufacturing tolerances. For the prior art circuits 2001, 2002, 2003, when the supply voltage is greater than 4V, the reference voltage Vref measured for the transistors 2001 and 2003 varies from 1.4V to 3.6V, which is about a 44% variation between the transistors. For the circuits 1001, 1002, 1003 of the present invention, the reference voltage Vref varies between 2.8V and 3V, which is about a 7% variation between the transistors, i.e. 1 / 6 for the prior art circuits.

[0062] Thus, the present invention makes it possible to effectively limit the variations in the reference voltage Vref due to the tolerances of the transistor manufacturing process. [Explanation of symbols]

[0063] 10 connected quadrupole 15 Second Dipole 20 connected quadrupole 25 Second Dipole 30 connected quadrupole 35 Second Dipole 40 connected quadrupole 45 Second Dipole 1000 Circuit of the present invention 1001 Circuit of the present invention 1002 Circuit of the present invention 1003 Circuit of the present invention 2000 Voltage Reference Circuit 2001 Prior Art Circuit 2002 Prior Art Circuit 2003 Prior Art Circuit 2005 Depletion mode transistor 2015 Capacitor 2020 Series Depletion Mode Transistors 2025 Enhancement mode transistor 2055 Enhancement mode transistor M1 Leading transistor M11 Leading transistor M21 Leading transistor M31 Leading transistor Vcc voltage source Vref Voltage Reference Vds voltage Vgs voltage M2 Trailing transistor M14 Trailing transistor M26 Trailing transistor M36 Trailing transistor Q1 terminal Q2 terminal Q3 Terminal Q4 terminal D1 First terminal of the second dipole D2 First terminal of the second dipole R1 resistor R11 resistor R21 resistor R31 resistor M22 Upper Transistor M23 Lower Transistor M24 Upper Transistor M25 Lower Transistor M34 Upper Transistor M35 Lower Transistor M4 Enhancement mode transistor M27 Enhancement mode transistor M28 Enhancement mode transistor M3 Enhancement mode transistor, base transistor M15 Enhancement mode transistor M16 Enhancement mode transistor M37 Enhancement mode transistor M38 Enhancement mode transistor M29 Enhancement mode transistor, base transistor M39 Enhancement mode transistor, base transistor

Claims

1. leading depletion mode transistors (M1, M11, M21, M31) with their drains connected to a voltage source (Vcc); a trailing depletion mode transistor (M2, M14, M26, M36) having a source connected to a terminal of a first dipole (R1, R11, R21, M4) and a gate connected to a second terminal of the first dipole (R1, R11, R21, M4); a coupled quadrupole (10, 20, 30, 40) having a first terminal (Q1) connected to the gates of the leading transistors (M1, M11, M21, M31), a second terminal (Q2) connected to the sources of the leading transistors (M1, M11, M21, M31), a third terminal (Q3) connected to the sources of the trailing transistors (M2, M14, M26, M36) and a fourth terminal (Q4) connected to the drains of the trailing transistors (M2, M14, M26, M36), and a reference voltage is provided to the sources of the leading transistors (M1, M11, M21, M31); a base enhancement mode transistor (M3, M15, M16, M27, M28, M29, M37, M38, M39) having a source connected to ground and a gate connected to its drain, the drain connected to a second terminal (D2) of a second dipole (15, 25, 35) and a first terminal (D1) connected to the second terminal of the first dipole (R1, R11, R21, M4).

2. 2. The voltage reference circuit of claim 1, wherein the coupling quadrupole (10) consists of two shorts connecting the first terminal and the third terminal (Q1, Q3) and the second terminal and the fourth terminal (Q2, Q4), respectively.

3. 2. The voltage reference circuit of claim 1, wherein the coupled quadrupole (20) includes two depletion mode transistors (M12, M13), an upper transistor (M12) and a lower transistor (M13), a source of the upper transistor (M12) is connected to a drain of the lower transistor (M13) and the first terminal (Q1) of the coupled quadrupole (20), a drain of the upper transistor (M12) is connected to the second terminal (Q2) of the coupled quadrupole (20), a gate of the lower transistor (M13) is connected to the third terminal (Q3) of the coupled quadrupole (20), and a gate of the upper transistor (M12) and a source of the lower transistor (M13) are connected to the fourth terminal (Q4) of the coupled quadrupole (20).

4. The coupled quadrupole (40) is composed of n elementary quadrupoles (QE1, QEi, QEi+1, QEn), where n>1, and each elementary quadrupole (QEi) includes two depletion mode transistors, an upper transistor (M22, M32, M24, M34) and a lower transistor (M23, M33, M25, M35). The sources of the upper transistors (M22, M32, M24, M34) are connected to the drains and and a first terminal (QEi-1) of the elementary quadrupole (QEi), the drains of the upper transistors (M22, M32, M24, M34) are connected to a second terminal (QEi-2) of the elementary quadrupole (QEi), the gates of the lower transistors (M23, M33, M25, M35) are connected to a third terminal (QEi-3) of the elementary quadrupole (QEi), and the gates of the upper transistors (M22, M32, M24, M34) and the gates of the lower transistors (M23, M33, M25, M35) are connected to a third terminal (QEi-4) of the elementary quadrupole (QEi). The sources of the transistors (M23, M33, M25, M35) are connected to the fourth terminal (QEi-4) of the elementary quadrupole (QEi), and the elementary quadrupoles are connected in series, and two successive elementary quadrupoles (QEi, QEi+1) are connected in series such that the first terminal (QEi+1-1) of the elementary quadrupole (QEi+1) is connected to the third terminal (QEi-3) of the elementary quadrupole (QEi), and the second terminal (QEi+1-2) of the elementary quadrupole (QEi+1) is connected to the fourth terminal (QEi-4) of the elementary quadrupole (QEi), and the second terminal (QEi+1-2) of the elementary quadrupole (QEi+1) is connected to the fourth terminal (QEi-4) of the elementary quadrupole (QEi), and the elementary quadrupoles are connected in series such that the first terminal (QEi+1-1) of the elementary quadrupole (QEi-1) is connected to the third terminal (QEi-3) of the elementary quadrupole (QEi), and the second terminal (QEi+1-2) of the elementary quadrupole (QEi+1) is connected to the fourth terminal (QEi-4 ...

2. The voltage reference circuit of claim 1, wherein the first and second terminals (QE1-1, QE1-2) of the elementary quadrupole (QE1) form the first and second terminals (Q1, Q2) of the coupled quadrupole (40), and the third and fourth terminals (QEn-3, QEn-4) of the elementary quadrupole (QEn) form the third and fourth terminals (Q3, Q4) of the coupled quadrupole.

5. 2. The voltage reference circuit of claim 1, wherein the depletion mode transistors (M1, M2, M11-M14, M21-M26, M31-M36) and enhancement mode (M3, M15, M27, M28, M37, M38) transistors are GaN transistors or MOS transistors.

6. 2. The voltage reference circuit of claim 1, wherein the first dipole is a resistor (R1, R11, R21).

7. 2. The voltage reference circuit of claim 1, wherein the first dipole is an enhancement mode transistor (M4), the gate of which is connected to its drain.

8. 3. A voltage reference circuit as claimed in claim 2, characterised in that the second dipole (15) is a short circuit.

9. 4. The voltage reference circuit of claim 3, wherein the second dipole (25) comprises an enhancement-mode transistor (M15) having its source connected to the second terminal of the second dipole (25), its gate connected to its drain, and its drain connected to the first terminal (D1) of the second dipole (25).

10. 5. The voltage reference circuit of claim 4, characterized in that the second dipole (45) comprises n enhancement mode transistors (M37, M38), each of which has its gate connected to its drain, the transistors (M37, M38) being connected in series, two successive transistors (M37, M38) being connected by one source and the other drain, the drain of a first transistor (M37) forming a first terminal (D1) of the second dipole (45) and the source of the last transistor (M38) forming a second terminal (D2) of the second dipole (45).

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