Substrate for evaluation and evaluation method

The evaluation board with sharp corners and narrowed portions in the solder resist layer efficiently detects cracks in fewer thermal cycles, addressing the inefficiency of existing methods by concentrating stress for rapid crack detection.

JP2025001130APending Publication Date: 2025-01-08TOPPAN HOLDINGS INC
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Patent Information

Application Number
JP2023100552
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2023-06-20
Publication Date
2025-01-08

AI Technical Summary

Technical Problem

Existing crack resistance evaluation methods for solder resist layers in multilayer wiring boards require a large number of temperature cycles to detect cracks, often exceeding 10,000 cycles, and may not accurately predict failure in actual products.

Method used

An evaluation board with a solder resist layer featuring at least two sharp corners and a narrowed portion between them, concentrating stress and strain in this area to facilitate crack detection with fewer thermal cycles.

Benefits of technology

The proposed method allows for the rapid detection of cracks in the solder resist layer with a significantly reduced number of thermal cycles, typically around 1000 cycles, providing a more efficient and predictive evaluation of crack resistance.

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Abstract

To confirm the generation of a crack in a smaller temperature cycle number in an evaluation of a hot-cold impact test of a solder resist.SOLUTION: For confirming generation of a crack in a smaller temperature cycle number, a substrate for evaluation in which a solder resist layer is formed, comprises: at least two openings (12 and 13) each having a sharp corner in a solder resist layer; and an evaluation pattern composed of the two openings and a narrow part 14 of the solder resist layer sandwiched between sharp corners of the two openings. Thus, strain due to a thermal stress or the like easily occurs in the narrow part and the crack easily occurs, so that a performance of the solder resist can be evaluated in an early stage.SELECTED DRAWING: Figure 1A
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Description

[Technical field]

[0001] The present invention relates to an evaluation substrate and an evaluation method. [Background technology]

[0002] In wiring boards such as multilayer wiring boards, a solder resist layer is formed on the outermost surface to insulate and protect the surface of the multilayer wiring board. In the area where the wiring board is to be electrically connected to the outside, an opening is provided in the solder resist layer. In the area for electrical connection, a pad portion having an area larger than that of a normal wiring is formed on the wiring board, and the solder resist layer has an opening formed to expose this pad portion. The solder resist layer in which the openings are formed expands and contracts due to changes in the surrounding temperature, but the area near the openings expands and contracts repeatedly, and when the expansion and contraction exceeds its limit, it is destroyed, causing cracks in that area and causing the solder resist layer to no longer function.

[0003] For this reason, for example, Patent Document 1 discloses the following technique for evaluating crack resistance. (Crack resistance evaluation) A substrate on which a 2 mm copper line pattern was formed was prepared, and pretreatment was performed using CZ8100 manufactured by MEC. On this substrate, a photosensitive laminated resin structure was formed using each dry film of each of the above-mentioned Examples and Comparative Examples, in the same manner as described above in (Resolution Evaluation (Evaluation of Minimum Opening Diameter)). Next, a pattern was exposed at the above-mentioned optimum exposure amount using an exposure device equipped with a high-pressure mercury lamp so that a 3 mm square opening pattern was formed on the copper line of the substrate through a negative pattern having a 3 mm square negative pattern as a negative mask for crack resistance evaluation, and after baking at 100 ° C. for 30 minutes, the PET film in contact with the protective layer (B) was peeled off, and development was performed under the same conditions as described above in (Resolution Evaluation (Evaluation of Minimum Opening Diameter)), a solder resist pattern was obtained, and then cured by ultraviolet irradiation and heating to prepare each crack resistance evaluation substrate. This evaluation board was placed in a thermal cycle machine that performs temperature cycles between -65°C for 30 minutes and 175°C for 30 minutes, and a thermal cycle test (TCT) was performed. The appearance after 600 cycles and 1000 cycles was observed with a SEM, and the occurrence of cracks was evaluated according to the following criteria.

[0004] Furthermore, Patent Document 2 discloses the following technique for evaluating crack resistance. "Crack Resistance Evaluation The evaluation laminate substrate on which the solder resist was formed in the same manner as in the above "Preparation of Evaluation Substrate" was exposed to the atmosphere at -65°C for 15 minutes, then heated at a heating rate of 180°C / min, and then exposed to the atmosphere at 150°C for 15 minutes, and then cooled at a heating rate of 180°C / min. This thermal cycle was repeated 1000 times. After exposure to such an environment, the degree of cracking and peeling of the permanent resist film of the evaluation laminate substrate was observed with a metal microscope at 100x magnification and evaluated according to the following criteria. That is, when 10 points of a 2 mm square opening were checked and no cracking or peeling of the permanent resist film was observed, it was rated as "3", when cracking and peeling were observed in 2 or less points out of 10 points, it was rated as "2", and when cracking and peeling were observed in 3 or more points out of 10 points, it was rated as "1". [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2022-62573 A [Patent Document 2] JP 2015-11265 A Summary of the Invention [Problem to be solved by the invention]

[0006] In the crack resistance evaluation techniques disclosed in the prior art documents, an evaluation board with square or round openings formed in the solder resist is used to keep the evaluation conditions constant. However, when a temperature cycle test such as a thermal shock test is performed using such an evaluation board, a long evaluation time is required before cracks appear in the solder resist, and in some cases, no cracks appear even after applying temperature cycles of more than 10,000 times. However, in actual products, there is a risk of failure due to cracks in the solder resist, and therefore a technology for effective accelerated testing of the crack resistance of solder resist is desired. Therefore, an object of the present invention is to provide an evaluation board and an evaluation method that are capable of checking for the occurrence of cracks with a small number of temperature cycles in evaluating a solder resist layer through a thermal shock test. [Means for solving the problem]

[0007] In order to solve the above problems, one representative evaluation board of the present invention is an evaluation board having a solder resist layer formed thereon, in which at least two openings with sharp corners are formed, and which is provided with an evaluation pattern in which a narrowed portion of the solder resist layer is located in the area between the sharp corners of each of the two openings. Effect of the Invention

[0008] According to the present invention, it is possible to provide an evaluation board and an evaluation method that are capable of checking for the occurrence of cracks with a small number of temperature cycles in the evaluation of a solder resist layer in a thermal shock test. Problems, configurations and effects other than those described above will become apparent from the following description of the preferred embodiment of the invention. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 1A is a schematic diagram showing a planar shape of an evaluation pattern. [Figure 1B]FIG. 1B is a schematic diagram showing a cross-sectional shape along line AA' in FIG. 1A. [Diagram 2] FIG. 11 is a plan view illustrating a modified example of the opening shape. [Diagram 3] FIG. 11 is a plan view illustrating a modified example of the opening shape. [Figure 4] FIG. 11 is a plan view illustrating a modified example of the opening shape. [Diagram 5] FIG. 11 is a plan view illustrating a modified example of the opening shape. [Figure 6] FIG. 11 is a plan view illustrating a modified example of the opening shape. [Figure 7] FIG. 13 is a plan view showing an example in which four sets of unit evaluation patterns are arranged. [Figure 8] FIG. 13 is a plan view showing an example in which a plurality of evaluation patterns having different pattern angles and lengths of constriction portions are arranged. [Figure 9] FIG. [Figure 10] 1 is a table and a graph showing the test results of the average number of durability cycles. [Figure 11] 1 is a table and a graph showing the test results of the average number of durability cycles. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the embodiment. In addition, in the description of the drawings, the same parts are denoted by the same reference numerals. When there are multiple components having the same or similar functions, they may be described by using the same reference numerals with different subscripts, or when there is no need to distinguish between these multiple components, the subscripts may be omitted. In addition, although terms such as "first," "second," and "third" may be used in the present disclosure to describe various elements or components, it will be understood that these elements or components should not be limited by these terms. These terms are used only to distinguish one element or component from another element or component. Thus, a first element or component discussed below can also be referred to as a second element or component without departing from the teachings of the inventive concept. In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0011] In addition, in this disclosure, "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Furthermore, "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing when a plate-shaped member or a layer contained in the plate-shaped member is illustrated. The "upper surface" and "lower surface" may also be referred to as the "first surface" and "second surface."

[0012] The term "side surface" refers to a surface of a plate-like member or a layer included in a plate-like member, or a portion of the thickness of a layer. Furthermore, a part of a surface and a side surface may be collectively referred to as an "end portion." In addition, "upward" refers to the vertically upward direction when a plate-like member or layer is placed horizontally. Furthermore, "upward" and its opposite, "downward," are sometimes referred to as the "Z-axis positive direction" and the "Z-axis negative direction," and the horizontal direction is sometimes referred to as the "X-axis direction" and the "Y-axis direction."

[0013] Additionally, the terms "planar shape" and "plan view" refer to the shape of a surface or layer when viewed from above. Furthermore, the terms "cross-sectional shape" and "cross-sectional view" refer to the shape of a plate-like member or layer when cut in a specific direction and viewed from the horizontal direction. Furthermore, the term "central portion" refers to the central portion other than the peripheral portion of the surface or layer, and the term "toward the center" refers to the direction from the peripheral portion of the surface or layer toward the center of the planar shape of the surface or layer.

[0014] (First embodiment) First, the configuration of an evaluation board according to a first embodiment of the present disclosure will be described with reference to FIGS. 1A and 1B. Fig. 1A is a schematic diagram showing the planar shape of an evaluation substrate 10 in the first embodiment, and Fig. 1B is a schematic diagram showing the cross-sectional shape along line AA' in Fig. 1A.

[0015] (Plane shape) 1A, at least two openings 12 and 13 having sharp corners 15 and 16 are formed in a solder resist layer 11. A narrowed portion 14 of the solder resist is formed in the region between the sharp corners 15 and 16. That is, in the example of FIG. 1A, the evaluation pattern is configured by the two openings 12 and 13 and the narrowed portion 14. 1A, the sharp corners 15 and 16 of the two openings 12 and 13 are provided opposite to each other, and the angle of the sharp corners is represented by θ. Furthermore, the length of the narrowed portion 14 of the solder resist in the region between the sharp corners 15 and 16 is represented by L. In FIG. 1A, the nickel-gold plating layer below the solder resist layer 11 is exposed from two openings 12 and 13.

[0016] (Cross-sectional shape) 1B, the cross-sectional shape of the evaluation board 10 will be described. First, a copper layer 18 that will become the wiring and pad portion of the multilayer wiring board is formed above a polyimide or substrate 17. A patterned solder resist layer 11 is formed above the copper layer 18, and a nickel-gold plating layer 19 is formed in the openings of the solder resist layer.

[0017] (Action and effect) When a thermal shock test is performed in which temperature cycles are applied to the evaluation board shown in the first embodiment, stress strain caused by the temperature cycles is concentrated in the narrowed portion 14, and cracks caused by the temperature cycles are more likely to occur in the narrowed portion 14 than in other regions around the opening. Therefore, by checking for the occurrence of cracks in the narrowed portion 14 after the thermal shock test, it is possible to check the crack resistance of the solder resist layer with a small number of temperature cycles.

[0018] Second embodiment Next, modified shapes of the openings 12 and 13 described in the first embodiment will be described with reference to Fig. 2. Fig. 2 is a schematic diagram showing modified shapes of the openings (a), (b), and (c) depicted by dashed lines, dashed dotted lines, and solid lines, respectively, superimposed on each other. The openings have almost the same shape for the area (FS) including the sharp corners, but the shapes and areas of the large area portions (BS) are different. The size of the sharp corners of these opening shapes can be changed as appropriate, as described below. FIGS. 3 to 5 show examples in which evaluation patterns (unit evaluation patterns) having these openings are arranged with sharp corners facing each other. These modified examples have different shapes and areas of the large area portion (BS), which allows the concentration of stress strain that occurs in the narrow area between the sharp corners to be changed, and the shape of the opening can be selected depending on the evaluation purpose.

[0019] In Figure 3, the large area portion (BS) is shaped like a ginkgo leaf. Therefore, compared to a triangular shape, the angles of the two corners of the large area portion (BS) can be made larger, so cracks are less likely to occur in this area and stress strain is more likely to concentrate in the narrowed area.

[0020] In Fig. 4, the large area portion (BS) is made to have a substantially circular shape. Therefore, since the large area portion (BS) has no corners, cracks are less likely to occur in the large area portion (BS) and stress strain is more likely to concentrate in the narrowed portion.

[0021] In FIG. 5, the large area portion (BS) is substantially rectangular in shape. Therefore, even if the angle of the sharp corner of the narrowed portion is increased, the large area portion (BS) does not protrude significantly toward the adjacent pattern side. In other words, it is possible to make the size of the large area portion (BS) of an evaluation pattern with a large sharp angle the same as that of an evaluation pattern with a small sharp angle, and evaluation patterns having different sharp corners can be arranged substantially uniformly regardless of the angle of the sharp corner. Therefore, by reducing the effect of stress strain due to the difference in area of ​​the large area portion (BS), it is easy to adjust the degree of change in the angle of the corner of the narrowed portion and the change in stress strain to the narrowed portion.

[0022] (Third embodiment) Next, a third embodiment will be described with reference to Fig. 6. The third embodiment differs from the first and second embodiments in that the sharp corners of the multiple openings are not completely symmetrical in the left-right direction of the drawing, but are shifted up and down. The sharp corners of the multiple openings do not necessarily need to be arranged perfectly symmetrically in the left-right direction; as long as the sharp corners are arranged close to each other and a narrowed portion is formed between the sharp corners, they can function as an evaluation pattern. In addition, the opening shape shown in FIG. 6 is the triangular opening shape described in the first embodiment, but the third embodiment is not limited to this and can be applied using the various opening shapes described in the second embodiment.

[0023] (Fourth embodiment) Next, a fourth embodiment in which a plurality of unit evaluation patterns are arranged will be described with reference to FIG. Figure 7 is a plan view showing an example of arranging four sets of unit evaluation patterns. The phenomenon of cracks occurring in the constricted portion between openings does not necessarily occur simultaneously in all constricted portions formed under the same conditions, and there may be variations in occurrence due to variations in the opening formation and non-uniformity of the test environment. For this reason, it is desirable to provide multiple sets of unit evaluation patterns and observe the occurrence of cracks. Furthermore, when the distance between adjacent unit evaluation patterns becomes short, cracks may occur in unintended places, such as between the adjacent unit evaluation patterns. Since such cracks make the task of counting the cracks cumbersome, it is desirable to set the arrangement interval between adjacent unit evaluation patterns so that cracks do not occur. 7, the layout is such that four unit evaluation patterns, each having a narrowed portion of 20 to 40 μm in an opening with a lateral dimension of 100 μm, are arranged at intervals of 120 μm. However, the layout of the unit evaluation patterns is not limited to this, and various modifications are possible.

[0024] Fifth embodiment Next, referring to Figure 8, we will explain a fifth embodiment in which multiple unit evaluation patterns are arranged, in which multiple evaluation patterns are formed with different sizes of the sharp corners of the openings (hereinafter sometimes referred to as "pattern angles") and / or different lengths of the narrowed portions. When conducting thermal shock tests on a solder resist layer, it is possible to effectively evaluate the solder resist under test by simultaneously testing evaluation patterns with various pattern angles and constriction length rather than evaluating using only one type of evaluation pattern. The evaluation board illustrated in FIG. 8 is an example of an evaluation pattern group 20 formed by accumulating approximately 100 unit evaluation patterns having a specific pattern angle and constriction length in an area of ​​approximately 5 mm square, and arranging such evaluation pattern groups in groups where the length of the constriction portion is changed vertically to 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, and 120 μm and the pattern angles are 60° and 90° horizontally, resulting in 24 types of evaluation pattern groups.

[0025] FIG. 9 shows an example of an evaluation pattern group 20 in which about 100 unit evaluation patterns each having a specific pattern angle and narrowed length are accumulated in an area of ​​about 5 mm square. By simultaneously testing a number of evaluation patterns with various configurations, it is possible to make a detailed statistical judgment on the tendency for cracks to occur in the solder resist based on factors such as the pattern angle, the length of the narrowed portion, and the number of thermal shocks. Furthermore, by providing an area in the evaluation board for recording the number of thermal shocks, it becomes possible to clarify the management of the evaluation board for the test results.

[0026] (Example) Next, an example will be described in which a thermal shock test was carried out on a specific solder resist opening pattern using the evaluation board shown in FIG.

[0027] (About the evaluation board) The board size shown in Fig. 8 is 37.5 mm × 37.5 mm, and the board thickness is 962 μm. The evaluation board in Fig. 8 includes samples for reliability tests other than crack tests, so it is made by stacking multiple insulating layers, and so the board thickness is 962 μm, but if only tests for crack occurrence due to thermal shock of the solder resist are to be performed, the board used for evaluation does not need to have a stacked structure. In the evaluation board shown in Figure 8, the left half has a pattern angle of 60°, and the right half has a pattern angle of 90°, and the length of the narrowed part of the evaluation pattern (hereinafter sometimes referred to as "pitch") is 10 to 120 μm, with areas of different pitches separated in 10 μm increments. When the pitch is 50 μm or more, cracks occur slowly, so tests with more than a certain number of thermal shocks were not performed.

[0028] (Creating an evaluation board) (1) Evaluation board The appearance of the evaluation board used for the evaluation is as shown in Figure 8.

[0029] (2) Creating an evaluation board The procedure for fabricating the substrate shown in FIG. 8 will be described below. First, a resin substrate is prepared by plating both sides with copper. The substrate may be a multi-layer wiring substrate, and a copper pattern may be formed on the outermost wiring layer, and an opening pattern for the solder resist may be formed.

[0030] (3) Solder resist material used Liquid type Four types of commercially available liquid solder resist (Resist A, Resist B, Resist C, Resist D) Dry film type Four types of commercially available dry film type solder resists (Resist E, Resist F, Resist G, Resist H) A total of eight types were used.

[0031] (4) Test pattern The unit evaluation pattern was arranged according to the dimensions shown in Fig. 7. In this example, a pair of isosceles triangles with a height of 100 μm was arranged as one opening pattern with the apex angles facing each other. Furthermore, multiple pairs of such triangles were arranged. When arranging unit evaluation patterns, adjacent patterns are arranged with a minimum distance of 120 μm between them, as shown in FIG. The unit evaluation patterns used are the evaluation pattern group explained in Fig. 9. In other words, 9 x 13 test patterns each consisting of a pair of triangles are arranged in a grid in an area of ​​5 mm square. Furthermore, as a variation of the test pattern, the pattern angle and the length of the narrowed portion were changed (conditions) and arranged as shown in FIG.

[0032] (5) Formation of solder resist layer Solder resist material used In this example, a total of eight products, including liquid type and dry film type, were used. For both types of solder resist material, the substrate on which the solder resist layer was formed was a double-sided copper solid board having copper foil on both sides. The solder resist was applied with a commonly used thickness of 19 to 23 μm. If the thickness of this solder resist layer is made thinner, the number of tests in which an abnormality occurs will be reduced, so in order to increase the evaluation efficiency, the thickness may be set to 10 to 15 μm.

[0033] The formation of a solder resist layer on the surface of a substrate will be described below. A method for forming a solder resist layer using a liquid type solder resist The liquid type solder resist was applied using a roll coater so that the coating thickness was uniform over the entire surface of the substrate. In this example, a roll coater was used as the coating device, but this is not limiting, and various other means such as a screen printing device, a curtain coater, and a spray coater can also be used. Then, the substrate coated with the liquid type solder resist was carried into a heating device, and a pre-baking process was performed in which the substrate was held at a predetermined temperature for a predetermined period of time.

[0034] -Method of forming a solder resist layer using a dry film First, a dry film of solder resist having a predetermined thickness is prepared. Generally, the dry film has a protective cover tape attached to the front and back of the solder resist layer, so when laminating the dry film to a substrate using a laminator, the cover tape is peeled off as appropriate and lamination processing is performed. In this disclosure, the dry film may also refer to the solder resist layer alone after the cover tape has been peeled off.

[0035] Pattern exposure The substrate on which the liquid solder resist was formed was exposed to light in the following manner. First, a photomask (not shown) on which the test pattern shown in FIG. 8 was drawn was prepared. This photomask had a quartz glass substrate and a chrome layer formed as a light-shielding layer. Next, this photomask was mounted in an exposure device, and an exposure process was performed so that a test pattern could be obtained on the pre-baked solder resist layer. In this example, quartz glass was used as the substrate for the photomask, but soda lime and resin film (PET, polyethylene terephthalate) could also be used.

[0036] For the dry film type solder resist, exposure was performed using a direct imaging exposure tool without using a photomask. When using this direct imaging exposure tool, the test pattern shown in Figure 8 is converted in advance into data that can be drawn by the direct imaging exposure tool.

[0037] Regarding the exposure method used in this embodiment, a direct imaging type exposure may be performed on a liquid solder resist, and a photomask type exposure may be performed on a dry film type solder resist.

[0038] ·developing The substrate that had been subjected to the above-mentioned exposure was subjected to a development process in a developing device in order to remove the solder resist from the portions that would become the openings. The solder resist that was not removed by the development process and remained may be subjected to an appropriate ultraviolet ray irradiation or heat treatment as a hardening process.

[0039] Copper surface treatment Next, in order to protect the copper layer exposed at the bottom of the opening of the obtained solder resist layer, a surface treatment was performed. Specifically, the copper surface was first cleaned by soft etching, and then a nickel layer and a palladium layer were formed on the copper surface in that order, and then a gold layer was formed on the top layer by plating. This completed the test substrate.

[0040] (6) Evaluation test A Thermal Shock Test (TST) Pre-treatment (for both liquid and dry film types) In order to prevent variations in the prepared samples due to natural moisture absorption, the test substrates were placed in an oven set at 125° C. and baked for one hour. B. Implementation Equipment and Conditions Test equipment: TSB-51 (ESPEC Corp.)

[0041] C. TST Conditions Three conditions were set for the TST test: high temperature condition: 150℃ / 5 minutes, room temperature exposure: 1 minute, and low temperature condition: -65℃ / 5 minutes. As for the operating conditions, the sample is inserted and the TST test starts at room temperature, then it moves to the cycle operation mode. One cycle of operation is performed in the order of high temperature condition, room temperature exposure, low temperature condition, and room temperature exposure. This cycle is then repeated a specified number of times. In a thermal shock test, the test is sometimes performed for a predetermined number of cycles (for example, 5000 times) without stopping midway, and the quality of the sample is judged only after the test is completed. However, in this embodiment, in order to know at what stage a crack (failure) occurred, the test was stopped every 500 cycles, the substrate was removed and evaluated, and the substrate was then put into the thermal shock test for 500 cycles again, and this was repeated until the total number of cycles reached 7000.

[0042] D Crack count After each 500 cycles of the thermal shock test, the number of patterns with cracks in the narrowed portion of the test substrate was visually counted using a metal microscope (Olympus). In this example, the portion where the cracks occurred was also included in the test, so the number of cracks that had occurred up to that point was also counted.

[0043] E. Tabulation of evaluation results How to handle counted numbers In the evaluation of this embodiment, cracks were checked every 500 cycles, so for example, if the number of test patterns with cracks confirmed after a total of 1500 cycles is n1, and the number of test patterns with cracks confirmed after a total of 2000 cycles is n2, then new cracks occurred in n2-n1 test patterns between 1500 and 2000 cycles. In other words, no cracks occurred in n2-n1 test patterns up to 1500 cycles, and the number of test patterns with a durability cycle of 1500 is n2-n1.

[0044] As described above, the number of test patterns in which new cracks occurred was counted for each number of cycles. In addition, the number of test patterns in which no cracks were observed after 7000 cycles was counted and calculated as the number of test samples with 7000 durability cycles. The number of durability cycles was weighted by the number of test patterns to calculate a weighted average, and the average number of durability cycles for each solder resist was calculated.

[0045] (7) Test results For two boards using eight types of resist, The results of the average number of endurance cycles for patterns with apex angles of 60° and 90° and constriction lengths of 20 μm, 30 μm, 40 μm, and 55 μm are shown in FIGS.

[0046] As shown in Figures 10 and 11, by using an evaluation board equipped with the evaluation pattern of the present disclosure, it became possible to confirm the occurrence of cracks after about 1,000 cycles of thermal shock testing, making it clear that the crack resistance can be evaluated quickly.

[0047] The present disclosure also includes the following aspects. (Aspect 1) In the evaluation substrate on which the solder resist layer is formed, The solder resist layer has at least two openings formed therein, the openings having sharp corners; and an evaluation pattern in which a narrowed portion of the solder resist layer is disposed in an area between the sharp corners of the two openings. Evaluation board.

[0048] (Aspect 2) In the evaluation substrate according to aspect 1, The size of the sharp corner of the opening is 90 degrees or less. Evaluation board.

[0049] (Aspect 3) In the evaluation substrate according to aspect 1 or 2, The length of the constriction is 40 μm or less. Evaluation board.

[0050] (Aspect 4) In the evaluation substrate according to any one of aspects 1 to 3, The opening exposes the nickel-gold plating layer. Evaluation board.

[0051] (Aspect 5) In the evaluation substrate according to any one of aspects 1 to 4, The nickel-gold plating layer is formed on top of the copper layer. Evaluation board.

[0052] (Aspect 6) In the evaluation substrate according to any one of aspects 1 to 5, A plurality of evaluation patterns are formed, each having the same size of the sharp corner of the opening and / or the same length of the narrowed portion. Evaluation board.

[0053] (Aspect 7) In the evaluation substrate according to any one of aspects 1 to 6, A plurality of evaluation patterns having the same size of the sharp corner of the opening and / or the same length of the narrowed portion are formed in a specific region. Evaluation board.

[0054] (Aspect 8) In the evaluation substrate according to any one of aspects 1 to 7, A plurality of evaluation patterns are formed, each having a different size of the sharp corner of the opening and / or a different length of the narrowed portion. Evaluation board.

[0055] (Aspect 9) In the evaluation substrate according to any one of aspects 1 to 8, The quality of the solder resist is evaluated by detecting the presence or absence of cracks occurring in the narrowed portion. Method for evaluating solder resist.

[0056] Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the gist of the present invention. For example, the size of the evaluation board can be changed to various sizes. Furthermore, the number of evaluation pattern groups arranged on the evaluation substrate, the arrangement method, the size of each evaluation pattern, the arrangement method, etc. can be appropriately changed as necessary. Furthermore, patterns, designs, letters, symbols, etc. other than the evaluation patterns described in this disclosure may be arranged on the evaluation substrate. [Explanation of symbols]

[0057] 10: Evaluation board 11: Solder resist layer 12:Aperture 13:Aperture 14: Stenosis 15: Sharp corner 16: Sharp corner 17: Substrate 18: Copper layer 19: Nickel-gold plating layer 20: Evaluation patterns

Claims

1. In the evaluation substrate on which the solder resist layer is formed, The solder resist layer has at least two openings formed therein, the openings having sharp corners; and an evaluation pattern in which a narrowed portion of the solder resist layer is disposed in a region between the sharp corners of the two openings. Evaluation board.

2. 2. The evaluation board according to claim 1, The size of the sharp corner of the opening is 90 degrees or less. Evaluation board.

3. 3. The evaluation board according to claim 1, The length of the narrowed portion is 40 μm or less. Evaluation board.

4. 3. The evaluation board according to claim 1, The opening exposes the nickel-gold plating layer. Evaluation board.

5. 5. The evaluation board according to claim 4, The nickel-gold plating layer is formed on the copper layer. Evaluation board.

6. 3. The evaluation board according to claim 1, A plurality of evaluation patterns are formed, each having the same size of the sharp corner of the opening and / or the same length of the narrowed portion. Evaluation board.

7. 7. The evaluation board according to claim 6, A plurality of evaluation patterns having the same size of the sharp corner of the opening and / or the same length of the narrowed portion are formed in a specific region. Evaluation board.

8. 3. The evaluation board according to claim 1, A plurality of evaluation patterns are formed, each having a different size of the sharp corner of the opening and / or a different length of the narrowed portion. Evaluation board.

9. 3. The evaluation board according to claim 1, The quality of the solder resist is evaluated by detecting the presence or absence of cracks occurring in the narrowed portion. Method for evaluating solder resist.

Citation Information

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