Semiconductor storage device and method for manufacturing the same

Abstract

To provide a semiconductor storage device with high reliability.SOLUTION: A semiconductor storage device 100 includes a first charge storage film 40 containing a metal oxide or metal oxynitride. The device comprises: a first laminate S1 in which a first insulating layer 10, a first conductive layer 20 and a second insulating layer 12 are sequentially stacked in the first direction Z; a semiconductor film 3 which is provided apart from the first laminate and extends in the first direction; a tunnel insulating film 4 which is provided between the first laminate and the semiconductor film and extends in the first direction; a first block insulating film 30 which is provided between the first conductive layer and the tunnel insulating film; a first portion 42 which is provided between the tunnel insulating film and the first block insulating film; a second portion 44 which is provided between the tunnel insulating film and the first insulating layer and is connected to the first portion; and a third portion 46 which is provided between the tunnel insulating film and the second insulating layer and is connected to the first portion.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof. [Background technology]

[0002] Large-capacity nonvolatile memories have been developed, which are capable of low-voltage and low-current operation, high-speed switching, and miniaturization and high integration of memory cells.

[0003] A large number of metal wirings called bit lines and word lines are arranged in the memory cell array of a large-capacity nonvolatile memory. A voltage is applied to the bit line and word line connected to a cell, and data is written to one memory cell corresponding to the bit line and word line. A semiconductor memory device has been proposed in which memory cells are arranged three-dimensionally and equipped with a laminated film in which conductive layers and insulating layers that serve as such word lines are alternately stacked. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2023 / 0037066 [Patent Document 2] US Patent Application Publication No. 2021 / 0143171 [Patent Document 3] US Patent Application Publication No. 2023 / 0034157 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the embodiment is to provide a semiconductor memory device having high charge retention characteristics. [Means for solving the problem]

[0006] The semiconductor memory device of the embodiment includes a first stack in which a first insulating layer, a first conductive layer, and a second insulating layer are stacked in a first direction, a semiconductor film spaced apart from the first stack and extending in the first direction, a tunnel insulating film provided between the first stack and the semiconductor film and extending in the first direction, a first block insulating film provided between the first conductive layer and the tunnel insulating film, a first portion provided between the tunnel insulating film and the first block insulating film, a second portion provided between the tunnel insulating film and the first insulating layer and connected to the first portion, and a third portion provided between the tunnel insulating film and the second insulating layer and connected to the first portion, and a first charge storage film containing a metal oxide or a metal oxynitride. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram of a semiconductor memory device according to a first embodiment. [Diagram 2] 2 is an equivalent circuit diagram of a memory cell array in the semiconductor memory device of the first embodiment. [Diagram 3] 1 is a schematic cross-sectional view of a main part of a semiconductor memory device according to a first embodiment. [Figure 4] 2A to 2C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device of the first embodiment. [Diagram 5] 2A to 2C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device of the first embodiment. [Figure 6] 2A to 2C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device of the first embodiment. [Figure 7] 2A to 2C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device of the first embodiment. [Figure 8] 2A to 2C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device of the first embodiment. [Figure 9] 2A to 2C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device of the first embodiment. [Figure 10] FIG. 11 is a schematic cross-sectional view of a main part of a semiconductor memory device according to a second embodiment. [Figure 11] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment.

[0008] Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same or similar parts are denoted by the same or similar reference numerals.

[0009] In this specification, in order to indicate the positional relationship of parts, etc., the upward direction of the drawing is described as "upper" and the downward direction of the drawing is described as "lower." In this specification, the concepts of "upper" and "lower" are not necessarily terms that indicate a relationship with the direction of gravity.

[0010] In the present specification, the qualitative and quantitative analysis of the chemical composition of the components constituting the semiconductor memory device can be performed using, for example, secondary ion mass spectroscopy (SIMS), energy dispersive X-ray spectroscopy (EDX), or electron energy loss spectroscopy (EELS).

[0011] Furthermore, for example, a transmission electron microscope (TEM) can be used to measure the thickness of members constituting the semiconductor memory device, the distance between members, and the like.

[0012] In addition, for identifying the constituent substances of the components that make up a semiconductor memory device and comparing the amount of presence, for example, a transmission electron microscope, X-ray diffraction analysis (XRD), electron beam diffraction analysis (EBD), X-ray photoelectron spectroscopy (XPS), or synchrotron radiation X-ray absorption fine structure analysis (XAFS) can be used.

[0013] (First embodiment) The semiconductor memory device of this embodiment includes a first stack in which a first insulating layer, a first conductive layer, and a second insulating layer are stacked in this order in a first direction, a semiconductor film spaced apart from the first stack and extending in the first direction, a tunnel insulating film provided between the first stack and the semiconductor film and extending in the first direction, a first block insulating film provided between the first conductive layer and the tunnel insulating film, a first portion provided between the tunnel insulating film and the first block insulating film, a second portion provided between the tunnel insulating film and the first insulating layer and connected to the first portion, and a third portion provided between the tunnel insulating film and the second insulating layer and connected to the first portion, and a first charge storage film containing a metal oxide or a metal oxynitride.

[0014] The method for manufacturing a semiconductor memory device according to the present embodiment includes forming a second stack in which a first insulating layer, a first sacrificial layer, and a second insulating layer are stacked in this order in a first direction, forming an opening penetrating the second stack and extending in the first direction, exposing a side surface of the first insulating layer, a side surface of the first sacrificial layer, and a side surface of the second insulating layer to the opening, forming a first film containing N (nitrogen) or Si (silicon) on the side surface of the first sacrificial layer, forming a first charge storage film having a first portion, a second portion, and a third portion and containing a metal oxide or a metal oxynitride, and forming a first charge storage film on the second portion. a first portion is adjacent to the first insulating layer and the first film, a third portion is adjacent to the second insulating layer and the first film, the first film is provided between the first sacrificial layer and the first portion, and the first portion is connected to the second portion and the third portion; the first film is oxidized to form a first block insulating film; a tunnel insulating film extending in a first direction is formed so that the first block insulating film is provided between the second stack and the tunnel insulating film; and a semiconductor film extending in the first direction is formed so that the tunnel insulating film is provided between the second stack and the semiconductor film.

[0015] The following describes the overall configuration of the semiconductor memory device 100. The semiconductor memory device 100 according to this embodiment is a NAND type flash memory capable of storing data in a non-volatile manner. Figure 1 is a block diagram of the semiconductor memory device 100 according to this embodiment.

[0016] The semiconductor memory device 100 includes a memory cell array 90, a row decoder 91, a column decoder 98, a sense amplifier 99, an input / output circuit 94, a command register 95, an address register 96, a sequencer (control circuit) 97, and the like.

[0017] The memory cell array 90 includes j blocks BLK0 to BLK(j-1), where j is an integer equal to or greater than 1. Each of the blocks BLK includes a plurality of memory cell transistors. The memory cell transistors include electrically rewritable memory cells. The memory cell array 90 includes a plurality of bit lines, a plurality of word lines, and a source line for controlling the voltage applied to the memory cell transistors. A specific configuration of the blocks BLK will be described later.

[0018] The row decoder 91 receives a row address from the address register 96 and decodes the row address. The row decoder 91 selects a word line or the like based on the decoded row address. The row decoder 91 then transfers a plurality of voltages required for write, read, and erase operations to the memory cell array 90.

[0019] The column decoder 98 receives a column address from the address register 96 and decodes the column address. The column decoder 98 selects a bit line based on the decoded column address.

[0020] The sense amplifier 99 detects and amplifies data read from the memory cell transistor to the bit line during a read operation, and transfers write data to the bit line during a write operation.

[0021] The input / output circuit 94 is connected to an external device (host device) via a plurality of input / output lines (DQ lines). The input / output circuit 94 receives a command CMD and an address ADD from the external device. The command CMD received by the input / output circuit 94 is sent to a command register 95. The address ADD received by the input / output circuit 94 is sent to an address register 96. The input / output circuit 94 also transmits and receives data DAT to and from the external device.

[0022] The sequencer 97 receives a control signal CNT from an external device. The control signal CNT includes a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn. The "n" added to the signal name indicates active low. The sequencer 97 controls the operation of the entire semiconductor memory device 100 based on the command CMD held in the command register 95 and the control signal CNT.

[0023] FIG. 2 is an equivalent circuit diagram of the semiconductor memory device 100 of the present embodiment.

[0024] As shown in FIG. 2, the semiconductor memory device 100 includes a plurality of word lines WL, a common source line CSL, a source select gate line SGS, a plurality of drain select gate lines SGD, a plurality of bit lines BL, and a plurality of memory strings MS.

[0025] The memory string MS includes a source select transistor STS, a plurality of memory cell transistors MT, and a drain select transistor STD, which are connected in series between a common source line CSL and a bit line BL.

[0026] It should be noted that the number of word lines WL, the number of bit lines BL, the number of memory strings MS, and the number of drain select gate lines SGD are not limited to those shown in FIG.

[0027] Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X direction and the Y direction are defined. The Z direction is an example of a first direction. The X direction is an example of a second direction. The Y direction is an example of the second direction.

[0028] FIG. 3 is a schematic cross-sectional view of a main part of the semiconductor memory device 100 of this embodiment.

[0029] A first insulating layer 10, a first conductive layer 20, a second insulating layer 12, a second conductive layer 24, and a third insulating layer 14 are laminated in this order in the Z direction. That is, the insulating layers and the conductive layers are alternately laminated in the Z direction. In this way, a first laminate S1 is provided. The first laminate S1 may further include other insulating layers and conductive layers. In this case, in the first laminate S1, a plurality of insulating layers and a plurality of conductive layers are laminated one by one in the Z direction.

[0030] The first insulating layer 10, the second insulating layer 12, and the third insulating layer 14 include an insulating material. The first insulating layer 10, the second insulating layer 12, and the third insulating layer 14 include, for example, silicon oxide.

[0031] The first conductive layer 20 and the second conductive layer 24 include a conductive material. The first conductive layer 20 and the second conductive layer 24 include, for example, tungsten, titanium nitride, or copper. Note that the first conductive layer 20 and the second conductive layer 24 may include other conductive materials such as metals, metal-semiconductor compounds, or semiconductors.

[0032] The memory pillar H1 penetrates the first stack S1 in the Z direction. A core insulating film 2, a semiconductor film 3, a tunnel insulating film 4, a first insulating film 5, a second insulating film 6, a third insulating film 7, a first block insulating film 30, a second block insulating film 32, a first charge storage film 40, and a second charge storage film 50 are provided in the memory pillar H1.

[0033] The core insulating film 2 extends in the Z direction. The core insulating film 2 includes, for example, silicon oxide.

[0034] The semiconductor film 3 is provided around the core insulating film 2 in the memory pillar H1. The semiconductor film 3 extends in the Z direction. The semiconductor film 3 functions as a channel of the memory pillar H1. The semiconductor film 3 includes a semiconductor material such as polysilicon.

[0035] The tunnel insulating film 4 is provided around the semiconductor film 3. The tunnel insulating film 4 is an insulating film that is insulating but allows a current to flow when a predetermined voltage is applied to it. The tunnel insulating film 4 includes, for example, silicon oxynitride.

[0036] The first block insulating film 30 is provided between the first conductive layer 20 and the tunnel insulating film 4. A part of the first block insulating film 30 is provided between the first insulating layer 10 and the tunnel insulating film 4 and between the second insulating layer 12 and the tunnel insulating film 4. The first block insulating film 30 is a film that suppresses the flow of charges between the first conductive layer 20 and the tunnel insulating film 4. The first block insulating film 30 includes, for example, an oxide or an oxynitride. The first block insulating film 30 includes, for example, a silicon oxide or a silicon oxynitride. The first block insulating film 30 is a film that suppresses the flow of charges between the first charge storage film 40 and the first conductive layer 20.

[0037] The second block insulating film 32 is provided between the second conductive layer 24 and the tunnel insulating film 4. A part of the second block insulating film 32 is provided between the second insulating layer 12 and the tunnel insulating film 4 and between the third insulating layer 14 and the tunnel insulating film 4. The second block insulating film 32 is a film that suppresses the flow of charges between the second conductive layer 24 and the tunnel insulating film 4. The second block insulating film 32 includes, for example, an oxide or an oxynitride. The second block insulating film 32 includes, for example, a silicon oxide or a silicon oxynitride. The second block insulating film 32 is a film that suppresses the flow of charges between the second charge storage film 50 and the second conductive layer 24.

[0038] The first charge storage film 40 has a first portion 42, a second portion 44, and a third portion 46. The first portion 42 is provided between the tunnel insulating film 4 and the first block insulating film 30. The second portion 44 is provided between the tunnel insulating film 4 and the first insulating layer 10, and is connected to the first portion 42. The third portion 46 is provided between the tunnel insulating film 4 and the second insulating layer 12, and is connected to the first portion 42. The first charge storage film 40 is a film having a material capable of storing charges.

[0039] The second charge storage film 50 has a sixth portion 52, a seventh portion 54, and an eighth portion 56. The sixth portion 52 is provided between the tunnel insulating film 4 and the second block insulating film 32. The seventh portion 54 is provided between the tunnel insulating film 4 and the second insulating layer 12, and is connected to the sixth portion 52. The eighth portion 56 is provided between the tunnel insulating film 4 and the third insulating layer 14, and is connected to the sixth portion 52. The second charge storage film 50 is a film having a material capable of storing charges.

[0040] The first charge storage film 40 and the second charge storage film 50 contain a metal oxide or a metal oxynitride because the metal oxide or the metal oxynitride has high charge retention properties.

[0041] The first charge storage film 40 and the second charge storage film 50 preferably contain at least one first element selected from the group consisting of Al (aluminum), Hf (hafnium), Zr (zirconium), Ti (titanium), V (vanadium), Ta (tantalum) and Nb (niobium), and may be an oxide or oxynitride of the first element. For example, when the first element is Hf, the first charge storage film 40 and the second charge storage film 50 may be HfO or HfON, and when the first element is Zr, the first charge storage film 40 and the second charge storage film 50 may be ZrO or ZrON.

[0042] Alternatively, the first charge storage film 40 and the second charge storage film 50 preferably contain at least one second element selected from the group consisting of N (nitrogen), Si (silicon), Al (aluminum) and lanthanoid elements, and Hf or Zr. The first charge storage film 40 and the second charge storage film 50 may be, for example, an oxide or oxynitride such as HfAlO, HfAlON, ZrAlO, or ZrAlON. Furthermore, the first charge storage film 40 and the second charge storage film 50 preferably contain 20 atomic % or less of the second element.

[0043] The first insulating film 5 is provided between the tunnel insulating film 4 and the first insulating layer 10. The second insulating film 6 is provided between the tunnel insulating film 4 and the second insulating layer 12. The third insulating film 7 is provided between the tunnel insulating film 4 and the third insulating layer 14. The second insulating film 6 is provided between the third portion 46 and the seventh portion 54 in the Z direction. The first insulating film 5, the second insulating film 6, and the third insulating film 7 contain an insulating material. The first insulating film 5, the second insulating film 6, and the third insulating film 7 contain, for example, silicon oxide. The first insulating film 5, the second insulating film 6, and the third insulating film 7 are films embedded between the respective charge storage films in the Z direction.

[0044] The third block insulating film 16 is provided between the first conductive layer 20 and the first insulating layer 10, between the first conductive layer 20 and the first block insulating film 30, and between the first conductive layer 20 and the second insulating layer 12. The third block insulating film 16 includes a metal insulating material such as aluminum oxide.

[0045] The fourth block insulating film 18 is provided between the second conductive layer 24 and the second insulating layer 12, between the second conductive layer 24 and the second block insulating film 32, and between the second conductive layer 24 and the third insulating layer 14. The fourth block insulating film 18 includes a metal insulating material such as aluminum oxide.

[0046] Furthermore, a barrier metal (not shown) is provided between the first conductive layer 20 and the third block insulating film 16 and between the second conductive layer 24 and the fourth block insulating film 18. The barrier metal contains, for example, titanium nitride.

[0047] Note that Fig. 3 illustrates one memory string MS among the memory strings MS illustrated in Fig. 2. The semiconductor memory device 100 includes a plurality of memory pillars H1.

[0048] In FIG. 3, the portion enclosed by the dashed line corresponds to one memory cell MC.

[0049] In addition, for example, a substrate (not shown) is provided under the first stack S1. The substrate (not shown) is, for example, a semiconductor wafer or an SOI wafer. A common source line CSL, a source select gate line SGS, and a plurality of source select transistors STS (not shown) are provided between the first stack S1 and the substrate (not shown).

[0050] Further, on the first stacked body S1, for example, a plurality of drain select gate lines SGD, a plurality of bit lines BL, and a plurality of drain select transistors STD (not shown) are provided.

[0051] 4 to 9 are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device of this embodiment.

[0052] First, for example, a common source line CSL, a source selection gate line SGS, and a plurality of source selection transistors STS (not shown) are formed on a substrate (not shown).

[0053] Next, a second stack S2 in which a first insulating layer 10, a first sacrificial layer 70, a second insulating layer 12, a second sacrificial layer 72, and a third insulating layer 14 are stacked in order in the Z direction is formed on the common source line CSL, the source selection gate line SGS, and the plurality of source selection transistors STS, for example, by a plasma-enhanced chemical vapor deposition (plasma CVD) method. Here, the first insulating layer 10, the second insulating layer 12, and the third insulating layer 14 contain, for example, silicon oxide. Also, the first sacrificial layer 70 and the second sacrificial layer 72 contain, for example, silicon nitride (FIG. 4).

[0054] Next, an opening H2 (through hole) penetrating the second laminate S2 in the Z direction and extending in the Z direction is formed by, for example, RIE (Reactive Ion Etching) method. This causes the side surface 11 of the first insulating layer, the side surface 71 of the first sacrificial layer, the side surface 13 of the second insulating layer, the side surface 73 of the second sacrificial layer, and the side surface 15 of the third insulating layer to be exposed in the opening H2 (FIG. 5).

[0055] Next, an adsorption inhibitor I is adsorbed onto side surface 11 of the first insulating layer, side surface 13 of the second insulating layer, and side surface 15 of the third insulating layer. The adsorption inhibitor I is not particularly limited, but may be, for example, C (carbon), hydrocarbon, or the like.

[0056] Next, a first film 80 containing N (nitrogen) or Si (silicon) is formed on the side surface 71 of the first sacrificial layer by, for example, selective growth (Area Selective Deposition: ASD). Also, a second film 82 containing N (nitrogen) or Si (silicon) is formed on the side surface 73 of the second sacrificial layer by, for example, selective growth. The first film 80 and the second film 82 containing silicon nitride are formed by, for example, selective CVD. Here, a part of the first film 80 may be formed adjacent to the side surface 11 of the first insulating layer and the side surface 13 of the second insulating layer. Also, a part of the second film 82 may be formed adjacent to the side surface 13 of the second insulating layer and the side surface 15 of the third insulating layer. The first film 80 and the second film 82 are formed spaced apart from each other (FIG. 6).

[0057] In the following figures, the adsorption inhibitor I will be omitted from the illustration.

[0058] Next, the first charge storage film 40, which has a first portion 42, a second portion 44, and a third portion 46 and contains a metal oxide or a metal oxynitride, is formed by, for example, selective growth. Here, the first charge storage film 40 is formed such that the second portion 44 is adjacent to the first insulating layer 10 and the first film 80, the third portion 46 is adjacent to the second insulating layer 12 and the first film 80, the first film 80 is provided between the first sacrificial layer 70 and the first portion 42, and the first portion 42 is connected to the second portion 44 and the third portion 46.

[0059] Further, the second charge storage film 50 having a sixth portion 52, a seventh portion 54, and an eighth portion 56 and containing a metal oxide or a metal oxynitride is formed by, for example, selective growth. Here, the second charge storage film 50 is formed such that the seventh portion 54 is adjacent to the second insulating layer 12 and the second film 82, the eighth portion 56 is adjacent to the third insulating layer 14 and the second film 82, the second film 82 is provided between the second sacrificial layer 72 and the sixth portion 52, and the sixth portion 52 is connected to the seventh portion 54 and the eighth portion 56.

[0060] Next, the first film 80 is oxidized to form the first block insulating film 30. Also, the second film 82 is oxidized to form the second block insulating film 32. For example, a gas containing oxygen is supplied into the opening H2, and the first film 80 is oxidized through the first charge storage film 40 using the first charge storage film 40 as a catalyst, thereby forming the first block insulating film 30. Also, a gas containing oxygen is supplied into the opening H2, and the second film 82 is oxidized through the second charge storage film 50 using the second charge storage film 50 as a catalyst, thereby forming the second block insulating film 32 (FIG. 8).

[0061] Next, a film containing, for example, silicon oxide is formed on the side surface 11 of the first insulating layer, the lower surface of the second portion 44, the side surface of the first portion 42, the side surface 13 of the second insulating layer, the side surface of the sixth portion 52, and the upper surface of the eighth portion 56. Next, a part of the film containing silicon oxide is removed by, for example, an RIE method so that the side surface of the first portion 42 and the side surface of the sixth portion 52 are exposed. As a result, a first insulating film 5 is formed on the side surface 11 of the first insulating layer. In addition, a second insulating film 6 is formed on the side surface 13 of the second insulating layer. In addition, a third insulating film 7 is formed on the side surface 15 of the third insulating layer (FIG. 9).

[0062] Next, the tunnel insulating film 4 and a part of the semiconductor film 3 are formed in this order in the opening H2, for example, by the ALD method. Next, the tunnel insulating film 4 and a part of the semiconductor film 3 are removed from the bottom of the opening H2, for example, by etching. Next, the remaining part of the semiconductor film 3 and the core insulating film 2 are formed in this order in the opening H2, for example, by ALD. As a result, the tunnel insulating film 4, the semiconductor film 3, and the core insulating film 2 are formed in this order in the opening H2.

[0063] In other words, in the opening H2, the tunnel insulating film 4 extending in the first direction is formed such that the first block insulating film 30 and the second block insulating film 32 are provided between the second stack S2 and the tunnel insulating film 4. Next, in the opening H2, the semiconductor film 3 extending in the first direction is formed such that the tunnel insulating film 4 is provided between the second stack S2 and the semiconductor film 3. Next, in the opening H2, the core insulating film 2 extending in the first direction is formed such that the semiconductor film 3 is provided between the second stack S2 and the core insulating film 2.

[0064] Next, a slit (not shown) is formed in the second laminate S2. Next, a chemical solution such as phosphoric acid is supplied using the slit to remove the first sacrificial layer 70 and the second sacrificial layer 72. Next, the third block insulating film 16 and the first conductive layer 20 are formed in order in the portion from which the first sacrificial layer 70 has been removed. Also, the fourth block insulating film 18 and the second conductive layer 24 are formed in order in the portion from which the second sacrificial layer 72 has been removed. In this manner, the first sacrificial layer 70 is replaced with the third block insulating film 16 and the first conductive layer 20. Also, the second sacrificial layer 72 is replaced with the fourth block insulating film 18 and the second conductive layer 24. This forms the first laminate S1.

[0065] Next, a plurality of drain select gate lines SGD, a plurality of bit lines BL, and a plurality of drain select transistors STD (not shown) are formed on the second stack S2, thereby obtaining the semiconductor memory device 100 of the present embodiment.

[0066] Next, the effects of the semiconductor memory device of this embodiment will be described.

[0067] The thickness of the insulating layer in the Z direction and the thickness of the conductive layer in the Z direction of the first laminate S1 tend to be thinner due to the high storage density of semiconductor memory devices. In this case, the distance between adjacent memory cells MC in the Z direction becomes narrower. Therefore, interference and charge transfer between adjacent memory cells MC in the Z direction can become a problem.

[0068] In order to solve this problem, it is conceivable to reduce the thickness of the charge storage film in the X direction or Y direction. However, when silicon nitride is used as the charge storage film, there is a problem that the amount of charge storage is rapidly reduced when the film thickness in the X direction or Y direction is thinner than, for example, about 5 nm.

[0069] For this reason, it is conceivable to use a film containing a metal oxide or a metal oxynitride extending in the Z direction as a charge storage film. However, this has the problem that charge transfer occurs between memory cells MC adjacent in the Z direction.

[0070] Therefore, the semiconductor memory device of this embodiment has a first block insulating film provided between the first conductive layer and the tunnel insulating film, a first portion provided between the tunnel insulating film and the first block insulating film, a second portion provided between the tunnel insulating film and the first insulating layer and connected to the first portion, and a third portion provided between the tunnel insulating film and the second insulating layer and connected to the first portion, and is equipped with a first charge storage film containing a metal oxide or a metal oxynitride.

[0071] According to the semiconductor memory device of this embodiment, the charge storage film is divided between the memory cells MC. Therefore, interference and charge transfer between adjacent memory cells MC in the Z direction are suppressed. Furthermore, the semiconductor memory device of this embodiment can ensure high capacitance. Therefore, it is possible to provide a semiconductor memory device with high charge retention characteristics.

[0072] The first charge storage film 40 and the second charge storage film 50 preferably contain at least one first element selected from the group consisting of Al (aluminum), Hf (hafnium), Zr (zirconium), Ti (titanium), V (vanadium), Ta (tantalum) and Nb (niobium), in order to make the first charge storage film 40 and the second charge storage film 50 have higher charge retention characteristics.

[0073] Moreover, the first charge storage film 40 and the second charge storage film 50 preferably contain at least one second element selected from the group consisting of N (nitrogen), Si (silicon), Al (aluminum) and lanthanoid elements, and Hf or Zr. Furthermore, the first charge storage film 40 and the second charge storage film 50 preferably contain 20 atomic % or less of the second element. This is to allow the first charge storage film 40 and the second charge storage film 50 to have higher charge retention characteristics.

[0074] In the method for manufacturing a semiconductor memory device of this embodiment, the first film 80 is oxidized to form the first block insulating film 30. For example, the first charge storage film 40 is used as a catalyst to oxidize the first film 80 via the first charge storage film 40 to form the first block insulating film 30. This is because, while forming the block insulating film, it is possible to form memory cells MC in which the charge storage film is divided in the Z direction.

[0075] It is preferable to adsorb the adsorption inhibitor I to side surface 11 of the first insulating layer, side surface 13 of the second insulating layer, and side surface 15 of the third insulating layer. This is because the formation of a film containing a metal oxide or a metal oxynitride can be suppressed on side surface 11 of the first insulating layer, side surface 13 of the second insulating layer, and side surface 15 of the third insulating layer.

[0076] According to the semiconductor memory device of this embodiment, it is possible to provide a semiconductor memory device having high charge retention characteristics.

[0077] Second embodiment The semiconductor memory device of this embodiment differs from the semiconductor memory device of the first embodiment in that the first conductive layer has a fourth portion provided between the first insulating layer and the second insulating layer, and a fifth portion provided between the second portion and the third portion, connected to the fourth portion, and having a thickness in the first direction greater than the thickness of the fourth portion in the first direction. Here, a description of the contents that overlap with the first embodiment will be omitted.

[0078] Fig. 10 is a schematic cross-sectional view of a main part of the semiconductor memory device 110 of this embodiment. Fig. 10(a) is a schematic cross-sectional view of a main part of the semiconductor memory device 110 of this embodiment. Fig. 10(b) is a schematic cross-sectional view of a main part of the semiconductor memory device 110 of this embodiment in the vicinity of the first conductive layer 20.

[0079] The first conductive layer 20 has a fourth portion 21 provided between the first insulating layer 10 and the second insulating layer 12, and a fifth portion 22 provided between the second portion 44 and the third portion 46. The fifth portion 22 is connected to the fourth portion 21. The film thickness of the fifth portion 22 in the Z direction is thicker than the film thickness of the fourth portion 21 in the Z direction.

[0080] The second conductive layer 24 has a ninth portion 25 provided between the second insulating layer 12 and the third insulating layer 14, and a tenth portion 26 provided between the seventh portion 54 and the eighth portion 56. The tenth portion 26 is connected to the ninth portion 25. The film thickness of the tenth portion 26 in the Z direction is thicker than the film thickness of the ninth portion 25 in the Z direction.

[0081] FIG. 11 is a schematic cross-sectional view showing a method for manufacturing the semiconductor memory device 110 of this embodiment.

[0082] The manufacturing method up to the manufacturing of the first charge storage film 40 and the second charge storage film 50 is similar to the manufacturing method of the semiconductor memory device 110 of the first embodiment.

[0083] In the manufacturing method of the semiconductor memory device 110 of this embodiment, when the first film 80 is oxidized to form the first block insulating film 30, a part of the first film 80 remains between the first sacrificial layer 70 and the first block insulating film 30. In other words, when the first film 80 is oxidized to form the first block insulating film 30, the first film 80 is oxidized so that a part of the first film 80 is provided between the first sacrificial layer 70 and the first block insulating film 30.

[0084] At this time, the length of the part of the first film 80 in the Z direction is longer than the length of the first sacrificial layer 70 in the Z direction.

[0085] Similarly, when the second film 82 is oxidized to form the second block insulating film 32, a portion of the second film 82 remains between the second sacrificial layer 72 and the second block insulating film 32. In other words, when the second film 82 is oxidized to form the second block insulating film 32, the second film 82 is oxidized such that a portion of the second film 82 is provided between the second sacrificial layer 72 and the second block insulating film 32.

[0086] At this time, the length of the part of the second film 82 in the Z direction is longer than the length of the second sacrificial layer 72 in the Z direction.

[0087] Next, the first sacrificial layer 70 and a part of the first film 80 are replaced with the third block insulating film 16 and the first conductive layer 20. As a result, the first conductive layer 20 having a fourth portion 21 and a fifth portion 22 is formed.

[0088] Moreover, the second sacrificial layer 72 and a part of the second film 82 are replaced with the fourth block insulating film 18 and the second conductive layer 24. As a result, the second conductive layer 24 having a ninth portion 25 and a tenth portion 26 is formed.

[0089] The rest of the manufacturing method is the same as that of the semiconductor memory device of the first embodiment.

[0090] When the first film 80 is oxidized to form the first block insulating film 30, a part of the first sacrificial layer 70 may be oxidized. In particular, the upper and lower surfaces of the first sacrificial layer 70 that are in contact with the first block insulating film 30 may be oxidized. Then, when the first sacrificial layer 70 is replaced with the third block insulating film 16 and the first conductive layer 20, the length in the Z direction of the part of the first conductive layer 20 that faces the first portion 42 in the X direction or the Y direction is shortened. Therefore, it becomes difficult to ensure a high electrostatic capacitance between the first portion 42 and the first conductive layer 20.

[0091] Therefore, in the semiconductor memory device of this embodiment, the first conductive layer 20 has a fourth portion 21 provided between the first insulating layer 10 and the second insulating layer 12, and a fifth portion 22 provided between the second portion 44 and the third portion 46, connected to the fourth portion 21, and having a thickness in the Z direction that is thicker than the thickness of the fourth portion 21 in the Z direction.

[0092] This makes it possible to ensure a high capacitance between the first portion 42 and the fifth portion 22.

[0093] Also, consider reducing the thickness of the insulating layers and the conductive layers in the first laminate S1. In this case, when the sacrificial layer is removed in order to replace the sacrificial layer with a conductive layer in the manufacturing process, the thickness of the insulating layers is too thin, so that there is a risk that the strength cannot be ensured. By providing a part of the first film 80 between the first sacrificial layer 70 and the first block insulating film 30, the strength can be ensured in the manufacturing process.

[0094] The semiconductor memory device of this embodiment also makes it possible to provide a semiconductor memory device that allows high integration.

[0095] Although some embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0096] 3 semiconductor film 4 tunnel insulating film 10 first insulating layer 11 side surface 12 second insulating layer 13 side surface 14 third insulating layer 15 side surface 16 third block insulating film 20 first conductive layer 21 fourth portion 22 fifth portion 24 second conductive layer 30 first block insulating film 32 second block insulating film 40 first charge storage film 42 first portion 44 second portion 46 third portion 50 second charge storage film 52 sixth portion 54 seventh portion 56 eighth portion 70 first sacrificial layer 71 side surface 72 second sacrificial layer 73 side surface 80 first film 100 semiconductor memory device 110 semiconductor memory device H2 opening I adsorption inhibitor S1 first laminate S2 second laminate

Claims

1. a first laminate in which a first insulating layer, a first conductive layer, and a second insulating layer are laminated in this order in a first direction; a semiconductor film provided at a distance from the first stack and extending in the first direction; a tunnel insulating film provided between the first stack and the semiconductor film and extending in the first direction; a first block insulating film provided between the first conductive layer and the tunnel insulating film; a first portion provided between the tunnel insulating film and the first block insulating film; a second portion provided between the tunnel insulating film and the first insulating layer and connected to the first portion; a third portion provided between the tunnel insulating film and the second insulating layer and connected to the first portion; a first charge storage film containing a metal oxide or a metal oxynitride; A semiconductor memory device comprising:

2. The first charge storage film contains at least one first element selected from the group consisting of Al (aluminum), Hf (hafnium), Zr (zirconium), Ti (titanium), V (vanadium), Ta (tantalum) and Nb (niobium); 2. The semiconductor memory device according to claim 1.

3. The first charge storage film is At least one second element selected from the group consisting of N (nitrogen), Si (silicon), Al (aluminum) and lanthanoid elements; Hf or Zr, Contains 2. The semiconductor memory device according to claim 1.

4. The first charge storage film contains the second element in an amount of 20 atomic % or less.

4. The semiconductor memory device according to claim 3.

5. The first conductive layer is a fourth portion provided between the first insulating layer and the second insulating layer; a fifth portion provided between the second portion and the third portion, connected to the fourth portion, and having a thickness in the first direction greater than a thickness of the fourth portion in the first direction; 2. The semiconductor memory device according to claim 1, comprising:

6. the first laminate includes the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, and a third insulating layer, which are laminated in this order in the first direction; The semiconductor memory device includes: a second block insulating film provided between the second conductive layer and the tunnel insulating film and spaced apart from the first block insulating film; a sixth portion provided between the tunnel insulating film and the second block insulating film; a seventh portion provided between the tunnel insulating film and the second insulating layer and connected to the sixth portion; an eighth portion provided between the tunnel insulating film and the third insulating layer and connected to the sixth portion; a second charge storage film comprising a metal oxide or a metal oxynitride and spaced apart from the first charge storage film; The semiconductor memory device according to claim 1 , further comprising:

7. a third block insulating film provided between the first insulating layer, the second insulating layer, the first block insulating film, and the first conductive layer; The semiconductor memory device according to claim 1 , further comprising:

8. forming a second laminate in which a first insulating layer, a first sacrificial layer, and a second insulating layer are laminated in this order in a first direction; forming an opening penetrating the second stack and extending in the first direction, exposing a side surface of the first insulating layer, a side surface of the first sacrificial layer, and a side surface of the second insulating layer in the opening; forming a first film containing N (nitrogen) or Si (silicon) on the side surface of the first sacrificial layer; forming a first charge storage film having a first portion, a second portion and a third portion, the first portion being adjacent to the first insulating layer and the first film, the third portion being adjacent to the second insulating layer and the first film, the first film being between the first sacrificial layer and the first portion, and the first portion being connected to the second portion and the third portion; oxidizing the first film to form a first blocking insulating film; forming a tunnel insulating film extending in the first direction such that the first block insulating film is provided between the second stack and the tunnel insulating film; forming a semiconductor film extending in the first direction such that the tunnel insulating film is provided between the second stacked body and the semiconductor film; A method for manufacturing a semiconductor memory device.

9. After oxidizing the first film to form the first block insulating film, replacing the first sacrificial layer with a first conductive layer; 9. The method for manufacturing a semiconductor memory device according to claim 8.

10. After oxidizing the first film to form the first block insulating film, Prior to replacing the first sacrificial layer with the first conductive layer, forming a third block insulating film so that the third block insulating film is provided between the first insulating layer, the second insulating layer, and the first block insulating film and the first conductive layer; The method for manufacturing a semiconductor memory device according to claim 9.

11. When the first film is oxidized to form the first block insulating film, a portion of the first film is provided between the first sacrificial layer and the first block insulating film; 9. The method for manufacturing a semiconductor memory device according to claim 8.

12. a length of the portion of the first film in the first direction is longer than a length of the first sacrificial layer in the first direction; The method for manufacturing a semiconductor memory device according to claim 11.

13. After oxidizing the first film to form the first block insulating film, replacing the first sacrificial layer and the portion of the first film with a first conductive layer; The method for manufacturing a semiconductor memory device according to claim 11.

14. The first conductive layer is a fourth portion provided between the first insulating layer and the second insulating layer; a fifth portion provided between the second portion and the third portion, connected to the fourth portion, and having a thickness in the first direction greater than a thickness of the fourth portion in the first direction; The method for manufacturing a semiconductor memory device according to claim 13, further comprising:

15. forming an opening extending in the first direction through the second stack to expose the side surface of the first insulating layer, the side surface of the first sacrificial layer, and the side surface of the second insulating layer; Before forming the first film containing N (nitrogen) or Si (silicon) on the side surface of the first sacrificial layer, an adsorption inhibitor is adsorbed onto the side surface of the first insulating layer and the side surface of the second insulating layer; 9. The method for manufacturing a semiconductor memory device according to claim 8.

16. The first charge storage film contains at least one first element selected from the group consisting of Al (aluminum), Hf (hafnium), Zr (zirconium), Ti (titanium), V (vanadium), Ta (tantalum) and Nb (niobium); 9. The method for manufacturing a semiconductor memory device according to claim 8.

17. The first charge storage film contains at least one second element selected from the group consisting of N (nitrogen), Si (silicon), Al (aluminum) and lanthanoid elements, and Hf or Zr.

9. The method for manufacturing a semiconductor memory device according to claim 8.

18. The first charge storage film contains the second element in an amount of 20 atomic % or less.

20. The method for manufacturing a semiconductor memory device according to claim 17.

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