Printed circuit board

Abstract

To provide a printed circuit board capable of forming cavities in a substrate without applying a metal stopper layer.SOLUTION: A printed circuit board 100A includes: a first insulating layer 111; a first wiring layer 121 arranged on the upper side of the first insulating layer; a second insulating layer 112 arranged on the top surface of the first insulating layer, covering at least a portion of the first wiring layer and forming a cavity C; and a first barrier layer 141 at least partially arranged between the first and second insulating layers and in contact with at least some sides of the first wiring layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] As the area of ​​packages increases, technology to embed bridges at the package level is under development. To embed the bridges, it is necessary to form a cavity in the substrate, which is generally achieved by using a laser and applying a metal stopper layer to control the depth of the cavity. However, in this case, the cost may increase due to the process of forming and removing the metal stopper layer, and the design freedom may be reduced. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE PRESENT EMBODIMENT One of several objects of the present invention is to provide a printed circuit board in which cavities can be formed in the board without applying a metal stopper layer. [Means for solving the problem]

[0004] One of the solutions proposed in the present invention is to form a barrier layer instead of a metal stopper layer using a thin film deposition method, such as ALD (Atomic Layer Deposition) or MVD (Molecular Vapor Deposition), and use this to form a cavity in the substrate.

[0005] For example, one example of a printed circuit board may include a first insulating layer, a first wiring layer arranged on an upper side of the first insulating layer, a second insulating layer arranged on an upper surface of the first insulating layer and having a cavity, and a first barrier layer at least partially arranged between the first and second insulating layers and in contact with at least a portion of a side of the first wiring layer.

[0006] For example, a printed circuit board according to one example may include a first insulating layer, a wiring layer arranged on an upper side of the first insulating layer, a second insulating layer arranged on an upper surface of the first insulating layer and having a cavity, and a barrier layer at least partially arranged between the first and second insulating layers, wherein the upper surface of the barrier layer and the upper surface of the wiring layer, or the lower surface of the barrier layer and the lower surface of the wiring layer, are substantially coplanar with each other. Effect of the Invention

[0007] One of the various effects of the present invention is that it is possible to provide a printed circuit board that can simplify the process by eliminating the circuit process for removing the metal stopper layer, thereby reducing costs.

[0008] Another advantage of the present invention is that it provides a printed circuit board that can minimize edge grooves of cavities that occur when removing a metal stopper layer.

[0009] Still another advantage of the present invention is that it provides a printed circuit board that allows greater freedom in cavity design. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating an example of a printed circuit board. [Figure 4] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 5a] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3 and the printed circuit board of FIG. 4. [Figure 5b] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3 and the printed circuit board of FIG. 4. [Figure 5c] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3 and the printed circuit board of FIG. 4. [Figure 5d] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3 and the printed circuit board of FIG. 4. [Figure 5e] 5A to 5C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 3 and the printed circuit board of FIG. 4. [Figure 6] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 7a] 7A to 7C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 6. [Figure 7b] 7A to 7C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 6. [Figure 7c] 7A to 7C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 6. [Figure 7d] 7A to 7C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 6. [Figure 7e] 7A to 7C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 6. [Figure 7f] 7A to 7C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 6. [Figure 7g] 7A to 7C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 6. [Figure 8] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 9] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 10a] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 8 and the printed circuit board of FIG. 9. [Figure 10b] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 8 and the printed circuit board of FIG. 9. [Figure 10c]10A to 10C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 8 and the printed circuit board of FIG. 9. [Figure 10d] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 8 and the printed circuit board of FIG. 9. [Figure 11] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 12a] 12A to 12C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 11. [Figure 12b] 12A to 12C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 11. [Figure 12c] 12A to 12C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 11. [Figure 12d] 12A to 12C are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG. 11. [Figure 13] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0012] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0013] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also connected to other electronic components described below to form various signal lines 1090.

[0014] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, the chip-related components 1020 may include other types of chip-related electronic components. Needless to say, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0015] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020 and with each other.

[0016] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may also include passive elements in the form of chip components used for various other different applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0017] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. The other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Needless to say, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0018] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0019] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0020] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components such as a camera module 1130 and / or a speaker 1140 that may or may not be physically and / or electrically connected to the motherboard 1110 are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built-in. Meanwhile, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0021] Printed Circuit Board FIG. 3 is a cross-sectional view that illustrates an example of a printed circuit board.

[0022] Referring to the drawings, an example of a printed circuit board 100A may include a first insulating layer 111, a first wiring layer 121 embedded in the upper side of the first insulating layer 111, a second insulating layer 112 disposed on the upper surface of the first insulating layer 111, covering at least a portion P1 of the first wiring layer 121, and having a cavity C, a first barrier layer 141 having at least a portion disposed between the first and second insulating layers 111 and 112, a second wiring layer 122 disposed on the lower surface of the first insulating layer 111, a first via layer 131 penetrating at least a portion of the first insulating layer 111 to connect at least a portion of each of the first and second wiring layers 121 and 122, a third wiring layer 123 embedded in the upper side of the second insulating layer 112, and a second via layer 132 penetrating at least a portion of the second insulating layer 112 to connect at least a portion of each of the first and third wiring layers 121 and 123.

[0023] The first barrier layer 141 may be a layer formed by using a thin film deposition method, for example, ALD (Atomic Layer Deposition), MVD (Molecular Vapor Deposition), or the like. For example, the first barrier layer 141 may include a thin insulating film having a thickness of less than 0.1 μm, preferably about 0.001 μm to 0.01 μm, and the insulating film may be an alumina film, but is not limited thereto. In this case, the first barrier layer 141 may be formed in a form covering the first wiring layer 121 between the first and second insulating layers 111 and 112 after the first wiring layer 121 is formed. Therefore, the first barrier layer 141 may contact a side surface of at least a portion P1 of the first wiring layer 121, and preferably cover at least a part of each of the side surface and the lower surface of at least a portion P1 of the first wiring layer 121. In addition, the upper surface of the first barrier layer 141 and the upper surface of the first wiring layer 121 may be substantially coplanar with each other. In addition, the upper surface of the first insulating layer 111 and the upper surface of at least a part P1 of the first wiring layer 121 may have a step. Such a first barrier layer 141 can be used as a stopper for blast (e.g., sandblast) processing as well as laser (e.g., CO2 laser) processing when forming the cavity C in the second insulating layer 112. Therefore, it is possible to prevent a foot from being generated on the bottom surface of the cavity C. In addition, the first barrier layer 141 functions as an adhesion auxiliary layer and can improve reliability.

[0024] The cavity C may penetrate the second insulating layer 112. At least a portion of the first barrier layer 141 may be disposed on the bottom surface of the cavity C. For example, the bottom surface of the cavity C may be formed of the first barrier layer 141. Also, at least a portion of the top surface of the first barrier layer 141 may be exposed from the first and second insulating layers 111 and 112 by the cavity C. Various types of components may be disposed in the cavity C, and the components may be attached to the exposed top surface of the first barrier layer 141. In this case, the components may be more easily built in, and reliability may be further improved. The cavity C may have a tapered shape in which the width of the upper side is greater than the width of the lower side, but is not limited thereto.

[0025] The first and second insulating layers 111 and 112 may each include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymeric materials may be used. The insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric). The first and second insulating layers 111 and 112 may have a boundary that is distinct from each other, but may be integrated after curing to such an extent that it is difficult to distinguish the boundary. When the boundary between the first and second insulating layers 111 and 112 is unclear, the boundary may be distinguished by drawing an imaginary line based on the upper surface of at least a portion P1 of the first wiring layer 121 in consideration of the manufacturing process.

[0026] Each of the first to third wiring layers 121, 122, and 123 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. Each of the first to third wiring layers 121, 122, and 123 may perform various functions according to the design. For example, the first to third wiring layers 121, 122, and 123 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of these patterns may have various forms, such as a line, a plane, and a pad. Each of the first to third wiring layers 121, 122, and 123 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Alternatively, the first to third wiring layers 121, 122, and 123 may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Alternatively, it may include a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be included instead of the electroless plating layer (or chemical copper), or both may be included as necessary.

[0027] Each of the first and second via layers 131 and 132 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. Each of the first and second via layers 131 and 132 may include a microvia. The microvia may be a filled via that fills a via hole, or a conformal via that is arranged along the wall surface of a via hole. The microvia may be arranged in a stacked type and / or staggered type. The microvia may perform various functions depending on the design of the layer. For example, the microvia may include a ground via, a power via, a signal via, and the like. The first and second via layers 131, 132 may each include, but are not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The first and second via layers 131, 132 may have tapered shapes in the same direction. For example, each of the cross sections may have a tapered shape in which the upper width is smaller than the lower width, but is not limited to this.

[0028] FIG. 4 is a cross-sectional view that illustrates another example of a printed circuit board.

[0029] Referring to the drawings, the printed circuit board 100B according to another example may be obtained by removing the first barrier layer 141 exposed through the cavity C by plasma etching or the like after forming the cavity C in the printed circuit board 100A according to the above example. In this case, the cavity C may expose at least a part of the upper surface of the first insulating layer 111, and at least a part of the upper surface of the first insulating layer 111 exposed through the cavity C may have a step with the upper surface of at least a part P1 of the first wiring layer 121. At least a part of the side surface of the first barrier layer 141 may be exposed through the cavity C, and at least a part of the side surface of the first barrier layer 141 exposed through the cavity C may not have a step with the wall surface of the cavity C. For example, it is possible to prevent a groove from being formed at the edge of the cavity C.

[0030] The other details are substantially the same as those described in the printed circuit board 100A according to the above-mentioned example, and therefore will not be described again.

[0031] 5a to 5e are cross-sectional views illustrating steps of a manufacturing process for the printed circuit board of FIG. 3 and the printed circuit board of FIG.

[0032] Referring to FIG. 5a, first, a substrate in the form of an ETS (Embedded Trace Substrate) is formed using a carrier 210. For example, a third wiring layer 123 is formed on the carrier 210 by a plating process or the like, a second insulating layer 112 is formed on the carrier 210 by a lamination process or the like, via holes are processed in the second insulating layer 112 by a laser processing or the like, and a first wiring layer 121 and a second via layer 132 are formed on the second insulating layer 112 by a plating process or the like. The carrier 210 may be in the form in which a copper (Cu) layer and a nickel (Ni) layer are sequentially formed on both sides of a core layer, but is not limited thereto. Next, a first barrier layer 141 is formed on the lower surface of the second insulating layer 112 in the form of covering the first wiring layer 121 by a thin film deposition method, for example, an ALD (Atomic Layer Deposition) method, an MVD (Molecular Vapor Deposition) method, or the like.

[0033] 5b, the first insulating layer 111 is formed on the lower surface of the second insulating layer 112 in a form covering the first barrier layer 141. The first insulating layer 111 can be formed by a lamination process or the like. Next, a via hole is processed in the first insulating layer 111 by laser processing or the like, and the second wiring layer 122 and the first via layer 131 are formed on the first insulating layer 111 by a plating process or the like. At least a part of the first barrier layer 141 may be removed for interlayer conduction when processing the via hole.

[0034] 5c, the carrier 210 is removed. For example, the manufactured stack can be detached from the carrier 210, and the copper (Cu) layer and nickel (Ni) layer of the carrier 210 remaining in the stack after detachment can be sequentially removed by etching.

[0035] 5d, a cavity C is formed through the second insulating layer 112 by CO2 laser processing or the like using the first barrier layer 141 as a stopper. Through a series of processes, the printed circuit board 100A according to the above example can be manufactured.

[0036] 5e, at least a portion of the first barrier layer 141 exposed through the cavity C is removed by plasma etching, etc. Through a series of processes, the printed circuit board 100B according to the above-mentioned example can be manufactured.

[0037] The other details are substantially the same as those described above for the printed circuit boards 100A and 100B, and therefore a duplicated description will be omitted.

[0038] FIG. 6 is a cross-sectional view that illustrates a schematic diagram of still another example of a printed circuit board.

[0039] Referring to the drawings, in the printed circuit board 100C according to another example, in the printed circuit board 100B according to the above-mentioned example, at least another portion P2 of the first wiring layer 121 may be exposed through the cavity C. In this case, a component disposed in the cavity C may be connected to at least another portion P2 of the first wiring layer 121 and electrically connected to a circuit inside the board. Therefore, more diverse electrical connection paths may be secured. To this end, the first barrier layer 141 may be formed only in a portion of the area between the first and second insulating layers 111 and 112, and then only the area exposed through the cavity C may be selectively removed by plasma etching or the like. Therefore, the at least one portion P1 and the at least another portion P2 of the first wiring layer 121 may have a step between their respective upper surfaces.

[0040] The other details are substantially the same as those described above for the printed circuit boards 100A and 100B, and therefore a duplicated description will be omitted.

[0041] 7a to 7g are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG.

[0042] 7a, a third wiring layer 123 is formed on a carrier 210 by a plating process or the like, then a second insulating layer 112 is formed on the carrier 210 by a lamination process or the like, and then a via hole V is processed in the second insulating layer 112 by laser processing or the like. The carrier 210 may have a form in which a copper (Cu) layer and a nickel (Ni) layer are sequentially formed on both sides of a core layer, but is not limited thereto.

[0043] 7b and 7c, first, a pattern region for forming the first barrier layer 141 is formed using a mask 220, and the first barrier layer 141 is formed in the mask pattern region on the lower surface of the second insulating layer 112 by a thin film deposition method, for example, ALD (Atomic Layer Deposition), MVD (Molecular Vapor Deposition), or the like. Next, the mask 220 is removed. The mask 220 may be a metal mask and can be removed by desorption, but is not limited thereto.

[0044] 7d, the first wiring layer 121 and the second via layer 132 are formed on the second insulating layer 112 and the first barrier layer 141 by a plating process or the like. At this time, at least a part P1 of the first wiring layer 121 and at least another part P2 may have a step. Next, the first insulating layer 111 is formed on the lower surface of the second insulating layer 112 in a form covering the first barrier layer 141. The first insulating layer 111 may be formed by a lamination process or the like. Next, a via hole is processed in the first insulating layer 111 by laser processing or the like, and the second wiring layer 122 and the first via layer 131 are formed on the first insulating layer 111 by a plating process or the like.

[0045] 7e, the carrier 210 is removed. For example, the manufactured laminate can be detached from the carrier 210, and the copper (Cu) layer and the nickel (Ni) layer of the carrier 210 remaining in the laminate after detachment can be sequentially removed by etching.

[0046] 7f and 7g, a cavity C penetrating the second insulating layer 112 is formed by CO2 laser processing or the like using the first barrier layer 141 as a stopper. Then, at least a portion of the first barrier layer 141 exposed through the cavity C is removed by plasma etching or the like. Through a series of processes, the printed circuit board 100C according to the above-mentioned further example can be manufactured.

[0047] The other details are substantially the same as those described above for the printed circuit boards 100A, 100B, and 100C, and therefore will not be described again.

[0048] FIG. 8 is a cross-sectional view that illustrates a schematic diagram of still another example of a printed circuit board.

[0049] Referring to the drawings, a printed circuit board 100D according to yet another example includes a first insulating layer 111, a first wiring layer 121 disposed on an upper surface of the first insulating layer 111, a second wiring layer 122 disposed on a lower surface of the first insulating layer 111, a first via layer 131 penetrating the first insulating layer 111 and connecting at least a portion of each of the first and second wiring layers 121 and 122, one or more second insulating layers 112-1 and 112-2 disposed on the upper surface of the first insulating layer 111 and having a cavity C, a first barrier layer 141 at least a portion of which is disposed between the first and second insulating layers 111, 112-1, and 112-2, one or more third insulating layers 113-1 and 113-2 disposed on the lower surface of the first insulating layer 111, and , 113-2, a second barrier layer 142 at least partially disposed between the first and third insulating layers 111, 113-1, 113-2, one or more third wiring layers 123-1, 123-2 disposed on the upper surfaces of the one or more second insulating layers 112-1, 112-2, one or more second via layers 132-1, 132-2 penetrating the one or more second insulating layers 112-1, 112-2, one or more fourth wiring layers 124-1, 124-2 disposed on the lower surfaces of the one or more third insulating layers 113-1, 113-2, and one or more third via layers 133-1, 133-2 penetrating the one or more third insulating layers 113-1, 113-2, respectively. One or more second via layers 132-1, 132-2 can connect the first wiring layer 121 to one or more third wiring layers 123-1, 123-2. One or more third via layers 133-1, 133-2 can connect the second wiring layer 122 to one or more fourth wiring layers 124-1, 124-2.

[0050] The first and second barrier layers 141 and 142 may be layers formed by using a thin film deposition method, such as an ALD (Atomic Layer Deposition) method or an MVD (Molecular Vapor Deposition) method. For example, the first and second barrier layers 141 and 142 may each include a thin insulating film having a thickness of less than 0.1 μm, preferably about 0.001 μm to 0.01 μm, and the insulating film may be an alumina film, but is not limited thereto. In this case, the first and second barrier layers 141 and 142 may be formed in a form covering the first and second wiring layers 121 and 122 after the first and second wiring layers 121 and 122 are formed, respectively. Therefore, the first barrier layer 141 may be in contact with a side surface of at least a portion P1 of the first wiring layer 121, and preferably may cover at least a portion of each of the side surface and the upper surface of at least a portion P1 of the first wiring layer 121. In addition, the second barrier layer 142 may contact at least a part of the side surfaces of the second wiring layer 122, and preferably may cover at least a part of each of at least a part of the side surfaces and the lower surface of the second wiring layer 122. In addition, the lower surface of the first barrier layer 141 and the lower surface of the first wiring layer 121 may be substantially coplanar with each other. In addition, the upper surface of the second barrier layer 142 and the upper surface of the second wiring layer 122 may be substantially coplanar with each other. Such a first barrier layer 141 may be used as a stopper for blast (e.g., sandblast) processing as well as laser (e.g., CO2 laser) processing when forming a cavity C in one or more second insulating layers 112-1 and 112-2. Therefore, it is possible to prevent a foot from being generated on the bottom surface of the cavity C. In addition, the first and second barrier layers 141 and 142 are adhesive auxiliary layers, and may improve reliability.

[0051] The cavity C may penetrate one or more of the second insulating layers 112-1 and 112-2. At least a portion of the first barrier layer 141 may be disposed on the bottom surface of the cavity C. For example, the bottom surface of the cavity C may be formed of the first barrier layer 141. Also, at least a portion of the top surface of the first barrier layer 141 may be exposed from the first and second insulating layers 111, 112-1 and 112-2 by the cavity C. Various types of components may be disposed in the cavity C, and the components may be attached to the exposed top surface of the first barrier layer 141. In this case, the components may be more easily built in, and the reliability may be further improved. The cavity C may have a tapered shape in which the width of the upper side is larger than the width of the lower side, but is not limited thereto.

[0052] Each of the first to third insulating layers 111, 112-1, 112-2, 113-1, and 113-2 may contain an insulating material. The insulating material may contain a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymer materials may be used. The insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric). Preferably, the first insulating layer 111 may be a core layer, and one or more of the second and third insulating layers 112-1, 112-2, 113-1, and 113-2 may be build-up layers. Therefore, the first insulating layer 111 may be thicker and have a higher modulus than each of the one or more second and third insulating layers 112-1, 112-2, 113-1, 113-2. The one or more second insulating layers 112-1, 112-2 may have a boundary between them, but may be integrated without a boundary after curing. The one or more third insulating layers 113-1, 113-2 may have a boundary between them, but may be integrated without a boundary after curing. If the boundary between the one or more second insulating layers 112-1, 112-2 is unclear, the boundary may be defined by drawing a virtual line based on the lower surface of one of the one or more third wiring layers 123-1, 123-2 in consideration of the manufacturing process. If the boundary between one or more third insulating layers 113-1, 113-2 is unclear, the boundary can be divided by drawing an imaginary line based on the top surface of one of the one or more fourth wiring layers 124-1, 124-2, taking into account the manufacturing process.

[0053] Each of the first to fourth wiring layers 121, 122, 123-1, 123-2, 124-1, and 124-2 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. Each of the first to fourth wiring layers 121, 122, 123-1, 123-2, 124-1, and 124-2 may perform various functions according to the design. For example, the first to fourth wiring layers 121, 122, 123-1, 123-2, 124-1, and 124-2 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of these patterns may have various forms, such as a line, a plane, and a pad. The first to fourth wiring layers 121, 122, 123-1, 123-2, 124-1, and 124-2 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Alternatively, they may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Alternatively, they may include a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electrolytic copper). Instead of the electroless plating layer (or chemical copper), a sputtering layer may be included, or both may be included as necessary.

[0054] Each of the first to third via layers 131, 132-1, 132-2, 133-1, and 133-2 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. The first via layer 131 may include a through via. The through via may be a filled via that fills a through hole, or may be a conformal via that is arranged along the wall surface of the through hole. Alternatively, the through via may be a conformal type but may include a plug inside. Each of the one or more second and third via layers 132-1, 132-2, 133-1, and 133-2 may include a microvia. The microvias may be filled vias that fill the via holes, or may be conformal vias that are arranged along the walls of the via holes. The microvias may be arranged in a stacked type and / or staggered type. The through vias and the microvias may perform various functions depending on the design of the layer. For example, they may include ground vias, power vias, signal vias, etc. The first to third via layers 131, 132-1, 132-2, 133-1, and 133-2 may each include, but are not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The first via layer 131 may have an hourglass shape, a cylindrical shape, etc., and one or more second and third via layers 132-1, 132-2, 133-1, and 133-2 may have tapered shapes in opposite directions.

[0055] FIG. 9 is a cross-sectional view that illustrates a schematic diagram of still another example of a printed circuit board.

[0056] With reference to the drawings, in the printed circuit board 100E according to yet another example, after the cavity C is formed in the printed circuit board 100D according to yet another example described above, the first barrier layer 141 exposed through the cavity C can be removed by plasma etching or the like. In this case, the cavity C can expose at least a part of the upper surface of the first insulating layer 111. Also, at least a part of the side surface of the first barrier layer 141 may be exposed through the cavity C, and at least a part of the side surface of the first barrier layer 141 exposed through the cavity C may not have a step with the wall surface of the cavity C. For example, it is possible to prevent a groove from being generated at the edge of the cavity C.

[0057] The other details are substantially the same as those described in the printed circuit board 100D according to the further example described above, and therefore will not be described again.

[0058] 10a to 10d are cross-sectional views illustrating steps of a manufacturing process for the printed circuit board of FIG. 8 and the printed circuit board of FIG.

[0059] 10a, first, a through hole is formed in the first insulating layer 111 by laser processing or the like, and then the first and second wiring layers 121, 122 and the first via layer 131 are formed by a plating process or the like. Next, the first and second barrier layers 141, 142 are formed on the upper and lower surfaces of the first insulating layer 111 by a thin film deposition method, for example, ALD (Atomic Layer Deposition) or MVD (Molecular Vapor Deposition) method, so as to cover the first and second wiring layers 121, 122, respectively.

[0060] Referring to FIG. 10b, in the build-up process, one or more second insulating layers 112-1, 112-2, one or more third insulating layers 113-1, 113-2, one or more third wiring layers 123-1, 123-2, one or more fourth wiring layers 124-1, 124-2, one or more second via layers 132-1, 132-2, and one or more third via layers 133-1, 133-2 are formed on the first insulating layer 111.

[0061] 10c, a cavity C is formed through one or more second insulating layers 112-1, 112-2 by CO2 laser processing or the like using the first barrier layer 141 as a stopper. Through a series of processes, the printed circuit board 100D according to the above-mentioned further example can be manufactured.

[0062] 10d, at least a portion of the first barrier layer 141 exposed through the cavity C is removed by plasma etching or the like. Through a series of processes, the printed circuit board 100E according to the above-mentioned further example can be manufactured.

[0063] The other details are substantially the same as those described above for the printed circuit boards 100D and 100E, and therefore a duplicated description will be omitted.

[0064] FIG. 11 is a cross-sectional view that illustrates a schematic diagram of still another example of a printed circuit board.

[0065] Referring to the drawings, in the printed circuit board 100F according to another example, in the printed circuit board 100E according to the above-mentioned another example, at least another portion P2 of the first wiring layer 121 may be exposed through a cavity C. In this case, a component disposed in the cavity C may be connected to at least another portion P2 of the first wiring layer 121 and electrically connected to a circuit inside the board. Therefore, various electrical connection paths may be secured.

[0066] The other details are substantially the same as those described above for the printed circuit boards 100D and 100E, and therefore a duplicated description will be omitted.

[0067] 12a to 12d are cross-sectional views illustrating an example of a manufacturing process for the printed circuit board of FIG.

[0068] 12a, first, a through hole is formed in the first insulating layer 111 by laser processing or the like, and then the first and second wiring layers 121, 122 and the first via layer 131 are formed by a plating process or the like. Next, the first and second barrier layers 141, 142 are formed on the upper and lower surfaces of the first insulating layer 111 by a thin film deposition method, for example, ALD (Atomic Layer Deposition) or MVD (Molecular Vapor Deposition) method, so as to cover the first and second wiring layers 121, 122, respectively.

[0069] Referring to FIG. 12b, in the build-up process, one or more second insulating layers 112-1, 112-2, one or more third insulating layers 113-1, 113-2, one or more third wiring layers 123-1, 123-2, one or more fourth wiring layers 124-1, 124-2, one or more second via layers 132-1, 132-2, and one or more third via layers 133-1, 133-2 are formed on the first insulating layer 111.

[0070] 12c and 12d, first, a cavity C penetrating one or more second insulating layers 112-1, 112-2 is formed by CO2 laser processing or the like using the first barrier layer 141 as a stopper. Next, at least a portion of the first barrier layer 141 exposed through the cavity C is removed by plasma etching or the like. Through a series of processes, the printed circuit board 100F according to the above-mentioned further example can be manufactured.

[0071] The other details are substantially the same as those described for the printed circuit boards 100D, 100E, and 100F described above, so a duplicated description will be omitted.

[0072] FIG. 13 is a cross-sectional view that illustrates a schematic diagram of still another example of a printed circuit board.

[0073] Referring to the drawings, the printed circuit board 100G according to another example may have a package form. For example, the first component 191 may be embedded in the package substrate 150, and the second and third components 192 and 193 may be mounted on the package substrate 150. The package substrate 150 may include the above-mentioned printed circuit boards 100A, 100B, 100C, 100D, 100E, and 100F. For example, the structure of the printed circuit board 100D according to another example may be partially modified and expanded and applied to the package substrate 150 of the printed circuit board 100G according to another example. Other configurations of the package substrate 150 may be those of a typical package substrate known in the art. The first component 191 may be a bridge for interconnecting the second and third components 192 and 193, and the bridge may be an organic bridge and / or a silicon bridge. The second and third components 192 and 193 may be semiconductor chips of the same type or different types. If necessary, the barrier layer may be formed on layers at other levels other than the stopper positions for forming the cavity. For example, the barrier layer may be formed on all layers on which the wiring layers are formed, but is not limited thereto. In the package substrate 150, the boundaries of the respective insulating layers may be defined or may be unclear. When the boundaries are unclear, the boundaries may be defined by drawing imaginary lines based on the upper or lower surfaces of the wiring layers of each layer, taking into consideration the manufacturing process.

[0074] The other contents are substantially the same as those described above for the printed circuit boards 100A, 100B, 100C, 100D, 100E, and 100F, so duplicated description will be omitted.

[0075] In the present invention, "substantially" includes process errors and positional deviations that occur in the manufacturing process, measurement errors, etc. For example, "line width, interval, thickness, height, etc., substantially have a specific value" includes not only the case where the value is the specified value, but also the case where the value is similar to the specified value. Furthermore, "substantially coplanar" includes not only the case where the values ​​are completely on the same plane, but also the case where the values ​​are almost on the same plane.

[0076] In the present invention, a cross section may refer to a cross-sectional shape obtained by cutting an object vertically or a cross-sectional shape obtained by viewing the object from a side, and a plane may refer to a planar shape obtained by cutting an object horizontally or a planar shape obtained by viewing the object from a top or bottom.

[0077] In the present invention, for convenience, the terms lower, bottom, and bottom surface are used to mean the downward direction based on the cross section of the drawing, and the terms upper, top, and top surface are used to mean the opposite direction. Also, the terms side and lateral surface are used to mean the direction perpendicular to the top and bottom surfaces. However, these are merely definitions of directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of the directions, and the concepts of up / down can be changed at any time.

[0078] In the present invention, "connected" is a concept including not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept including both physical connection and no connection. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component, within the scope of the right.

[0079] The term "one example" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe unique features that are different from each other. However, the above-mentioned one example does not exclude that it is realized in combination with the features of another example. For example, even if the matter described in a specific example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0080] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0081] 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera 1060:Antenna 1070:Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts package 1130: Camera module 1140: Speaker 100A, 100B, 100C, 100D, 100E, 100F, 100G: Printed circuit boards 111, 112, 112-1, 112-2, 113-1, 113-2: insulating layer 121, 122, 123, 123-1, 123-2, 124-1, 124-2: Wiring layer 131, 132, 132-1, 132-2, 133-1, 133-2: via layers 141, 142: Barrier layer 150: Package substrate 191, 192, 193: Parts 210: Career 220: Mask

Claims

1. A first insulating layer; a first wiring layer disposed on an upper side of the first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer and having a cavity; a first barrier layer, at least a portion of which is disposed between the first insulating layer and the second insulating layer and in contact with at least a portion of a side of the first wiring layer.

2. 10. The printed circuit board of claim 1, wherein the first barrier layer comprises an alumina film having a thickness of less than 0.1 μm.

3. The printed circuit board according to claim 1 , wherein the first barrier layer covers at least a portion of a side surface of at least a portion of the first wiring layer and at least a portion of an upper surface or a lower surface of at least a portion of the first wiring layer.

4. The printed circuit board of claim 1 , wherein at least a portion of the first barrier layer is disposed on a bottom surface of the cavity.

5. a first component disposed within the cavity and attached to at least a portion of the first barrier layer disposed on a bottom surface of the cavity; The printed circuit board of claim 4 , further comprising: a second component and a third component, each disposed on an upper surface of the second insulating layer and each coupled to the first component.

6. The printed circuit board of claim 1 , wherein the cavity exposes at least a portion of a top surface of the first insulating layer.

7. The printed circuit board of claim 6 , wherein at least a portion of a side surface of the first barrier layer is exposed through the cavity.

8. The printed circuit board according to claim 7 , wherein at least a portion of the side surface of the first barrier layer exposed through the cavity has no step with a wall surface of the cavity.

9. The printed circuit board according to claim 6 , wherein at least another portion of the first wiring layer is exposed through the cavity.

10. a second wiring layer disposed on a lower surface of the first insulating layer; a first via layer that penetrates at least a portion of the first insulating layer and connects at least a portion of the first wiring layer and the second wiring layer; a third wiring layer embedded on the upper side of the second insulating layer; a second via layer penetrating at least a portion of the second insulating layer and connecting at least a portion of the first wiring layer and the third wiring layer, The printed circuit board of claim 1 , wherein the first wiring layer is embedded above the first insulating layer.

11. The printed circuit board according to claim 10 , wherein the first barrier layer covers at least a portion of each of the side surfaces and the bottom surface of at least a portion of the first wiring layer, and at least a portion of the first barrier layer contacts a side surface of the first via layer.

12. the cavity exposes at least a portion of a top surface of the first insulating layer; The printed circuit board according to claim 10 , wherein at least a portion of the upper surface of the first insulating layer exposed through the cavity has a step with respect to at least a portion of the upper surface of the first wiring layer.

13. At least another part of the first wiring layer is exposed through the cavity, The printed circuit board according to claim 12 , wherein an upper surface of at least a portion of the first wiring layer has a step with an upper surface of at least another portion of the first wiring layer.

14. a second wiring layer disposed on a lower surface of the first insulating layer; a first via layer that penetrates at least a portion of the first insulating layer and connects at least a portion of the first wiring layer and the second wiring layer; a third wiring layer disposed on an upper surface of the second insulating layer; a second via layer that penetrates at least a portion of the second insulating layer and connects at least a portion of the first wiring layer and the third wiring layer; a third insulating layer disposed on a lower surface of the first insulating layer; a fourth wiring layer disposed on a lower surface of the third insulating layer; a third via layer that penetrates at least a portion of the third insulating layer and connects at least a portion of the second wiring layer and the fourth wiring layer; a second barrier layer, at least a portion of which is disposed between the first insulating layer and the third insulating layer and in contact with at least a portion of a side surface of the second wiring layer; The printed circuit board of claim 1 , wherein the first wiring layer is disposed on an upper surface of the first insulating layer.

15. the first barrier layer covers at least a portion of each of at least a portion of a side surface and an upper surface of the first wiring layer, and at least a portion of the first barrier layer contacts a side surface of the second via layer; The printed circuit board according to claim 14 , wherein the second barrier layer covers at least a portion of each of the side surfaces and the bottom surface of at least a portion of the second wiring layer, and at least a portion of the second barrier layer contacts a side surface of the third via layer.

16. A wiring layer disposed on the first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer and having a cavity; a barrier layer at least partially disposed between the first insulating layer and the second insulating layer; A printed circuit board, wherein the upper surface of the barrier layer and the upper surface of the wiring layer, or the lower surface of the barrier layer and the lower surface of the wiring layer, are substantially coplanar with each other.

17. 17. The printed circuit board of claim 16, wherein the barrier layer comprises an alumina film having a thickness of less than 0.1 μm.

Images