Power semiconductor device including gate with trench and method for forming such device

Abstract

To provide a semiconductor device and a method for forming the device.SOLUTION: A method for forming a semiconductor device includes steps of: forming a trench in a semiconductor layer structure, the semiconductor layer structure having first and second main surfaces; forming a lower dielectric layer in the trench, the step of forming the lower dielectric layer including a step of forming and annealing a preliminary lower dielectric layer; forming a dielectric layer directly in the trench, conformally in the center of the lower dielectric layer; forming a gate electrode in the trench on a gate dielectric layer; and forming a shield region in a drift layer under the trench.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 080,956, filed October 27, 2020, the entire contents of which are incorporated by reference herein as if set forth in their entirety.

[0002] The present invention relates to semiconductor devices, and more particularly to power semiconductor devices including trenched gates. [Background technology]

[0003] A Metal Insulating Semiconductor Field Effect Transistor (MISFET) is a well-known type of semiconductor transistor that can be used as a switching device. A MISFET is a three-terminal device having a gate, drain, and source terminals, and a semiconductor body. The source and drain regions are formed in the semiconductor body separated by a channel region, and the gate electrode (which may act as the gate terminal or be electrically connected to the gate terminal) is separated from the channel region by a thin insulating layer called the "gate dielectric layer." A MISFET can be turned on or off by applying a bias voltage to the gate electrode. When a MISFET is turned on (i.e., the MISFET is in its "on-state"), current is conducted through the channel region of the MISFET between the source and drain regions. When the bias voltage is removed from the gate electrode (or reduced below a threshold level), current stops conducting through the channel region. By way of example, an n-type MISFET has n-type source and drain regions and a p-type channel.

[0004] In most cases, the gate dielectric layer that separates the gate electrode of a power MISFET from the channel region is implemented as a thin oxide layer (e.g., a silicon oxide layer). MISFETs with oxide gate dielectric layers are called Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Because oxide-based gate dielectric layers are almost always used due to their superior properties, the discussion herein will focus on MOSFETs as opposed to MISFETs, although it will be recognized that the techniques according to embodiments of the invention described herein are equally applicable to devices having gate dielectric layers formed of materials other than oxides.

[0005] The gate electrode of a MOSFET is insulated from the channel region by a gate dielectric layer, so a minimum gate current is required to maintain the MOSFET in its on state or to switch the MOSFET between its on state and its off state. The gate current is kept small during switching because the gate forms a capacitor with the channel region. Therefore, only minimal charge and discharge currents are required during switching, allowing for less complicated gate drive circuitry and faster switching speeds. MOSFETs can be standalone devices or can be combined with other circuit devices. For example, an Insulated Gate Bipolar Transistor (IGBT) is a semiconductor device that includes both a MOSFET and a Bipolar Junction Transistor (BJT), where the BJT combines the high impedance gate electrode of a MOSFET with the small on-state conduction losses that a BJT can provide. An IGBT can be implemented, for example, as a Darlington pair that includes a high voltage n-channel MOSFET at the input and a BJT at the output. The base current of the BJT is supplied through the channel of the MOSFET, thereby allowing for a simplified external drive circuit (since the drive circuit only charges and discharges the gate electrode of the MOSFET).

[0006] In some applications, MOSFETs may need to carry large currents in their on-state and / or be capable of blocking high voltages (e.g., several thousand volts) in their reverse blocking state. Such MOSFETs are often referred to as "power" MOSFETs. Power MOSFETs and power IGBTs are often fabricated from wide bandgap semiconductor materials, such as silicon carbide ("SiC") or gallium nitride ("GaN") based semiconductor materials. As used herein, wide bandgap semiconductor materials refer to semiconductor materials having a bandgap greater than 1.40 eV.

[0007] A conventional power semiconductor device typically has a semiconductor substrate, such as a silicon carbide substrate having a first conductivity type (e.g., an n-type substrate), on which an epitaxial layer structure having a first conductivity type (e.g., n-type) is formed. A portion of the epitaxial layer structure (which may comprise one or more separate layers) serves as a drift region of the power semiconductor device. The power semiconductor device typically includes an active region, which may be formed on and / or within the drift region. The active region serves as a primary junction to block voltage in a reverse bias direction and provide current in a forward bias direction. One or more power semiconductor devices may be formed on the substrate. After the substrate is fully processed, the resulting structure may be diced to separate the individual power semiconductor devices. The power semiconductor devices may have a unit cell structure, in which the active region of each power semiconductor device includes a plurality of individual "unit cell" devices that are arranged parallel to one another and function together as a single power semiconductor device.

[0008] A power semiconductor device may have a lateral or vertical structure. In a device having a lateral structure, the terminals of the device (e.g., the drain, gate, and source terminals for a power MOSFET device) are on the same major (i.e., top or bottom) surface of a semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate. As used herein, the term "semiconductor layer structure" refers to a structure that includes one or more semiconductor layers, such as a semiconductor substrate and / or a semiconductor epitaxial layer.

[0009] Vertical power semiconductor devices including MOSFET transistors can have a standard gate electrode design, in which the gate electrode of the transistor is formed on top of a semiconductor layer structure, or alternatively, can have the gate electrode embedded in a trench in the semiconductor layer structure. A gate electrode embedded in a trench is typically referred to as a trenched gate, and MOSFETs including trenched gates are often referred to as U-Shaped MOSFETs (UMOSFETs). UMOSFETs include a vertically disposed channel and provide enhanced performance.

[0010] One failure mechanism for power UMOSFETs is the so-called "breakdown" of the gate oxide layer. When power UMOSFETs are in their conducting or "on" state, all portions of the gate oxide layer are subjected to high electric fields. Similarly, when power UMOSFETs are in their reverse blocking or "off" state, the lower portions of the gate oxide layer are similarly subjected to high electric fields. The stresses on the gate oxide layer caused by these high electric fields create defects in the oxide material, which accumulate over time. When the concentration of defects reaches a critical value, a so-called "percolation path" may be created through the gate oxide layer, which electrically connects the gate electrode to the semiconductor layer structure, thereby creating a short circuit that can destroy the device. The "lifetime" of the gate oxide layer (i.e., how long the device can operate before breakdown occurs) is a function of, among other things, the magnitude of the electric field to which the gate oxide layer is subjected and the length of time the field is applied. FIG. 1 is a schematic graph showing the relationship between the time of operation until breakdown occurs ("gate oxide lifetime") and the level of the electric field applied to the gate oxide layer. The graph assumes that the same electric field is always applied (not necessarily), and also assumes a gate oxide layer having a particular thickness. As shown in FIG. 1, the relationship can in some cases be generally linear when the gate oxide lifetime is plotted on a logarithmic scale. The key point to draw from FIG. 1 is that as the electric field level increases, the lifetime of the gate oxide layer decreases exponentially. The lifetime of the gate oxide layer can be increased by increasing the thickness of the gate oxide layer, but the performance of the MOSFET is also a function of the thickness of the gate oxide layer, and therefore increasing the thickness of the gate oxide layer is typically not an acceptable way to increase the lifetime of the gate oxide layer. Summary of the Invention [Means for solving the problem]

[0011] According to an embodiment of the present invention, there is provided a semiconductor device including a semiconductor layer structure having a trench in an upper surface thereof, the trench having rounded upper corners and rounded lower corners, a dielectric layer in a lower portion of the trench, where a central portion of the upper surface of the dielectric layer is curved and the dielectric layer is on opposing sidewalls of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure.

[0012] In some embodiments, the dielectric layer can comprise a lower dielectric layer on a lower surface of the trench and on a lower portion of the sidewalls of the trench, and a gate dielectric layer on an upper portion of the sidewalls of the trench and on the lower dielectric layer, where a central portion of the curved upper surface of the dielectric layer can be a central portion of the upper surface of the gate dielectric layer.

[0013] In some embodiments, the central portion of the curved top surface of the gate dielectric layer can have a radius of curvature between 0.25 times the lesser of the trench width and depth and 3 times the greater of the trench width and depth.

[0014] According to an embodiment of the present invention, there is provided a semiconductor device comprising: a semiconductor layer structure comprising a trench in an upper surface thereof, the trench comprising rounded top corners and rounded bottom corners; a lower dielectric layer in a lower portion of the trench; a gate dielectric layer on sidewalls of the trench and on the lower dielectric layer; and a gate electrode in the trench and on the gate dielectric layer facing the semiconductor layer structure, wherein the lower dielectric layer comprises a first concentration of an additive and the gate dielectric layer has a second concentration of the additive that is less than the first concentration.

[0015] According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor layer structure having a trench in an upper surface thereof, the trench having rounded upper corners and rounded lower corners; a lower dielectric layer in a lower portion of the trench; a gate dielectric layer on sidewalls of the trench and on the lower dielectric layer, the gate dielectric layer comprising a different material than the lower dielectric layer; and a gate electrode in the trench and on the gate dielectric layer facing the semiconductor layer structure.

[0016] According to an embodiment of the present invention, there is provided a semiconductor device including a semiconductor layer structure having a trench in an upper surface thereof, the trench having rounded upper corners and rounded lower corners, a lower dielectric layer in a lower portion of the trench, a gate dielectric layer on sidewalls of the trench and on the lower dielectric layer, a barrier layer between the lower dielectric layer and the gate dielectric layer, and a gate electrode in the trench and on the gate dielectric layer facing the semiconductor layer structure.

[0017] In some embodiments, the central portion of the lower surface of the gate dielectric layer can be curved and can have a radius of curvature between 0.25 times the smaller of the trench width and depth and 3 times the larger of the trench width and depth, or between 0.5 times the smaller of the trench width / depth and 2 times the larger of the trench width / depth, or between 0.75 times the smaller of the trench width / depth and 1.5 times the larger of the trench width / depth in any semiconductor device. The central portion of the lower surface of the gate dielectric layer refers to the portion of the lower surface of the gate dielectric layer that extends in the width direction of the trench from the center of the trench halfway to each of the trench sidewalls.

[0018] In some embodiments, the gate dielectric layer of any of the semiconductor devices may comprise a different material than the underlying dielectric layer.

[0019] In some embodiments, the lower dielectric layer of any semiconductor device of the semiconductor device may comprise a spin-on glass layer.

[0020] In some embodiments, the lower dielectric layer of any of the semiconductor devices can include an additive including boron (B), phosphorous (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and / or lead (Pb).

[0021] In some embodiments, the gate dielectric layer of any of the semiconductor devices may include the lower dielectric layer additive.

[0022] In some embodiments, the gate dielectric layer of any of the semiconductor devices may include an impurity different from the impurity of the underlying dielectric layer.

[0023] In some embodiments, any one of the semiconductor devices may further comprise a barrier layer between the lower dielectric layer and the gate dielectric layer.

[0024] In some embodiments, a semiconductor layer structure of any of the semiconductor devices may include a drift layer having a first conductivity type, a well having a second conductivity type in an upper portion of the drift layer, and a source region having the first conductivity type in an upper portion of the well, and a top edge of the barrier layer may be closer to a lower surface of the trench than to a lower surface of the well.

[0025] In some embodiments, the barrier layer of any of the semiconductor devices may comprise a silicon nitride layer and / or a silicon oxide layer.

[0026] In some embodiments, a gate dielectric layer of any of the semiconductor devices may comprise a first portion on the lower dielectric layer and a second portion on the sidewalls of the trench, the central portion of the lower dielectric layer may have a first thickness in a depth direction of the trench, the first portion of the gate dielectric layer may have a second thickness in a depth direction of the trench, and the second portion of the gate dielectric layer may have a third thickness in a width direction of the trench, and the sum of the first thickness and the second thickness may be greater than the third thickness.

[0027] In some embodiments, the first thickness can be in the range of 2 nanometers to 90 nanometers.

[0028] In some embodiments, the third thickness can be in the range of 10 nanometers to 90 nanometers.

[0029] In some embodiments, the depth of the trench may be at least 1.5 times the sum of the first thickness and the second thickness.

[0030] In some embodiments, the sum of the first thickness and the second thickness is greater than the third thickness.

[0031] In some embodiments, the second thickness can be within 10% of the third thickness.

[0032] In some embodiments, the sum of the first thickness and the second thickness can be greater than the third thickness.

[0033] In some embodiments, the lower dielectric layer in any of the semiconductor devices may be a reflowed dielectric layer.

[0034] In some embodiments, the lower dielectric layer in any of the semiconductor devices may be a spin-on glass material.

[0035] In some embodiments, a semiconductor layer structure of any of the semiconductor devices may include 4H-silicon carbide and a top surface of the semiconductor layer structure may comprise a (0001) plane of 4H-silicon carbide.

[0036] In some embodiments, the semiconductor layer structure of any of the semiconductor devices may include silicon carbide or silicon, and the dielectric layer of any of the semiconductor devices may include silicon oxide.

[0037] In some embodiments, the dielectric layer of any semiconductor device of the semiconductor device may be a reflowed dielectric layer, and the reflowed dielectric layer may include a portion on a sidewall of a trench, the thickness of the portion of the reflowed dielectric layer increasing with the depth of the trench.

[0038] In some embodiments, the dielectric layer of any of the semiconductor devices can include additives including boron (B), phosphorous (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and / or lead (Pb).

[0039] In some embodiments, a central portion of the bottom surface of the trench may be curved in any of the semiconductor devices.

[0040] In some embodiments, each of the rounded top corners and the rounded bottom corners may have a radius of curvature within a range of 0.01 microns to 0.5 microns in any one of the semiconductor devices.

[0041] In some embodiments, in any one of the semiconductor devices, the opening of the trench can have a first width and a bottom surface of the trench can have a second width that is narrower than the first width.

[0042] In some embodiments, a semiconductor layer structure of any of the semiconductor devices may include a drift layer having a first conductivity type, a well having a second conductivity type in an upper portion of the drift layer, and a source region having the first conductivity type in an upper portion of the well, a trench may extend through the well, and the drift layer may define a lower surface of the trench.

[0043] In some embodiments, the semiconductor layer structure of any one of the semiconductor devices may further comprise a shield region having a second conductivity type and located within the drift layer.

[0044] In some embodiments, the semiconductor layer structure of any of the semiconductor devices may further comprise a source contact electrically connected to the source region and spaced apart from the trench.

[0045] In some embodiments, any of the semiconductor devices may be a metal-insulator-semiconductor field effect transistor ("MISFET") or an insulated gate bipolar transistor ("IGBT").

[0046] According to an embodiment of the present invention, there is provided a method of forming a semiconductor device, the method comprising: The method may include forming a trench in a semiconductor substrate, forming a lower dielectric layer in the trench, including forming and annealing a preliminary lower dielectric layer, and a preliminary lower dielectric layer reflow process during annealing, and forming a gate electrode in the trench on the lower dielectric layer.

[0047] According to an embodiment of the present invention, there is provided a method of forming a semiconductor device, the method including forming a trench in a semiconductor substrate, forming a lower dielectric layer in the trench, which may include forming and annealing a preliminary lower dielectric layer, which may be annealed at a temperature at least about a glass transition temperature of the preliminary lower dielectric layer, and forming a gate electrode in the trench on the lower dielectric layer.

[0048] According to an embodiment of the present invention, there is provided a method of forming a semiconductor device, the method including forming a trench in a semiconductor substrate, forming a lower dielectric layer in the trench, where the lower dielectric layer may comprise boron (B), phosphorus (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and / or lead (Pb), forming a gate dielectric layer on the lower dielectric layer, where the gate dielectric layer contacts an upper portion of a sidewall of the trench and may comprise a first material different from the lower dielectric layer, and thereafter forming a gate electrode in the trench on the lower dielectric layer.

[0049] According to an embodiment of the present invention, there is provided a method of forming a semiconductor device, the method including forming a trench in a semiconductor substrate, forming a lower dielectric layer in the trench, which may include forming a spin-on glass layer, and then performing an oxidation process, forming a gate dielectric layer on the lower dielectric layer, which may include a first material different from the lower dielectric layer, and then forming a gate electrode in the trench on the lower dielectric layer.

[0050] In some embodiments, annealing the preliminary lower dielectric layer may be performed at a temperature at least about the glass transition temperature of the preliminary lower dielectric layer in any of the methods.

[0051] In some embodiments, the preliminary lower dielectric layer of any of the methods may be formed and annealed simultaneously.

[0052] In some embodiments, forming and annealing the preliminary lower dielectric layer may include oxidizing the semiconductor substrate in any of the methods.

[0053] In some embodiments, oxidizing the semiconductor substrate can include performing thermal oxidation using O2, O3, and / or NO as an oxidizing agent or performing plasma oxidation using NO as an oxidizing agent in any of the methods.

[0054] In some embodiments, oxidizing the semiconductor substrate may be performed in any of the methods in an environment including a network modifier, the network modifier including boron (B), phosphorus (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and / or lead (Pb).

[0055] In some embodiments, the preliminary lower dielectric layer of any of the methods may include a network modifier.

[0056] In some embodiments, the preliminary lower dielectric layer of any of the methods may include a network modifier in an amount of less than 4% by weight of the preliminary lower dielectric layer.

[0057] In some embodiments, in any of the methods, forming the preliminary lower dielectric layer can include forming a spin-on glass layer, and annealing the preliminary lower dielectric layer can be performed after forming the spin-on glass layer.

[0058] In some embodiments, the spin-on glass layer of any of the methods can include boron (B), phosphorous (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and / or lead (Pb).

[0059] In some embodiments, the spin-on glass layer of any of the methods may comprise an undoped silicon oxide layer.

[0060] In some embodiments, forming the preliminary lower dielectric layer can include depositing the preliminary lower dielectric layer in any of the methods.

[0061] In some embodiments, any of the methods may further include planarizing the preliminary lower dielectric layer after depositing the preliminary lower dielectric layer and prior to annealing the preliminary lower dielectric layer.

[0062] In some embodiments, any of the methods may further include forming a barrier layer on the lower dielectric layer prior to forming the gate electrode, and the barrier layer may comprise a first material different from the lower dielectric layer.

[0063] In some embodiments, the barrier layer of any of the methods may comprise a silicon nitride layer and / or a silicon oxide layer.

[0064] In some embodiments, the gate electrode of any of the methods can contact the upper surface of the barrier layer.

[0065] In some embodiments, any of the methods may further include forming a gate dielectric layer on the barrier layer prior to forming the gate electrode, the gate dielectric layer may comprise a second material different from the barrier layer.

[0066] In some embodiments, any of the methods may further include a gate dielectric layer on the lower dielectric layer prior to forming the gate electrode, and the gate dielectric layer may comprise a different material than the lower dielectric layer.

[0067] In some embodiments, the gate electrode of any of the methods may contact the upper surface of the lower dielectric layer.

[0068] In some embodiments, any of the methods may further include forming a semiconductor layer structure in the semiconductor substrate, the semiconductor layer structure may include a drift layer having a first conductivity type, a well having a second conductivity type in an upper portion of the drift layer, and a source region having the first conductivity type in an upper portion of the well.

[0069] In some embodiments, any of the methods can further include forming a source trench, which can be in the semiconductor layer structure and spaced from the trench, and forming a source contact in the source trench.

[0070] In some embodiments, any of the methods can further include forming a first shield region in the drift layer below the source trench.

[0071] In some embodiments, any of the methods may further include forming a thin dielectric layer in the trench and, after forming the thin dielectric layer, forming a shield region in the drift layer below the trench by implanting an impurity element into a portion of the drift layer, and the lower dielectric layer may be formed after the shield region is formed.

[0072] In some embodiments, forming the thin dielectric layer may include oxidizing the semiconductor substrate or forming a spin-on glass layer in any of the methods.

[0073] In some embodiments, the preliminary lower dielectric layer of any of the methods may include silicon oxide, and annealing the preliminary lower dielectric layer may be performed at a temperature of at least about 1300° C. in any of the methods.

[0074] In some embodiments, the semiconductor substrate of any of the methods may include silicon carbide.

[0075] In some embodiments, the semiconductor layer structure of any of the methods may include 4H-silicon carbide and an upper surface of the semiconductor layer structure may comprise a (0001) plane of the 4H-silicon carbide.

[0076] In some embodiments, forming the lower dielectric layer can further include, in any of the methods, etching an upper portion of the preliminary lower dielectric layer until an upper surface of the semiconductor substrate is exposed.

[0077] In some embodiments, forming the lower dielectric layer may further include planarizing the preliminary lower dielectric layer in any of the methods. [Brief description of the drawings]

[0078] [Figure 1] 1 is a graph illustrating the relationship between the lifetime of a gate dielectric layer and the applied electric field strength. [Diagram 2] FIG. 1 is a schematic cross-sectional view of a related art power UMOSFET. [Diagram 3] FIG. 1 is a schematic cross-sectional view of a power UMOSFET according to an embodiment of the present invention. [Figure 3A] FIG. 3 is an enlarged view of region B in FIG. [Figure 3B] FIG. 3 is an enlarged view of region C in FIG. [Figure 4] FIG. 1 is a schematic cross-sectional view of a power UMOSFET according to an embodiment of the present invention. [Diagram 5] FIG. 1 is a schematic cross-sectional view of a power UMOSFET according to an embodiment of the present invention. [Figure 6]FIG. 1 is a schematic cross-sectional view of a power UMOSFET according to an embodiment of the present invention. [Figure 7] FIG. 1 is a schematic cross-sectional view of a power UMOSFET according to an embodiment of the present invention. [Figure 8] FIG. 1 is a schematic cross-sectional view of a power UMOSFET according to an embodiment of the present invention. [Figure 9] FIG. 1 is a schematic cross-sectional view of a power UMOSFET according to an embodiment of the present invention. [Figure 10] FIG. 1 is a schematic cross-sectional view of a power UMOSFET according to an embodiment of the present invention. [Figure 11] 2 is a flow chart illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 12] 2 is a flow chart illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 13] 2 is a flow chart illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 14] 2 is a flow chart illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 15] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 16] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 17] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 18] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 19] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 20] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 21] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 22] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Diagram 23] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 24] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Diagram 25] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 26] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 27] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. [Figure 28] 1A to 1C are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0079] According to embodiments of the present invention, a power UMOSFET is provided that includes a gate dielectric layer having an increased lifetime. The lifetime of the gate dielectric layer may be increased, for example, by reducing the strength of the electric field applied to the gate dielectric layer during reverse blocking operation. In some embodiments, the electric field strength applied to the gate dielectric layer may be reduced by rounding corners of the gate trench and / or adding a lower dielectric layer in a lower portion of the gate trench. In some embodiments, the gate dielectric layer and the lower dielectric layer may comprise different materials. In some embodiments, the lower dielectric layer may include additives (e.g., network modifiers) and the gate dielectric layer may be substantially free of these additives. In some embodiments, the gate dielectric layer may include additives of the lower dielectric layer that have diffused from the lower dielectric layer. In such embodiments, the additive concentration of the gate dielectric layer may be lower than the additive concentration of the lower dielectric layer. In some embodiments, the gate dielectric layer may include an impurity different from the additive of the lower dielectric layer. The gate dielectric layer and the lower dielectric layer may be collectively referred to as a dielectric layer, and a central portion of the top surface of the dielectric layer may be curved.

[0080] FIG. 2 is a schematic cross-sectional view of a conventional power UMOSFET 100. As shown in FIG. 2, the power UMOSFET 100 includes an n-type semiconductor substrate 110. The semiconductor substrate 110 may comprise, for example, a monocrystalline 4H silicon carbide semiconductor substrate that is heavily doped with n-type impurities (i.e., an n+ silicon carbide substrate). A lightly doped n-type (n-) silicon carbide drift layer 120 is provided on the substrate 110. An upper portion of the n-type silicon carbide drift layer 120 may be doped p-type, for example, by ion implantation, to form a silicon carbide p-well 130. A heavily doped (n+) n-type silicon carbide region 150 may be formed in the upper portion of the silicon carbide p-well 130. The n-type silicon carbide region 150 may be formed by ion implantation. The heavily doped (n+) n-type silicon carbide region 150 serves as a source region for the device 100. The drift layer 120 and the substrate 110 together act as a common drain region for the device 100. The n-type substrate 110, the n-type drift layer 120, the p-well 130, and the n-type source region 150 formed within the device 100 together may comprise a semiconductor layer structure 140 of the device 100.

[0081] A trench 122 is provided in the drift layer 120. A lower surface of the trench 122 extends into the drift layer 120 below a lower surface of the well 130. A gate dielectric layer 160 is provided on the lower surface and sidewalls of the trench 122 and on the source region 150. The gate dielectric layer 160 may include, for example, a silicon oxide (SiO2) layer. A p-type shield region 124 may be formed in the drift layer 120 below the gate trench 122. The shield region 124 may help protect a lower corner of the final gate dielectric layer 160 from high electric fields during reverse blocking operation.

[0082] A gate electrode 170 is formed in the trench 122 on the gate dielectric layer 160 opposite the semiconductor layer structure 140. The gate electrode 170 can include, for example, a silicide (e.g., NiSi, TiSi, WSi, CoSi), doped polycrystalline silicon (polySi), and / or a stable conductor. Other suitable materials for the gate electrode 170 include various metals, such as Ti, Ta, or W, or metal nitrides, such as TiN, TaN, or WN. A channel region 131 is provided in the p-well 130 adjacent to the sidewall of the trench 122 between the source region 150 and the drift layer 120.

[0083] A dielectric insulating pattern 180 is formed on the gate dielectric layer 160 and the gate electrode 170, and a source metallization 190 is formed on the semiconductor layer structure 140, the gate dielectric layer 160, and the dielectric insulating pattern 180. A drain contact (not shown) may be provided on the lower surface of the substrate 110 opposite the drift layer 120.

[0084] It will be appreciated that the above description is for n-type MOSFETs. In p-type devices, the locations of the source and drain contacts may be reversed and the conductivity types of the other n-type and p-type regions may be swapped. All of the embodiments disclosed herein may be implemented as n-type or p-type devices.

[0085] As discussed above, when the UMOSFET 100 is in its conductive or on-state, the gate dielectric layer 160 is subjected to a high electric field. The strength of this electric field may be particularly high at the portion of the gate dielectric layer 160 that contacts the top corner A of the trench 122 because the top corner A of the trench 122 is sharp. Thus, the portion of the gate dielectric layer 160 that contacts the top corner A of the trench 122 will typically be the first to experience dielectric breakdown.

[0086] Furthermore, when the UMOSFET 100 is in the blocking state, leakage current may flow through the device 100 because the gate electrode 170 is electrically isolated from the n-type silicon carbide drift layer 120 only by the thin gate dielectric layer 160.

[0087] According to an embodiment of the present invention, a power semiconductor device is provided that includes a gate trench having rounded top and / or bottom corners. When the gate oxide layer has sharp corner regions, the electric field crowding effect tends to significantly increase the magnitude of the electric field in the gate dielectric layer at these corner regions. For example, the electric field value at the sharp corner regions of the gate dielectric layer may be 5 times greater than the electric field value just outside the corner regions. The rounded corners of the gate trench will reduce the electric field in the portions of the gate dielectric layer that contact these rounded corners during both the on-state (mainly for the top corners) and off-state (mainly for the bottom corners) of operation. Therefore, by rounding the corners of the gate trench, the lifetime of the gate dielectric layer may be increased. Furthermore, according to an embodiment of the present invention, a power semiconductor device is provided that includes a thick bottom dielectric layer at a lower portion of the gate trench. The thick bottom dielectric layer will reduce the electric field in the device in the blocking state, and the leakage current of the device in the blocking state will be reduced.

[0088] 3 is a schematic cross-sectional view of a power UMOSFET 200-1 according to an embodiment of the present invention. The power UMOSFET 200-1 includes a semiconductor layer structure 240 including a heavily doped n-type silicon carbide semiconductor substrate 210, a lightly doped n-type (n-) silicon carbide drift layer 220, a silicon carbide p-type well 230, and a heavily doped (n+) n-type silicon carbide source region 250. A trench 222 is provided in the drift layer 220. A lower surface of the trench 222 can extend into the drift layer 220 below a lower surface of the p-type well 230. An opening of the trench 222 has a width greater than the width of the lower surface of the trench 222. A p-type shield region 224 can be formed in the drift layer 220 below the trench 222. The shielding regions 224 can help protect the bottom corners of the final gate dielectric layer 160 (discussed below) from high electric fields during reverse blocking operation. Although the discussion herein will focus on silicon carbide semiconductor substrates, it will be recognized that the techniques according to embodiments of the invention described herein are similarly applicable to devices including silicon semiconductor substrates or any other substrate.

[0089] A gate dielectric layer 260 is provided on the sidewalls of trench 222 and on source region 250. A gate electrode 270 is formed in trench 222 on the gate dielectric layer 260 opposite semiconductor layer structure 240. A dielectric insulation pattern 280 is formed on the gate dielectric layer 260 and gate electrode 270, and a source metallization 290 is formed on the semiconductor layer structure 240, the gate dielectric layer 260, and the dielectric insulation pattern 280. A drain contact (not shown) may be provided on a lower surface of substrate 210 opposite drift layer 220.

[0090] The regions / layers of UMOSFET 200-1 of FIG. 3 may be substantially identical to the corresponding regions / layers of UMOSFET 100 of FIG. 2 with two exceptions. First, trench 222 includes rounded upper corners. In some embodiments, the lower corners of trench 222 may also have rounded corners. Second, a lower dielectric layer 232 may be provided in a lower portion of the trench between gate dielectric layer 260 and a lower surface of trench 222.

[0091] FIG. 3A is an enlarged view of region B of FIG. 3. As shown in FIG. 3A, the top corner of trench 222 may be defined by source region 250 and may be a rounded corner. For example, the rounded top corner of trench 222 may have a first radius of curvature r1 in a range of 0.01 microns to 0.5 microns. The bottom corner of trench 222 may be defined by drift layer 220 and may be a rounded corner. For example, the rounded bottom corner of trench 222 may have a second radius of curvature r2 in a range of 0.01 microns to 0.5 microns. In some embodiments, either or both of first radius of curvature r1 and / or second radius of curvature r2 may be in a range of 0.05 microns to 0.4 microns, in a range of 0.1 microns to 0.45 microns, in a range of 0.2 microns to 0.4 microns, or in a range of 0.25 microns to 0.4 microns. In other embodiments, either or both of the first radius of curvature r1 and / or the second radius of curvature r2 can be in the range of 0.01 microns to 0.1 microns, in the range of 0.1 microns to 0.2 microns, in the range of 0.2 microns to 0.3 microns, in the range of 0.3 microns to 0.4 microns, or in the range of 0.4 microns to 0.6 microns.

[0092] The rounded top corners of trench 222 can reduce the magnitude of the electric field applied to the portions of dielectric layer 260 that contact the rounded top corners, resulting in increased lifetime of the gate dielectric layer.

[0093] The lower dielectric layer 232 may include a different material than the gate dielectric layer 260. The lower dielectric layer 232 may include an insulating material such as silicon oxide or a spin-on glass layer in some embodiments and may further include additives (e.g., network modifiers) such as boron (B), phosphorus (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and / or lead (Pb). The gate dielectric layer 260 may be additive-free or may have a low concentration of additive diffused from the lower dielectric layer 232. The lower dielectric layer 232 may include a first additive concentration and the gate dielectric layer 260 may have a second additive concentration lower than the first additive concentration. In some embodiments, the lower dielectric layer 232 may be a reflowed dielectric layer formed by a reflow process and the gate dielectric layer 260 may be formed by an oxidation process or a deposition process. The reflowed dielectric layer of the lower dielectric layer 232 may include an additive that lowers the glass transition temperature of the lower dielectric layer 232, such that the lower dielectric layer 232 with the additive will reflow at a lower temperature than the lower dielectric layer 232 without the additive. In some embodiments, the gate dielectric layer 260 may include impurities, which may be different chemical elements than the additive of the lower dielectric layer 232. The impurities of the gate dielectric layer 260 may be unintentionally included in the gate dielectric layer 260 during the fabrication process and may be, for example, carbon (C) and / or nitrogen (N). It will be appreciated that the impurity concentration of the gate dielectric layer 260 may be low enough not to affect the performance of the UMOSFET.

[0094] As shown in FIG. 3, a central portion of the top surface of the lower dielectric layer 232 is curved. The gate dielectric layer 260 may be conformally disposed on the lower dielectric layer 232, the sidewalls of the trench 222, and the top surface of the source region 250. The portion of the gate dielectric layer 260 on the central portion of the top surface of the lower dielectric layer 232 may have curved upper and lower surfaces, and the portion of the gate dielectric layer 260 on the upper corners of the trench 222 may have similarly curved surfaces. Each of the gate dielectric layer 260 and the lower dielectric layer 232 may include a dielectric layer, and thus the gate dielectric layer 260 and the lower dielectric layer 232 may be collectively referred to as a dielectric layer. As shown in FIG. 3, the dielectric layer may be in the lower portion of the trench 222, the central portion of the top surface of the dielectric layer may be curved, and the dielectric layer may be on the opposing sidewalls of the trench 222.

[0095] 3B is an expanded view of region C of FIG. 3. As shown in FIG. 3B, the central portion of the lower dielectric layer 232 has a first thickness T1 along the depth of the trench 222, and the gate dielectric layer 260 includes a first portion on the lower dielectric layer 232 and having a second thickness T2 along the depth of the trench 222, and a second portion on the sidewalls of the trench 222 and having a third thickness T3 along the width of the trench 222. In some embodiments, the sum of the first thickness T1 and the second thickness T2 can be greater than the third thickness T3. In such embodiments, the dielectric material within the trench 222 (i.e., the combination of the lower dielectric layer 232 and the gate dielectric layer 260) can extend upward from a lower surface of the trench 222 compared to extending outward from an upper sidewall of the trench 222.

[0096] For example, the first thickness T1 can be in a range of 2 nanometers to 90 nanometers, the second thickness T2 can be in a range of 5 nanometers to 90 nanometers, and the third thickness T3 can be in a range of 10 nanometers to 90 nanometers. The depth D of the trench 222 can be at least 1.5 times the sum of the first thickness T1 and the second thickness T2. In some embodiments, the second thickness T2 can be within 10% of the third thickness T3. For example, the second thickness T2 can be the same as or approximately the same as the third thickness T3. The first thickness T1 can be greater than, equal to, or less than the second thickness T2. In some embodiments, the sum of the first thickness T1 and the second thickness T2 can be greater than the third thickness T3.

[0097] 3 and 3B, in some embodiments, the upper surface of the lower dielectric layer 232 having a curved surface may have a radius of curvature that is between 0.25 times the smaller of the width W and depth D of the trench 222 and 3 times the larger of the width / depth of the trench 222. In other embodiments, the curvature may be between 0.5 times the smaller of the width / depth of the trench 222 and 2 times the larger of the width / depth of the trench 222, or between 0.75 times the smaller of the width / depth of the trench 222 and 1.5 times the larger of the width / depth of the trench 222. It will be appreciated that the curvature of the curved surface of the lower dielectric layer 232 may not necessarily be constant, and only a portion of the central portion of the upper surface of the lower dielectric layer 232 may have the specified curvature. Furthermore, because trench 222 typically has a uniform depth and width along its length, the upper surface of lower dielectric layer 232 comprises a surface rather than a line, but each cross-section of trench 222 may be substantially the same along the length of trench 222. The central portion of the lower surface of lower dielectric layer 232 refers to the portion of the lower surface of lower dielectric layer 232 that extends across the width of trench 222 from the center of the trench halfway to each of the sidewalls of trench 222 (i.e., the central 50% portion of trench 222).

[0098] The gate dielectric layer 260 may be conformally disposed on the lower dielectric layer 232, the sidewalls of the trench 222, and the upper surface of the source region 250. The portion of the gate dielectric layer 260 on the central portion of the upper surface of the lower dielectric layer 232 may have a uniform thickness and may have curved upper and lower surfaces, each having a radius of curvature that is the same as the radius of curvature of the curved surface of the lower dielectric layer 232. In some illustrative embodiments, the curved lower surface of the gate dielectric layer 260 may have a radius of curvature that is between 0.25 times the smaller of the width / depth of the trench 222 and 3 times the larger of the width / depth of the trench 222. In other embodiments, the curvature of the gate dielectric layer 260 may be between 0.5 times the smaller of the width / depth of the trench 222 and 2 times the larger of the width / depth of the trench 222, or between 0.75 times the smaller of the width / depth of the trench 222 and 1.5 times the larger of the width / depth of the trench 222. The central portion of the lower surface of the gate dielectric layer 260 refers to the portion of the lower surface of the gate dielectric layer 260 that extends in the width direction of the trench 222 from the center of the trench 222 halfway to each of the sidewalls of the trench 222 (i.e., the central 50% portion of the trench 222).

[0099] 4 is a schematic cross-sectional view of a power UMOSFET 200-2 according to an embodiment of the present invention. The UMOSFET 200-2 can be substantially identical to the power UMOSFET 200-1 of FIG. 3, except for the shape of the lower dielectric layer 232'. In some embodiments, the lower dielectric layer 232' can have a flat upper surface, as shown in FIG.

[0100] 5 is a schematic cross-sectional view of a power UMOSFET 200-3 according to an embodiment of the present invention. The UMOSFET 200-3 may be substantially identical to the power UMOSFET 200-1 of FIG. 3, except for the shape of the lower surface of the trench 222'. A central portion of the lower surface of the trench 222' may be curved, as shown in FIG.

[0101] FIG. 6 is a schematic cross-sectional view of a power UMOSFET 200-4 according to an embodiment of the present invention. The UMOSFET 200-4 may be substantially identical to the power UMOSFET 200-1 of FIG. 3, except for an additional barrier layer 234 provided between the lower dielectric layer 232 and the gate dielectric layer 260. The barrier layer 234 may prevent the diffusion of elements (e.g., impurities and / or additives) contained in the lower dielectric layer 232 to surrounding regions / layers (e.g., into the gate dielectric layer 260 and / or into the gate electrode 270). The barrier layer 234 may include a different material than the lower dielectric layer 232. For example, the barrier layer 234 may include a silicon nitride layer and / or a silicon oxide layer. In some embodiments, the barrier layer 234 may be free of or may be free of the impurities and / or additives contained in the lower dielectric layer 232.

[0102] The barrier layer 234 may be conformally disposed on the lower dielectric layer 232, and a central portion of the barrier layer 234 may be curved, as shown in Figure 6. In some embodiments, a top edge of the barrier layer 232 may be closer to a lower surface of the trench 222 than to a lower surface of the portions of the p-well 232 that form portions of the respective sidewalls of the trench 222. Thus, only the gate dielectric layer 260 may be interposed between the channel (e.g., channel 231 in Figure 3) and the gate electrode 270.

[0103] FIG. 7 is a schematic cross-sectional view of a power UMOSFET 200-5 according to an embodiment of the present invention. The UMOSFET 200-5 may be substantially identical to the power UMOSFET 200-1 of FIG. 3, except that the power UMOSFET 200-5 does not include a separate gate dielectric layer (e.g., gate dielectric layer 260). In the power UMOSFET 200-5, the lower dielectric layer 232'' may function as the gate dielectric layer. The lower dielectric layer 232'' may be a reflowed dielectric layer. The lower dielectric layer 232'' may have a first thickness on a lower surface of the trench 222 and a second thickness on the sidewalls of the trench 222, the first thickness being greater than the second thickness. The lower dielectric layer 232'' includes portions on the sidewalls of the trench 222, and the thickness of these portions of the lower dielectric layer 232'' may increase with the depth of the trench 222, as shown in FIG. 6.

[0104] 8 is a schematic cross-sectional view of a power UMOSFET 200-6 according to an embodiment of the present invention. The UMOSFET 200-6 may be substantially identical to the power UMOSFET 200-5 of FIG. 7, except that an additional barrier layer 234' is provided between the lower dielectric layer 232'' and the gate electrode 270. As shown in FIG. 8, the barrier layer 234' may be in direct contact with both the lower dielectric layer 232'' and the gate electrode 270.

[0105] 9 is a schematic cross-sectional view of a power UMOSFET 200-7 according to an embodiment of the present invention. The UMOSFET 200-7 may be substantially identical to the power UMOSFET 200-1 of FIG. 3, except that the p-shield region 224 is formed in the drift layer 220 under the p-well 230, as opposed to being formed under the gate trench 222. It will be appreciated that the p-shield region 224 may be formed under the gate trench 222, under the p-well 230, or under both, in each of the embodiments of the present invention disclosed herein.

[0106] 10 is a schematic cross-sectional view of a power UMOSFET 300 according to an embodiment of the present invention. The power UMOSFET 300 includes a semiconductor layer structure 340 including a heavily doped n-type silicon carbide semiconductor substrate 310, a lightly doped n-type (n-) silicon carbide drift layer 320, a silicon carbide p-type well 330, and a heavily doped (n+) n-type silicon carbide source region 350. A trench 322 is provided in the drift layer 320. A lower dielectric layer 332 may be provided in a lower portion of the trench 322, and a gate dielectric layer 360 may be provided on an upper surface of the lower dielectric layer 332, a sidewall of the trench 322, and the source region 350. A gate electrode 370 is formed in the trench 322 on the gate dielectric layer 360 facing the lower dielectric layer 332. A dielectric insulating pattern 380 is formed on the gate dielectric layer 360 and the gate electrode 370. The top corners of the trench 322 may be rounded corners, so that the magnitude of the electric field in the portion of the gate dielectric layer 360 that contacts the top corners of the trench 322 may be reduced and the lifetime of the gate dielectric layer 360 may be increased.

[0107] The regions / layers of the power UMOSFET 300 may be substantially identical to the corresponding regions / layers of the UMOSFET 200-1 of FIG. 3, except for the additional source trenches 324 and source metallization 390, portions of which are provided in the respective source trenches 324 to form source contacts. The source trenches 324 may extend through the source region 350 and the silicon carbide p-well 330, and the lower surface of the source trenches 324 may be in the drift layer 320. An interlayer insulating layer 385 may be provided between the dielectric insulating pattern 380 and the source metallization 390. Deep shield regions 325 may be formed under each of the source trenches. The deep shield regions 325 are electrically connected to the p-well 330, so that they act as a shield to facilitate protecting the gate dielectric layer 360 during reverse blocking operation. In the illustrated embodiment, these electrical connections are made outside the cross-section of the figure. It will be appreciated, however, that deep shield region 325 may alternatively be connected to p-type well 330 by a deep shield connection pattern visible in the cross section of Figure 10. For example, one or both sidewalls of source trench 324 may be implanted with p-type ions to form such a deep shield connection pattern (not shown) in the cross section of Figure 10.

[0108] It will be appreciated that UMOSFET 200-2 of FIG. 4, UMOSFET 200-3 of FIG. 5, UMOSFET 200-5 of FIG. 7, UMOSFET 200-7 of FIG. 9, and UMOSFET 300 of FIG. 10 can also include a barrier layer (e.g., barrier layer 234 of FIG. 6) directly on the lower dielectric layer (e.g., lower dielectric layer 232 of FIG. 9 or lower dielectric layer 332 of FIG. 10).

[0109] Figures 11-14 are flow charts illustrating a method of forming a power UMOSFET according to an embodiment of the invention. In particular, Figure 11 illustrates the general steps of a method of forming a power UMOSFET according to an embodiment of the invention. Figures 12-14 illustrate several different ways of performing one of the steps of the method of Figure 11, namely, forming a lower dielectric layer (block 920 of Figure 11), and Figures 15-18 are schematic cross-sectional views illustrating various steps illustrated in the flow chart of Figures 11-14.

[0110] 11 and 15, the method may include forming a preliminary trench 221 in a substrate (block 910). The substrate herein may refer to a semiconductor layer structure 240 including a semiconductor substrate 210, a drift layer 220, a well 230, and a source region 250. The preliminary trench 221 may be formed after all layers / regions of the semiconductor layer structure 240 are formed. In some embodiments, some layers / regions of the semiconductor layer structure 240 (e.g., the source region 250) and / or the shield region 224 may be formed after the preliminary trench 221 is formed. The preliminary trench 221 may be formed by an etch process, and the preliminary trench 221 may have a steep upper corner and a steep lower corner, as shown in FIG.

[0111] 11, 12, and 16, the preliminary lower dielectric layer 232p can be formed (block 921) after the preliminary trench 221 is formed by oxidizing the substrate. Oxidizing the substrate converts the exposed portion of the silicon carbide semiconductor layer to silicon oxide, thereby forming a silicon oxide layer both in and on the exposed portion of the semiconductor layer structure 240 (since silicon oxide "grows" into and outward from the semiconductor layer structure 240 upon addition of oxygen atoms). The oxidation is performed at a temperature that is sufficient to reflow the silicon oxide, so that the preliminary lower dielectric layer 232p can be formed and reflowed at the same time (block 921). For example, the oxidation can be performed at temperatures as high as about 900° C. for SiC oxidation when a network modifier dopant is present, or up to about 1550° C. for pure O2 oxidation of SiC.

[0112] Oxidizing the substrate may be performed by performing thermal oxidation using O2, O3, N2O, and / or H2O as an oxidizing agent, or plasma oxidation using any of the gases or other oxidizing agents mentioned above. Oxidizing the substrate may be performed at a temperature at least about the glass transition temperature of the preliminary lower dielectric layer 232p in some embodiments, which may be formed and reflowed at the same time. The steep upper corners and the steep lower corners of the preliminary trench 221 may be rounded by oxidizing the source region 250 and the predetermined portion of the drift layer 220, thereby forming the trench 222. The preliminary lower dielectric layer 232p may flow into the trench 222 by a reflow process, and the central portion of the upper surface of the preliminary lower dielectric layer 232p may be curved as shown in FIG. 16. The amount of dielectric material flowing into the preliminary trench 221 may be controlled by controlling the parameters of the oxidation process.

[0113] In some embodiments, the oxidizing of the substrate may be performed in an environment including a network modifier, and the preliminary lower dielectric layer 232p may include the network modifier. The network modifier may be, for example, boron (B), phosphorus (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and / or lead (Pb). The network modifier lowers the glass transition temperature of the preliminary lower dielectric layer 232p, and the preliminary lower dielectric layer 232p may reflow at a temperature lower than the glass transition temperature of the preliminary lower dielectric layer 232p without the network modifier. The preliminary lower dielectric layer 232p may include the network modifier in an amount of less than 4% by weight of the preliminary lower dielectric layer 232p. For example, the preliminary lower dielectric layer 232p may include the network modifier in an amount of 1% to 2% by weight of the preliminary lower dielectric layer 232p.

[0114] 12 and 17, the preliminary lower dielectric layer 232p can be optionally planarized (block 922) using a chemical-mechanical polish (CMP) process or an etch process. Although FIG. 17 shows that planarizing the preliminary lower dielectric layer 232p leaves a portion of the preliminary lower dielectric layer 232p and the top surface of the source region 250, in some embodiments, the planarization process can be performed until the top surface of the source region 250 is exposed.

[0115] 11 and 18, a portion of the preliminary lower dielectric layer 232p may be removed (block 930), thereby forming the lower dielectric layer 232 in the lower portion of the trench 222. That portion of the preliminary lower dielectric layer 232p may be removed by an etch process. The preliminary lower dielectric layer 232p may be etched while maintaining the profile of the top surface of the preliminary lower dielectric layer 232p, such that the lower dielectric layer 232 may have a top surface that is curved in its central portion.

[0116] 6 and 11, a barrier layer 234 may be formed on the lower dielectric layer 232 (block 940). The barrier layer 234 may contact an upper surface of the lower dielectric layer 232. The barrier layer 234 may be formed, for example, by conformally forming the barrier layer 234 on the underlying structures (e.g., the well 230 and the source region 250) and then isotropically etching the barrier layer 234. In some embodiments, forming the barrier layer 234 may be omitted. In some embodiments, the barrier layer 234 may be deposited in an anisotropic (directional) manner, such that a sidewall portion of the barrier layer 234 (i.e., a portion of the barrier layer 234 formed on a sidewall of the trench 222) may be thinner than a bottom portion of the barrier layer 223 (i.e., a portion of the barrier layer 234 formed on a bottom surface of the trench 222), which helps to allow the isotropic etch to remove the sidewall portion of the barrier layer 234 before the bottom portion of the barrier layer 234 is removed. Additionally, the method may include sequentially forming a gate dielectric layer 260 (block 950) and a gate electrode 270 (block 960).

[0117] 19-21 and 22-23 are schematic cross-sectional views illustrating a method for forming a power UMOSFET according to a further embodiment of the present invention. Referring to Figs. 13, 19, and 22, forming the lower dielectric layer 232 (block 920) may include coating or depositing a preliminary lower dielectric layer 232p in the preliminary trench 221 (block 923). Coating the preliminary lower dielectric layer 232p may be coating a spin-on glass layer, which may fill the preliminary trench 221 and may have a flat upper surface as shown in Fig. 19. The preliminary lower dielectric layer 232p formed by a deposition process may not fill the preliminary trench 221 as shown in Fig. 22. As shown in Figs. 19 and 22, coating or depositing the preliminary lower dielectric layer 232p may not change the shape of the preliminary trench, and thus the preliminary trench 221 includes sharp upper and lower corners. Coating or depositing the preliminary lower dielectric layer 232p can be coating a spin-on glass layer or depositing the preliminary lower dielectric layer 232p, such as a silicon oxide layer, using, for example, a chemical vapor deposition (CVD) process. The spin-on glass layer can include boron (B), phosphorus (P), sodium (Na), potassium (K), lithium (Li), calcium (Ca), magnesium (Mg), and / or lead (Pb).

[0118] 13, 20, and 23, forming the lower dielectric layer 232 (block 920) may also include annealing the preliminary lower dielectric layer 232p in an environment including an oxidizing agent at a temperature at least about the glass transition temperature of the preliminary lower dielectric layer 232p (block 924). Since the annealing is performed in an environment including an oxidizing agent, the substrate may be oxidized, and the trench 222 having rounded upper corners and rounded lower corners may be formed during the annealing. Furthermore, since the annealing is performed at a temperature at least about the glass transition temperature of the preliminary lower dielectric layer 232p, the preliminary lower dielectric layer 232p may reflow and flow into the trench 222 during the annealing. Referring to FIG. 20, when the preliminary lower dielectric layer 232p is formed by the coating process shown in FIG. 19, the annealing process may not change the shape of the preliminary lower dielectric layer 232p. Referring to FIG. 23, when the preliminary lower dielectric layer 232p is formed by the deposition process shown in FIG. 22, the preliminary lower dielectric layer 232p can flow into the trench 222 and the upper surface of the preliminary lower dielectric layer 232p can be less curved.

[0119] Forming the lower dielectric layer 232 (block 920) may optionally further include planarizing the preliminary lower dielectric layer 232p (block 925). It will be appreciated that planarizing the preliminary lower dielectric layer 232p may be performed before or after annealing the preliminary lower dielectric layer 232p (block 924).

[0120] 13 and 21, the portion of the lower dielectric layer 232 that includes the spin-on glass layer of FIG. 20 may be removed (block 930), for example, by an etch-back process. After the portion of the lower dielectric layer 232 is removed, the top surface of the lower dielectric layer 232 may have a small curvature, as shown in FIG. 21, with the lowest portion being at the center of the curvature.

[0121] 24-26 are schematic cross-sectional views illustrating a method for forming a power UMOSFET according to an embodiment of the present invention. With reference to FIG. 14 and FIG. 24, the method may include forming a thin dielectric layer 232_1 (block 926) after the preliminary trench 221 is formed. The thin dielectric layer 232_1 may be conformally formed on the underlying structure as shown in FIG. 24. The thin dielectric layer 232_1 may be formed by coating using a conformal coating technique such as atomic layer deposition (ALD) or depositing a dielectric layer using other approaches. The underlying structure may not include a p-type shield region (e.g., the p-type shield region 224 of FIG. 3). With reference to FIG. 25, the p-type shield region 224 may be formed after the thin dielectric layer 232_1 is formed. The p-type shield region 224 may be formed by implanting impurities into a portion of the drift layer 220 through the thin dielectric layer 232_1.

[0122] 14 and 26, the method may also include forming and reflowing the preliminary lower dielectric layer 232p (block 927). The forming and reflowing of the preliminary lower dielectric layer 232p may be performed simultaneously by an oxidation process similar to the process discussed with reference to FIG. 12, or may be performed sequentially by a process similar to the process discussed with reference to FIG. 13. Thereafter, planarizing the preliminary lower dielectric layer 232p (block 928) may be performed. The remaining processes may be performed (e.g., blocks 930-960 of FIG. 11).

[0123] 27 and 28 are schematic cross-sectional views illustrating a method of forming a power UMOSFET according to an embodiment of the present invention. Referring to FIG. 27, a preliminary lower dielectric layer 232p may be formed by the process discussed above, and the preliminary lower dielectric layer 232p may then be patterned to form the lower dielectric layer 232'' shown in FIG. 28. Referring again to FIG. 7, a gate electrode 270 may be formed directly on the lower dielectric layer 232'', which may be used as the gate dielectric layer of the device.

[0124] This disclosure describes an approach to improve interface protection in metal oxide (or insulator) semiconductor (MOS or MIS) devices, which can be particularly useful for improving the gate region in power transistors (e.g., MOSFETs, MISFETs, or IGBTs).

[0125] Although various of the embodiments discussed above show the structure of an n-channel MOSFET unit cell, it will be appreciated that in accordance with further embodiments of the present invention, the polarity of each of the semiconductor layers within each device may be reversed to provide a corresponding p-channel MOSFET.

[0126] The present invention has been described above with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it will be understood that the element or layer may be directly on, or directly connected or coupled to, the other element or layer, or that intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout.

[0127] Although the terms first and second are used herein to describe various regions, layers, and / or elements, it will be understood that these regions, layers, and / or elements should not be limited by these terms. These terms are only used to distinguish one region, layer, or element from another region, layer, or element. Thus, a first region, layer, or element discussed below can be referred to as a second region, layer, or element, and similarly, a second region, layer, or element can be referred to as a first region, layer, or element without departing from the scope of the present invention.

[0128] Relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It will be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if a device in the figures is flipped over, an element described as being on the "lower" side of another element would be oriented on the "upper" side of the other element. Thus, the exemplary term "lower" can encompass both an "under" and an "upper" orientation, depending on the particular orientation of the figure. Similarly, if a device in one of the figures is flipped over, an element described as being "below" or "beneath" another element would be oriented "above" the other element. Thus, the exemplary terms "below" or "below" can encompass both an upward and downward orientation.

[0129] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, elements and / or components but do not exclude the presence or addition of one or more other features, elements, components, features and / or groups thereof.

[0130] Embodiments of the invention are described herein with reference to cross-sectional views, which are schematic illustrations. Thus, variations from the shapes of the illustrations, for example as a result of manufacturing techniques and / or tolerances, are expected. As such, embodiments of the invention should not be construed as limited to the particular shapes of regions shown herein, and include deviations in shape due to, for example, manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and / or implant concentration gradients at its edges, rather than a binary transition from implanted to unimplanted regions. As such, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of a region of a device, and are not intended to limit the scope of the invention.

[0131] It will be understood that the embodiments disclosed herein may be combined, such that a feature depicted and / or described with respect to a first embodiment may also be included in a second embodiment, and vice versa.

[0132] Although the above embodiments are described with reference to certain figures, it is understood that some embodiments of the invention can include additional and / or intervening layers, structures, or elements, and / or certain layers, structures, or elements can be omitted. Although a few exemplary embodiments of the invention have been described, those skilled in the art will readily recognize that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and advantages of the invention. Accordingly, all such modifications are intended to be included within the scope of the invention as defined in the claims. Accordingly, it is understood that the above is illustrative of the invention and is not to be construed as being limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The invention is defined by the following claims, together with any equivalents of the claims that may be included in the scope of the claims.

Claims

1. 1. A method of forming a semiconductor device, comprising: forming a trench in a semiconductor layer structure, the semiconductor layer structure having first and second major surfaces; forming a lower dielectric layer in the trench, the forming of the lower dielectric layer comprising forming and annealing a preliminary lower dielectric layer; forming a dielectric layer conformally in the trench directly over a central portion of the lower dielectric layer; forming a gate electrode in the trench on the gate dielectric layer; forming a shield region in the drift layer below the trench; A method comprising:

2. 2. The method of claim 1, further comprising planarizing the preliminary lower dielectric layer after forming the preliminary lower dielectric layer and before annealing the preliminary lower dielectric layer.

3. The method of claim 1 , wherein forming the preliminary lower dielectric layer comprises forming a layer of spin-on glass.

4. 2. The method of claim 1, wherein the step of forming the lower dielectric layer further comprises etching an upper portion of the preliminary lower dielectric layer until an upper surface of the semiconductor layer structure is exposed.

5. The method of claim 1 , wherein said preliminary lower dielectric layer reflows during said anneal.

6. The method of claim 1 , wherein the gate dielectric layer is of a different material than the lower dielectric layer.

7. 2. The method of claim 1, wherein the lower dielectric layer has a first thickness at a bottom of the trench and a second thickness at sidewalls of the trench, the second thickness being less than the first thickness.

8. 10. The method of claim 1, further comprising forming a barrier layer on the lower dielectric layer prior to forming the gate dielectric layer, the barrier layer being comprised of a second material different from the lower dielectric layer.

9. The method of claim 1 , wherein the preliminary lower dielectric layer is simultaneously formed and annealed.

10. moreover, forming a source contact on the first major surface of the semiconductor layer structure; forming a drain contact on the second major surface of the semiconductor layer structure; Including, The method of claim 1 , wherein the gate electrode is configured to control a flow of current through a channel interposed between the source contact and the drain contact.

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