Spin orbital-spin orbital logic

Abstract

To provide an integrated circuit that uses a spin orbital-spin orbital (SO-SO) logic cell.SOLUTION: An integrated circuit comprises a plurality of SO-SO logic cells 250, and each SO-SO logic cell comprises a first spin orbit torque (SOT1) layer 204, a second spin orbit torque (SOT2) layer 214, and a ferromagnetic layer (FM) 208 disposed between the SOT1 layer and SOT2 layer. Each SO-SO logic cell includes a first current path Iinput that is in a plane of the SOT1 layer, and a second current path Isupply that is perpendicular to a plane of the SOT2 layer, and the second current path extends in the ferromagnetic layer. The integrated circuit further comprises a common voltage source connected to each SOT device, and one or more interconnections disposed between adjacent SOT devices of the plurality of SOT devices and connect the adjacent SOT devices to each other.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 521,306, filed June 15, 2023, the contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD Embodiments of the present disclosure relate generally to integrated circuits that utilize spin-orbit-spin-orbit logic. [Background technology]

[0003] 2. Description of Related Art Over the past few decades, miniaturization of functions in integrated circuits has been a driving force behind the ever-growing semiconductor industry. Miniaturization allows for greater integration of functional units in the limited area of ​​a semiconductor chip. For example, shrinking transistor size allows for an increased number of memory and logic devices on a chip, which contributes to the production of higher capacity products.

[0004] Magneto Electric Spin Orbital (MESO) structures have recently been proposed and used as new logic elements because they require at least ten times lower voltages to switch and are much more energy efficient than, for example, Complementary Metal Oxide Semiconductor (CMOS) transistors. However, MESO structures are difficult to fabricate and difficult to properly bias. If a MESO structure is improperly biased, it is impossible to control the current and voltage between different parts of the device.

[0005] Moreover, MESO structures use different mechanisms for the input and output: the input stage uses magnetoelectric elements, typically multiferroic materials such as BiFeO3, to perform charge-to-spin conversion, while the output stage uses spin-orbit coupling, such as the inverse spin Hall effect, to perform spin-to-charge conversion. Therefore, the input and output stages need to be separated, and MESO consumes a larger area.

[0006] Moreover, the input stage multiferroic material, BiFeO3, has a large variation in the switching threshold voltage of the ferroelectric polarity. For example, a 20-nm-thick BiFeO3 layer has a switching voltage that varies from 0.15 V to 1.5 V. Such a large variation in the switching threshold voltage at the wafer scale is unfavorable for integrated circuits.

[0007] Thus, there is a need in the art for improved semiconductor logic. Summary of the Invention

[0008] The present disclosure generally relates to an integrated circuit utilizing spin-orbit-spin-orbit (Spinorbit-Spinorbit, hereafter abbreviated as "SO-SO") logic. The integrated circuit comprises a plurality of SO-SO logic cells, each SO-SO logic cell comprising a first spin-orbit torque (SOT1) layer, a second spin-orbit torque (SOT2) layer, and a ferromagnetic layer disposed between the SOT1 layer and the SOT2 layer. Each SO-SO logic cell is configured for a first current path in the plane of the SOT1 layer and a second current path perpendicular to the plane of the SOT2 layer, the second current path configured to extend to the ferromagnetic layer. The integrated circuit further comprises a common voltage source connected to each SOT device and one or more interconnects disposed between adjacent SOT devices of the plurality of SOT devices, the one or more interconnects connecting the adjacent SOT devices together.

[0009] In one embodiment, a device includes a first spin-orbit torque (SOT1) layer, a second spin-orbit torque (SOT2) layer, and a ferromagnetic layer disposed between the SOT1 and SOT2 layers, the device configured to have a first current path in the plane of the SOT1 layer and a second current path perpendicular to the plane of the SOT2 layer, the second current path configured to extend through the ferromagnetic layer.

[0010] In another embodiment, an integrated circuit (IC) comprises a first spin-orbit torque (SOT) device comprising a first spin-orbit torque layer, a second spin-orbit torque layer coupled to a first output terminal, and a ferromagnetic layer disposed between the first spin-orbit torque layer and the second spin-orbit torque layer, a second SOT device comprising a first spin-orbit torque layer coupled to a first input terminal, the second spin-orbit torque layer, and a ferromagnetic layer disposed between the first spin-orbit torque layer and the second spin-orbit torque layer, and a first interconnect disposed between a first output terminal of the first SOT device and a first input terminal of the second SOT device.

[0011] In yet another embodiment, an integrated circuit (IC) comprises a plurality of spin-orbit torque (SOT) devices, a common voltage source connected to each SOT device, and one or more interconnects disposed between adjacent SOT devices of the plurality of SOT devices connecting the adjacent SOT devices. Each SOT device comprises a first spin-orbit torque (SOT1) layer, a second spin-orbit torque (SOT2) layer, a ferromagnetic layer disposed between the SOT1 and SOT2 layers, and a MgO layer disposed between the ferromagnetic layer and the SOT2 layer. Each SOT device is configured for a first current path in the plane of the SOT1 layer and a second current path configured to be perpendicular to the plane of the SOT2 layer and extend through the ferromagnetic layer.

[0012] In another embodiment, an integrated circuit (IC) comprises a first spin-orbit torque (SOT) device configured to accept an input to a neural network node, the first SOT device comprising a first spin-orbit torque layer coupled to the input interconnect, a second spin-orbit torque layer coupled to the output interconnect, and a ferromagnetic layer disposed between the first and second spin-orbit torque layers and configured to encode a weight; and a second SOT device configured to accept an input to the neural network node, the second SOT device comprising the first spin-orbit torque layer coupled to the input interconnect, the second spin-orbit torque layer coupled to the output interconnect, and a ferromagnetic layer disposed between the first and second spin-orbit torque layers and configured to encode a weight, the output interconnects of the first SOT device and the second SOT device being coupled to a sum output interconnect. [Brief description of the drawings]

[0013] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be made by reference to the embodiments illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure, since other equally effective embodiments may be recognized. [Figure 1A] FIG. 1A shows a conventional magnetoelectric spin-orbit (MESO) structure. [Figure 1B] FIG. 1B illustrates the biasing problem in a conventional MESO transistor that implements the MESO structure of FIG. 1A. [Figure 2A] FIG. 2A illustrates a spin-orbit-spin-orbit (SO-SO) logic cell according to one embodiment. [Figure 2B] FIG. 2B illustrates an SO-SO logic device including the SO-SO logic cell of FIG. 2A, according to one embodiment. [Diagram 3] FIG. 3 shows a graph of output current density versus device width for the SO-SO logic device of FIG. 2B, according to one embodiment. [Figure 4] FIG. 4 shows a graph of total energy consumption per logic cell versus device width for the SO-SO logic device of FIG. 2B, in accordance with one embodiment. [Diagram 5] FIG. 5 shows an example of a neural network. [Figure 6] FIG. 6 illustrates a SO-SO logic device configured to perform a Multiply-Accumulate (MAC) operation on neuron nodes, according to one embodiment. [Figure 7] FIG. 7 illustrates an SO-SO logic device configured to perform an activation function for a neuron node, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] To facilitate understanding, the same reference numerals have been used whenever possible to designate identical elements common to the figures, and elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.

[0015] In the following, reference will be made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specific described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is intended to implement and practice the present disclosure. Furthermore, the embodiments of the present disclosure may achieve advantages over other possible solutions and / or over the prior art, but whether or not a particular advantage is achieved by a given embodiment does not limit the present disclosure. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims unless expressly recited in the claim(s). Similarly, reference to "the present disclosure" is not to be construed as a generalization of any inventive subject matter disclosed herein, and is not to be considered elements or limitations of the appended claims unless expressly recited in the claims.

[0016] The present disclosure generally relates to an integrated circuit utilizing spin-orbit-spin-orbit (SO-SO) logic, where a ferromagnetic layer is used to encode logic states and both input (write) and output (read) of the logic cells are based on spin-orbit mechanisms. The integrated circuit comprises a plurality of SO-SO logic cells, each SO-SO logic cell comprising a first spin-orbit torque (SOT1) layer, a second spin-orbit torque (SOT2) layer, and a ferromagnetic layer disposed between the SOT1 layer and the SOT2 layer. Each SO-SO logic cell is configured to have a first current path in the plane of the SOT1 layer and a second current path perpendicular to the plane of the SOT2 layer, the second current path configured to extend through the ferromagnetic layer. The integrated circuit further comprises a common voltage source connected to each SOT device, and one or more interconnects disposed between adjacent SOT devices of the plurality of SOT devices and connecting the adjacent SOT devices.

[0017] Figure 1A illustrates a conventional magnetoelectric spin orbit (MESO) structure 150. Figure 1B illustrates a conventional MESO transistor 100 that includes one or more MESO structures 150 of Figure 1A.

[0018] The conventional MESO structure 150 is c The system comprises a first interconnect 152 for a current input (I 1 ). The first interconnect 152 is coupled to a magnetoelectric material 154 such that the magnetoelectric material 154 is stacked in the -z direction on the first interconnect 152. The magnetoelectric material 154 is coupled to a nanomagnet or ferromagnet 156 such that the nanomagnet 156 is stacked in the -z direction on the magnetoelectric material 154. The nanomagnet 156 extends in the y direction, the nanomagnet 156 is coupled to a first contact 164 in the -z direction and is coupled to a spin injection layer 158 in the z direction. The spin injection layer 158 is coupled to a spin orbit coupling stack 160 such that the spin injection layer 158 is stacked on the spin orbit coupling stack 160. The spin orbit coupling stack 160 is then coupled to a second interconnect 162 in the x direction, the second interconnect for a current output (I c(output). The spin-orbit coupling stack 160 is further coupled in the z-direction to a second contact 166. The first contact 164 and the second contact 166 are connected to electronics and a power source. The second contact 166 is further connected to ground.

[0019] In the MESO structure 150, the input current (I c (input) is supplied through a first interconnect 152 and coupled to a magnetoelectric material 154, which converts the input current into magnetism that switches the magnetization direction of a nanomagnet 156. The direction of the nanomagnet 156 represents the on / off state of the MESO structure 150. To read out the state of the nanomagnet 156, the supplied current (I supply ) is applied perpendicular to the nanomagnet 156, and a spin polarized current is injected into the spin-orbit coupling stack 160 by the spin injection layer 158. The spin-orbit coupling stack 160 converts the spin polarized current into a charge current and outputs a current (I c In this case, the output is the inverse of the input. The output of MESO structure 150 (MESO structure 150a in FIG. 1B) is connected to the input of a second MESO structure 150 (MESO structure 150b in FIG. 1B), and multiple devices are arranged to build various logic circuits, as shown in FIG. 1B. Note that for simplicity, the supply current paths and associated contacts 164, 166 are not shown for second MESO structure 150b.

[0020] As shown in the MESO transistor 100 of FIG. 1B, the spin-orbit coupled stack 160 of the first MESO structure 150a has a first potential point 170, and the nanomagnet 156 of the second MESO structure 150b has a second potential point 168. The potential of the first potential point 170 must be the same as the potential of the second potential point 168. If the potentials of the first point 170 and the second point 168 are not the same, the current and voltage cannot be controlled in the MESO transistor 100. Thus, biasing the MESO transistor 100 is complicated.

[0021] Moreover, MESO structures use different mechanisms for the input and output: the input stage uses magnetoelectric elements, typically multiferroic materials such as BiFeO3, to perform charge-to-spin conversion, while the output stage uses spin-orbit coupling, such as the inverse spin Hall effect, to perform spin-to-charge conversion. Therefore, the input and output stages need to be separated, and MESO consumes a larger area.

[0022] Moreover, the input stage multiferroic material, BiFeO3, has a large variation in the switching threshold voltage of the ferroelectric polarity. For example, the switching voltage of a 20-nm-thick BiFeO3 layer varies from 0.15 V to 1.5 V. Such a large variation in the switching threshold voltage at the wafer scale is unfavorable for integrated circuits.

[0023] As mentioned above, the input portion of the MESO structure relies on magnetoelectric effects for transduction (the "ME" part of MESO). In contrast, the present disclosure generally relates to integrated circuits utilizing spin-orbit-spin-orbit (SO-SO) logic, where ferromagnetic layers are used to encode logic states and both the input (write) and output (read) of the logic cell are based on spin-orbit based mechanisms. FIG. 2A illustrates a spin-orbit-spin-orbit (SO-SO) logic cell 250 according to one embodiment. FIG. 2B illustrates an integrated circuit or SO-SO logic device 200 comprising one or more SO-SO logic cells 250a, 250b, 250c of FIG. 2A according to one embodiment. The various layers of the SO-SO logic cell 250 are not drawn to scale and are for illustrative purposes only. SO-SO logic cells may be referred to herein as SOT devices.

[0024] In some embodiments, the SO-SO logic cell 250 includes a seed layer 202, a first spin-orbit torque (SOT) layer 204 (SOT1) disposed on the seed layer 202, a first IL layer 206 disposed on the first SOT layer 204, a ferromagnetic (FM) layer 208 disposed on the first IL layer 206, an MgO layer 210 disposed on the FM layer 208, a second IL layer 212 disposed on the MgO layer 210, a second SOT layer 214 (SOT2) disposed on the second IL layer 212, a buffer layer 216 disposed on the second SOT layer 214, and a cap layer 218 disposed on the buffer layer 216. The second SOT layer 214 is coupled to an interconnect 220a (shown in FIG. 2B), which is coupled to the first SOT layer 204 of a second SO-SO logic cell 250b (shown in FIG. 2B). In this manner, multiple SO-SO logic cells 250a-250c are arranged to construct various logic circuits. The seed layer 202, intermediate layers 206 and 212, MgO layer 210, and cap layer 218 are optional in some embodiments. These layers may also be tuned to optimize the properties of the SOT layers 204, 214 (e.g., increase the effective spin Hall angle to improve overall device efficiency).

[0025] In operation, the SO-SO logic cell is a hybrid device that utilizes the spin Hall effect (SHE) for the write path and the inversive spin Hall effect (iSHE) for the read path. To "write" a logic state, an input current (I input ) is applied to the first SOT layer 204 as a Current In Plane (CIP) current to switch the FM layer 208 via the generation of the SHE. To “read” the state of the FM layer 208, a supply current (I supply) is applied vertically through the SO-SO logic cell 250 to the second SOT layer 214 as a Current Perpendicular to Plane (CPP). The current through the FM layer 208 becomes spin polarized, and such spin polarized current is injected into the second SOT layer 214, and an electrical voltage proportional to the magnitude of the spin polarized current is induced in the second SOT layer 214 through the iSHE. Such a voltage potential results in a current output (I output ) to generate a charge current. Thus, I output reflects the magnetization of the FM layer 208, which encodes a logic state. Thus, rather than utilizing magnetoelectric effects as in MESO structure 150 and MESO transistor 100 of FIGS. 1A-1B, SO-SO logic cell 250 utilizes spin-orbit effects to both "write" and "read" the logic states encoded in FM layer 208.

[0026] As mentioned above, SO-SO devices use the same spin-orbit interaction mechanism for charge-spin and spin-charge conversion, so the input and output stages can be stacked together, saving the device footprint and increasing the integration density.

[0027] As described above, the SO-SO logic cell 250 includes a first current path (I input ) and a second current path (I supply 2B ) and the second current path is configured to extend to the FM layer 208. In some embodiments, the second current path is configured to extend to the first SOT layer 204 as well. For example, when writing data, the SO-SO logic device 200 may have an input current (V in[N], where N denotes an individual interconnectable logic cell, and the first SOT layer 204 is configured to affect the magnetization orientation of the FM layer 208 with an input current. When reading the logic state encoded by the magnetization of the FM layer 208, the SO-SO logic device 200 receives a supply current (I supply ) and outputs an output current (I output ) (V shown in Figure 2B out[N] )

[0028] The seed layer 202 may be a multi-layer structure including a combination of the following layers: (1) one or more amorphous conditioning layers, such as NiTa, NiW, NiFeTa, NiFeW, etc.; (2) a RuAl texturing layer; (3) a MgO layer; and (4) a Ni x Ru (1-x) Al (where x is 0 to 1) alloy, any crystalline or nanocrystalline non-magnetic element, or alloy material having an equivalent BCC or B2 lattice constant in the range of 2.93 Å to 3.03 Å that does not react with SOT and does not contain heavy metals. In some embodiments, the seed layer 202 is NiFeTa / RuAl / NiFeGe, NiTa / NiFeGe, NiTa / NiFeGe / Ge, NiFeTa / RuAl / CuGe, NiTa / Ni x Ru (1-x) It may also be a textured seed layer consisting of a combination of an amorphous / crystalline transition layer and a seed layer, such as Al / NiGe (" / " indicates layer separation).

[0029] The first intermediate layer 206, the second intermediate layer 212, and the buffer layer 216 are each individually made of Ni x Ru (1-x)Al (where x is 0 to 1), any crystalline or nanocrystalline non-magnetic element, or alloy material having an equivalent BCC or B2 lattice constant in the range of 2.93 Å to 3.03 Å that does not react with SOT and does not contain heavy metals. In some embodiments, the first interlayer 206, the second interlayer 212, and the buffer layer 216 may each individually be composed of an amorphous / crystalline layer or combination of layers, such as Ge, NiFeGe, NiGe, CuGe, Ge / NiAl, Ge / RuAl, RuGe, MgO / Ge, MgO / NiFeGe, NiAlGe, or RuAlGe.

[0030] The cap layer 218 may be composed of MgO, any of the materials of the first interlayer 206, the second interlayer 212, or the buffer layer 216, an amorphous high-resistance material, or a combination of layers thereof, such as a multi-layer stack of MgO and NiFeGe or other high-resistance materials. The cap layer 218 may be a textured cap layer 218 composed of a combination of a high-resistance crystalline or amorphous material, such as TiO, TiN, MgO, MgOTiO, a composite material, such as NiFeGe, or Ge. The FM layer 208 may be composed of a bcc or Heusler FM material, such as CoFe, CoFeMnGe, CoFeGe, CoFeAl, CoFeSi, etc.

[0031] In some embodiments, the first SOT layer 204 and the second SOT layer 214 are each individually composed of a topological insulator material. The SOT layer 214 may be composed of at least one of BiSb, a topological insulator, a topological half-Heusler alloy such as YPtBi, and a weakly oxidized heavy metal. In some embodiments, the topological insulator material may be BiSb with a (012) orientation to achieve the highest spin-Hall angle (current-spin conversion efficiency). BiSb material has been shown to have a large giant spin-Hall angle of 52 and a large inverse spin-Hall angle of 61, and therefore can be applied to the first SOT layer 204 and the second SOT layer 214. Furthermore, the BiSb layer can be epitaxially grown by using an appropriate seed layer or intermediate layer, which can significantly reduce the variation in switching current density of the FM layer at the wafer scale. The first SOT layer 204 and the second SOT layer 214 are each individually placed in contact with a suitable buffer layer 216 and / or intermediate layer 206, 212 to minimize diffusion and roughness. The first SOT layer 204 and the second SOT layer 214 may each individually be composed of undoped BiSb or doped BiSbX with less than about 10 at.% dopant, where X is selected from elements that do not readily react with Bi, such as B, N, Al, Si, Ti, V, Ni, Cu, Ge, Y, Zr, Ru, Mo, Ag, Hf, W, Re, Ir, or alloy combinations with one or more of the aforementioned elements, such as CuAg, CuNi, RuGe. The advantage of the high spin Hall angle of the materials of the first and second SOT layers 204, 214 is utilized to both write and read the logic states or values ​​encoded in the FM layer 208.

[0032] 2B illustrates an SO-SO logic device 200 comprising one or more SO-SO logic cells 250a, 250b, 250c of FIG. 2A, according to one embodiment. Although the SO-SO logic device 200 illustrates three SO-SO logic cells 250a, 250b, 250c, the SO-SO logic device 200 may comprise any number of SO-SO logic cells 250, which may be interconnected in arrangements other than those illustrated. Additionally, one or more layers of each of the SO-SO logic cells 250a, 250b, 250c are not illustrated for clarity purposes only. The SO-SO logic device 200 may be referred to herein as an integrated circuit (IC).

[0033] The first SO-SO logic cell 250a comprises a first SOT layer 204a coupled to a first interconnect 220a, an FM layer 208a disposed on the first SOT layer 204a, an MgO layer 210a disposed on the FM layer 208a, and a second SOT layer 214a disposed on the MgO layer 210a. The first interconnect 220a is coupled to a first voltage input (V in1 ) to an input terminal 226a of the first SOT layer 204a. The second interconnect 220b is coupled to the second SOT layer 214a at an output terminal 228a and provides a first voltage output (V out1 The second interconnect 220b is also coupled to the first SOT layer 204b of the second SO-SO logic cell 250b at an input terminal 226b and provides a second voltage input (V in2 The first SOT layer 204a is further connected to a ground terminal 222a.

[0034] Similarly, the second SO-SO logic cell 250b includes an FM layer 208b disposed on the first SOT layer 204b, an MgO layer 210b disposed on the FM layer 208b, and a second SOT layer 214b disposed on the MgO layer 210b. The second SOT layer 214b is coupled to a third interconnect 220c at an output terminal 228b and provides a second voltage output (V out2 ). The third interconnect 220c provides a third voltage input (V in3) is coupled to the first SOT layer 204c of the second SO-SO logic cell 250c. The second SOT layer 214b is further coupled to a ground terminal 222b.

[0035] The third SO-SO logic cell 250c includes an FM layer 208c disposed adjacent to the first SOT layer 204c, an MgO layer 210c disposed on the FM layer 208c, and a second SOT layer 214c disposed on the MgO layer 210c. The second SOT layer 214c is coupled to a fourth interconnect 220d at an output terminal 228c and provides a third voltage output (V out3 ) The fourth interconnect 220d is coupled to the first SOT layer of a fourth SO-SO logic cell (not shown) at an input terminal (not shown). The first SOT layer 204c is further connected to a ground terminal 222c.

[0036] Each SO-SO logic cell 250a, 250b, 250c has an x-direction width 224 of about 5 nm to about 20 nm, which is defined by logic design rules based on available semiconductor industry process nodes. The first, second, and third interconnects 220a, 220b, 220c are each individually constructed of, for example, Cu. The first, second, and third interconnects 220a, 220b, 220c are each individually constructed of, for example, Cu, which is defined by logic design rules based on density requirements.

[0037] Each SO-SO logic cell 250a, 250b, and 250c is connected to a power supply voltage (V DD) are connected to the SO-SO logic cells 250a, 250b, 250c. A clocking control element or clock 230 may be connected between each of the SO-SO logic cells 250a, 250b, 250c and a power supply voltage. The MgO layers 210a, 210b, 210c disposed between the FM layer 208a, 208b, 208c and the second SOT layer 214a, 214b, 214c of each SO-SO logic cell 250a, 250b, 250c (collectively referred to herein as SO-SO logic cells 250) enhance the first, second, and third voltage outputs and further ensure that the first, second, and third voltage outputs are higher (lower) than the voltage input of the next SO-SO logic cell. The MgO layers 210a, 210b, 210c also help prevent the backflow of net spin currents due to the output current.

[0038] Each of the first SOT layers 204a, 204b, 204c (collectively referred to herein as the first SOT layer 204) and each of the second SOT layers 214a, 214b, 214c (collectively referred to herein as the second SOT layer 214) is properly biased in adjacent SO-SO logic cells so that their midpoint potentials are the same, preventing unexpected current flow between the voltage output and the voltage input.

[0039] For each SO-SO logic cell 250a, 250b, 250c, there are three energy terms: the energy due to the current flowing through the pillars and the energy due to the current flowing through each SOT layer 204, 214. When a topological insulator material such as BiSb(012), which has a giant spin Hall angle (52) and inverse spin Hall angle (61), is used for the first and second SOT layers 204, 214, the hybrid SO-SO logic cell 250 has an energy density of approximately 1×10 6 A / cm 2current density of more than 1000 m / s, which is high enough to drive the next stage SO-SO logic cell input. In this situation, the power consumption of the SOT switching of the FM layer is significantly smaller than the energy consumed by the pillars. The total energy is essentially constant and is determined mainly by the energy of the pillars due to the transistor drive current. The estimated energy of about 50 aJ for the SO-SO logic device 200 is smaller than that of a conventional CMOS transistor, which has an estimated energy of about 300 aJ. Thus, the SO-SO logic device 200 significantly reduces the energy consumption.

[0040] FIG. 3 illustrates the current density (A / cm ) of the SO-SO logic device 200 of FIG. 2B , according to one embodiment. 2 3 shows a graph 300 of the number of SO-SO logic cells 250 per cell versus device width (nm). As shown, when each SO-SO logic cell 250 has a width between about 8 nm and about 20 nm, the SO-SO logic device 200 has a number of cell sizes of about 3×10 5 A / cm 2 and 1×10 6 A / cm 2 , which is high enough to drive the next stage or SO-SO logic cell inputs.

[0041] FIG. 4 illustrates a graph 400 of total energy per logic cell (J) versus device width (nm) for the SO-SO logic device 200 of FIG. 2B, according to one embodiment. Line 420 represents the total energy from each SOT layer 204, 214 individually. Line 410 is the pillar energy combined with the total dissipated energy (the lines here overlap and are substantially the same, indicating that the total energy is determined primarily by the pillar energy due to the transistor drive current). As shown, when each SO-SO logic cell 250 is between about 8 nm and about 20 nm wide, the SO-SO logic device 200 consumes about 50 aJ (1 aJ=10 -18 We achieve an estimated energy of J, units on the Y-axis, which is significantly smaller than the energy of conventional CMOS transistors.

[0042] 5-7 show an example embodiment of a SO-SO logic device in a neural network configuration. Figure 5 shows an example of a neural network 500. A neural node 501 is shown, with weights W1...W n By multiplying the input X1···X n This is also called a Multiply-Accumulate (MAC) operation. In addition to the MAC operation, the node feeds the MAC output to an activation function to provide the final output of the node. The activation function may be a step-like function, such as a Rectified Linear Unit (ReLU) activation function, to generate an output for the node(s) in the next layer of the neural network. The output in some embodiments depends on whether the result of the MAC operation satisfies a threshold of the step-like function (is activated or not activated).

[0043] The MAC operation and activation functions constitute the two core functions of a neuron node, and Figures 6-7 show how each function can be implemented using SO-SO logic devices. Figure 6 shows an SO-SO logic device configured to perform a MAC operation, according to one embodiment. In this example, each of the SO-SO logic devices 601-603 can be fabricated and configured as previously described in Figures 2A-2B. Here, the input bias current I 1-n (I in Fig. 2A supply ) corresponds to the neural network input X in Figure 5. 1-n , i.e., the input value to the neuron node. The magnetization states in the FM layers of the SO-SO logic devices 601-603 represent the weights of the neural network (W in FIG. 5). 1-n ). The magnetization (M) state can be either +M (positive), -M (negative), or any analog value in between, depending on the position of the domain wall in the FM layer. In some embodiments, the magnetization state is represented by the Control 1-n (I in Fig. 2A input) via the input currents labeled as X , and X , respectively. In this manner, each SO-SO logic device 601-603 can be controlled by a set current pulse width or amplitude via the input currents labeled as X , n ×Weight W n As further shown, the results of devices 601 to 603 (Y 1-n ) are then summed at interconnect 604. Thus, the total output current is Y=Σ(X i W i ), which represents the MAC operations shown in Figure 5. In this manner, SO-SO logic devices can be configured together to perform MAC operations.

[0044] FIG. 7 illustrates an SO-SO logic device configured to perform a neuron node activation function, according to one embodiment. This figure is a continuation of FIG. 6, and shows the summed total output current Y=Σ(X i W i ) is fed to the output SO-SO logic device 701, which in one embodiment has a steep threshold current density for switching of its FM layer. This can be achieved by reducing the size of the FM layer of the SO-SO logic device 710 so that the magnetization switching mechanism is coherent switching. This output SO-SO logic device 701 therefore logically functions as a step-like transfer function as shown in FIG. 5. Furthermore, the output bias current of the output SO-SO logic device 701 can be set so that the output Z is high enough to drive the next stage. This final output Z is provided to the next neuron layer. In this way, the SO-SO logic device can be configured to perform activation function operations. FIG. 6-7 shows how multiple SO-SO logic devices can be configured to perform the function of a neuron node of a neural network.

[0045] In this way, by using an SO-SO logic device composed of a plurality of SO-SO logic cells, each of which is composed of a first SOT layer and a second SOT layer, the SO-SO logic device effectively functions as a semiconductor device that can perform logic operations while reducing energy consumption. Furthermore, the simplified structure of the SO-SO logic device has advantages in terms of scaling while maintaining low energy consumption, and the SO-SO logic device is easy to mass-produce and easy to bias voltage.

[0046] In one embodiment, a device includes a first spin-orbit torque (SOT1) layer, a second spin-orbit torque (SOT2) layer, and a ferromagnetic layer disposed between the SOT1 and SOT2 layers, the device being configured for a first current path in the plane of the SOT1 layer and a second current path perpendicular to the plane of the SOT2 layer, the second current path being configured to extend through the ferromagnetic layer.

[0047] The device is further configured to receive an input current through a first current path, and the SOT1 layer is configured to affect the magnetization direction of the ferromagnetic layer by the input current. The device is further configured to receive a supply current through a second current path and generate an output current responsive to the magnetization direction of the ferromagnetic layer through the SOT2 layer. The device further comprises an MgO layer disposed between the ferromagnetic layer and the second spin-orbit torque layer. The device has a width between about 8 nm and about 20 nm. The first SOT layer and the second SOT layer each individually comprise undoped BiSb. The first SOT layer and the second SOT layer each individually comprise doped BiSbX, where the dopant is less than about 10 at.%, and X is a material selected from the group consisting of B, N, Al, Si, Ti, V, Ni, Cu, Ge, Y, Zr, Ru, Mo, Ag, Hf, Re, W, and Ir. The first SOT layer and the second SOT layer each individually have a (012) orientation. The integrated circuit includes a device, the first SOT layer and the second SOT layer each individually including YPtBi.

[0048] In another embodiment, an integrated circuit (IC) comprises a first spin-orbit torque (SOT) device comprising a first spin-orbit torque layer, a second spin-orbit torque layer coupled to a first output terminal, and a ferromagnetic layer disposed between the first spin-orbit torque layer and the second spin-orbit torque layer, a second SOT device comprising the first spin-orbit torque layer coupled to a first input terminal, the second spin-orbit torque layer, and a ferromagnetic layer disposed between the first spin-orbit torque layer and the second spin-orbit torque layer, and a first interconnect disposed between the first output terminal of the first SOT device and the first input terminal of the second SOT device.

[0049] The first SOT device further comprises a MgO layer disposed between the ferromagnetic layer and the second spin orbit torque layer, and the second SOT device further comprises a MgO layer disposed between the ferromagnetic layer and the second spin orbit torque layer. The second spin orbit torque layer of the second SOT device is coupled to a second output terminal, and the device further comprises a third SOT device comprising the first spin orbit torque layer coupled to the second input terminal, the second spin orbit torque layer, and a ferromagnetic layer disposed between the first spin orbit torque layer and the spin orbit torque layer, and a second interconnect disposed between the second output terminal of the second SOT device and the second input terminal of the third SOT device. The first SOT layer and the second SOT layer each individually comprise YPtBi.

[0050] The IC further comprises a common voltage source for the first, second and third SOT devices, and a clocking control element between the voltage source and the first, second and third SOT devices. The first spin orbit torque layer of the first SOT device is connected to a first ground terminal, and the second spin orbit torque layer of the second SOT device is connected to a second ground terminal. The first spin orbit torque layer of the first SOT device, the second spin orbit torque layer of the first SOT device, the first spin orbit torque layer of the second SOT device and the second spin orbit torque layer of the second SOT device each individually comprise BiSb. The first SOT device and the second SOT device each individually have a width between about 8 nm and about 20 nm. The first SOT device is configured for a first current path in the plane of the first spin orbit torque layer and a second current path perpendicular to the plane of the second spin orbit torque layer, the second current path configured to extend to the ferromagnetic layer. The second SOT device is configured for a first current path in the plane of the first spin orbit torque layer and a second current path perpendicular to the plane of the second spin orbit torque layer, the second current path being configured to extend through the ferromagnetic layer.

[0051] In yet another embodiment, an integrated circuit (IC) comprises a plurality of spin-orbit torque (SOT) devices, a common voltage source connected to each SOT device, and one or more interconnects disposed between adjacent SOT devices of the plurality of SOT devices connecting the adjacent SOT devices. Each SOT device comprises a first spin-orbit torque (SOT1) layer, a second spin-orbit torque (SOT2) layer, a ferromagnetic layer disposed between the SOT1 and SOT2 layers, and a MgO layer disposed between the ferromagnetic layer and the SOT2 layer. Each SOT device is configured for a first current path that is in the plane of the SOT1 layer and a second current path that is perpendicular to the plane of the SOT2 layer and configured to extend to the ferromagnetic layer.

[0052] Each SOT device is further configured to receive an input current via a first current path, with the SOT1 layer configured to affect the magnetization orientation of the ferromagnetic layer via the input current. Each SOT device is further configured to receive a supply current via a second current path and generate an output current via the SOT2 layer responsive to the magnetization orientation of the ferromagnetic layer. The first SOT layer and the second SOT layer each individually comprise YPtBi.

[0053] In another embodiment, an integrated circuit (IC) includes a first spin-orbit torque (SOT) device configured to accept input to a neural network node, the first SOT device comprising a first spin-orbit torque layer coupled to the input interconnect, a second spin-orbit torque layer coupled to the output interconnect, and a ferromagnetic layer disposed between the first and second spin-orbit torque layers and configured to encode a weight; a second SOT device configured to accept input to a neural network node, the second SOT device comprising a first spin-orbit torque layer coupled to the input interconnect, a second spin-orbit torque layer coupled to the output interconnect, and a ferromagnetic layer disposed between the first and second spin-orbit torque layers and configured to encode a weight; and the output interconnects of the first SOT device and the second SOT device are coupled to a sum output interconnect.

[0054] The IC further comprises a third SOT device comprising a first spin-orbit torque layer coupled to a sum output interconnect, a second spin-orbit torque layer coupled to an output interconnect for the third SOT device, and a ferromagnetic layer disposed between the first spin-orbit torque layer and the second spin-orbit torque layer and configured to encode a threshold of the activation function. The first SOT layer and the second SOT layer each individually comprise YPtBi.

[0055] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which scope is determined by the claims which follow.

Claims

1. A device, comprising: a first spin-orbit torque (SOT1) layer; a second spin-orbit torque (SOT2) layer; a ferromagnetic layer disposed between the SOT1 layer and the SOT2 layer; the device is configured for a first current path in the plane of the SOT1 layer and a second current path perpendicular to the plane of the SOT2 layer configured to extend to a ferromagnetic layer; device.

2. The device is further configured to receive an input current in the first current path; The SOT1 layer is configured to affect a magnetization direction of the ferromagnetic layer by the input current. The device of claim 1 .

3. the device is further configured to receive a supply current in the second current path and generate, via the SOT2 layer, an output current responsive to a magnetization orientation of the ferromagnetic layer. The device of claim 1 .

4. further comprising an MgO layer disposed between the ferromagnetic layer and the SOT2 layer; The device of claim 1 .

5. having a width between about 8 nm and about 20 nm; The device of claim 1 .

6. The SOT1 layer and the SOT2 layer each individually contain undoped BiSb. The device of claim 1.

7. the SOT1 layer and the SOT2 layer each comprise individually doped BiSbX, the dopant being less than about 10 at. %; X is a material selected from the group consisting of B, N, Al, Si, Ti, V, Ni, Cu, Ge, Y, Zr, Ru, Mo, Ag, Hf, Re, W, and Ir; The device of claim 1 .

8. The first SOT layer and the second SOT layer each have a (012) orientation. The device of claim 1 .

9. the first SOT layer and the second SOT layer each individually contain YPtBi; The device of claim 1 .

10. 13. A device comprising: Integrated circuits.

11. a first spin-orbit torque (SOT) device comprising a first spin-orbit torque layer, a second spin-orbit torque layer coupled to a first output terminal, and a ferromagnetic layer disposed between the first spin-orbit torque layer and the second spin-orbit torque layer; a second SOT device comprising a first spin-orbit torque layer coupled to a first input terminal, a second spin-orbit torque layer, and a ferromagnetic layer disposed between the first spin-orbit torque layer and the second spin-orbit torque layer; a first interconnect disposed between the first output terminal of the first SOT device and the first input terminal of the second SOT device. Integrated circuits.

12. the first SOT device further comprising a MgO layer disposed between the ferromagnetic layer and the second spin-orbit torque layer; the second SOT device further comprising an MgO layer disposed between the ferromagnetic layer and the second spin-orbit torque layer.

12. The integrated circuit of claim 11.

13. the second spin-orbit torque layer of the second SOT device is coupled to a second output terminal; The device comprises: a third SOT device comprising a first spin-orbit torque layer coupled to the second input terminal; A second spin-orbit torque layer; and a ferromagnetic layer disposed between the first spin-orbit torque layer and the second spin-orbit torque layer, a second interconnect is disposed between the second output terminal of the second SOT device and the second input terminal of the third SOT device; 13. The integrated circuit of claim 12.

14. a common voltage source for the first, second and third SOT devices; and a clocking control element between the voltage source and the first, second and third SOT devices.

14. The integrated circuit of claim 13.

15. the first spin-orbit torque layer of the first SOT device is connected to a first ground terminal; the second spin-orbit torque layer of the second SOT device is connected to a second ground terminal.

12. The integrated circuit of claim 11.

16. the first spin-orbit torque layer of the first SOT device, the second spin-orbit torque layer of the first SOT device, the first spin-orbit torque layer of the second SOT device, and the second spin-orbit torque layer of the second SOT device each individually comprise BiSb.

12. The integrated circuit of claim 11.

17. the first SOT device and the second SOT device each individually have a width between about 8 nm and about 20 nm; 12. The integrated circuit of claim 11.

18. The first SOT device is a first current path in the plane of the first spin-orbit torque layer; a second current path perpendicular to the plane of the second spin-orbit torque layer configured to extend through the ferromagnetic layer; The second SOT device is a first current path in the plane of the first spin-orbit torque layer; a second current path perpendicular to the plane of the second spin-orbit torque layer, the second current path being configured to extend through the ferromagnetic layer; 12. The integrated circuit of claim 11.

19. the first SOT layer and the second SOT layer each individually contain YPtBi; 12. The integrated circuit of claim 11.

20. A plurality of spin-orbit torque (SOT) devices, each SOT device comprising: a first spin-orbit torque (SOT1) layer; a second spin-orbit torque (SOT2) layer; a ferromagnetic layer disposed between the SOT1 layer and the SOT2 layer; a MgO layer disposed between the ferromagnetic layer and the SOT2; Each SOT device is configured for a first current path in the plane of the SOT1 layer and a second current path perpendicular to the plane of the SOT2 layer configured to extend to the ferromagnetic layer; A common voltage source is connected to each SOT device; one or more interconnects are disposed between adjacent SOT devices of the plurality of SOT devices, connecting the adjacent SOT devices together; Integrated circuits.

21. Each SOT device is further configured to receive an input current in the first current path; The SOT1 layer is configured to affect a magnetization direction of the ferromagnetic layer by the input current.

21. The integrated circuit of claim 20.

22. Each SOT device is further configured to receive a supply current in the second current path and generate, via the SOT2 layer, an output current responsive to a magnetization orientation of the ferromagnetic layer.

21. The integrated circuit of claim 20.

23. the first SOT layer and the second SOT layer each individually contain YPtBi; 21. The integrated circuit of claim 20.

24. a first spin-orbit torque (SOT) device configured to accept an input to a neural network node, the first spin-orbit torque layer coupled to the input interconnect, a second spin-orbit torque layer coupled to the output interconnect, and a ferromagnetic layer disposed between the first spin-orbit torque layer and the second spin-orbit torque layer, the ferromagnetic layer configured to encode a weight; a second SOT device configured to accept an input to a neural network node, the second SOT device comprising a first spin-orbit torque layer coupled to an input interconnect, a second spin-orbit torque layer coupled to an output interconnect, and a ferromagnetic layer disposed between the first spin-orbit torque layer and the second spin-orbit torque layer, the ferromagnetic layer configured to encode a weight; the output interconnects of the first SOT device and the second SOT device are coupled to a sum output interconnect; Integrated circuits.

25. Further comprising a third SOT device; The third SOT device is a first spin-orbit torque layer coupled to the sum output interconnect; a second spin-orbit torque layer coupled to an output interconnect for the third SOT device; a ferromagnetic layer disposed between the first spin-orbit torque layer and the second spin-orbit torque layer, the ferromagnetic layer configured to encode a threshold of an activation function.

25. The integrated circuit of claim 24.

26. the first SOT layer and the second SOT layer each individually contain YPtBi; 25. The integrated circuit of claim 24.

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