Film stack simplification for high aspect ratio patterning and vertical scaling

Abstract

To provide methods and apparatuses of fabricating semiconductor devices, for forming patterned multi-layer stacks including a metal-containing layer.SOLUTION: The methods comprise: using a silicon-containing non-metal materials in a multi-layer stack including one sacrificial layer to be later removed and replaced with metal while maintaining etch contrast to pattern the multi-layer stack and to selectively remove the sacrificial layer prior to depositing metal; and using silicon oxycarbide in lieu of silicon nitride, and a sacrificial non-metal material in lieu of a metal-containing layer, to fabricate the multi-layer stack, to pattern the multi-layer stack, to selectively remove the sacrificial non-metal material to leave spaces in the stack, and to deposit a metal-containing material in the spaces. The sacrificial non-metal material includes silicon nitride and doped polysilicon, such as boron-doped silicon.SELECTED DRAWING: None

Description

[Technical field]

[0001] [Incorporated by reference] A PCT application is being filed contemporaneously herewith as a part of this application. Each application to which this application claims benefit or priority, as identified in the contemporaneously filed PCT application, is hereby incorporated by reference in its entirety for all purposes. [Background technology]

[0002] The fabrication of semiconductor devices involves the fabrication of various devices, such as flash memory. As devices become smaller, complex and efficient memory cell fabrication structures are used to maximize the density of memory cells in memory devices. 3D NAND technology addresses the challenges associated with 2D NAND technology by stacking memory cells vertically. Additionally, fabrication can involve increasingly complex multi-layer stacks that include combinations of conductive and dielectric materials.

[0003] The background description provided herein is intended to generally describe the contents of the present disclosure. To the extent that it is described in this Background section, the inventors' work cited herein, and aspects of the present disclosure that may not specifically be regarded as prior art at the time of filing, are not expressly or implicitly admitted as prior art to the present disclosure. Summary of the Invention

[0004] Provided herein are methods and apparatus for fabricating semiconductor devices. One embodiment involves a method including providing a semiconductor substrate, depositing a metal-free multilayer stack having at least three different materials, at least one of the three different materials being a sacrificial layer, etching a trench or via in the metal-free multilayer stack having at least three different materials, after etching the trench or via, selectively etching the sacrificial layer relative to other materials of the metal-free multilayer stack to form at least one space between layers of the metal-free multilayer stack, and depositing a metal in the at least one space to form a metal-containing multilayer stack with an etched trench or via.

[0005] In various embodiments, the metal-free multi-layer stack includes three different materials.

[0006] In various embodiments, the metal-free multi-layer stack includes four different materials.

[0007] The method may also include recessing a dielectric material on sidewalls of the trench or via of the metal-free multi-layer stack after etching the trench or via and before selectively etching the sacrificial layer.

[0008] In various embodiments, the sacrificial layer is polysilicon or silicon nitride.

[0009] In various embodiments, the at least three different materials include one or more of silicon oxide, undoped polysilicon, doped polysilicon, silicon nitride, oxygen doped silicon carbide, and nitrogen doped silicon carbide.

[0010] In various embodiments, the metal is tungsten or molybdenum.

[0011] The method may also include depositing a metal-containing liner in the at least one space prior to depositing the metal, whereby the metal is deposited on the metal-containing liner in the at least one space, hi some embodiments, the metal-containing liner is selected from the group consisting of titanium nitride, aluminum oxide, and tungsten carbonitride.

[0012] In various embodiments, the metal-free multi-layer stack includes alternating layers of silicon oxycarbide, nitrogen doped silicon carbide, and silicon oxide.

[0013] In various embodiments, the metal-free multi-layer stack includes a sacrificial dielectric layer and alternating layers of silicon oxycarbide and silicon oxide.

[0014] In various embodiments, the at least three different materials include silicon nitride, silicon oxide, nitrogen-doped silicon carbide, and oxygen-doped silicon carbide.

[0015] In various embodiments, the at least three different materials include polysilicon, silicon oxide, nitrogen doped silicon carbide, and oxygen doped silicon carbide.

[0016] In various embodiments, the at least three different materials include polysilicon, silicon nitride, silicon oxide, and oxygen-doped silicon carbide.

[0017] In some embodiments, the sacrificial layer is silicon nitride. In some embodiments, the sacrificial layer may be polysilicon or doped polysilicon.

[0018] In various embodiments, the layers of the metal-free multi-layer stack are deposited by atomic layer deposition.

[0019] In some embodiments, the layers of the metal-free multi-layer stack are deposited in different chambers of a single tool.

[0020] In various embodiments, the layers of the metal-free multi-layer stack are deposited without breaking vacuum.

[0021] In some embodiments, the layers of the metal-free multi-layer stack are deposited in four different tools.

[0022] In various embodiments, the at least two layers of the metal-free multi-layer stack are deposited in a first tool and the other at least two layers of the metal-free multi-layer stack are deposited in a second tool.

[0023] In some embodiments, the layers of the metal-free multi-layer stack are deposited by chemical vapor deposition.

[0024] In various embodiments, the layers of the metal-free multi-layer stack are deposited by plasma-enhanced chemical vapor deposition.

[0025] In some embodiments, the layers of the metal-free multi-layer stack are deposited by physical vapor deposition.

[0026] In various embodiments, the method also includes recessing one of the at least three different materials after etching the trench or via to form a recessed region of the via, depositing a dielectric or semiconductor material in the trench or via, etching back the dielectric or semiconductor material in the trench or via to form smooth sidewalls and leaving the dielectric or semiconductor material in the recessed region, and depositing a gate material in the trench or via before selectively etching the sacrificial silicon nitride.

[0027] Another aspect involves a method including providing a semiconductor substrate, depositing a multi-layer stack of alternating sacrificial silicon nitride layers and non-oxide layers, etching a trench or via in the multi-layer stack of alternating sacrificial silicon nitride layers and non-oxide layers, selectively etching the sacrificial silicon nitride layers after etching the trench to form spaces between the non-oxide layers, and depositing a metal in the spaces to form a substrate including alternating metal and non-oxide layers and a trench etched in at least one dielectric barrier layer.

[0028] In various embodiments, the at least one dielectric barrier layer comprises oxygen-doped silicon carbide, for example, the oxygen concentration in the oxygen-doped silicon carbide may be between about 1 atomic % and about 65 atomic %.

[0029] In various embodiments, the non-oxide layer includes one or more of oxidized silicon carbide, polysilicon, and a second silicon nitride having a wet etch contrast to the sacrificial silicon nitride.

[0030] In some embodiments, the polysilicon is doped. For example, the polysilicon may be doped with a dopant selected from the group consisting of boron, phosphorous, and arsenic.

[0031] In various embodiments, the metal comprises tungsten.

[0032] In various embodiments, the metal comprises molybdenum.

[0033] In various embodiments, the sacrificial silicon nitride has a wet etch contrast of at least about 10:1 in 100:1 dilute hydrofluoric or phosphoric acid relative to non-oxide layers and the at least one dielectric barrier layer.

[0034] In various embodiments, the method also includes recessing a layer of the multi-layer stack after etching the trench or via to form a recessed area of ​​the via, depositing a dielectric or semiconductor material in the trench or via after recessing the layer, etching back the dielectric or semiconductor material in the trench or via to form smooth sidewalls and leaving the dielectric or semiconductor material in the recessed area, and depositing a gate material in the trench or via before selectively etching the sacrificial silicon nitride.

[0035] These and other aspects are further described below with reference to the drawings. [Brief description of the drawings]

[0036] [Figure 1] FIG. 1 is a process flow diagram of operations performed according to a method of forming a three-dimensional NAND structure.

[0037] [Diagram 2] FIG. 2 is a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation. [Diagram 3] FIG. 3 is a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation. [Figure 4A] FIG. 4A is a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation. [Figure 4B] FIG. 4B is a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation. [Figure 5A] FIG. 5A is a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation. [Figure 5B] FIG. 5B is a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation. [Figure 6] FIG. 6 is a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation. [Figure 7] FIG. 7 is a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation. [Figure 8]FIG. 8 is a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation.

[0038] [Figure 9A] FIG. 9A shows a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation. [Figure 9B] FIG. 9B shows a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation. [Figure 9C] FIG. 9C shows a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation. [Figure 9D] FIG. 9D shows a schematic diagram of an exemplary cross section of a multi-layer stack during a processing operation.

[0039] [Figure 10] FIG. 10 is a process flow diagram of operations that may be performed in accordance with certain disclosed embodiments.

[0040] [Figure 11A] FIG. 11A is a process flow diagram of operations that may be performed in accordance with certain disclosed embodiments.

[0041] [Figure 11B] FIG. 11B is a process flow diagram of operations that may be performed in accordance with certain disclosed embodiments.

[0042] [Figure 12A] FIG. 12A illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12B] FIG. 12B illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12C] FIG. 12C illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12D] FIG. 12D illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12E] FIG. 12E illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12F] FIG. 12F illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12G] FIG. 12G illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12H] FIG. 12H illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12I] FIG. 12I illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12J] FIG. 12J illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12K] FIG. 12K illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12L] FIG. 12L illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments. [Figure 12M] FIG. 12M illustrates an exemplary cross-sectional schematic diagram of a multi-layer stack during operations performed in accordance with certain disclosed embodiments.

[0043] [Figure 13] FIG. 13 depicts a block diagram illustrating various reactor components arranged to implement techniques in accordance with certain disclosed embodiments.

[0044] [Figure 14] FIG. 14 illustrates one embodiment of a multi-station cluster tool in accordance with disclosed embodiments.

[0045] [Figure 15] FIG. 15 illustrates a schematic diagram of another example of a multi-station process tool in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in connection with specific embodiments, it will be understood that no limitation of the disclosed embodiments is intended.

[0047] Semiconductor device processing involves the formation of multi-layer stacks that may be used to fabricate various three-dimensional devices, such as 3D NAND structures. Some stacks include multiple alternating layers of dielectric and conductive materials, each of which may be approximately 10 nm or thicker. One approach to forming such stacks involves depositing multiple alternating layers of oxide and nitride materials (ONON multi-layer deposition), then selectively removing the nitride material and backfilling and depositing metal into the space previously occupied by the nitride material. This method may be used to fabricate 3D NAND structures.

[0048] Another approach is to directly pattern a stack of multiple alternating layers of oxide and polysilicon (or “poly” as used elsewhere herein) where the polysilicon remains as a conductive layer. In some cases, the stack may include a metal such as a tungsten material. However, forming a stack including a dielectric, polysilicon, and metal can be cumbersome using some techniques. In particular, etching a trench to recess the sidewalls of the oxide material that forms, for example, the floating gate, may be difficult. Also, etching with metal in the stack itself can result in a high risk of leaving metal on the resulting device, which may undesirably change the profile of the etch pattern. In some cases, the fabrication of three-terminal devices involves multiple different materials, but cannot be fabricated using existing techniques. In some cases, the fabrication of two-terminal capacitors in a three-dimensional NAND structure faces challenges as individual source / drain regions would be fabricated on each device.

[0049] FIG. 1 illustrates a process flow diagram of operations performed according to a method for forming a three-dimensional NAND structure. In operation 182, a substrate is provided. In various embodiments, the substrate is a semiconductor substrate. The substrate may be a silicon wafer, including a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, having one or more layers of materials, such as dielectric materials, conductive materials, or semiconductive materials, deposited thereon. An exemplary substrate 100 is provided in schematic form in FIG. 2. Returning to FIG. 1, in operation 184, a film stack of alternating oxide and nitride films is deposited on the substrate. In various embodiments, the deposited oxide layers are silicon oxide layers. In various embodiments, the deposited nitride layers are silicon nitride layers. Each oxide and nitride layer is deposited to about the same thickness, such as about 10 nm to about 100 nm, or about 350 Angstroms, in some embodiments. The oxide layers may be deposited at a deposition temperature of about room temperature to about 600° C. As used herein, "deposition temperature" (or "substrate temperature") should be understood to refer to the temperature at which the pedestal holding the substrate is set during deposition.

[0050] The oxide and nitride layers forming the alternating oxide and nitride film stack may be deposited using any suitable technique, such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or sputtering. In various embodiments, the oxide and nitride layers are deposited by PECVD.

[0051] The film stack may include 48 to 512 alternating oxide and nitride layers, with each oxide or nitride layer constituting a layer. In some embodiments, the film stack may include fewer than 48 or more than 512 alternating oxide and nitride layers, depending on the application. A film stack including alternating oxide and nitride layers may be referred to as an ONON stack. Although the film stack described above involves alternating oxide and nitride layers, it is understood that additional layers may be included in the stack, and furthermore, other materials may be used for the alternating layers that are neither oxide nor nitride layers. For example, silicon germanium may be used in place of the nitride or silicon nitride layers in some cases. Other additional layers that may be present on the stack include silicon-containing layers, germanium-containing layers, or both. Examples of silicon-containing layers include doped and undoped silicon carbide layers, doped and undoped polysilicon layers, amorphous silicon layers, doped and undoped silicon oxide layers, and doped and undoped silicon nitride layers. The dopant may include a non-metallic dopant. For example, one example of the doped silicon carbide layer is oxygen doped silicon carbide. In another example, one example of the doped silicon carbide layer is nitrogen doped silicon carbide.

[0052] Figure 3 shows an exemplary schematic diagram of a substrate 100 having alternating oxide (101) and nitride (102) films deposited on the substrate 100. Although the structure shown in Figure 3 is shown with the oxide deposited first, followed by the nitride, oxide, nitride, etc., the nitride may be deposited first, followed by the oxide, nitride, oxide, etc.

[0053] After depositing the ONON stack, a channel (not shown in FIG. 3) may be etched into the substrate. Next, referring to FIG. 1, in operation 186, a staircase pattern is formed on the substrate. What is referred to herein as a "staircase pattern" includes two or more steps, each step including an oxide layer and a nitride layer. It is understood that the upper layer of each pair of oxide and nitride layers may be either oxide or nitride to form the steps of the staircase. In various embodiments, the staircase pattern includes between 24 and 256 steps. The staircase pattern may be formed using various patterning techniques. For example, one technique may include depositing a sacrificial layer on the substrate, masking areas of the substrate, and etching each pair of oxide and nitride layers to form the steps.

[0054] In FIG. 4A, an example of a substrate 100 is provided that includes a staircase pattern of oxide (111) and nitride (112) layers, with a hard mask 110 covering the top nitride layer. Although FIG. 4A shows a staircase pattern with four steps, it is understood that the staircase pattern may have 24 to 256 steps. Each step includes nitride and oxide layers, and the distance d shown in FIG. 4A may be from 150 nm to about 1000 nm, for example about 500 nm. This area of ​​each step that extends from the edge of the step above it may be referred to as a "pad" having a particular distance d.

[0055] For purposes of discussion, the following discussion and schematic diagrams of the substrate will include a half-view 199, as shown in FIG. 4B.

[0056] In operation 188 of FIG. 1, an oxide is deposited on the substrate. In various embodiments, the oxide may be of the same composition as the oxide deposited in the layers of the ONON stack. In various embodiments, the oxide deposited on the substrate is deposited at a deposition temperature different from the deposition temperature used to deposit the oxide layers in the ONON stack. The deposition temperature may be from room temperature to about 600° C. A vertical slit 135 may then be etched into the substrate after the oxide is deposited. FIG. 5A shows an exemplary substrate 100 including an ONON staircase, a hard mask 110, and an oxide 122 deposited on the substrate. FIG. 5B shows a side view of the substrate 100 after etching the vertical slit 130.

[0057] Returning to FIG. 1, in operation 190, the nitride is selectively etched relative to the oxide on the substrate. The etching may be performed using a selective dry etching process, such as by exposing the substrate to any one or more of the following gases: chlorine (Cl2), oxygen (O2), nitrous oxide (N2O), tetrafluoromethane (CF4), sulfur tetrafluoride (SF4), carbon dioxide (CO2), fluoromethane (CH3F), nitrogen trifluoride (NF3), nitrogen (N2), hydrogen (H2), ammonia (NH3), methane (CH4), sulfur hexafluoride (SF6), argon (Ar), carbonyl sulfide (COS), carbon disulfide (CS2), hydrogen sulfide (HS), and nitric oxide (NO). This operation removes the nitride layer from the ONON stack, such that etching species flow into the vertical slits and selectively etch the nitride. Selective etching should be understood to involve etching a first material at a faster rate than etching a second material. For example, selectively etching a nitride relative to an oxide means etching the nitride at a faster rate than etching the oxide. The nitride is selectively etched using a wet etching process, such as by exposing the substrate to phosphoric acid (H3PO4) and / or diluted hydrofluoric acid ("DHF") or a mixture of these solutions. Figure 6 shows a cross-sectional side view of a substrate with gaps 132 formed from selectively etching the nitride.

[0058] Returning to FIG. 1, in operation 192, tungsten is deposited into the gaps of the substrate to form tungsten wordlines. Tungsten may be deposited by any suitable technique, such as ALD, CVD, PEALD, and / or PECVD. In some embodiments, a barrier layer and / or tungsten nucleation layer is deposited prior to depositing bulk tungsten. Examples of barrier layers include titanium nitride, aluminum oxide, and tungsten carbonitride. FIG. 7 shows a simplified side view of a cross section of a substrate with tungsten 140 deposited into the gaps where nitride was previously present. As shown, metal deposition may result in deposition on the sidewalls of the oxide 111. Although tungsten is described herein, other metals such as molybdenum may be used.

[0059] Returning to Figure 1, in operation 194, vias are formed by etching the substrate vertically, which may include etching the oxide deposited on the steps as well as etching the metal to remove it from the sidewalls of the oxide in alternating layers. The oxide may be etched by dry etching using exposure to one or more of the following gases: O2, Ar, C4F6, C4F8, SF6, CHF3, and CF4. Figure 8 shows an exemplary substrate 100 including an ONON stack in a step pattern with a via 135 etched into the stack.

[0060] In FIG. 1, in operation 196, tungsten may be deposited in the vias to form interconnects to tungsten word lines. The vias may vary in depth and may have a depth of about 1 micron to about 12 microns. Shallow vias may be defined as having a depth less than 3.0 microns, such as about 1.5 microns to 3.0 microns. Deep vias may have a depth greater than 3.0 microns. The critical dimension of the vias formed in the oxide may be about 50 nm to about 500 nm. The vias may be etched using a dry etching process that may involve masking operations to pattern the oxide. In various embodiments, the patterning process may include more operations not shown in FIG. 1. For example, after depositing an oxide on the substrate in operation 188, a channel may be etched to form a channel. The channel may be filled with a charge trapping layer and a large trench or slit is etched before selectively etching the nitride in operation 190. The tungsten may be removed from the sidewalls before etching the vertical oxide and after depositing the tungsten wordlines.

[0061] 1 provides an example where tungsten backfill is deposited by CVD for ONON gate replacement. Such techniques may be used in ONON or OPOP integration schemes to form memory cell stacks, such as in some embodiments where polysilicon remains as the gate in the OPOP scheme. Both ONON and OPOP schemes can be etched in this manner without significant risk. However, there are challenges in applying such techniques to complex multi-layer stacks.

[0062] For example, the layers may include silicon oxide, tungsten, polysilicon, and another dielectric in the final structure. This may involve recessing the sidewalls of the dielectric, similar to floating gate formation in the OPOP scheme. One approach is to use the wet etch contrast between silicon oxide, silicon nitride, polysilicon, and tungsten to etch a film stack containing silicon oxide, silicon nitride, polysilicon, and tungsten and then recess the silicon oxide or silicon nitride, as described with respect to Figures 9A-9D, but such a process presents several challenges.

[0063] 9A-9D show another set of schematic diagrams for processing different multi-layer stacks. FIG. 9A includes a silicon nitride layer 902, a tungsten layer 940 (with an optional titanium nitride liner (not shown) between the tungsten layer 940 and the silicon nitride 902), a polysilicon layer 900 (with an optional titanium nitride layer (also not shown) between the tungsten layer 940 and the polysilicon layer 900), a silicon oxide layer 901, and a silicon nitride layer 902. Now, in FIG. 9B, a via or trench 950 is etched, which involves etching all of the above materials in the stack, including the metal, which may result in undesired metal residue on the substrate. The silicon oxide layer 901 may be further recessed to form the structure of the substrate. In FIG. 9C, the polysilicon 900 is filled to fill in the recessed areas adjacent to the silicon oxide layer 901. In FIG. 9D, polysilicon layer 900 is further etched to again form vias, thereby including the structure shown in FIG. 9D.

[0064] However, such processes involve etching not only tungsten and / or metal, but also other silicon-containing materials, which can be challenging. First, etching a multi-layer stack of dielectrics and metals while maintaining a vertical profile is extremely difficult, in part due to the use of different etch rates and etch chemistries for the different materials. This may result in feature collapse and degradation of the feature profile. Second, metal residues remaining in high aspect ratio structures are extremely difficult to clean up, and metal residues may affect device integrity. Third, deposition of tungsten films can lead to the formation of rough surfaces, which can cause device performance control issues.

[0065] Provided herein are methods and apparatus for forming and etching multiple film stacks to perform high aspect ratio patterning and vertical three-dimensional scaling. The multiple film stacks may include a set of layers deposited repeatedly. Each set of layers may include at least three different materials. In some embodiments, each set includes four different materials. The same set of layers may be stacked several times, such as about five times, or about ten times, or about twenty times, or more.

[0066] High aspect ratio vias or trenches patterned using certain disclosed embodiments may have aspect ratios greater than about 5:1, or from about 5:1 to about 20:1, or from about 25:1 to about 35:1, or even more. Some embodiments involve replacing a metal in a film stack with another dielectric that has similar dry etch behavior to the other materials, but exhibits significant wet etch contrast to the other materials. For example, the wet etch contrast of the dielectric that replaces the metal may be about 10:1 to the other materials in 100:1 dilute hydrofluoric or phosphoric acid. The disclosed embodiments may be implemented to form structures having both metal and dielectric materials without risk of producing metal residues on the substrate. In various embodiments, the metal is deposited after patterning of the structures, thus avoiding etching the substrate having both metal and dielectric materials. That is, in various embodiments, the metal-free film stack is etched and processed without the presence of metal by depositing and placing a dielectric material in the areas where the metal will later be deposited, forming the desired structure, then removing the dielectric material, and subsequently depositing metal in its place to create the desired pattern or device. Certain disclosed embodiments involve integrating the process of forming a structure including a dielectric material and a sacrificial layer in the areas where the metal will later be deposited, patterning the structure to leave a space, then etching the sacrificial layer, and depositing metal in the space. The disclosed embodiments may be advantageous for recessing sidewalls to form special devices such as floating gates. Certain disclosed embodiments also allow for better profile control.

[0067] Certain disclosed embodiments can be used to avoid etching tungsten in a multi-layer stack by using a sacrificial material of silicon nitride to etch a pattern, then using the etch contrast between silicon nitride and other dielectric materials to selectively remove the silicon nitride to create spaces, and then depositing metal in the spaces. Also, if the multi-layer stack includes other silicon nitride layers that are not sacrificial, these materials may be replaced with oxygen-doped silicon carbide, which can provide etch contrast when selectively removing silicon nitride, and can also provide properties similar to those of silicon nitride to perform the function of that particular layer. The dielectric layers described herein, such as SiOC, will have a wet etch contrast during SiN removal and SiO2 recession, but have similar dry etch behavior during high aspect ratio patterning. The dielectric can also be other materials that provide similar performance. Such materials can be polysilicon with different dopants, or SiN, or nitrogen-doped SiC (SiNC), which are deposited under different process conditions with very different wet etch rates than sacrificial SiN.

[0068] The disclosed embodiments may be used in a variety of applications, including fabrication of 3D NAND devices, floating gates, etc. Described herein is one example of a particular stack that may be formed using certain disclosed embodiments; it is understood that other materials and other patterning schemes and stacks may be formed using certain disclosed embodiments, and the disclosed embodiments are not limited to this example.

[0069] In certain disclosed embodiments, the stack is deposited using silicon nitride as a sacrificial layer onto which metal may be subsequently deposited, with the sacrificial layer being removed after the etching operation to form a space for the metal material, and the metal backfilling the space. Tungsten is described herein as an exemplary metal, but it is understood that other metals, such as molybdenum, may be used. In another embodiment, instead of silicon nitride, a polysilicon material, or doped polysilicon, may be used as the sacrificial layer. If other silicon nitride films (top and bottom of the provided stack) are present in the stack being fabricated, such layers are replaced with oxygen-doped silicon carbide to avoid etching these layers when removing the sacrificial silicon nitride layer. One advantage of oxygen-doped silicon carbide is that it can provide an etch contrast to other materials on the substrate, including silicon nitride and polysilicon, when performing removal or recession of SiN, poly, or SiO2.

[0070] Thus, an alternating stack of oxygen doped silicon carbide and silicon oxide may be formed, and silicon nitride may be used as a sacrificial layer if tungsten is subsequently deposited, and the silicon oxide may be recessed prior to polysilicon deposition, since the silicon oxide may be etched with an etch contrast to oxygen doped silicon carbide and silicon nitride. In some embodiments, the silicon oxide may be recessed with an etch contrast to nitrogen doped silicon carbide and silicon nitride. In some embodiments, the silicon oxide may be etched with an etch contrast to oxygen doped silicon carbide and silicon germanium. In some embodiments, the silicon oxide may be recessed with an etch contrast to any other non-oxidized silicon material on the substrate, including, but not limited to, nitrogen doped silicon carbide, doped Si, silicon nitride, and silicon germanium. After polysilicon deposition or any other patterning process, the silicon nitride sacrificial layer may be selectively removed using a wet etch process. A titanium nitride liner may be optionally deposited, and tungsten is deposited in the areas previously occupied by the silicon nitride sacrificial layer. Such a process avoids patterning with tungsten on the stack, thereby reducing redeposition of tungsten on the substrate. Furthermore, the tungsten material in the stack is not subjected to various process conditions that may distort and / or alter the grain structure of the tungsten material, because the tungsten is deposited after all other processes have been performed. Etching of the stack is simplified because the etch chemistry is not limited to chemistries that can etch tungsten; rather, the stack materials are all silicon-containing materials and can be precisely etched using a variety of existing etch processes.

[0071] Certain disclosed embodiments involve depositing a metal-free multilayer stack having at least three different materials, at least one of which is a sacrificial layer. As used herein, the term "metal-free" includes silicon-containing materials; that is, metal-free refers to materials that do not contain primarily transition metals or metalloids, but do contain semiconducting materials. Examples of metal-free materials include, but are not limited to, silicon nitride, silicon carbide, doped silicon carbide, silicon oxide, amorphous silicon, doped silicon, and polysilicon. In various embodiments, the metal-free stack does not contain tungsten. In various embodiments, the metal-free stack is tungsten-free. A sacrificial layer is used during etching and patterning of the multilayer stack; the sacrificial layer can be used to avoid etching the metal. Following patterning, the sacrificial layer may be etched and replaced with a metal material for the resulting structure. For example, in some embodiments, a metal-free multilayer stack having at least three different materials is deposited, trenches or vias are etched into the metal-free multilayer stack, and after etching, the sacrificial layer is selectively etched relative to other materials of the stack to form spaces, and metal is deposited in the spaces. In various embodiments, the metal-free multilayer stack has four different silicon-containing materials. In some embodiments, the metal-free multilayer stack has four different metal-free materials. In some embodiments, "different" materials refer to materials having different molecular or atomic compositions, or different grain textures, or different lattice structures. Selective etching of the sacrificial layer may be achievable by using the etch contrast between the materials upon exposure to different etchants, including liquid etchants.

[0072] In various embodiments, the sacrificial layer may be a polysilicon or silicon nitride material. Etch contrast for a silicon nitride sacrificial layer may be achieved by using other materials in the multi-layer stack, including but not limited to silicon oxide, oxygen doped silicon carbide or silicon oxide carbide, and polysilicon. Etch contrast for a polysilicon sacrificial layer may be achieved by using an etchant in which the polysilicon etches substantially faster than other materials on the substrate. Even if the other materials on the stack include polysilicon, etch contrast can be achieved using the difference in dopant concentration of the polysilicon. The dopant concentration of polysilicon is about 1E19 atoms / cm 3 ~About 1E20atoms / cm 3 For example, in some embodiments, the multi-layer stack may include boron doped polysilicon, while the sacrificial layer includes undoped polysilicon that can be etched with an etch contrast to the boron doped polysilicon to leave space for subsequent metal deposition. It is understood that metal deposition may be performed by first depositing a liner layer, such as, but not limited to, titanium nitride, followed by metal deposition.

[0073] Various variations of the multi-layer stack may be used. For example, in some embodiments, the multi-layer stack includes silicon nitride, silicon oxide, and oxygen-doped silicon carbide. In some embodiments, the terms silicon oxide carbide and oxygen-doped silicon carbide may be used interchangeably. In some embodiments, the multi-layer stack includes polysilicon, silicon oxide, and oxygen-doped silicon carbide. In some embodiments, the multi-layer stack includes polysilicon, silicon nitride, silicon oxide, and oxygen-doped silicon carbide.

[0074] In some embodiments, the multilayer stack includes alternating layers of silicon nitride and non-oxide layers, and a trench or via is etched in the multilayer stack, followed by selective etching of the silicon nitride to form a space between the non-oxide layers. A metal may then be deposited in the space. The non-oxide layer may be a silicon nitride material that has a wet etch contrast to silicon oxycarbide, polysilicon, or other silicon nitride materials. In some embodiments, the multilayer stack including the above alternating layers may also include another layer or non-oxide layer having a material different from silicon nitride. This layer may be a dielectric barrier layer. In some embodiments, this layer is not a dielectric barrier layer. In some embodiments, this layer is not a dielectric material. In some embodiments, this other layer and non-oxide layer having a material different from silicon nitride is an oxygen-doped silicon carbide layer. In some embodiments, this other layer is used to achieve an etch contrast when etching the silicon nitride. In some embodiments, this multilayer stack may be used to form a three-dimensional NAND structure.

[0075] As described herein, oxygen-doped silicon carbide or silicon oxycarbide has an oxygen concentration of about 1 atomic % to about 65 atomic %.

[0076] 10 is a process flow diagram depicting operations performed in accordance with certain disclosed embodiments. In operation 1082, a substrate is provided. The substrate may be a silicon wafer, for example, a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including a silicon wafer having one or more layers of material, such as a dielectric material, a conductive material, or a semiconductive material, deposited thereon. In operation 1084, a film stack is deposited including layers of oxide and oxygen-doped carbide, and one or more layers of sacrificial silicon nitride, where the sacrificial silicon nitride is deposited in spaces where metal is desired in the resulting structure. Although silicon oxide, silicon nitride, and oxygen-doped silicon carbide are described herein, it should be understood that other oxides, nitrides, and oxygen-doped carbides may be used in some embodiments.

[0077] Oxygen-doped silicon carbide may be deposited by plasma-assisted chemical vapor deposition by introducing a silicon-containing precursor, an oxygen-containing reactant, and a carbon-containing reactant during plasma ignition.

[0078] The precursor molecules for depositing silicon carbide may include silicon-containing molecules having silicon-hydrogen (Si-H) and / or silicon-silicon (Si-Si) and silicon-carbon (Si-C) bonds. In some embodiments, the precursor molecules for depositing silicon carbide layers may be silicon-containing and carbon-containing precursors. The precursor molecules for depositing silicon oxide carbide include silicon-containing molecules having silicon-hydrogen (Si-H) and / or silicon-silicon (Si-Si) and silicon-oxygen (Si-O) and / or silicon-carbon (Si-C) bonds. The precursor molecules for depositing silicon carbonitride include silicon-containing molecules having silicon-hydrogen (Si-H) and / or silicon-silicon (Si-Si) and silicon-nitrogen (Si-N) and / or silicon-carbon (Si-C) bonds. Precursor molecules for depositing silicon oxynitricarbide include silicon-containing molecules having silicon-hydrogen (Si-H) and / or silicon-silicon (Si-Si) bonds, and silicon-nitrogen (Si-N), silicon-oxygen (Si-O), and / or silicon-carbon (Si-C) bonds. In some embodiments, the silicon-containing precursors can include reactants with Si-O bonds and reactants with Si-C bonds. It is understood that any number of suitable reactants may be employed within the scope of the present disclosure. The silicon-containing precursors include one or more Si-H bonds and / or one or more Si-Si bonds. During the deposition process, the Si-H and / or Si-Si bonds are broken and serve as reaction sites for forming bonds between the silicon-containing precursors of the deposited silicon carbide film. The broken bonds can also serve as cross-linking sites during thermal treatments during or after deposition. Bonding and cross-linking at the reaction sites can collectively form a first backbone or matrix in the resulting silicon carbide film.In place of oxygen-doped silicon carbide, in some embodiments, silicon carbide, nitrogen-doped silicon carbide, boron-and-nitrogen-doped silicon carbide, and combinations thereof, including combinations with oxygen-doped silicon carbide, may be used.

[0079] As described, the precursors employed in forming the silicon carbide film can include silicon-containing precursors, at least some of which have at least one Si-H bond and / or at least one Si-Si bond. In certain embodiments, the silicon-containing precursors have at most one hydrogen atom per silicon atom. Thus, for example, a precursor with one silicon atom has at most one hydrogen atom bonded to the silicon atom; a precursor with two silicon atoms has one hydrogen atom bonded to one silicon atom and optionally another hydrogen atom bonded to a second silicon atom; a precursor with three silicon atoms has at least one hydrogen atom bonded to one silicon atom and optionally another one or two hydrogen atoms bonded to one or two of the remaining silicon atoms, and so on. Furthermore, the silicon-containing precursor may include at least one Si-O bond, at least one Si-N bond, and / or at least one Si-C bond. While any number of suitable precursors can be used in forming silicon carbide films, at least some of the precursors will include silicon-containing precursors having at least one Si—H or Si—Si bond, and optionally at least one Si—O bond, Si—N bond, and / or Si—C bond.

[0080] In certain embodiments, at least some of the carbon provided for the silicon carbide film is provided by one or more hydrocarbon moieties on the silicon-containing precursor. Such moieties may be from alkyl groups, alkene groups, alkyne groups, aryl groups, etc. In certain embodiments, the hydrocarbon group has a single carbon atom to minimize steric hindrance of the Si-H and / or Si-Si bond cleavage reactions during deposition. However, the precursor is not limited to a single carbon group; more carbon atoms may be used, such as 2, 3, 4, 5, or 6 carbon atoms. In certain embodiments, the hydrocarbon group is linear. In certain embodiments, the hydrocarbon group is cyclic.

[0081] In some embodiments, the silicon-containing precursor falls into the chemical classes, it being understood that other chemical classes of silicon-containing precursors may be employed and the silicon-containing precursor is not limited to the chemical classes listed below.

[0082] In some embodiments, the silicon-containing precursor can be a siloxane. In some embodiments, the siloxane can be cyclic. The cyclic siloxane can include cyclotetrasiloxanes, such as 2,4,6,8-tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), and heptamethylcyclotetrasiloxane (HMCTS). Other cyclic siloxanes can also include, but are not limited to, cyclotrisiloxane and cyclopentasiloxane. An embodiment using a cyclic siloxane is a ring structure that can introduce porosity into the oxygen-doped silicon carbide film, with the size of the pores corresponding to the radius of the ring. For example, the cyclotetrasiloxane ring can have a radius of about 6.7 Angstroms.

[0083] In some embodiments, siloxanes may have a three-dimensional structure or a cage structure. Cage siloxanes have silicon atoms crosslinked with each other through oxygen atoms to form polyhedra or any three-dimensional structure. An example of a cage siloxane precursor molecule is silsesquioxane. Cage siloxane structures are described in more detail in commonly owned U.S. Patent No. 6,576,345 to Cleemput et al., which is incorporated by reference in its entirety and for all purposes. Like cyclic siloxanes, cage siloxanes can introduce porosity into oxygen-doped silicon carbide films. In some embodiments, the porous scales are mesopores.

[0084] In some embodiments, the siloxane may be linear. Examples of suitable linear siloxanes include, but are not limited to, disiloxanes, such as pentamethyldisiloxane (PMDSO) and tetramethyldisiloxane (TMDSO), and trisiloxanes, such as hexamethyltrisiloxane and heptamethyltrisiloxane.

[0085] In some embodiments, the silicon-containing precursor can be an alkylsilane or other hydrocarbon-substituted silane. An alkylsilane comprises a central silicon atom to which one or more alkyl groups and one or more hydrogen atoms are attached. In certain embodiments, any one or more of the alkyl groups contain 1-5 carbon atoms. The hydrocarbon group can be saturated or unsaturated (e.g., alkene (e.g., vinyl), alkyne, and aromatic groups). Examples include, but are not limited to, trimethylsilane (3MS), triethylsilane, pentamethyldisilamethane ((CH3)2Si-CH2-Si(CH3)3)), and dimethylsilane (2MS).

[0086] In some embodiments, the silicon-containing precursor can be an alkoxysilane. An alkoxysilane comprises a central silicon atom to which one or more alkoxy groups and one or more hydrogen atoms are attached. Examples include, but are not limited to, trimethoxysilane (TMOS), dimethoxysilane (DMOS), methoxysilane (MOS), methyldimethoxysilane (MDMOS), diethoxymethylsilane (DEMS), dimethylethoxysilane (DMES), and dimethylmethoxysilane (DMMOS).

[0087] Additionally, disilane, trisilane, or other higher order silanes may be used instead of monosilane. One such disilane from the alkylsilane family is hexamethyldisilane (HMDS). Another such disilane from the alkylsilane family is pentamethyldisilane (PMDS). Other types of alkylsilanes include alkylcarbosilanes, which can have branched polymeric structures with not only carbon bonded to silicon atoms, but also alkyl groups bonded to silicon atoms. Examples include dimethyltrimethylsilylmethane (DTMSM) and bis-dimethylsilylethane (BDMSE). In some embodiments, one of the silicon atoms can have a carbon-containing or hydrocarbon-containing group attached, and one of the silicon atoms can have a hydrogen atom attached.

[0088] In some embodiments, two or more different chemical sources may be used. For example, one chemical source may include silicon and a second chemical source may include carbon. In some embodiments, the silicon-containing chemical source may be TEOS or any of the silanes as described above. In some embodiments, the carbon-containing chemical source may include methane, alkanes (such as ethane (C2H6)), alkenes (such as ethylene (C2H4)), and alkynes (such as C2H3).

[0089] When depositing silicon carbide, multiple silicon-containing precursors can be present in the process gas. For example, a siloxane and an alkylsilane can be used together, or a siloxane and an alkoxysilane can be used together. The relative proportions of the individual precursors can be selected based on the chemical structure of the precursor selected and the application of the resulting silicon carbide film.

[0090] Some silicon carbide films of the multi-layer stack may have high breakdown voltage and low leakage current. An example of a breakdown voltage achieved by certain disclosed embodiments is about 4 MV / cm. An example of a low leakage current achieved by certain disclosed embodiments is about 1E-8 at 2 MV / cm.

[0091] In some embodiments, the process conditions can substantially preserve the Si-C bonds, and if present, the Si-O and Si-N bonds in the as-deposited layer of the silicon carbide film. Accordingly, the reaction conditions adjacent to the substrate provide selective scission of Si-H and / or Si-Si bonds, e.g., extraction of hydrogen from the scission Si-H bonds, but the reaction conditions do not provide extraction of oxygen from the Si-O bonds, nitrogen from the Si-N bonds, or carbon from the Si-C bonds. However, carbon may be extracted from the Si-C bonds by introduction of a co-reactant such as oxygen, as described below. In general, the reaction conditions described are present at the exposed surface of the substrate (the surface on which the silicon carbide film is deposited). Such reaction conditions may also be present a little above the substrate, e.g., from about 0.5 micrometers to about 150 millimeters above the substrate. In practice, precursor activation may occur in the gas phase well above the substrate. Although some variability may be acceptable for a particular application, suitable reaction conditions are typically uniform or nearly uniform across the entire exposed surface of the substrate.

[0092] The silicon-containing precursor is typically delivered in the environment adjacent to the substrate along with other species, particularly a carrier gas. In some implementations, the silicon-containing precursor is present along with radical species and other species, including other reactive species and / or carrier gases. In some embodiments, the silicon-containing precursor may be introduced as a mixture. The silicon-containing precursor may be mixed with an inert carrier gas upstream from the deposition reaction surface. Examples of inert carrier gases include, but are not limited to, nitrogen (N2), argon (Ar), and helium (He). Additionally, the silicon-containing precursor may be introduced in a mixture having a major and minor species, with the minor species containing some element or structural feature (e.g., ring structure, cage structure, unsaturated bond, etc.) that is present in a relatively low concentration in the silicon carbide film. Multiple precursors may be present in equimolar or relatively equal proportions, as appropriate, to form the first trunk or matrix of the resulting silicon carbide film. In other embodiments, the relative amounts of the different precursors are not substantially equimolar.

[0093] To deposit silicon oxide, one or more silicon-containing precursors may be used. Suitable silicon-containing precursors for use in accordance with the disclosed embodiments include polysilanes (H3Si(SiH2) n —SiH3), where n≧0. Examples of silanes include silane (SiH4), disilane (Si2H6), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, t-butylsilane, dimethylsilane, diethylsilane, di-t-butylsilane, allylsilane, sec-butylsilane, thexylsilane, isoamylsilane, t-butyldisilane, and di-t-butyldisilane.

[0094] Halosilanes contain at least one halogen group and may or may not contain hydrogen and / or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes, and fluorosilanes. Although halosilanes, particularly fluorosilanes, may form reactive halide species capable of etching silicon materials when the plasma is struck, in some embodiments, the halosilane may not be introduced into the chamber when the plasma is struck, so that the formation of reactive halide species from the halosilane may be mitigated. Specific chlorosilanes include tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, t-butyldimethylchlorosilane, thexyldimethylchlorosilane, and the like.

[0095] Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes include mono-, di-, tri-, and tetra-aminosilane (HSi(NH), HSi(NH), HSi(NH), and Si(NH), respectively), as well as substituted mono-, di-, tri-, and tetra-aminosilanes, such as t-butylaminosilane, methylaminosilane, tert-butylsilane amine, bis(tert-butylamino)silane (SiH(NHC(CH))(BTBAS), tert-butylsilylcarbamate, SiH(CH)-(N(CH), SiHCl-(N(CH), (Si(CH)NH), etc. An additional example of an aminosilane is trisilylamine (N(SiH). In various embodiments, a plasma may not be used during deposition of any layer of the multilayer stack. In some embodiments, a plasma may be used during deposition of any layer of the multilayer stack.

[0096] Examples of techniques for depositing some of the layers described herein are provided in U.S. Pat. No. 8,741,394, U.S. Pat. No. 9,028,924, and U.S. Patent Application Publication No. 2011 / 0236594, which are hereby incorporated by reference in their entireties.

[0097] Oxygen doping may be adjusted using specific techniques such as temperature, pressure, plasma power and frequency, as well as oxygen-containing reactant gas flow relative to other gas flows. The amount of oxygen doping can affect the associated etch contrast. For example, silicon nitride may have a specific etch contrast of about 0% to about 65% relative to oxygen-doped silicon carbide, while the same material may have a lower etch contrast to oxygen-doped silicon carbide at 66% at the same process conditions. Silicon nitride has an etch contrast to silicon oxide in hot phosphoric acid (H3PO4). Silicon oxide carbide can be used to provide both an etch contrast to silicon nitride in a wet etch with H3PO4 and an etch contrast to silicon oxide in a wet etch with hydrofluoric acid (HF).

[0098] Returning to FIG. 10, in operation 1086, any pattern may be etched on the substrate. For example, in some embodiments, a trench or via may be etched through the multi-layer stack, and the etch may be performed using existing dielectric etch techniques without any metal residue or risk of degrading the etch profile. For example, the operation may involve recessing a silicon oxide material, which may be performed because oxygen-doped silicon carbide, silicon nitride, and polysilicon can provide sufficient etch contrast for etching silicon oxide. In various embodiments, the etch chemistry used to pattern the stack includes one or more of tetrafluoromethane (CF4), fluoromethane (CFH3), difluoromethane (CH2F2), octafluorocyclobutane (C4F8), and nitrogen trifluoride (NF3). Patterning may be performed to etch the trench or via. In some embodiments, the operation may not include a silicon oxide recess operation.

[0099] During patterning in operation 1086, the etch contrast may vary depending on the materials of the stack. In some embodiments, the silicon oxide is recessed after etching the trench to selectively remove the silicon oxide from the sidewalls of the trench, thereby causing the trench to have different widths at certain depths in the stack. For example, a trench may be etched into a stack containing silicon nitride, silicon oxide, and polysilicon, with silicon oxide between the silicon nitride and polysilicon, and then the silicon oxide may be etched into the trench to recess the sidewalls of the trench with the silicon oxide. The recessing of the silicon oxide may be performed using a special etch chemistry that has an etch contrast to other materials on the substrate. In various embodiments, silicon oxide etches about 5 to about 1000 times faster than silicon nitride, polysilicon, and oxygen-doped silicon carbide.

[0100] Silicon oxide is provided as an example. In some embodiments, the dielectric material is recessed to selectively remove it from the sidewalls of the trench. Examples of dielectric materials include, but are not limited to, silicon oxide and doped silicon oxide.

[0101] In operation 1090, the sacrificial silicon nitride material is selectively etched from the substrate relative to other materials on the substrate (polysilicon, oxide, oxygen-doped silicon carbide). This operation may be performed in a wet etching process using the etch contrast of the sacrificial silicon nitride relative to these materials. For example, in some embodiments, the sacrificial silicon nitride may be etched by immersing the substrate in hot H3PO4. This etching results in the formation of spaces where silicon nitride previously occupied on the substrate. The etch selectivity of silicon nitride relative to other materials on the substrate may be from about 10 to about 1000, where the other materials are silicon oxide, oxygen-doped silicon carbide, and polysilicon.

[0102] In operation 1092, tungsten is deposited in the space previously occupied by the sacrificial silicon nitride material on the substrate. For example, tungsten can be deposited in the horizontal space between the oxide layers. In some embodiments, a metal-containing liner is deposited prior to depositing the metal. The metal-containing liner may be titanium nitride, aluminum oxide, or tungsten carbonitride in various embodiments. The metal deposited in operation 1092 may be deposited directly on or above the metal-containing liner. For example, tungsten may be deposited on a titanium nitride liner.

[0103] FIG. 11A shows an exemplary process flow diagram illustrating operations performed according to certain disclosed embodiments. In this example, in operation 1282, a substrate is provided. In operation 1284, a metal-free film stack is deposited as described with respect to FIG. 9A and FIG. 12A below. In operation 1285, a trench is etched into the metal-free stack. In various embodiments, the etched trench has a high aspect ratio, such as from about 5:1 to about 20:1. In various embodiments, the width of the trench is from about 30 nm to about 200 nm. In operation 1286, the silicon oxide may be recessed. In various embodiments, the silicon oxide recess is performed such that the etch rate of the silicon oxide is at least about 50 times faster than other materials in the metal-free stack. The silicon oxide recess may be performed using any suitable etch chemistry, including, but not limited to, halogen-based chemistries such as hydrofluoric acid. In operation 1290, the sacrificial silicon nitride layer is selectively removed. In various embodiments, the sacrificial silicon nitride layer is etched using a phosphorus-based wet etch chemistry, such as using diluted H3PO4. In operation 1292, tungsten is deposited in the location where the sacrificial silicon nitride was removed.

[0104] FIG. 11B illustrates yet another exemplary process flow diagram depicting operations performed in accordance with certain disclosed embodiments. In this example, in operation 1182, a substrate is provided. In operation 1184, a film stack is deposited such that multiple sets of the following film stacks are deposited one on top of the other from top to bottom: oxygen doped silicon carbide, silicon nitride, doped polysilicon, silicon oxide, doped polysilicon, and silicon nitride. In operation 1186a, the silicon oxide may be recessed. In operation 1186b, the polysilicon is filled into the substrate. In some embodiments, the material used to fill the substrate may be a dielectric material or a semiconductor material. In operation 1190, the sacrificial silicon nitride layer is selectively removed. In operation 1192, tungsten is deposited where the sacrificial silicon nitride was removed.

[0105] 12A-12E show exemplary diagrams of various substrates undergoing certain disclosed process embodiments.

[0106] In FIG. 12A, compared to FIG. 9, a substrate is provided having oxygen doped silicon carbide 400, a sacrificial silicon nitride layer 402, polysilicon 100, silicon oxide 101, and oxygen doped silicon carbide 400. In FIG. 12B, a trench is formed and the silicon oxide 101 is recessed. In FIG. 12C, polysilicon 100 is deposited to fill the space recessed from the silicon oxide 101. In some embodiments, the polysilicon 100 may be etched back in an operation between FIG. 12C and FIG. 12D. In FIG. 12D, the sacrificial silicon nitride layer 402 is selectively removed, such as by wet etching. In FIG. 12E, tungsten 440 is deposited in the space previously occupied by the silicon nitride layer. The presence of polysilicon 100 in the structure avoids etching tungsten during the formation of the vias and recessing the silicon oxide, since tungsten is not deposited on the sidewalls of previously patterned trenches or vias.

[0107] In various embodiments, silicon nitride is replaced by oxygen-doped silicon carbide, which may be deposited by PECVD, and silicon nitride replaces tungsten and titanium nitride. The materials used can be etched using techniques developed for OPOP and ONON etching processes, so there is a low risk of high aspect ratio etching of the film stack and no risk of metal residues. Silicon oxide can be recessed as well, since oxygen-doped silicon carbide, silicon nitride, and polysilicon provide sufficient etch contrast. Finally, silicon nitride can be removed and backfilled with titanium nitride and tungsten, and the roughness of the tungsten becomes unimportant, since the surface is now constrained by dielectric sidewalls.

[0108] Another approach is to replace tungsten and titanium nitride with doped polysilicon. This would potentially simplify the etching process by changing the number of etched materials from five to three for high aspect ratio etches. However, doped and undoped polysilicon have very different wet etch crates, so the doped polysilicon can be removed by wet etching and then backfilled with titanium nitride and tungsten. Examples of dopants include boron, phosphorus, and arsenic.

[0109] Various dopant precursors may be used during deposition of the doped polysilicon to form the doped polysilicon. In some embodiments, a suitable dopant source may be elemental arsenic, or arsine (AsH), or arsenic doped silicate glass (ASG), or diarsenic trioxide (As2O3) and / or diarsenic pentoxide (As2O 5+ In other embodiments, the suitable dopant source may be elemental boron or a boron compound such as diborane (B2H6), and the suitable dopant precursor may be a boron compound such as an alkyl borate. For example, trimethyl borate (TMB) (shown below) is a particular alkyl borate that can function well as a dopant precursor to form the dopant source boron trioxide (BO3); however, other dopant precursors may also be suitable to form various boron-based dopant sources. Additionally, dopant sources based on elements other than boron and arsenic may also be suitable, such as dopant sources based on gallium or phosphorus. [ka]

[0110] Trimethyl borate is one suitable dopant precursor, but other compounds may also function as suitable dopant precursors. For example, other suitable boron-based dopant precursors may include: trimethyl boron, triethyl boron, triphenyl boron, tri-i-propyl borate, tri-n-amyl borate, B-tribromo borazine, tris(pentafluorophenyl) borane, and other similar boron-containing compounds, as well as other alkyl borates, such as triethyl borate, triisopropyl borate, and tri-n-butyl borate. Also, dopant sources based on elements other than boron may be suitable. Examples include dopant sources based on gallium, phosphorus, arsenic, or other elements suitable for doping semiconductor substrates, such as trivalent and pentavalent elements. Arsenic-based dopant precursors may include, but are not limited to, alkylarsine, alkoxyarsine, and aminoarsine chemical families, including but not limited to the following specific compounds: arsine, triethylarsenate, trimethylarsine, triethylarsine, triphenylarsine, triphenylarsine oxide, ethylenebis(diphenylarsine), tris(dimethylamino)arsine, and As(OR)3, where R is -CH3 or -C2H5, or other alkyl groups (including saturated and unsaturated alkyl groups), and other similar arsenic-containing compounds. Phosphorus-based dopant precursors may include, but are not limited to, phosphine (PH3), triethylphosphine oxide, trimethyl phosphate, trimethyl phosphite, and other similar phosphorus-containing compounds. The choice of dopant precursor is usually determined by the ease of integration into existing delivery systems, purity of the film, and overall cost.

[0111] Heavily boron doped polysilicon can have a higher wet etch rate, thus providing an etch contrast to other materials on the substrate during patterning. The wet etch rate increases with increasing boron concentration, thereby providing an etch contrast that is tunable depending on the dopant concentration.

[0112] "Silicon oxide" as used herein includes all stoichiometric possibilities for Si with integer values of x and y and non-integer values of x and y, and some H that can bond to Si or O therein. x O y It is to include all stoichiometric possibilities regarding. For example, "silicon oxide" includes compounds having the formula SiOn, where 1 < n < 2 and n can be an integer value or a non-integer value. "Silicon oxide" can include sub-stoichiometric compounds such as SiO 1.8 and the like. Also, "silicon oxide" includes silicon dioxide (SiO2) and silicon monoxide (SiO). Further, "silicon oxide" includes both natural and synthetic variations and all crystal structures and molecular structures including tetrahedral coordination where oxygen atoms surround the central silicon atom. Also, "silicon oxide" includes amorphous silicon oxide and silicates.

[0113] "Silicon nitride" as used herein is to include all stoichiometric possibilities regarding Si x N y and Si x N y includes integer values of x and y and non-integer values of x and y such as x = 3 and y = 4. For example, "silicon nitride" includes compounds having the formula SiN n where 1 < n < 2 and n can be an integer value or a non-integer value. "Silicon nitride" can include sub-stoichiometric compounds such as SiN 1.8 and the like. Also, "silicon nitride" includes Si3N4, and silicon nitride having some and / or interstitial hydrogen (SiNH), and silicon nitride having trace amounts and / or interstitial oxygen (SiON). Also, "silicon nitride" includes both natural and synthetic variations and all lattice structures, crystal structures, and molecular structures including trigonal α-silicon nitride, hexagonal β-silicon nitride, and cubic γ-silicon nitride. Also, "silicon nitride" includes amorphous silicon nitride and can include silicon nitride having trace impurities. Also, hydrogen will be present in SiN and may be bonded to Si or N, or both. The hydrogen concentration in silicon nitride can range from about 1% to about 30%.

[0114] 12F-12M show further exemplary patterning schemes in simplified diagram form for various substrates during certain disclosed process embodiments.

[0115] In FIG. 12F, a substrate is provided having silicon oxide 1201 with doped polysilicon 1210 directly above and below the silicon oxide 1201, as well as oxygen doped silicon carbide 1200 and a sacrificial silicon nitride layer 1202, with an etch stop layer 1230 below the lower sacrificial silicon nitride layer 1202. In FIG. 12F, a trench 1250 is formed. In FIG. 12H, the silicon oxide 1201 is recessed at 1240. In FIG. 12I, polysilicon 1260 is deposited to fill the space created by the trench 1250 and the recessed silicon oxide 1201. In FIG. 12J, the doped polysilicon 1260 may be etched back as shown. In some embodiments, the polysilicon 1260 may be made into a thin film transistor. In FIG. 12K, a gate 1270 is deposited in the trench. In FIG. 12L, the sacrificial silicon nitride layer 1202 is selectively removed, such as by a wet etch, to create feature 1225. In FIG. 12M, tungsten 1240 is deposited in the feature 1225 previously occupied by the silicon nitride layer. This avoids etching tungsten during the formation of the via and recessing of the silicon oxide because the presence of polysilicon 1210 in the structure prevents tungsten from being deposited on the sidewalls of the previously patterned trench or via. Although certain materials are described with respect to FIGS. 12F-12M, it should be understood that the multilayer stack of FIG. 12F may include other dielectric materials having different etch contrasts than those shown or described herein. Certain disclosed embodiments may be used to form devices other than transistors, such as capacitors or other memory cells, within the recessed areas of schemes such as those depicted in FIG. 12J.

[0116] (Device) 13 depicts a schematic diagram of an embodiment of an atomic layer deposition (ALD) and / or chemical vapor deposition (CVD) process station 1300 having a process chamber body 1302 for maintaining a low pressure environment. Multiple process stations 1300 may be included in a common low pressure process tool environment. For example, FIGS. 14 and 15 depict exemplary embodiments of a multi-station processing tool. In some embodiments, one or more hardware parameters of the ALD process station 1300, including those described in more detail below, may be programmatically adjusted by one or more computer controllers 1350.

[0117] The process station 1300 is in fluid communication with a reactant delivery system 1301a that delivers process gases to a distributed showerhead 1306. The reactant delivery system 1301a includes a mixing vessel 1304 for blending and / or adjusting process gases, such as a silicon precursor gas or a second reactant gas (e.g., an oxygen-containing reactant, a carbon-containing reactant, etc.), delivered to the showerhead 1306. One or more mixing vessel inlet valves 1320 may control the introduction of process gases to the mixing vessel 1304. A plasma may be delivered to the showerhead 1306 or may be generated within the process station 1300. The reactant delivery system 1301a may be configured to deliver process gases to a substrate provided to the process station 1300.

[0118] As an example, the embodiment of FIG. 13 includes a vaporization point 1303 for vaporizing a liquid reactant that is fed to a mixing vessel 1304. In some embodiments, the vaporization point 1303 may be a heated vaporizer. Saturated vapor of the reactant from such a vaporizer may condense in downstream delivery piping. When incompatible gases are exposed to the condensed reactant, small particles may be generated. These small particles may clog the piping, interfere with valve operation, or contaminate the substrate. Some approaches to solving these problems involve purging and / or evacuating the delivery piping to remove residual reactants. However, purging the delivery piping may increase the cycle time of the process station and reduce the throughput of the process station. Therefore, in some embodiments, the delivery piping downstream of the vaporization point 1303 may be heat traced. Also, in some embodiments, the mixing vessel 1304 may be heat traced as well. In one non-limiting example, the piping downstream of the vaporization point 1303 has a ramped temperature profile ranging from about 100° C. to about 150° C. at the mixing vessel 1304 .

[0119] In some embodiments, liquid precursors or liquid reactants may be vaporized with a liquid injector. For example, the liquid injector may inject a pulse of liquid reactant into a carrier gas stream upstream of the mixing vessel. In one embodiment, the liquid injector may vaporize the reactant by flashing the liquid from high pressure to low pressure. In another example, the liquid injector may atomize the liquid into dispersed droplets, which are then vaporized in a heated delivery line. Smaller droplets may vaporize faster than larger droplets, reducing the delay between liquid injection and complete vaporization. Faster vaporization may reduce the length of piping downstream from the vaporization point 1303. In one scenario, the liquid injector may be attached directly to the mixing vessel 1304. In another scenario, the liquid injector may be attached directly to the showerhead 1306.

[0120] In some embodiments, a liquid flow controller (LFC) may be provided upstream of the vaporization point 1303 to control the mass flow rate of the liquid to be vaporized and delivered to the process station 1300. For example, the LFC may include a thermal mass flow meter (MFM) disposed downstream of the LFC. The plunger valve of the LFC may then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller in electronic communication with the MFM. However, it may take more than a second to stabilize the liquid flow rate using feedback control. This may extend the time to dose the liquid reactant. Therefore, in some embodiments, the LFC may be dynamically switched between feedback and direct control modes. In some embodiments, this may be done by disabling the sensing tube and PID controller of the LFC.

[0121] The showerhead 1306 distributes process gases toward the substrate 1319. In the embodiment illustrated in Figure 13, the substrate 1319 is shown disposed below the showerhead 1306 and resting on a pedestal 1308. The showerhead 1306 may have any suitable shape and any suitable number and arrangement for dispersing process gases to the substrate 1319.

[0122] In some embodiments, the pedestal 1308 may be raised and lowered to expose the substrate 1319 to the volume between the substrate 1319 and the showerhead 1306. Of course, in some embodiments, the height of the pedestal may be programmatically adjusted by a suitable computer controller 1350.

[0123] In another scenario, the plasma density may be altered during a plasma activation cycle in an embodiment process to ignite a plasma by adjusting the height of the pedestal 1308. At the end of a processing step, the pedestal 1308 may be lowered to allow removal of the substrate 1319 from the pedestal 1308 during another substrate transfer step.

[0124] In some embodiments, the pedestal 1308 may be temperature controlled via a heater 1310. In some embodiments, the pedestal 1308 may be heated to a temperature of at least about 250° C., or in some embodiments, less than about 300° C., such as about 250° C., during deposition of the silicon nitride film as described in the disclosed embodiments. In some embodiments, the pedestal is set to a temperature between about 50° C. and about 300° C., such as a temperature between about 200° C. and about 275° C. In some embodiments, the pedestal is set to a temperature between about 50° C. and about 300° C. In some embodiments, the pedestal is set to a temperature between about 200° C. and about 275° C.

[0125] Additionally, in some embodiments, pressure control for the process station 1300 may be provided by a butterfly valve 1312. As shown in the embodiment of Figure 13, the butterfly valve 1312 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of the process station 1300 may be adjusted by varying the flow rate of one or more gases introduced to the process station 1300.

[0126] In some embodiments, the position of the showerhead 1306 may be adjusted relative to the pedestal 1308 to change the volume between the substrate 1319 and the showerhead 1306. It will further be appreciated that the vertical position of the pedestal 1308 and / or the showerhead 1306 may be changed by any suitable mechanism within the scope of this disclosure. In some embodiments, the pedestal 1308 may include a rotation axis for rotating the orientation of the substrate 1319. It will be appreciated that in some embodiments, one or more of these exemplary adjustments may be performed programmatically by one or more suitable computer controllers 1350.

[0127] In some embodiments, where the plasma may be used as described above, the showerhead 1306 and pedestal 1308 are in electrical communication with a radio frequency (RF) power supply 1314 and matching network 1316 for powering the plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power supply 1314 and matching network 1316 may be operated at any suitable power to form a plasma having a particular composition of radical species. Examples of suitable powers are included above. Similarly, the RF power supply 1314 may provide RF power at a suitable frequency. In some embodiments, the RF power supply 1314 may be configured to control high and low frequency RF power sources independently of one another. Examples of low frequency RF frequencies may include, but are not limited to, frequencies between 0 kHz and 500 kHz. Examples of high frequency RF frequencies may include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz, or greater than about 13.56 MHz, or greater than 27 MHz, or greater than 180 MHz, or greater than 60 MHz. Of course, any suitable parameters may be adjusted, either discretely or continuously, to provide plasma energy to the surface reactions.

[0128] In some embodiments, the plasma may be monitored in situ by one or more plasma monitors. In one scenario, the plasma power may be monitored by one or more voltage, current sensors (e.g., VI probes). In another scenario, the plasma density and / or process gas concentration may be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters may be programmatically adjusted based on measurements from such in situ plasma monitors. For example, OES sensors may be used in a feedback loop to provide programmatic control of the plasma power. Of course, in some embodiments, other monitors may be used to monitor the plasma and other process characteristics. Such monitors include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

[0129] In some embodiments, instructions to the controller 1350 may be provided via input / output control (IOC) sequence instructions. In one example, instructions to set the conditions for a process step may be included in the corresponding recipe step of the process recipe. In some cases, the process recipe steps may be arranged in a sequence such that all instructions for a process step are executed simultaneously with that process step. In some embodiments, instructions to set one or more reactor parameters may be included in a recipe step. For example, a first recipe step may include instructions to set a flow rate of an inert gas and / or a reactant gas (e.g., a first precursor such as a silicon precursor), instructions to set a flow rate of a carrier gas (such as argon), and a time delay instruction for the first recipe step. A subsequent second recipe step may include instructions to adjust or stop the flow rate of the inert gas and / or a reactant gas, instructions to adjust a flow rate of a carrier gas or a purge gas, and a time delay instruction for the second recipe step. A third recipe step may include instructions to adjust a flow rate of a second reactant gas, instructions to adjust a flow rate of a carrier gas or a purge gas, and a time delay instruction for the third recipe step. A subsequent fourth recipe step may include instructions to adjust or stop the flow of inert and / or reactive gases, instructions to adjust the flow of carrier or purge gases, and time delay instructions for the fourth recipe step. Of course, these recipe steps may be further subdivided and / or repeated in any suitable manner within the scope of the disclosed embodiments.

[0130] As previously mentioned, one or more process stations may be included in a multi-station processing tool. FIG. 14 shows a schematic diagram of an embodiment of a multi-station processing tool 1400 with an input load lock 1402 and an output load lock 1404, one or both of which may include a remote plasma source. A robot 1406 is configured to move a wafer from a cassette loaded through a pod 1408 into the input load lock 1402 through an atmospheric pressure port 1410. The wafer is placed by the robot 1406 on a pedestal 1412 in the input load lock 1402, the atmospheric pressure port 1410 is closed, and the load lock is pumped down. If the input load lock 1402 includes a remote plasma source, the wafer may be subjected to a remote plasma treatment in the load lock before being introduced into the processing chamber 1414. Additionally, the wafer may also be heated in the input load lock 1402, for example to remove moisture and adsorbed gases. The chamber transport port 1416 to the processing chamber 1414 is then opened and another robot (not shown) places the wafer into the reactor and onto the pedestal of the first station shown within the reactor for processing. Although the embodiment depicted in Figure 14 includes a load lock, it will be appreciated that in some embodiments the wafer may enter directly into the process station.

[0131] The illustrated processing chamber 1414 includes four process stations, numbered 1-4 in the embodiment shown in FIG. 14. Each station includes a heated pedestal (indicated by reference number 1418 for station 1) and a gas line inlet. Of course, in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between an ALD mode and a plasma-assisted ALD process mode. Additionally or alternatively, in some embodiments, the processing chamber 1414 may include one or more corresponding pairs of ALD and plasma-assisted ALD process stations. Although the illustrated processing chamber 1414 includes four stations, it should be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0132] 14 illustrates one embodiment of a wafer handling system 1490 for transferring wafers within the processing chamber 1414. In some embodiments, the wafer handling system 1490 may transfer wafers between various process stations and / or between process stations and load locks. Of course, any suitable wafer handling system may be employed. Non-limiting examples include a wafer carousel or a wafer handling robot.

[0133] Of course, in some embodiments, a low pressure transfer chamber may be included in a multi-station processing tool to facilitate transfer between multiple processing chambers. For example, FIG. 14 illustrates a schematic of another embodiment of a multi-station processing tool 1500. In the embodiment illustrated in FIG. 14, the multi-station processing tool 1400 includes multiple processing chambers 1414 including multiple process stations (numbered 1-4). The processing chambers 1414 are interfaced with a low pressure transport chamber 1404 including a robot 1406 configured to transport substrates between the processing chambers 1414 and a load lock 1419. An atmospheric substrate transfer module 1410 including an atmospheric robot 1412 is configured to facilitate transfer of substrates between the load lock 1419 and the pod 1408.

[0134] 14 also illustrates one embodiment of a system controller 1450 that may be employed to control process conditions and hardware states of the process tool 1400. The system controller 1450 may include one or more memory devices 1456, one or more mass storage devices 1454, and one or more processors 1452. The processor 1452 may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc.

[0135] In some embodiments, the system controller 1450 controls all activity of the process tool 1400. The system controller 1450 executes system control software 1458 stored in mass storage device 1454, loaded into memory device 1456, and executed by processor 1452. Alternatively, the control logic may be hard-coded into the controller 1450. Application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), and the like may be used for these purposes. In the following discussion, wherever "software" or "code" is used, functionally equivalent hard-coded logic may be used instead. The system control software 1458 may include instructions that control the timing, mixture of gases, gas flow rates, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor position, and other parameters of a particular process performed by the process tool 1400. The system control software 1458 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components used to perform the various process tool processes. The system control software 1458 may be coded in any suitable computer readable programming language.

[0136] In some embodiments, the system control software 1458 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. Other computer software and / or programs stored in the mass storage device 1454 and / or memory device 1456 associated with the system controller 1450 may be employed in some embodiments. Examples of such programs or portions of programs include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0137] The substrate positioning program may include program code for process tool components used to load the substrate onto the pedestal 1418 and to control the spacing between the substrate and other parts of the process tool 1400.

[0138] The process gas control program may include code for controlling gas composition (e.g., silicon precursor gases, and carbon-containing gases, carrier gases, and purge gases as described herein) and flow rates, and optionally, code for flowing gases into one or more process stations prior to deposition to stabilize the pressure in the process station. The pressure control program may include code for controlling the pressure in the process station by, for example, adjusting a throttle valve in the exhaust system of the process station, gas flow into the process station, etc.

[0139] The heater control program may include code for controlling the current to a heating unit used to heat the substrate, or the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate.

[0140] The plasma control program may include code for setting RF power levels applied to process electrodes in one or more process stations according to certain embodiments herein.

[0141] The pressure control program may include code for maintaining pressure in a reaction chamber according to some embodiments herein.

[0142] In some embodiments, there may be a user interface associated with the system controller 1450. The user interface may include a display screen, a graphical software display of equipment and / or process conditions, and a user input device such as a pointing device, keyboard, touch screen, microphone, etc.

[0143] In some embodiments, the parameters adjusted by the system controller 1450 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (e.g., RF bias power levels), etc. These parameters may be provided to a user in the form of a recipe, which may be entered using a user interface.

[0144] Signals for monitoring the process may be provided from various process tool sensors through analog and / or digital input connections of the system controller 1450. Signals for controlling the process may be output at analog and digital output connections of the process tool 1400. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Data from these sensors may be used in conjunction with appropriately programmed feedback and control algorithms to maintain process conditions.

[0145] The system controller 1450 may provide program instructions for implementing the deposition processes described above. The program instructions may control various process parameters such as DC power levels, RF bias power levels, pressure, temperature, etc. The instructions may control the parameters to operate the in situ deposition of a film stack according to various embodiments described herein.

[0146] The system controller 1450 typically includes one or more memory devices and one or more processors configured to execute instructions that cause the device to perform methods in accordance with the disclosed embodiments. Machine-readable media containing instructions for controlling process operations in accordance with the disclosed embodiments may also be coupled to the system controller 1450.

[0147] In some implementations, the system controller 1450 is part of a system, which may be part of the examples described above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling system operations before, during, and after processing of a semiconductor wafer or substrate. Such electronics may be referred to as a "controller" and may control various components or subcomponents of one or more systems. The system controller 1450 may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and motion settings, and wafer transfer in and out of tools and other transfer tools and / or load locks connected or interfaced with the particular system, depending on the processing conditions and / or type of system.

[0148] Broadly, the system controller 1450 may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include chips that store program instructions in the form of firmware, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute the program instructions (e.g., software). The program instructions may be in the form of various individual settings (or program files) communicated to the system controller 1450 and may be instructions that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0149] The system controller 1450 may, in some implementations, be part of or coupled to a computer that is integrated with, coupled to, or otherwise networked with the system, or a combination thereof. For example, the system controller 1450 may reside in the "cloud" or be all or part of a fab host computer system, thereby enabling remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a fabrication operation, examine the history of past fabrication operations, or examine trends or performance metrics from multiple fabrication operations to modify parameters of a current process, set processing steps following a current process, or initiate a new process. In some embodiments, a remote computer (e.g., a server) may provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some embodiments, the system controller 1450 receives instructions in the form of data, which specify parameters for each process step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the system controller 1450 is configured to interface with or control. Thus, as described above, the system controller 1450 may be distributed, such as by including one or more separate controllers that are networked together and cooperate toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would include one or more integrated circuits in the chamber that communicate with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) and coupled to control the processes in the chamber.

[0150] Without being limited thereto, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0151] As described above, depending on the process step or steps being performed by the tool, the system controller 1450 may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to carry containers of wafers to or from tool locations and / or load ports within a semiconductor manufacturing factory.

[0152] 15 is a schematic diagram of one embodiment of a multi-station processing tool 1500 having an input load lock 1502 and an output load lock 1504, either or both of which may include a remote plasma source. An example of a commercial embodiment of a suitable tool is the Strata tool available from Lam Research Corporation of Fremont, Calif.

[0153] The illustrated processing tool 1500 includes four processing chambers 1510a, 1510b, 1510c, and 1510d. Each processing chamber includes four processing stations, labeled 1, 2, 3, and 4 in processing chamber 1510a. Each station includes a heated pedestal (shown for processing station 1 in processing chamber 1510a) and a gas line inlet. Of course, in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, a processing station may be switchable between PECVD, ALD, and plasma-assisted ALD process modes. Additionally or alternatively, in some embodiments, processing chamber 1510a may include one or more corresponding pairs of PECVD, ALD, and plasma-assisted ALD process stations. Although the illustrated processing chamber 1510b includes four stations 1, 2, 3, and 4, it should be understood that a processing chamber according to the present disclosure may have any suitable number of stations. Each station within each processing chamber may be used to process four different materials, with one material being deposited at each station. In some embodiments, each station may be used to deposit four different materials. In some embodiments, a single station processing chamber may be used. In some embodiments, a four station processing chamber may be used.

[0154] Additionally, while four processing chambers are shown in processing tool 1500, it should be understood that a processing tool may include more than four or less than four processing chambers, each having one or more processing stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments, a processing chamber may have three or fewer stations.

[0155] FIG. 15 includes a wafer handling system 1590 for transferring wafers within the processing tool 1500 between the processing chambers 1510a, 1510b, 1510c, and 1510d.

[0156] In some embodiments, the wafer handling system 1590 may transfer wafers between various process stations and / or between the process stations and load locks. Of course, any suitable wafer handling system may be employed. Non-limiting examples include a wafer carousel or a wafer handling robot.

[0157] 15 also illustrates one embodiment of a system controller 1550 that may be employed to control process conditions and hardware states of the process tool 1500. The system controller 1550 may include one or more memory devices 1556, one or more mass storage devices 1554, and one or more processors 1552. The processor 1552 may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc.

[0158] In some embodiments, the system controller 1550 controls all activity of the process tool 1500. The system controller 1550 executes system control software 1558 stored in mass storage device 1554, loaded into memory device 1556, and executed by processor 1552. Alternatively, the control logic may be hard-coded into the controller 1550. Application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), and the like may be used for these purposes. In the following discussion, wherever "software" or "code" is used, functionally equivalent hard-coded logic may be used instead. The system control software 1558 may include instructions that control the timing, mixture of gases, gas flow rates, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor position, and other parameters of a particular process performed by the process tool 1500. The system control software 1558 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components used to perform the various process tool processes. The system control software 1558 may be coded in any suitable computer readable programming language.

[0159] Controller 1550 may have any of the features described above with respect to controller 1450 .

[0160] Suitable apparatus for carrying out the methods disclosed herein are further described and illustrated in U.S. patent application Ser. No. 13 / 084,399, entitled "PLASMA ACTIVATED CONFORMAL FILM DEPOSITION," filed Apr. 11, 2011 (now U.S. Patent No. 8,728,956); and U.S. patent application Ser. No. 13 / 084,305, entitled "SILICON NITRIDE FILMS AND METHODS," filed Apr. 11, 2011, each of which is incorporated herein by reference in its entirety.

[0161] The apparatus / processes described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, but not necessarily, such tools / processes will be used or performed together in a common fabrication facility. Lithographic patterning of a film typically includes some or all of the following operations, each of which can be performed using many available tools: (1) applying photoresist onto a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing the photoresist using a hotplate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or X-ray light using a tool such as a wafer stepper; (4) developing the resist using a tool such as a wet bench to selectively remove and pattern the resist; (5) transferring the resist pattern to an underlying film or workpiece by using a dry etching tool or a plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

[0162] (experiment) Experiments were performed to etch high aspect ratio trenches in a multi-layer stack with multiple sets of metal-free layers between silicon dioxide layers and an ashable hardmask layer on the top silicon oxide layer. The set of metal-free layers included silicon-containing layers. The metal-free layers did not contain any tungsten. Between 4 and 12 sets of metal-free layers were present in the substrate. High aspect ratio features were etched and the resulting features exhibited smooth profiles with no line collapse.

[0163] A second experiment was conducted to recess the sidewalls of silicon oxide materials in a patterned multilayer stack having multiple sets of metal-free layers. Each set of metal-free layers included at least one silicon oxide layer. As the multilayer stack was patterned, the pillars of the multilayer stack were etched simultaneously such that the sidewalls of the silicon oxide layers were etched together throughout the multilayer pillars. The spaces between the pillars were negative features with aspect ratios of about 25:1 to about 35:1. An etch selectivity of at least 50:1 was achieved for silicon oxide versus other silicon-containing metal-free layers on the substrate. The etch was performed using 100:1 dilute HF. Highly isotropic etch selectivity was achieved for silicon oxide materials versus silicon nitride, polysilicon, and silicon oxide carbide materials.

[0164] (Conclusion) The ranges set forth herein include their endpoints. Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain modifications and variations may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Thus, the present embodiments are to be regarded as illustrative rather than restrictive, and the present embodiments are not to be limited to the details set forth herein.

Claims

1. 1. A method comprising: Providing a semiconductor substrate; depositing a multilayer stack of alternating sacrificial silicon nitride and non-oxide layers and another layer sandwiched between said non-oxide layers; Etching a trench or via through the multilayer stack of alternating sacrificial silicon nitride and non-oxide layers and the further layer; after etching the trench or the via, recessing the other layer in the multi-layer stack to form a recessed region; depositing a dielectric or semiconductor material into the trench or via; etching back the dielectric or semiconductor material in the trench or via to form smooth sidewalls, leaving the dielectric or semiconductor material in the recessed region; forming a space between the non-oxide layers after etching the trench; depositing a metal in the space to form a substrate including alternating metal and non-oxide layers and the trench etched into at least one dielectric barrier layer; A method comprising:

2. 10. The method of claim 1, The method, wherein the at least one dielectric barrier layer comprises oxygen-doped silicon carbide.

3. 3. The method of claim 2, The method of claim 1, wherein the oxygen concentration in the oxygen-doped silicon carbide ranges from 1 atomic % to 65 atomic %.

4. 10. The method of claim 1, The method wherein the non-oxide layer comprises a material selected from the group consisting of silicon oxycarbide, polysilicon, and a second silicon nitride having a wet etch contrast to the sacrificial silicon nitride.

5. 5. The method of claim 4, The method wherein the non-oxide layer comprises polysilicon, and the polysilicon is doped.

6. 6. The method of claim 5, The method wherein the non-oxide layer comprises polysilicon, the polysilicon being doped with a dopant selected from the group consisting of boron, phosphorus, and arsenic.

7. 10. The method of claim 1, The method, wherein the metal comprises tungsten.

8. 10. The method of claim 1, The method wherein the metal comprises molybdenum.

9. 10. The method of claim 1, The method of claim 1, wherein the sacrificial silicon nitride layer has a wet etch contrast to the non-oxide layer and the at least one dielectric barrier layer of at least 10:1 in 100:1 dilute hydrofluoric or phosphoric acid.

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