Imaging device

Abstract

To speed up AD conversion and a frame rate and to reduce power consumption by reducing a load of signal wiring for reference signals.SOLUTION: An imaging device includes: a plurality of photoelectric conversion elements that are arranged in a first direction and a second direction, which intersect each other, each of the plurality of photoelectric conversion elements accumulating a charge corresponding to an amount of incident light; a plurality of pixel circuits that respectively output pixel signals corresponding to the charges accumulated in the plurality of photoelectric conversion elements; a plurality of comparators that compare each of the plurality of pixel signals outputted from the plurality of pixel circuits with a reference signal; a digital signal generator that, on the basis of comparison results from the plurality of comparators, generates a digital signal in which the plurality of pixel signals are converted from analog to digital; and a plurality of switches that switch whether the reference signal is inputted to the plurality of comparators.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] In imaging devices, a vertical signal line is typically provided for each pixel column, and the pixel signals of each pixel in the pixel column are transmitted via the vertical signal line to a column signal processing circuit, where signal processing such as analog-to-digital conversion (hereinafter referred to as AD conversion) is performed.

[0003] However, when the number of pixels in an imaging device increases, the distance to the column signal processing circuit varies depending on the position of the pixel, which causes a delay in the propagation of the pixel signal on the vertical signal line and a change in the signal level. To solve such problems, a technology has been proposed in which the vertical signal line is divided into multiple lines and AD conversion is performed for each divided vertical signal line (see Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2023 / 058720A1 Summary of the Invention [Problem to be solved by the invention]

[0005] To perform AD conversion on a pixel signal, it is necessary to compare the pixel signal with a reference signal, generally called a ramp signal. In Patent Document 1, a separate AD converter is provided for each of the divided vertical signal lines. This requires that the reference signal be distributed to multiple AD converters, which increases the load on the signal wiring that transmits the reference signal and takes time for AD conversion, which may be an obstacle to increasing the frame rate and reducing power consumption.

[0006] Therefore, the present disclosure provides an imaging device that can achieve faster AD conversion and frame rate and lower power consumption by reducing the load on the signal wiring of the reference signal. [Means for solving the problem]

[0007] In order to solve the above problems, according to the present disclosure, there is provided a liquid crystal display device comprising: a plurality of photoelectric conversion elements arranged in a first direction and a second direction intersecting each other, each of which accumulates a charge according to the amount of incident light; a plurality of pixel circuits each outputting a pixel signal corresponding to the charge accumulated in the plurality of photoelectric conversion elements; a plurality of comparators that compare each of the plurality of pixel signals output from the plurality of pixel circuits with a reference signal; a digital signal generator that generates digital signals by performing analog-to-digital conversion on the pixel signals based on comparison results of the comparators; and a plurality of switches that switch whether or not the reference signal is to be input to the plurality of comparators.

[0008] The plurality of switches may sequentially select one of the plurality of comparators to input the reference signal so that the reference signal is not input to two or more of the comparators at the same time.

[0009] a signal line that transmits the pixel signals output from two or more of the pixel circuits arranged in the second direction; a conversion circuit that performs analog-to-digital conversion on the plurality of pixel signals transmitted through the signal lines, The conversion circuit includes: The digital signal generator may include the comparator.

[0010] A plurality of the signal lines arranged in the first direction; The converter may further comprise a plurality of the conversion circuits connected to the plurality of signal lines.

[0011] the signal line includes a plurality of split signal lines that are split along the second direction, each of the plurality of divided signal lines transmits the pixel signals output from two or more of the pixel circuits arranged along the second direction; One or more of the comparators may be provided for each of the plurality of divided signal lines.

[0012] Each of the plurality of comparators may be provided for each of the plurality of pixel circuits.

[0013] The plurality of switches may switch, for each pixel group including two or more of the pixel circuits arranged in the first direction or the second direction, whether or not to input the reference signal to the corresponding two or more of the comparators.

[0014] The plurality of switches may sequentially switch to select one of a plurality of pixel groups corresponding to a pixel region of interest from among a plurality of pixel groups each including two or more of the pixel circuits arranged in the first direction or the second direction.

[0015] The plurality of switches may sequentially switch to select one of two or more pixel groups adjacent in the first direction or the second direction among a plurality of pixel groups each including two or more of the pixel circuits arranged in the first direction or the second direction.

[0016] The digital signal generator may include a counter that outputs, as the digital signal, a count value corresponding to a timing at which the pixel signal and the reference signal match in each of the plurality of comparators.

[0017] At least one of the plurality of switches is a first transistor of a first conductivity type that switches between conducting and blocking the first node and the second node in response to a switching control signal; The input / output terminal may further include a second transistor of a second conductivity type that switches whether the first node and the second node are conductive or cut off in response to an inverted switching control signal having an inverse logic to the switching control signal.

[0018] At least one of the plurality of switches is a third transistor of a first conductivity type having a source and a drain connected to the first node and a gate to which the inverted switching control signal is input; a fourth transistor of the first conductivity type having a source and a drain connected to the second node and a gate to which the inverted switching control signal is input; a fifth transistor of a second conductivity type having a source and a drain connected to the first node and a gate to which the switch control signal is input; The sixth transistor may include a sixth transistor of the second conductivity type having a source and a drain connected to the second node and a gate to which the switching control signal is input.

[0019] a capacitor disposed between the second node and a reference voltage node; The second node may be connected to input nodes of the plurality of comparators.

[0020] At least one of the plurality of switches is a first transistor that switches between conducting and blocking the first node and the second node in response to a switching control signal; a voltage source that outputs a bias voltage between the third node and the fourth node; a first switch, a second switch, and a third switch connected in series between the third node and a reference voltage node; a fourth switch and a fifth switch connected in series between the fourth node and the first node; a first capacitor connected between a connection node between the first switch and the second switch and a connection node between the fourth switch and the fifth switch; a second capacitor connected between the second node and the reference voltage node; the switching control signal output from a connection node between the second switch and the third switch is input to a gate of the first transistor; When the first node and the second node are made conductive, the first switch, the third switch, and the fourth switch are cut off, and the second switch and the fifth switch are made conductive; When the first node and the second node are cut off, the first switch, the third switch, and the fourth switch may be made conductive, and the second switch and the fifth switch may be cut off.

[0021] At least one of the plurality of switches is a first transistor that switches between conducting and blocking the first node and the second node in response to a switching control signal; a first switch, a second switch, and a third switch connected in series between a first reference voltage node and a second reference voltage node; a fourth switch and a fifth switch connected in series between the second reference voltage node and the first node; a first capacitor connected between a connection node between the first switch and the second switch and a connection node between the fourth switch and the fifth switch; a second capacitor connected between the second node and the second reference voltage node; the switching control signal output from a connection node between the second switch and the third switch is input to a gate of the first transistor; When the first node and the second node are made conductive, the first switch, the third switch, and the fourth switch are cut off, and the second switch and the fifth switch are made conductive; When the first node and the second node are cut off, the first switch, the third switch, and the fourth switch may be made conductive, and the second switch and the fifth switch may be cut off.

[0022] a plurality of preamplifiers each having a plurality of source follower circuits arranged between the plurality of switches and the plurality of comparators, the preamplifiers converting impedances of the reference signals output from the plurality of switches; Each of the plurality of source follower circuits comprises: a first transistor to whose gate the reference signal output from the corresponding switch is input; a second transistor of a first conductivity type connected to a drain side of the first transistor, turned on when the corresponding switch outputs the reference signal, and turned off when the corresponding switch does not output the reference signal; and a third transistor of the second conductivity type connected to a source side of the first transistor, turned on when the corresponding switch outputs the reference signal, and turned off when the corresponding switch does not output the reference signal.

[0023] Each of the plurality of source follower circuits comprises: a fourth transistor acting as a current source; a fifth transistor for adjusting the voltage of the corresponding input node of the comparator; The fourth transistor, the third transistor, the fifth transistor, the first transistor, and the second transistor may be connected in this order between a first reference voltage node and a second reference voltage node, or the fourth transistor, the fifth transistor, the third transistor, the first transistor, and the second transistor may be connected in this order.

[0024] a plurality of preamplifiers each having a plurality of source follower circuits arranged between the plurality of switches and the plurality of comparators, the preamplifiers converting impedances of the reference signals output from the plurality of switches; Each of the plurality of source follower circuits comprises: a first transistor to whose gate the reference signal output from the corresponding switch is input; a second transistor of a first conductivity type connected to a drain side of the first transistor, turned on when the corresponding switch outputs the reference signal, and turned off when the corresponding switch does not output the reference signal; a third transistor connected to a source side of the first transistor and functioning as a current source; a fourth transistor for adjusting the voltage of the corresponding input node of the comparator; a fifth transistor connected to a gate of the fourth transistor and turned on when the corresponding switch outputs the reference signal to turn on the fourth transistor; The input / output circuit may further include a sixth transistor connected to a gate of the fourth transistor and turned on to turn off the fourth transistor when the corresponding switch does not output the reference signal.

[0025] The input / output circuit may further include a precharge circuit that supplies a precharge signal to the source of the first transistor in a source follower circuit that does not output the reference signal from the source of the first transistor among the plurality of source follower circuits.

[0026] the precharge circuit further includes a replica circuit having the same circuit configuration as the plurality of source follower circuits and generating, as the precharge signal, a reference voltage of the reference signal when the plurality of comparators start a comparison operation; The precharge circuit may supply the reference voltage generated by the replica circuit to a source of the first transistor in a source follower circuit among the plurality of source follower circuits that does not input the reference signal to a corresponding comparator. [Brief description of the drawings]

[0027] [Figure 1] FIG. 1 is a block diagram showing a configuration of an example of an electronic device commonly applicable to the embodiments. [Diagram 2] FIG. 1 is a block diagram showing an example configuration of an imaging device according to each embodiment of the present disclosure. [Diagram 3] FIG. 1 is a schematic diagram illustrating signal processing for a pixel signal according to existing technology. [Figure 4A] FIG. 13 is a diagram showing an example in which an imaging device according to the present disclosure is formed using a stacked CIS with a two-layer structure. [Figure 4B] FIG. 13 is a diagram showing an example in which an imaging device according to the present disclosure is formed using a stacked CIS with a three-layer structure. [Diagram 5] FIG. 1 is a schematic diagram showing a structure of an example of an imaging device. [Figure 6] 5 is a schematic diagram illustrating signal processing for a pixel signal according to the present disclosure. FIG. [Figure 7] FIG. 13 is a schematic diagram showing an example in which a pixel array portion is divided into a plurality of regions in the vertical direction. [Figure 8] 5 is a schematic diagram illustrating signal processing for pixel signals in the imaging device according to the present disclosure. [Figure 9] 1 is a schematic diagram for explaining division of a VSL according to an imaging device according to the present disclosure. [Figure 10A] A diagram showing the selection of the topmost of the four column readout units. [Figure 10B] A diagram showing the selection of the second from the top out of four column readout units. [Figure 11] 11 is a graph showing the relationship between the number of reference signal switches that are turned on simultaneously and the load on a reference signal line. [Figure 12] 12A and 12B are graphs showing the relationship between the settling time and the signal band of a reference signal on a reference signal line. [Figure 13] FIG. 2 is a timing chart of the imaging apparatus according to the first embodiment. [Figure 14] FIG. 4 is a circuit diagram showing a first example of a reference signal switcher. [Figure 15] FIG. 11 is a circuit diagram showing a second example of a reference signal switcher. [Figure 16] FIG. 11 is a circuit diagram showing a third example of a reference signal switcher. [Figure 17] FIG. 13 is a circuit diagram showing a fourth example of a reference signal switcher. [Figure 18] FIG. 13 is a circuit diagram showing a fifth example of a reference signal switcher. [Figure 19A] FIG. 11 is a block diagram of the periphery of a column readout unit of an imaging device according to a second embodiment. [Figure 19B] FIG. 11 is a block diagram of the periphery of a column readout unit of an imaging device according to a second embodiment. [Figure 20] FIG. 2 is a circuit diagram showing a first example of the internal configuration of a preamplifier. [Figure 21] FIG. 4 is a circuit diagram showing a second example of the internal configuration of a preamplifier. [Figure 22]FIG. 11 is a circuit diagram showing a third example of the internal configuration of a preamplifier. [Diagram 23] FIG. 11 is a circuit diagram showing a fourth example of the internal configuration of a preamplifier. [Figure 24] 11 is a graph showing the settling time of a reference signal input to a column readout section when the output node of a source follower circuit is precharged and when it is not precharged. [Diagram 25] FIG. 11 is a circuit diagram of the periphery of a column readout unit 17 of an imaging device according to a third embodiment. [Figure 26A] 13A to 13C are diagrams illustrating a precharge operation of the imaging apparatus according to the third embodiment. [Figure 26B] 13A to 13C are diagrams illustrating a precharge operation of the imaging apparatus according to the third embodiment. [Figure 27] FIG. 26C is a timing diagram corresponding to the illustrations of FIGS. 26A and 26B. [Figure 28] FIG. 13 is a block diagram of an imaging apparatus according to a fourth embodiment. [Figure 29] FIG. 29 is a diagram showing an example of the locations of two column readout units in FIG. 28. [Diagram 30] FIG. 13 is a block diagram of an imaging device according to a modified example of the fourth embodiment. [Diagram 31] FIG. 31 is a diagram showing the locations of two column readout units in FIG. 30. [Diagram 32] FIG. 13 is a timing chart of an imaging apparatus according to a fourth embodiment. [Diagram 33] FIG. 13 is a timing chart of an imaging device according to a modified example of the fourth embodiment. [Diagram 34] 13A to 13C are diagrams illustrating an imaging apparatus according to a fifth embodiment. [Diagram 35] FIG. 13 is a diagram for explaining an imaging device according to a modified example of the fifth embodiment. [Diagram 36] FIG. 13 is a diagram for explaining an imaging apparatus according to a sixth embodiment. [Figure 37] FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system. [Figure 38] FIG. 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, an embodiment of an imaging device will be described with reference to the drawings. The following description will focus on the main components of the imaging device, but the imaging device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0029] (Electronic devices commonly applicable to each embodiment) Fig. 1 is a block diagram showing an example of a configuration of an electronic device that can be commonly applied to each embodiment. In Fig. 1, the electronic device 1000 includes an optical system 1002, a control unit 1003, an imaging device 1004, an image processing unit 1005, a memory 1006, a storage unit 1007, a display unit 1008, an interface (I / F) unit 1009, and an input device 1012. Here, a digital still camera, a digital video camera, a mobile phone or a smartphone with an imaging function, or the like can be applied as the electronic device 1000. In addition, a surveillance camera, an in-vehicle camera, a medical camera, or the like can also be applied as the electronic device 1000.

[0030] The imaging device 1004 includes a plurality of photoelectric conversion elements arranged, for example, in a matrix array. The photoelectric conversion elements convert received light into electric charges through photoelectric conversion. The imaging device 1004 includes a drive circuit for driving the plurality of photoelectric conversion elements, a signal processing circuit for reading electric charges from each of the plurality of photoelectric conversion elements and generating image data based on the read electric charges, and a power supply circuit for supplying power to the drive circuit.

[0031] The optical system 1002 includes a main lens formed by a combination of one or more lenses, and a mechanism for driving the main lens, and forms an image of image light (incident light) from a subject on a light receiving surface of the imaging device 1004 via the main lens. The optical system 1002 also includes an autofocus mechanism that adjusts the focus according to a control signal, and a zoom mechanism that changes the zoom ratio according to a control signal. The electronic device 1000 may also make the optical system 1002 detachable so that it can be replaced with another optical system 1002.

[0032] The image processing unit 1005 executes a predetermined image processing on the pixel data output from the imaging device 1004. For example, the image processing unit 1005 is connected to a memory 1006 such as a frame memory, and writes the image data output from the imaging device 1004 to the memory 1006. The image processing unit 1005 executes a predetermined image processing on the pixel data written to the memory 1006, and writes the image-processed pixel data back to the memory 1006. The memory 1006 can store one frame's worth of pixel data as image data.

[0033] The storage unit 1007 is a non-volatile memory such as a flash memory or a hard disk drive, and stores image data output from the image processing unit 1005 in a non-volatile manner. The display unit 1008 includes a display device such as an LCD (Liquid Crystal Display) and a drive circuit for driving the display device, and can display an image based on the image data output from the image processing unit 1005. The I / F unit 1009 is an interface for transmitting the image data output from the image processing unit 1005 to the outside. For example, a USB (Universal Serial Bus) can be applied as the I / F unit 1009. However, the I / F unit 1009 may be an interface that can be connected to a network by wired communication or wireless communication.

[0034] The input device 1012 includes an operator for accepting user input, etc. If the electronic device 1000 is, for example, a digital still camera, a digital video camera, or a mobile phone or smartphone with an imaging function, the input device 1012 may include a shutter button for instructing the imaging device 1004 to capture an image, or an operator for realizing the function of the shutter button.

[0035] The control unit 1003 includes a processor such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory), and controls the overall operation of the electronic device 1000 using the RAM as a work memory in accordance with a program pre-stored in the ROM. For example, the control unit 1003 can control the operation of the electronic device 1000 in response to a user input received by an input device 1012. The control unit 1003 can also control an autofocus mechanism in the optical system 1002 based on the image processing result of the image processing unit 1005.

[0036] (First embodiment) Fig. 2 is a block diagram of an imaging device 1004 according to the first embodiment of the present disclosure. In Fig. 2, the imaging device 1004 includes a pixel array unit 11, a vertical driving unit 12, a system control unit 13, a DAC (Digital to Analog Converter) 14, a column control unit 15, a plurality of reference signal switches (switches) 16, a plurality of column readout units 17, a column signal processing unit 18, and a horizontal driving unit 19. The imaging device 1004 can be configured as a CMOS image sensor (CIS) in which each of these units is integrally formed using a complementary metal oxide semiconductor (CMOS).

[0037] The pixel array section 11 includes a plurality of pixels 10 arranged in a first direction (eg, horizontal direction or row direction) X and a second direction (eg, vertical direction or column direction) Y.

[0038] In the pixel array section 11, each pixel 10 includes a photoelectric conversion element that generates an electric charge in response to received light, and a pixel circuit that outputs a pixel signal based on the electric charge generated by the photoelectric conversion element. The vertical drive section 12 drives each pixel 10 included in the pixel array section 11 row by row, causing each pixel 10 to output a pixel signal. At this time, the vertical drive section 12 drives each pixel 10 sequentially according to the row order, causing each pixel 10 to output a pixel signal. In other words, the vertical drive section 12 functions as a read control circuit that controls the reading of electric charges from the photoelectric conversion element and the output of the pixel signal.

[0039] The system control unit 13 controls the operation timing of each of the vertical drive unit 12, the DAC 14, the column control unit 15, the multiple column readout units 17, the column signal processing unit 18, and the horizontal drive unit 19 in synchronization with a vertical synchronization signal VSYNC. The vertical synchronization signal VSYNC is a periodic signal of a predetermined frequency (e.g., 60 (Hz (Hertz))) indicating the imaging timing.

[0040] The DAC 14 generates a predetermined reference signal by DA (Digital to Analog) conversion. For example, a sawtooth ramp signal is used as the reference signal. The DAC 14 supplies the reference signal to the column signal processing unit 18.

[0041] In the imaging device 1004 of the first embodiment, each of a plurality of vertical signal lines VSL extending in a second direction (column direction) Y of the pixel array section 11 is divided into a plurality of parts, and a plurality of column control sections 15 are provided corresponding to the divided plurality of divided signal lines.

[0042] The column control units 15 perform switching control of the reference signal switchers 16 in response to an instruction from the system control unit 13. The reference signal switchers 16 switch whether or not to input the reference signal generated by the DAC 14 to the column reading units 17.

[0043] Each of the multiple column readout units 17 has multiple analog-to-digital converters (hereinafter, ADC), and each ADC converts a pixel signal into a digital signal. As described later, the ADC has a comparator (also called a comparator) 20 and a counter 30 (digital signal generator). The multiple reference signal switches 16 described above are provided corresponding to the multiple column readout units 17. The multiple reference signal switches 16 sequentially select one of the multiple column readout units 17 and input a reference signal to it, so that a reference signal is not input to two or more column readout units 17 at the same time.

[0044] The column signal processing unit 18 performs signal processing such as CDS (Correlated Double Sampling) processing on the digital pixel signals AD converted by the multiple column readout units 17 for each column. The column signal processing unit 18 outputs digital pixel signals (pixel data) after the signal processing. The pixel data output from the column signal processing unit 18 is supplied to the image processing unit 1005.

[0045] The horizontal driver 19 has a shift register, an address decoder, and the like, and causes the column signal processor 18 to sequentially output pixel data that has been subjected to signal processing for each column.

[0046] (Processing flow using existing technology) Next, the signal processing for pixel signals by the existing technology will be briefly described. Fig. 3 is a schematic diagram showing the signal processing for pixel signals by the existing technology. In Fig. 3, the comparator 20 and the counter 30 are included in, for example, the column readout unit 17 in Fig. 2, and the logic circuit is included in, for example, the column signal processing unit 18 in Fig. 2.

[0047] The analog pixel signal output from the pixel 10 is supplied to the comparator 20. The comparator 20 is further supplied with a reference signal RAMP as a reference signal from the DAC 14. The reference signal RAMP is a signal whose level (voltage value) decreases stepwise in a time series according to, for example, a predetermined clock pulse. The comparator 20 compares the pixel signal with the reference signal RAMP and supplies the comparison result to the counter 30. For example, when the level of the reference signal RAMP is higher than the level of the pixel signal, the comparator 20 outputs a High difference signal to the counter 30. On the other hand, when the level of the reference signal RAMP is equal to or lower than the level of the pixel signal, the comparator 20 inverts the output and outputs a Low difference signal to the counter 30.

[0048] The counter 30 counts the time from when the reference signal RAMP starts to drop in voltage to when it becomes equal to or lower than the pixel signal in response to the difference signal input from the comparator 20 during each of a P-phase (Preset Phase) period and a D-phase (Data Phase) period, and outputs each count result to the logic circuit 40. Note that the P-phase period is a period in which the reset level of the pixel signal is detected in CDS processing, and the D-phase period is a detection period in which the signal level of the pixel signal is detected in CDS processing.

[0049] The logic circuit 40 performs CDS processing and AD conversion processing based on the count result during the P phase period and the count result during the D phase period input from the counter 30, to generate and output a digital pixel signal (pixel data).

[0050] (Structure of the imaging device 1004 applicable to each embodiment) Next, a general description will be given of the structure of the image pickup device 1004 applicable to each embodiment. The image pickup device 1004 according to the embodiment can be formed by a stacked structure in which a plurality of semiconductor chips are stacked.

[0051] As an example, the imaging device 1004 can be formed with a two-layer structure in which semiconductor chips are stacked in two layers. Fig. 4A is a diagram showing an example in which the imaging device 1004 according to each embodiment is formed with a two-layer stacked CIS. In the structure of Fig. 4A, a pixel section 2010 is formed in a first layer of semiconductor chips, and a memory + logic section 2011 is formed in a second layer of semiconductor chips.

[0052] The pixel section 2010 includes at least a pixel array section 11. The memory + logic section 2011 can include, for example, a vertical drive section 12, a system control section 13, a DAC 14, a column signal processing section 18, a horizontal drive section 19, and an interface for communicating between the imaging device 1004 and the outside. The memory + logic section 2011 can also include, for example, a memory for storing pixel data output from the column signal processing section 18.

[0053] As shown on the right side of FIG. 4A, the imaging device 1004 is configured as one solid-state imaging element 2000a by bonding the semiconductor chip of the first layer and the semiconductor chip of the second layer together while being in electrical contact with each other.

[0054] As another example, the imaging device 1004 can be formed with a three-layer structure in which semiconductor chips are stacked in three layers. FIG. 4B is a diagram showing an example in which the imaging device 1004 according to each embodiment is formed with a three-layer stacked CIS. In the structure of FIG. 4B, a pixel section 2010 is formed in a semiconductor chip of a first layer, a memory section 2012 is formed in a semiconductor chip of a second layer, and a logic section 2011' is formed in a semiconductor chip of a third layer. In this case, the logic section 2011' can include a vertical drive section 12, a system control section 13, a DAC 14, a column signal processing section 18, a horizontal drive section 19, and an interface for communicating between the imaging device 1004 and the outside. The memory section 2012 can include a memory for storing pixel data output from, for example, the column signal processing section 18.

[0055] As shown on the right side of Figure 4B, the imaging device 1004 is constructed as a single solid-state imaging element 2000b by bonding the first layer semiconductor chip, the second layer semiconductor chip, and the third layer semiconductor chip together while maintaining electrical contact.

[0056] (Laminated structure) As shown in FIG. 4A and FIG. 4B, the imaging device 1004 according to the first embodiment can be configured by stacking a plurality of semiconductor substrates. The number of layers is arbitrary. FIG. 5 is a schematic diagram showing a stacked structure of the imaging device 1004 according to the first embodiment. In the example of FIG. 5, the imaging device 1004 applies the solid-state imaging element 2000a having a two-layer structure described with reference to FIG. 4A. Here, in the case of a back-illuminated image sensor, a photoelectric conversion element is formed on a first layer 2010a of a substrate, and a pixel circuit that converts the charge generated by the photoelectric conversion element into a pixel signal and outputs the pixel signal is formed on a second layer 2010b of the substrate. The first layer 2010a and the second layer 2010b configure the pixel unit 2010.

[0057] 5, photoelectric conversion units 100 including photoelectric conversion elements and transistors for controlling the reading of charges from the photoelectric conversion elements are arranged in a matrix on the first layer 2010a. Circuit units 101 including pixel circuits for converting charges read from the photoelectric conversion units 100 into pixel signals are arranged in a matrix on the second layer 2010b in correspondence with the photoelectric conversion units 100 on the first layer 2010a. More specifically, the circuit units 101 are arranged between the first layer 2010a and the second layer 2010b in a one-to-one relationship with the photoelectric conversion units 100 that correspond to their positions on the first layer 2010a, while being in electrical contact with each other.

[0058] In each embodiment, the circuit unit 101 (denoted as Pixel-CMP(1) in the figure) further includes a part of the comparator 20. That is, in each embodiment, the comparator 20 is divided into at least two parts: a first circuit (denoted as CMP(1)) to which a pixel signal is directly supplied from the pixel circuit, and a second circuit and a third circuit (denoted as CMP(2), (3)) to which the output of the first circuit is supplied. The first circuit includes, for example, a circuit that compares the pixel signal output from the pixel circuit with a reference signal RAMP supplied from the DAC 14.

[0059] 5, for a memory+logic section 2011, a vertical drive section 12, a counter 30, a logic circuit 40, a peripheral circuit 50, and an interface circuit 60 (also referred to as an IF circuit in the drawing) are arranged.

[0060] The peripheral circuit 50 includes a DAC 14. Furthermore, the interface circuit 60 is an interface for transmitting and receiving signals between the imaging device 1004 serving as the solid-state imaging element 2000a and the outside.

[0061] 5, the vertical drive section 12 is arranged at one end in the row direction of the memory+logic section 2011 (the right end in the example of the figure) along the column direction of the pixel array section 11. The interface circuit 60 is arranged at the other end in the row direction of the memory+logic section 2011 (the left end in the example of the figure) along the column direction of the pixel array section 11.

[0062] Further, a second circuit 210 in which the comparator 20 is divided is disposed for the memory+logic section 2011. In the example of FIG. 5, the second circuit 210 is disposed at one end and the other end in the column direction (top and bottom ends in the example of FIG. 5) along the row direction of the memory+logic section 2011. The second circuit 210 is provided for each column in the pixel array section 11. In the example of FIG. 5, the second circuit 210 is provided at both ends in the column direction of the memory+logic section 2011 along the row direction of the pixel array section 11.

[0063] The second circuit 210 is shared by a plurality of circuit units 101 arranged along a column in the second layer 2010b. For example, each second circuit 210 arranged at one end (e.g., the upper end in the figure) of the memory+logic unit 2011 in the column direction is shared by each circuit unit 101 arranged in the half on the one end side (the upper half in the example of FIG. 5) of each circuit unit 101 arranged on the second layer 2010b for each column. Similarly, each second circuit 210 arranged at the other end (e.g., the lower end in FIG. 5) of the memory+logic unit 2011 in the column direction is shared by each circuit unit 101 arranged in the half on the other end side (the lower half in the example of FIG. 5) of each circuit unit 101 arranged on the second layer 2010b for each column.

[0064] Each pixel 10 (each photoelectric conversion unit 100 and each circuit unit 101) is scanned in the column direction, i.e., the vertical direction, as indicated by the arrows. The output from each pixel 10 (each circuit unit 101) is transferred to the memory + logic unit 2011 row by row.

[0065] FIG. 6 is a schematic diagram illustrating the signal processing for a pixel signal according to the present disclosure. The comparator 20 according to the present disclosure can be configured by being divided into a plurality of circuits. In the example of FIG. 6, the comparator 20 is divided into three circuits, a first-stage comparator 201, a middle-stage comparator 202, and a latter-stage comparator 203. The first-stage comparator 201 corresponds to the first circuit described with reference to FIG. 5, and includes a circuit for comparing, for example, a pixel signal output from the pixel 10 with a reference signal RAMP supplied from the DAC 14. The middle-stage comparator 202 and the latter-stage comparator 203 correspond to the second circuit described with reference to FIG. 5, and compare the output of the first circuit with a threshold value. The middle-stage comparator 202 and the latter-stage comparator 203 can also be configured as one circuit.

[0066] (Example of dividing the pixel array section 11 into regions) By dividing the pixel array unit 11 into multiple regions in the vertical direction and transferring pixel signals for each divided region, it is possible to shorten the transmission distance of the pixel signals. Figure 7 is a schematic diagram showing an example in which the pixel array unit 11 is divided into multiple regions in the vertical direction.

[0067] 7, in the pixel section 2010, the pixel array section 11 is vertically divided into four regions: pixel regions 11Up1 and 11Up2, and pixel regions 11Dwn1 and 11Dwn2. Of these, the pixel regions 11Up1 and 11Up2 are the first and second pixel regions on the upper side, respectively, and the pixel regions 11Dwn1 and 11Dwn2 are the first and second pixel regions on the lower side, respectively.

[0068] In the memory+logic section 2011, an analog circuit 80Up1 and a logic circuit 40Up1 are arranged at a position corresponding to the pixel region 11Up1, and an analog circuit 80Up2 and a logic circuit 40Up2 are arranged at a position corresponding to the pixel region 11Up2. Similarly, an analog circuit 80Dwn1 and a logic circuit 40Dwn1 are arranged at a position corresponding to the pixel region 11Dwn1, and an analog circuit 80Up2 and a logic circuit 40Dwn2 are arranged at a position corresponding to the pixel region 11Up2.

[0069] Each of the analog circuits 80Up1, 80Up2, 80Dwn1, and 80Dwn2 includes, for example, a pixel circuit, a comparator 20, and a counter 30.

[0070] The pixel signals output from each pixel in the pixel area 11Up1 are transferred row by row from an end of the pixel area 11Up1 to the memory+logic unit 2011 via the vertical signal lines VSL in the pixel area 11Up1, and input to the analog circuit 80Up1. The output of the analog circuit 80Up1 is input to the logic circuit 40Up1. The same applies to the pixel areas 11Up2, 11Dwn1, and 11Dwn2.

[0071] 7, the pixel signal output from each pixel is transferred over a distance of at most ¼ of the distance between both ends in the column direction of the pixel array unit 11. However, the pixel signal is transmitted via the vertical signal line VSL, which is the same as the existing configuration. Therefore, the parasitic capacitance of the shortened vertical signal line VSL only affects the settling in the pixel 10, and is unlikely to lead to improved characteristics such as noise effects.

[0072] In contrast, in each embodiment of the present disclosure, the distance over which a pixel signal corresponding to the charge generated in the pixel 10 is transmitted to the first-stage comparator 201 is extremely short, so that the settling time in the pixel 10 can be shortened, thereby making it possible to speed up the readout time of the charge from the pixel 10. In addition, since the vertical signal line VSL, which is a large load, is connected to the output side of the first-stage comparator 201, the bandwidth of the signal transferred to the vertical signal line VSL can be narrowed, enabling low noise.

[0073] In the above description, the vertical signal line VSL is divided in the vertical direction to reduce the load on the vertical signal line VSL. However, even if the number of divisions of the vertical signal line VSL is increased, it is difficult to increase the processing speed and the frame rate because wiring to the input terminal of the ADC provided in the column signal processing unit 18 is required. For example, in a two-layer stacked structure, the number of divisions of the vertical signal line VSL is limited to about two. Also, since one ADC corresponds to multiple pixels, the load at the pixel switching point becomes heavy.

[0074] For this reason, in the imaging device 1004 according to the present disclosure, one first-stage comparator 201 is arranged for each divided region of the vertical signal line VSL in the middle layer (second layer of the first substrate) of the three-layer configuration consisting of the first and second layers of the first substrate and the second substrate, and the output of the first-stage comparator 201 is switched by a select switch and input to the middle-stage comparator 202. With this configuration, the load on the VSL is reduced by the increased number of divisions of the vertical signal line VSL, enabling faster processing and a higher frame rate.

[0075] Furthermore, in the imaging device 1004 according to the present disclosure, a plurality of pixels (photoelectric conversion units 100) are connected to one first-stage comparator 201. That is, in the imaging device 1004 according to the present disclosure, the connection is switched at two points, between the pixel and the first-stage comparator 201, and between the first-stage comparator 201 and the middle-stage comparator 202. This can reduce the load at the pixel switching points (i.e., the VSL wiring).

[0076] FIG. 8 is a schematic diagram illustrating signal processing for pixel signals in the imaging device 1004 according to the present disclosure.

[0077] 8, similarly to the above-mentioned Fig. 6, the comparator 20 includes a first-stage comparator 201, a middle-stage comparator 202, and a second-stage comparator 203, and the output of the second-stage comparator 203 is input to a counter 30, and the output of the counter 30 is input to a logic circuit 40. In addition, a reference signal RAMP output from a DAC 14 is supplied to the first-stage comparator 201.

[0078] In the configuration shown in FIG. 8, the first-stage comparator 201 includes N (N≧1) pixels 101, 102, . . . , 10 N The pixel signals from the first comparator 201 and the pixels 101, 102, ..., 10 N M (M≧2) pixel / first-stage comparator units 2501, 2502, ..., 250 M The output of the second comparator 202 is input to the middle comparator 202.

[0079] Among these, the pixel first-stage comparator units 2501, 2502, ..., 250 M Each of the pixels 101, 102, ..., 10 N are arranged on a first layer 2010a of the pixel section 2010, and the initial-stage comparators 201 are arranged on a second layer 2010b of the pixel section 2010. The configuration after the middle-stage comparator 202 is arranged in the memory+logic section 2011.

[0080] 9 is a schematic diagram for explaining division of the VSL in the imaging device 1004 according to the present disclosure. In FIG. 9, the first-stage comparators 2011 to 201 M are also indicated as a first circuit CMP(1). The rear stage circuit 251 includes a middle stage comparator 202 and a rear stage comparator 203 (second and third circuits CMP(2), (3)), and a counter 30.

[0081] As shown in FIG. 9, the VSL includes pixel first-stage comparator units 2501, 2502, . . . , 250 M In each of the pixels 101 to 10 N and the corresponding first stage comparator 2011~201 M That is, in the imaging device 1004 according to the present disclosure, the VSL is connected to the first-stage comparators 2011 to 201 M It is divided into each.

[0082] In this manner, in the imaging device 1004 according to the present disclosure, each of the pixels 101 to 10 N and the first-stage comparator 201, and each pixel and first-stage comparator unit 2501 to 250 M Therefore, VSL is configured to switch the signal path between the first comparators 2011 to 201 M This reduces the load on the VSL wiring.

[0083] (Detailed Description of the First Embodiment) As shown in FIG. 2, the imaging device 1004 according to the first embodiment has a plurality of reference signal switches 16 corresponding to a plurality of column readout units 17. The plurality of reference signal switches 16 are switched on or off by the column control unit 15. When the plurality of reference signal switches 16 are turned on, they input reference signals to the corresponding column readout units 17. Two or more reference signal switches 16 are not turned on at the same time. The column control unit 15 sequentially turns on the plurality of reference signal switches 16 to sequentially input reference signals to the plurality of column readout units 17. This reduces the load on the reference signal line Sramp that transmits the reference signal, and can speed up the AD conversion process and the frame rate.

[0084] 10A and 10B show an example in which four column readout units 17 and four reference signal switches 16 are provided corresponding to four divided signal lines obtained by dividing the vertical signal line VSL into four. Fig. 10A shows an example in which the topmost reference signal switch 16 of the four reference signal switches 16 is turned on, and Fig. 10B shows an example in which the second reference signal switch 16 from the top of the four reference signal switches 16 is turned on. When the reference signal switch 16 is turned on, the reference signal is input to the corresponding column readout unit 17 and AD conversion is performed.

[0085] The column control unit 15 sequentially turns on the four reference signal switches 16 while the imaging device 1004 according to the first embodiment generates one frame of a captured image.

[0086] As described above, in the first embodiment, two or more of the multiple reference signal switches 16 are prevented from being turned on simultaneously, thereby reducing the load on the reference signal line Sramp.

[0087] Fig. 11 is a graph showing the relationship between the number of reference signal switches 16 that are turned on simultaneously and the load on the reference signal line Sramp. The horizontal axis of Fig. 11 is the number of reference signal switches that are turned on simultaneously, and the vertical axis is the signal band ratio. A smaller signal band ratio indicates a larger load. As shown in Fig. 11, as the number of reference signal switches 16 that are turned on simultaneously increases, the signal band ratio decreases and the load on the reference signal line Sramp increases.

[0088] Fig. 12 is a graph showing the relationship between the settling time of the reference signal RAMP on the reference signal line Sramp and the signal band. Fig. 12A shows a graph in the case where only one reference signal switch 16 is turned on at the same time, and Fig. 12B shows a graph in the case where two or more reference signal switches 16 are turned on at the same time. The horizontal axis of Fig. 12A and Fig. 12B is time, and the vertical axis is signal level.

[0089] As can be seen from FIGS. 12A and 12B, when two or more reference signal switches 16 are turned on simultaneously, the load on the reference signal line Sramp increases, the settling time becomes longer, and the signal band becomes narrower.

[0090] Fig. 13 is a timing diagram of the imaging device 1004 according to the first embodiment. Fig. 13 illustrates waveforms of a vertical synchronization signal XVS, a horizontal synchronization signal XHS, a plurality of switching control signals output by the column control unit 15, a reference signal output from the DAC 14 and input to a plurality of reference signal switches 16, and output signals of the plurality of reference signal switches 16. In this specification, the plurality of reference signal switches 16 are referred to as reference signal switches 16a, 16b, 16c, and 16d. In Fig. 13, times t1 to t5 correspond to one frame period, and the vertical synchronization signal XVS is output at times t1 and t5.

[0091] The column control unit 15 shifts the phases of four switching control signals that turn on or off the four reference signal switches 16a to 16d. When each switching control signal is at a high level, the corresponding reference signal switch 16 turns on. By shifting the phases of the four phase control signals, the reference signals are input sequentially to the four column readout units 17 during one frame period. As a result, at times t1 to t2, t2 to t3, t3 to t4, and t4 to t5, the reference signals are input to different column readout units 17, and the pixel signals are AD converted in each column readout unit 17.

[0092] As described above, in this embodiment, rather than inputting reference signals to the four column readout units 17 simultaneously using a single reference signal line Sramp, the four reference signal switches 16a to 16d are turned on one by one with a time lag, and the reference signals are input to the four column readout units 17 with a time lag. This reduces the load on the input node of each column readout unit 17, speeds up AD conversion, and ultimately speeds up the frame rate.

[0093] 14 is a circuit diagram showing a first example of the reference signal switcher 16. The reference signal switcher 16 according to the first example has a PMOS transistor Q1 connected between a first node n1 and a second node n2, and an NMOS transistor Q2 connected between the first node n1 and the second node n2. Switching control signals Φ1 and Φ2 having opposite logic are input to the gates of the PMOS transistor Q1 and NMOS transistor Q2.

[0094] In this way, by connecting a PMOS transistor and an NMOS transistor in parallel between the first node n1 and the second node n2, it is possible to output the reference signal input to the first node n1 from the second node n2 without attenuating the signal level of the reference signal.

[0095] 15 is a circuit diagram showing a second example of reference signal switcher 16. In addition to the circuit configuration of the first example, reference signal switcher 16 according to the second example includes a capacitor C1 connected between the second node n2 and a reference voltage node (for example, a ground node). This capacitor C1 functions as a hold capacitance, and can hold the reference signal for a long period of time even if the switching control signal outputs a pulse for only a short time and reference signal switcher 16 is turned on for only a short time.

[0096] FIG. 16 is a circuit diagram showing a third example of the reference signal switch 16. The reference signal switch 16 according to the third example has a circuit configuration that takes measures against injection current. The injection current is an electric charge that flows from the gate into the signal wiring when the switch is switched, and is a factor that causes the voltage level of the signal wiring to fluctuate. The reference signal switch 16 according to the third example has a PMOS transistor Q1 and an NMOS transistor Q2 connected in parallel between a first node n1 and a second node n2, PMOS transistors Q3 and Q4, NMOS transistors Q5 and Q6, and a capacitor C1. The source and drain of the transistor Q3 are connected to the first node n1. The source and drain of the transistor Q4 are connected to the second node n2. An inverted switching control signal having the opposite logic to the switching control signal input to the gate of the transistor Q1 is input to the gates of the transistors Q3 and Q4. The source and drain of the transistor Q5 are connected to the first node n1. The source and drain of the transistor Q6 are connected to the second node n2. A switching control signal having the same logic as the switching control signal input to the gate of the transistor Q1 is input to the gates of the transistors Q5 and Q6.

[0097] By reversing the logic of the switching control signals applied to the gates of the transistors Q1 and Q3, the injection current can be released from the gate of the transistor Q1 to the gate of the transistor Q3, as shown by the arrow y1. Similarly, by reversing the logic of the switching control signals applied to the gates of the transistors Q1 and Q4, the injection current can be released from the gate of the transistor Q1 to the gate of the transistor Q3, as shown by the arrow y2. Similarly, by reversing the logic of the switching control signals applied to the gates of the transistors Q2 and Q5, the injection current can be released from the gate of the transistor Q2 to the gate of the transistor Q5, as shown by the arrow y3. Similarly, by reversing the logic of the switching control signals applied to the gates of the transistors Q2 and Q6, the injection current can be released from the gate of the transistor Q2 to the gate of the transistor Q6, as shown by the arrow y4.

[0098] In this way, the reference signal switcher 16 of the third example shown in FIG. 16 reverses the logic of the switching control signal input to the gate of transistor Q1 and the gates of transistors Q3 and Q4, and reverses the logic of the switching control signal input to the gate of transistor Q2 and the gates of transistors Q5 and Q6, thereby allowing the injection current to escape and suppressing fluctuations in the voltage level of the second node n2.

[0099] 17 is a circuit diagram showing a fourth example of the reference signal switch 16. The reference signal switch 16 according to the fourth example has a circuit configuration that keeps the voltage between the gate and source of the main switch constant. As shown in FIG. 17, the reference signal switch 16 according to the fourth example has an NMOS transistor Q1 that is a main switch connected between a first node n1 and a second node n2, a voltage source 21 that outputs a bias voltage between a third node n3 and a fourth node n4, a first switch 22, a second switch 23, and a third switch 24 that are connected in series between the third node n3 and a reference voltage (e.g., ground voltage) node, a fourth switch 25 and a fifth switch 26 that are connected in series between the fourth node n4 and the first node n1, a first capacitor C1 that is connected between the connection node of the first switch 22 and the second switch 23 and the connection node of the fourth switch 25 and the fifth switch 26, and a second capacitor C2 that is connected between the second node n2 and a reference voltage (e.g., ground voltage) node.

[0100] A switching control signal output from the connection node of the second switch 23 and the third switch 24 is input to the gate of the transistor Q1. When the first node n1 and the second node n2 are made conductive, the first switch 22, the third switch 24, and the fourth switch 25 are made disconnected, and the second switch 23 and the fifth switch 26 are made conductive. When the first node n1 and the second node n2 are made disconnected, the first switch 22, the third switch 24, and the fourth switch 25 are made conductive, and the second switch 23 and the fifth switch 26 are made disconnected.

[0101] The first capacitor C1 accumulates a charge according to the bias voltage Vb. The gate-source voltage Vgs of the transistor Q1, which is the main switch, is a fixed value expressed by the bias voltage Vb, the capacitance Cb of the first capacitor C1, and the gate capacitance Cg of the transistor Q1, as shown in the following equation (1).

[0102] Vgs = (Cb × Vb) / Cg … (1) The column control unit 15 outputs a switching control signal φ1 that controls the switching of the first switch 22, the third switch 24, and the fourth switch 25, and a switching control signal φ2 that controls the switching of the second switch 23 and the fifth switch 26. The switching control signals φ1 and φ2 have mutually inverse logic.

[0103] When the switching control signal φ1 is at a high level and the switching control signal φ2 is at a low level, the first switch 22, the third switch 24, and the fourth switch 25 are conductive, and the second switch 23 and the fifth switch 26 are cut off. At this time, the first capacitor C1 performs a sampling operation to accumulate a charge according to the bias voltage Vb. Also, the transistor Q1 is turned off.

[0104] When the switching control signal φ1 is at a low level and the switching control signal φ2 is at a high level, the first switch 22, the third switch 24, and the fourth switch 25 are cut off, and the second switch 23 and the fifth switch 26 are conductive. At this time, the first capacitor C1 holds the accumulated charge, and the transistor Q1 is turned on.

[0105] In the reference signal switcher 16 according to the fourth example, the gate-source voltage Vgs of the transistor Q1 is constant, and therefore it is possible to maintain a constant on-resistance of the reference signal switcher 16. Therefore, even if the signal level of the reference signal changes, the signal quality (linearity, etc.) of the second node n2, which is the output node of the reference signal switcher 16, can be maintained.

[0106] In addition, by maintaining the gate-source voltage Vgs of the transistor Q1, which is the main switch, at a high voltage, the on-resistance can be reduced, and signal quality such as signal bandwidth and noise can be improved. Normally, to improve signal quality, it is necessary to increase the aspect ratio of the main switch, and the area of ​​the transistor Q1 and the first capacitor C1 can be reduced.

[0107] When the voltage level of the bias voltage Vb is increased, it becomes necessary to take into consideration the withstand voltage margin of the gate of the transistor Q1.

[0108] Fig. 18 is a circuit diagram showing a fifth example of the reference signal switch 16. As shown in Fig. 18, the reference signal switch 16 according to the fifth example includes an NMOS transistor Q1 serving as a main switch connected between a first node n1 and a second node n2, a first switch 22, a second switch 23, and a third switch 24 connected in series between a first reference voltage (e.g., power supply voltage) node and a second reference voltage (e.g., ground voltage) node, a fourth switch 25 and a fifth switch 26 connected in series between the second reference voltage (e.g., ground voltage) node and the first node n1, a first capacitor C1 connected between a connection node of the fourth switch 25 and the fifth switch 26, and a second capacitor C2 connected between the second node n2 and a reference voltage (e.g., ground voltage) node.

[0109] The first switch 22, the second switch 23, the third switch 24, the fourth switch 25, and the fifth switch 26 in the reference signal switch 16 in the fifth example are switched and controlled by switching control signals φ1 and φ2, similar to the first switch 22 to the fifth switch 26 in the reference signal switch 16 in the fourth example.

[0110] The reference signal switch 16 according to the fifth example is characterized in that the voltage source 21 of the reference signal switch 16 according to the fourth example is omitted, and the bias voltage Vb is set to the difference voltage between the power supply voltage VDD and the ground voltage VSS. In this way, the imaging device 1004 according to the first embodiment sequentially shifts the timing at which the multiple reference signal switches 16 are turned on, so that the reference signals are input to the multiple column readout units 17 one by one with a time shift. This reduces the load on the reference signal line Sramp, and speeds up the AD conversion and frame rate in each column readout unit 17, while reducing power consumption.

[0111] Second embodiment In the first embodiment, one of the multiple reference signal switches 16 is turned on in sequence to sequentially input the reference signal RAMP to the corresponding column readout unit 17. However, a configuration in which a preamplifier is placed in front of each column readout unit 17 to improve the drive capability of the reference signal is also conceivable.

[0112] 19A and 19B are block diagrams of the periphery of a column readout unit 17 of an imaging device 1004 according to the second embodiment. The imaging device 1004 according to the second embodiment has a preamplifier 31 disposed in front of each of the column readout units 17. Except for the preamplifier 31 being disposed in front of each column readout unit 17, the imaging device 1004 has the same configuration as in FIGS. 10A and 10B.

[0113] 19A shows an example in which the topmost reference signal switch 16 of the four reference signal switches 16 is turned on, and the reference signal RAMP is input to the column readout unit 17 via the topmost preamplifier 31. Fig. 19B shows an example in which the second-highest reference signal switch 16 of the four reference signal switches 16 is turned on, and the reference signal RAMP is input to the column readout unit 17 via the second-highest preamplifier 31.

[0114] The preamplifier 31 has a source follower circuit 32. The preamplifier 31 performs impedance conversion of the reference signal by the source follower circuit 32, thereby lowering the output impedance and outputting the reference signal RAMP that changes faithfully in response to changes in the signal level of the input reference signal RAMP.

[0115] 20 is a circuit diagram showing a first example of the internal configuration of a preamplifier 31. The preamplifier 31 according to the first example is a source follower circuit 32 having a current source transistor Q11, a first current cut transistor Q12, a cascode transistor Q13, an input transistor Q14, and a second current cut transistor Q15, which are connected in series between a first reference voltage (e.g., power supply voltage) node and a second reference voltage (e.g., ground voltage) node. Only the second current cut transistor Q15 in the source follower circuit 32 is an NMOS transistor, and the other transistors are PMOS transistors.

[0116] The current source transistor Q11 functions as a current source, and a predetermined voltage is input to its gate. The first current cut transistor Q12 and the second current cut transistor Q15 are used to prevent current from flowing between the source and drain of the input transistor Q14 when the input transistor Q14 is turned on. The reference signal RAMP is input to the gate of the input transistor Q14.

[0117] The source of the input transistor Q14 and the drain of the cascode transistor Q13 are connected to the output node of the preamplifier 31. An impedance-converted reference signal RAMP is output from the output node of the preamplifier 31. The reference signal RAMP output from the output node of the preamplifier 31 is input to the corresponding column readout unit 17, where it is subjected to AD conversion processing.

[0118] The first current cut transistor Q12 and the second current cut transistor Q15 in the source follower circuit 32 connected to the front stage of the column readout unit 17 to which the reference signal RAMP is not input are set to OFF. This allows the input node of the corresponding column readout unit 17 to have high impedance, and prevents unnecessary current from flowing to the source follower circuit 32, thereby reducing power consumption. On the other hand, the first current cut transistor Q12 and the second current cut transistor Q15 in the source follower circuit 32 connected to the front stage of the column readout unit 17 to which the reference signal RAMP is input are set to ON. This causes the reference signal RAMP with low output impedance to be output from the output node of the source follower circuit 32 and input to the corresponding column readout unit 17.

[0119] Various modifications are possible for the internal configuration of the source follower circuit 32 constituting the preamplifier 31. Fig. 21 is a circuit diagram showing a second example of the internal configuration of the preamplifier 31. In the preamplifier 31 of the second example, the connection order of the first current cut transistor Q12 and the cascode transistor Q13 in the preamplifier 31 of the first example is reversed, and the rest of the circuit configuration is the same.

[0120] In FIG. 21, when the first current cut transistor Q12 is turned off, the drain side of the first current cut transistor Q12 becomes high impedance, resulting in the same circuit operation as when the cascode transistor Q13 is turned off. Therefore, the connection order of the first current cut transistor Q12 and the cascode transistor Q13 can be reversed.

[0121] Fig. 22 is a circuit diagram showing a third example of the internal configuration of the preamplifier 31. The preamplifier 31 according to the third example omits the first current cut transistor Q12 of Fig. 20, and connects a current cut switcher 39 having the same function as the first current cut transistor Q12 to the gate. This allows the cascode transistor Q13 to essentially function as the first current cut transistor Q12. The current cut switcher 39 has a PMOS transistor Q16 connected between the gate of the cascode transistor Q13 and a first reference voltage (e.g., power supply voltage) node, and a PMOS transistor Q17 connected between the gate of the cascode transistor Q13 and a second reference voltage (e.g., ground voltage) node.

[0122] Switching control signals of opposite logic are input to the gates of PMOS transistor Q16 and PMOS transistor Q17. When PMOS transistor Q16 is on, PMOS transistor Q17 is off and cascode transistor Q13 is off. When PMOS transistor Q16 is off, PMOS transistor Q17 is on and cascode transistor Q13 is on. In this way, by using the current cut switch 39, the cascode transistor Q13 can be reliably turned off.

[0123] Fig. 23 is a circuit diagram showing a fourth example of the internal configuration of preamplifier 31. Preamplifier 31 according to the fourth example includes a precharge circuit 33 connected to the output node of preamplifier 31 according to any of the first to third examples. Fig. 23 shows a configuration in which precharge circuit 33 is connected to the output node of preamplifier 31 according to the first example, but precharge circuit 33 may be connected to the output node of preamplifier 31 shown in Fig. 21 or Fig. 22.

[0124] The precharge circuit 33 has a precharge switch 34 connected to the output node of the preamplifier 31. The precharge switch 34 switches whether or not to supply a precharge signal to the output node of the preamplifier 31. As will be described later, the precharge signal is, for example, a signal at the reference voltage level of the reference signal RAMP.

[0125] Of the multiple column readout units 17, only one receives the reference signal RAMP via the multiple reference signal switches 16 and multiple preamplifiers 31, and the column readout units 17 to which the reference signal RAMP is input are switched in sequence. The input node of the column readout unit 17 to which the reference signal RAMP is not input may have a signal level that is significantly different from the signal level of the reference signal RAMP, and the settling time becomes longer when the reference signal RAMP is input. Therefore, by precharging the signal level of the input node of the column readout unit 17 to which the reference signal RAMP is not input with a precharge signal, the settling time when the reference signal RAMP is input can be shortened.

[0126] As described above, in the second embodiment, a preamplifier 31 is disposed in front of each column readout unit 17, and the first current cut transistor Q12 and the second current cut transistor Q15 of the source follower circuit 32 in the preamplifier 31 are turned on / off in synchronization with the on / off of the multiple reference signal switches 16. This makes it possible to prevent unnecessary current from flowing in the source follower circuit 32 when the reference signal RAMP is not input to the column readout unit 17, thereby reducing power consumption.

[0127] Furthermore, by connecting the precharge circuit 33 to the output node of the preamplifier 31, the output node of the preamplifier 31 to which the reference signal RAMP is not input can be precharged, and when the reference signal RAMP is subsequently input, the output node of the preamplifier 31 can be quickly set to a desired voltage level, thereby shortening the settling time.

[0128] (Third embodiment) The third embodiment relates to a circuit that generates a precharge signal for precharging the output node of the source follower circuit 32 in the preamplifier 31 in the second embodiment.

[0129] Fig. 24 is a graph showing the settling time of the reference signal input to the column readout unit 17 when the output node of the source follower circuit 32 is precharged and when it is not precharged. The horizontal axis of Fig. 24 is time, and the vertical axis is the voltage level of the input node of the column readout unit 17. The upper waveform shows the voltage waveform of the input node of the column readout unit 17 when the output node of the source follower circuit 32 is not precharged, and the lower waveform shows the voltage waveform of the input node of the column readout unit 17 when the output node of the source follower circuit 32 is precharged.

[0130] As can be seen by comparing the two waveforms in Fig. 24, when the output node of the source follower circuit 32 is not precharged, the settling time is longer than when it is precharged. In the example of Fig. 24, the settling time is reduced to almost zero by precharging the output node of the source follower circuit 32. The AZ level is the reference level of the comparator 20 in the column readout section 17.

[0131] As described in the second embodiment, when the first current cut transistor Q12 and the second current cut transistor Q15 in the source follower circuit 32 are turned off, the output node of the source follower circuit 32 is in a high impedance state and the voltage level is indefinite. For this reason, as shown in FIG. 23, when the first current cut transistor Q12 and the second current cut transistor Q15 are turned off, it is desirable to precharge the output node of the source follower circuit 32 with a precharge signal. The voltage level of the precharge signal may be the same as the power supply voltage or the ground voltage, and the circuit that inputs the precharge signal may be a simple circuit such as a pull-up resistor or a pull-down resistor. However, if the voltage level of the precharge signal is not appropriate, the settling time when the reference signal is input becomes long, and the AD time in the column readout section 17 becomes long.

[0132] The third embodiment is characterized in that the output node of the source follower circuit 32 is precharged to the reference voltage level (AZ level) of the reference signal RAMP used when performing AD conversion in the column readout unit 17, thereby shortening the settling time when the reference signal RAMP is input to the column readout unit 17.

[0133] 25 is a circuit diagram of the periphery of a column readout unit 17 of an imaging device 1004 according to the third embodiment. The imaging device 1004 according to the third embodiment includes a plurality of reference signal switches 16, a plurality of preamplifiers 31, a plurality of column readout units 17, and a precharge circuit 33.

[0134] The precharge circuit 33 has a replica circuit 36 ​​having substantially the same circuit configuration as the source follower circuit 32 in the preamplifier 31. The replica circuit 36 ​​has, for example, a current source transistor Q11, a first current cut transistor Q12, a cascode transistor Q13, an input transistor Q14, and a second current cut transistor Q15.

[0135] The plurality of reference signal switches 16 have, for example, any of the circuit configurations shown in Fig. 14 to Fig. 18. The plurality of reference signal switches 16 are provided corresponding to the plurality of preamplifiers 31. In addition, a reference signal switch 16 for a precharge circuit 33 is newly provided.

[0136] The replica circuit 36 ​​constituting the precharge circuit 33 outputs a signal at a reference voltage level of the reference signal. A plurality of precharge switches 34 are connected between the output node of the replica circuit 36 ​​and the output nodes of the plurality of source follower circuits 32 in the plurality of preamplifiers 31. Among the plurality of precharge switches 34, the precharge switches 34 connected to the output nodes of the source follower circuits 32 on the front side of all the column readout units 17 except the column readout unit 17 to which the reference signal is input are turned on, and the output nodes of the source follower circuits 32 are precharged. On the other hand, the precharge switches 34 connected to the output nodes of the source follower circuits 32 on the front side of the column readout unit 17 to which the reference signal is input are turned off, and the reference signal RAMP output from the source follower circuit 32 is input to the column readout unit 17.

[0137] In this embodiment, for the sake of simplicity, an imaging device 1004 including two reference signal switches 16 (16a, 16b) (hereinafter, the first reference signal switch 16a and the second reference signal switch 16b), a reference signal switch 16 for a replica circuit 36 ​​(hereinafter, the third reference signal switch 16c), two source follower circuits 32 (the first source follower circuit 32a and the second source follower circuit 32b), and two column readout units 17 (the first column readout unit 17 and the second column readout unit 17) will be described. In this specification, the first source follower circuit 32a may be abbreviated as SF1, and the second source follower circuit 32b may be abbreviated as SF2.

[0138] Fig. 26A and Fig. 26B are diagrams for explaining the precharge operation of the imaging device 1004 according to the third embodiment, and Fig. 27 is a timing chart corresponding to the explanations of Fig. 26A and Fig. 26B. Fig. 27 shows waveforms of the reference signal RAMP, the gate voltage of the first current cut transistor Q12 in the first source follower circuit 32a, the gate voltage of the second current cut transistor Q15 in the first source follower circuit 32a, the switching control signal of the first reference signal switcher 16a, the output voltage of the first source follower circuit 32a, the gate voltage of the first current cut transistor Q12 in the second source follower circuit 32b, the gate voltage of the second current cut transistor Q15 in the second source follower circuit 32b, the switching control signal of the second reference signal switcher 16b, and the output voltage of the second source follower circuit 32b.

[0139] Fig. 26A shows the precharge operation when first reference signal switch 16a is turned on and second reference signal switch 16b is turned off. Fig. 26B shows the precharge operation when first reference signal switch 16a is turned off and second reference signal switch 16b is turned on.

[0140] 27, the period from time t1 to time t2 corresponds to a vertical blanking (V-blank) period. During the vertical blanking period, first reference signal switch 16a and third reference signal switch 16c are temporarily turned on. As a result, first reference signal switch 16a and third reference signal switch 16c each sample and hold reference signal RAMP.

[0141] During the period from time t2 to t6, the first reference signal switch 16a is turned on, and the reference signal RAMP that has passed through the first reference signal switch 16a is input to the first source follower circuit 32a. During this period, the second reference signal switch 16b is turned off. At each of times t2, t3, t4, and t5, the third reference signal switch 16c is temporarily turned on, and the third reference signal switch 16c samples and holds the reference signal RAMP. This causes the voltage level of the output node of the replica circuit 36 ​​to rise stepwise. The output node of the replica circuit 36 ​​is connected to the output node of the second source follower circuit 32b via the precharge switch 34. Since the precharge switch 34 is in the on state, the output node of the second source follower circuit 32b is precharged to the same voltage level as the output node of the replica circuit 36, as shown in FIG. 26A.

[0142] Therefore, when the first current cut transistor Q12 and the second current cut transistor Q15 in the second source follower circuit 32b are turned on at time t6, as shown in FIG. 26B, the second source follower circuit 32b can start outputting the reference signal RAMP at approximately the same voltage level as before time t6.

[0143] In this way, in the third embodiment, a replica circuit 36 ​​having the same circuit configuration as the source follower circuit 32 is provided to precharge the output nodes of all source follower circuits 32 connected to the column readout unit 17 to which the reference signal RAMP is not input, thereby shortening the settling time of the input node of the column readout unit 17 when the reference signal is input.

[0144] (Fourth embodiment) In the first to third embodiments, an example has been described in which a column readout unit 17 is provided for each divided signal line obtained by dividing the vertical signal line VSL into a plurality of lines, but the present invention is also applicable to a configuration in which a plurality of column readout units 17 are provided without dividing the vertical signal line VSL into a plurality of lines. In the following, an imaging device 1004 in which two column readout units 17 are provided without dividing the vertical signal line VSL into a plurality of lines will be described.

[0145] Fig. 28 is a block diagram of an imaging device 1004 according to the fourth embodiment. As shown in Fig. 28, the imaging device 1004 according to the fourth embodiment includes a vertical driving unit 12, a system control unit 13, a DAC 14, a column control unit 15, two reference signal switches 16 (16a, 16b), a pixel array unit 11, and two column readout units 17. Note that the column signal processing unit 18 and the horizontal driving unit 19 are omitted in Fig. 28.

[0146] Fig. 29 is a diagram showing an example of the locations of the two column readout units 17 in Fig. 28. As shown in Fig. 29, the two column readout units 17 are arranged close to each other near the lower end in the second direction (vertical direction) Y. Two reference signal switches 16 (16a, 16b) are arranged between the two column readout units 17 and the DAC 14.

[0147] The two column readout units 17 may be arranged at an upper end side and a lower end side in the second direction (vertical direction) Y, spaced apart from each other.

[0148] Fig. 30 is a block diagram of an imaging device 1004 according to a modified example of the fourth embodiment. In Fig. 30, compared to Fig. 29, the column control unit 15 is divided into two and arranged at the upper end side and the lower end side, and two reference signal switches 16 (16a, 16b) and two column readout units 17 are arranged beside the column control units 15. In Fig. 30, two system control units 13 are provided in correspondence with the two column control units 15, but one system control unit 13 may control two column control units 15.

[0149] Fig. 31 is a diagram showing the locations of the two column readout units 17 in Fig. 30. The DAC 14 is disposed near the center of the pixel array unit 11 in the second direction (vertical direction) Y, two reference signal switches 16 (16a, 16b) are disposed at positions approximately equidistant from the DAC 14, and two column readout units 17 are disposed at positions approximately equidistant from the two reference signal switches 16 (16a, 16b). This makes the propagation delay and wiring load of the reference signal line Sramp equal.

[0150] In the following, the two reference signal switchers 16 (16a, 16b) shown in Figures 28 and 30 will be referred to as the first reference signal switcher 16a and the second reference signal switcher 16b, and the two column reading units 17 will be referred to as the first column reading unit 17 and the second column reading unit 17.

[0151] Fig. 32 is a timing diagram of the imaging device 1004 according to the fourth embodiment. Fig. 32 shows timing when the reference signal input to one of the two column readout units 17 is switched on a frame-by-frame basis. Fig. 32 shows waveforms of the vertical synchronization signal XVS, the horizontal synchronization signal XHS, the switching control signal of the first reference signal switch 16a, the switching control signal of the second reference signal switch 16b, the reference signals input to the first and second reference signal switch 16b, the output signal of the first reference signal switch 16a, and the output signal of the second reference signal switch 16b.

[0152] During one frame period from time t1 to t2, the first reference signal switch 16a is turned on and the second reference signal switch 16b is turned off. Therefore, a reference signal is output from the first reference signal switch 16a and input to the first column readout section 17. The output of the second reference signal switch 16b remains at a low level, and no reference signal is input to the second column readout section 17.

[0153] FIG. 32 shows an example in which the reference signal input to one of the two column readout units 17 is switched every frame, but the reference signals input to the two column readout units 17 may also be switched within the scanning period of each horizontal line.

[0154] Fig. 33 is a timing diagram of an imaging device 1004 according to a modified example of the fourth embodiment. Fig. 33 shows waveforms of the horizontal synchronization signal XHS, the switching control signal of the first reference signal switch 16a, the switching control signal of the second reference signal switch 16b, the output signal of the first reference signal switch 16a, and the output signal of the second reference signal switch 16b.

[0155] From time t1 to t2 and from time t3 to t4, first reference signal switch 16a is on and second reference signal switch 16b is off, and from time t2 to t3, first reference signal switch 16a is off and second reference signal switch 16b is on.

[0156] At times t1 to t2 and t3 to t4, a reference signal for low conversion efficiency is generated, and at times t2 to t3, a reference signal for high conversion efficiency is generated. Also, at times t1 to t2, AD conversion of the reset level is performed, and at times t3 to t4, AD conversion of the pixel signal level is performed. At times t1 to t2, AD conversion of the reset level and the pixel signal level is performed continuously.

[0157] Thus, in the fourth embodiment, even if multiple column readout units 17 are provided without dividing the vertical signal line VSL, the load on the reference signal line Sramp can be reduced by sequentially supplying a reference signal to any one of the column readout units 17 using multiple reference signal switchers 16, thereby enabling a reduction in AD time and a high frame rate.

[0158] Fifth embodiment In the fifth embodiment, an imaging device 1004 according to the present disclosure is applied to a pixel ADC or an area ADC.

[0159] Fig. 34 is a diagram illustrating an image pickup device 1004 according to a fifth embodiment. The image pickup device 1004 in Fig. 34 has an AD converter for each pixel, and a reference signal line Sramp for transmitting a reference signal RAMP used in the AD converter of each pixel is provided for each pixel column.

[0160] The multiple reference signal lines Sramp are aligned in a first direction (horizontal direction) X, and the multiple reference signal lines Sramp are connected to multiple reference signal switches 16. When one of the multiple reference signal switches 16 is turned on, the reference signal RAMP output from the turned-on reference signal switch 16 is input to each AD converter of each pixel in the corresponding pixel column.

[0161] Fig. 35 is a diagram illustrating an image pickup device 1004 according to a modified example of the fifth embodiment. The image pickup device 1004 shown in Fig. 35 has an AD converter for each pixel, but can capture only a pixel region of any size as a ROI (Region Of Interest).

[0162] 35, only the reference signal switches 16 connected to the pixel columns corresponding to the pixel region of the ROI are sequentially turned on, and the reference signal switches 16 connected to the pixel columns corresponding to the pixel regions other than the pixel region of the ROI are turned off. This makes it possible to speed up the AD conversion time and the frame rate.

[0163] In this way, in the fifth embodiment, when an AD converter is provided for each pixel and a reference signal line Sramp is provided for each pixel column, multiple reference signal switches 16 are connected to the multiple reference signal lines Sramp, and one of the multiple reference signal switches 16 is turned on in sequence to supply a reference signal to only one of the reference signal lines Sramp, so that the load on the reference signal line Sramp can be reduced and AD conversion and frame rate can be increased. Also, when imaging only the pixel region of the ROI, one of the multiple reference signal lines Sramp corresponding to the pixel region of the ROI is selected in sequence to supply a reference signal, so that AD conversion and frame rate can be increased.

[0164] Sixth embodiment 36 is a diagram for explaining an imaging device 1004 according to the sixth embodiment. The imaging device 1004 according to the sixth embodiment is a so-called column ADC, and is provided with a column readout unit 17 that performs AD conversion for each vertical signal line VSL extending in the second direction (vertical direction) Y. A plurality of vertical signal lines VSL arranged in the first direction (horizontal direction) X are connected to the column readout unit 17. The column readout unit 17 has a plurality of AD converters that perform AD conversion of pixel signals transmitted through each vertical signal line VSL. That is, the column readout unit 17 has the same number of AD converters as the number of vertical signal lines VSL.

[0165] In this embodiment, there is provided a first reference signal switch 16a that switches whether or not a reference signal is input to an AD converter to which pixel signals from odd-numbered vertical signal lines VSL among the multiple vertical signal lines VSL are input, and a second reference signal switch 16b that switches whether or not a reference signal is input to an AD converter to which pixel signals from even-numbered vertical signal lines VSL are input.

[0166] The first reference signal switch 16a and the second reference signal switch 16b are turned on / off exclusively, and when one of them is turned on, the other is turned off. This reduces the load on the reference signal line Sramp that transmits the reference signal generated by the DAC 14.

[0167] As an application example of this embodiment, it is also possible to perform AD conversion by transmitting the result of adding pixel signals on two adjacent vertical signal lines VSL through any one of the vertical signal lines VSL. In this case, the reference signal switch 16 that inputs a reference signal to the AD converter to which the pixel signal on the vertical signal line VSL to which the addition result is transmitted is turned on, and the reference signal switch 16 that inputs a reference signal to the AD converter to which the vertical signal line VSL that does not transmit the addition result is connected is turned off. This reduces the load on the reference signal line Sramp.

[0168] In this manner, in the sixth embodiment, two reference signal switches 16 (first reference signal switch 16a and second reference signal switch 16b) are connected to a column readout section 17 having a plurality of AD converters connected to a plurality of vertical signal lines VSL, and the first reference signal switch 16a switches whether or not a reference signal is input to an odd-numbered AD converter, and the second reference signal switch 16b switches whether or not a reference signal is input to an even-numbered AD converter. By turning on either the first reference signal switch 16a or the second reference signal switch 16b and turning off the other, the load on the reference signal line Sramp can be reduced, and AD conversion and frame rate can be increased.

[0169] Seventh embodiment As a concept that encompasses the above-mentioned first to sixth embodiments, an imaging device 1004 according to the seventh embodiment includes a plurality of photoelectric conversion elements, a plurality of pixel circuits, a plurality of comparators, a digital signal generator, and a plurality of switches.

[0170] The multiple photoelectric conversion elements are arranged in a first direction X and a second direction Y that intersect with each other, as shown in FIG. 2, for example, and each accumulates electric charges according to the amount of incident light.

[0171] The pixel circuits each output a pixel signal corresponding to the charge accumulated in the photoelectric conversion elements.

[0172] A plurality of comparators (comparators 20) compare each of a plurality of pixel signals output from a plurality of pixel circuits with a reference signal. The comparators are included in the column readout unit 17 shown in FIG.

[0173] The digital signal generator generates digital signals by performing analog-to-digital conversion on the pixel signals based on the comparison results of the comparators. The digital signal generator is, for example, the counter 30 shown in FIG.

[0174] A plurality of switches (reference signal switches 16) switch whether or not to input a reference signal to a plurality of comparators. In the imaging device 1004 according to the first embodiment, as shown in FIG. 2, a plurality of switches are provided corresponding to a plurality of column readout units 17. In the imaging device 1004 according to the fifth embodiment, as shown in FIG. 34, a plurality of switches are provided corresponding to a plurality of ADCs connected to a plurality of vertical signal lines VSL. The plurality of switches sequentially select one of the plurality of comparators to input a reference signal so that a reference signal is not input to two or more comparators at the same time.

[0175] According to the seventh embodiment, since the reference signal is not input to a plurality of comparators at the same time, the load on the reference signal line can be reduced, and the AD conversion and frame rate of the ADC including the comparators can be increased.

[0176] <Applications to moving objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0177] FIG. 37 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0178] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 37, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053 are illustrated.

[0179] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0180] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0181] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0182] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0183] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0184] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0185] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0186] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0187] The audio / video output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 37, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0188] FIG. 38 is a diagram showing an example of the installation position of the imaging unit 12031.

[0189] In FIG. 38, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0190] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield in the vehicle interior mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield in the vehicle interior is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0191] 38 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0192] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0193] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0194] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0195] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0196] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging device 1004 among the configurations described above. By applying the technology according to the present disclosure, noise of the imaging device 1004 can be further reduced.

[0197] The present technology can be configured as follows. (1) a plurality of photoelectric conversion elements arranged in a first direction and a second direction intersecting each other, each of which accumulates an electric charge according to the amount of incident light; a plurality of pixel circuits each outputting a pixel signal corresponding to the charge accumulated in the plurality of photoelectric conversion elements; a plurality of comparators that compare each of the plurality of pixel signals output from the plurality of pixel circuits with a reference signal; a digital signal generator that generates digital signals by performing analog-to-digital conversion on the pixel signals based on comparison results of the comparators; and a plurality of switches for switching whether or not the reference signal is input to the plurality of comparators. Imaging device. (2) the plurality of switches sequentially select one of the plurality of comparators to input the reference signal so that the reference signal is not input to two or more of the comparators at the same time; The imaging device described in (1). (3) a signal line transmitting the pixel signals output from two or more of the pixel circuits arranged in the second direction; and a conversion circuit that performs analog-to-digital conversion on the plurality of pixel signals transmitted through the signal lines, The conversion circuit includes: The comparator and the digital signal generator are included. An imaging device as described in (1) or (2). (4) a plurality of the signal lines arranged in the first direction; a plurality of the conversion circuits connected to the plurality of signal lines, The imaging device according to (3). (5) the signal line includes a plurality of split signal lines that are split along the second direction, each of the plurality of divided signal lines transmits the pixel signals output from two or more of the pixel circuits arranged along the second direction; One or more of the comparators are provided for each of the plurality of divided signal lines. An imaging device according to (3) or (4). (6) Each of the plurality of comparators is provided for each of the plurality of pixel circuits. An imaging device as described in (1) or (2). (7) The plurality of switches switch, for each pixel group including two or more of the pixel circuits arranged in the first direction or the second direction, whether or not to input the reference signal to the corresponding two or more of the comparators. The imaging device according to (6). (8) The plurality of switches sequentially switch and select one of a plurality of pixel groups corresponding to a pixel region of interest from a plurality of pixel groups each including two or more of the pixel circuits arranged in the first direction or the second direction. The imaging device according to (6). (9) The plurality of switches sequentially select one of two or more pixel groups adjacent to each other in the first direction or the second direction among a plurality of pixel groups each including two or more of the pixel circuits arranged in the first direction or the second direction. The imaging device according to (6). (10) The digital signal generator includes a counter that outputs, as the digital signal, a count value corresponding to a timing at which the pixel signal and the reference signal match in each of the plurality of comparators. An imaging device according to any one of (1) to (9). (11) At least one of the plurality of switches is a first transistor of a first conductivity type that switches between conducting and blocking the first node and the second node in response to a switching control signal; a second transistor of a second conductivity type that switches between conducting and blocking the first node and the second node in response to an inverted switching control signal having an inverse logic to the switching control signal; An imaging device according to any one of (1) to (10). (12) At least one of the plurality of switches is a third transistor of a first conductivity type having a source and a drain connected to the first node and a gate to which the inverted switching control signal is input; a fourth transistor of the first conductivity type having a source and a drain connected to the second node and a gate to which the inverted switching control signal is input; a fifth transistor of a second conductivity type having a source and a drain connected to the first node and a gate to which the switch control signal is input; a sixth transistor of a second conductivity type having a source and a drain connected to the second node and a gate to which the switching control signal is input; The imaging device according to (11). (13) A capacitor is provided between the second node and a reference voltage node, the second node is connected to input nodes of the plurality of comparators; The imaging device according to (11) or (12). (14) At least one of the plurality of switches is a first transistor that switches between conducting and blocking the first node and the second node in response to a switching control signal; a voltage source that outputs a bias voltage between the third node and the fourth node; a first switch, a second switch, and a third switch connected in series between the third node and a reference voltage node; a fourth switch and a fifth switch connected in series between the fourth node and the first node; a first capacitor connected between a connection node between the first switch and the second switch and a connection node between the fourth switch and the fifth switch; a second capacitor connected between the second node and the reference voltage node; the switching control signal output from a connection node between the second switch and the third switch is input to a gate of the first transistor; When the first node and the second node are made conductive, the first switch, the third switch, and the fourth switch are cut off, and the second switch and the fifth switch are made conductive; When the first node and the second node are cut off, the first switch, the third switch, and the fourth switch are made conductive, and the second switch and the fifth switch are made conductive. An imaging device according to any one of (1) to (10). (15) At least one of the plurality of switches is a first transistor that switches between conducting and blocking the first node and the second node in response to a switching control signal; a first switch, a second switch, and a third switch connected in series between a first reference voltage node and a second reference voltage node; a fourth switch and a fifth switch connected in series between the second reference voltage node and the first node; a first capacitor connected between a connection node between the first switch and the second switch and a connection node between the fourth switch and the fifth switch; a second capacitor connected between the second node and the second reference voltage node; the switching control signal output from a connection node between the second switch and the third switch is input to a gate of the first transistor; When the first node and the second node are made conductive, the first switch, the third switch, and the fourth switch are cut off, and the second switch and the fifth switch are made conductive; When the first node and the second node are cut off, the first switch, the third switch, and the fourth switch are made conductive, and the second switch and the fifth switch are made conductive. An imaging device according to any one of (1) to (10). (16) A plurality of preamplifiers are provided between the plurality of switches and the plurality of comparators, the preamplifiers having a plurality of source follower circuits that convert impedances of the reference signals output from the plurality of switches; Each of the plurality of source follower circuits comprises: a first transistor to whose gate the reference signal output from the corresponding switch is input; a second transistor of a first conductivity type connected to a drain side of the first transistor, turned on when the corresponding switch outputs the reference signal, and turned off when the corresponding switch does not output the reference signal; a third transistor of a second conductivity type connected to a source side of the first transistor, turned on when the corresponding switch outputs the reference signal, and turned off when the corresponding switch does not output the reference signal; An imaging device according to any one of (1) and (15). (17) Each of the plurality of source follower circuits comprises: a fourth transistor acting as a current source; a fifth transistor for adjusting the voltage of the corresponding input node of the comparator; the fourth transistor, the third transistor, the fifth transistor, the first transistor, and the second transistor are connected in this order between a first reference voltage node and a second reference voltage node, or the fourth transistor, the fifth transistor, the third transistor, the first transistor, and the second transistor are connected in this order; The imaging device according to (16). (18) A plurality of preamplifiers are provided between the plurality of switches and the plurality of comparators, the preamplifiers having a plurality of source follower circuits that convert impedances of the reference signals output from the plurality of switches; Each of the plurality of source follower circuits comprises: a first transistor to whose gate the reference signal output from the corresponding switch is input; a second transistor of a first conductivity type connected to a drain side of the first transistor, turned on when the corresponding switch outputs the reference signal, and turned off when the corresponding switch does not output the reference signal; a third transistor connected to a source side of the first transistor and functioning as a current source; a fourth transistor for adjusting the voltage of the corresponding input node of the comparator; a fifth transistor connected to a gate of the fourth transistor and turned on when the corresponding switch outputs the reference signal to turn on the fourth transistor; a sixth transistor connected to a gate of the fourth transistor and turned on to turn off the fourth transistor when the corresponding switch does not output the reference signal; An imaging device according to any one of (1) to (15). (19) The input / output terminal further includes a precharge circuit that supplies a precharge signal to a source of the first transistor in a source follower circuit that does not output the reference signal from a source of the first transistor among the plurality of source follower circuits. (16) The imaging device according to any one of (16) to (18). (20) The precharge circuit further includes a replica circuit having the same circuit configuration as the plurality of source follower circuits and configured to generate, as the precharge signal, a reference voltage of the reference signal when the plurality of comparators start a comparison operation; the precharge circuit supplies the reference voltage generated by the replica circuit to a source of the first transistor in a source follower circuit that does not input the reference signal to the corresponding comparator among the plurality of source follower circuits; The imaging device according to (19).

[0198] The aspects of the present disclosure are not limited to the above-mentioned individual embodiments, but include various modifications that may be conceived by a person skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. In other words, various additions, modifications, and partial deletions are possible within the scope that does not deviate from the conceptual idea and intent of the present disclosure derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0199] 10 pixel, 11 pixel array section, 12 vertical drive section, 13 system control section, 15 column control section, 16 reference signal switch, 16a first reference signal switch, 16b second reference signal switch, 16c third reference signal switch, 17 column readout section, 18 column signal processing section, 19 horizontal drive section, 20 comparator, 21 voltage source, 22 first switch, 23 second switch, 24 third switch, 25 fourth switch, 26 fifth switch, 30 counter, 31 preamplifier, 32 source follower circuit, 32a first source follower circuit, 32b second source follower circuit, 33 precharge circuit, 34 precharge switch, 36 replica circuit, 39 current cut switch, 40 logic circuit, 50 peripheral circuit, 60 interface circuit, 100 photoelectric conversion section, 101 pixel, 101 Circuit section, 102 pixel, 201 first stage comparator, 202 middle stage comparator, 203 last stage comparator

Claims

1. a plurality of photoelectric conversion elements arranged in a first direction and a second direction intersecting each other, each of which accumulates electric charges according to the amount of incident light; a plurality of pixel circuits each outputting a pixel signal corresponding to the charge accumulated in the plurality of photoelectric conversion elements; a plurality of comparators that compare each of the plurality of pixel signals output from the plurality of pixel circuits with a reference signal; a digital signal generator that generates digital signals by analog-to-digital conversion of the pixel signals based on comparison results of the comparators; and a plurality of switches for switching whether or not the reference signal is input to the plurality of comparators. Imaging device.

2. the plurality of switches sequentially select one of the plurality of comparators to input the reference signal so that the reference signal is not input to two or more of the comparators at the same time; The imaging device according to claim 1 .

3. a signal line that transmits the pixel signals output from two or more of the pixel circuits arranged in the second direction; a conversion circuit that performs analog-to-digital conversion on the plurality of pixel signals transmitted through the signal lines, The conversion circuit includes: The comparator and the digital signal generator are included. The imaging device according to claim 1 .

4. A plurality of the signal lines arranged in the first direction; a plurality of the conversion circuits connected to the plurality of signal lines, The imaging device according to claim 3 .

5. the signal line includes a plurality of split signal lines that are split along the second direction, each of the plurality of divided signal lines transmits the pixel signals output from two or more of the pixel circuits arranged along the second direction; One or more of the comparators are provided for each of the plurality of divided signal lines. The imaging device according to claim 3 .

6. Each of the plurality of comparators is provided for each of the plurality of pixel circuits. The imaging device according to claim 1 .

7. the plurality of switches switch, for each pixel group including two or more of the pixel circuits arranged in the first direction or the second direction, whether or not to input the reference signal to the corresponding two or more of the comparators; The imaging device according to claim 6.

8. the plurality of switches sequentially switch and select one of a plurality of pixel groups corresponding to a pixel region of interest, among a plurality of pixel groups each including two or more of the pixel circuits arranged in the first direction or the second direction; The imaging device according to claim 6.

9. the plurality of switches sequentially switch and select one of two or more pixel groups adjacent to each other in the first direction or the second direction among a plurality of pixel groups each including two or more of the pixel circuits arranged in the first direction or the second direction, The imaging device according to claim 6.

10. the digital signal generator has a counter that outputs, as the digital signal, a count value corresponding to a timing at which the pixel signal and the reference signal match in each of the plurality of comparators; The imaging device according to claim 1 .

11. At least one of the plurality of switches is a first transistor of a first conductivity type that switches between conducting and blocking the first node and the second node in response to a switching control signal; a second transistor of a second conductivity type that switches between conducting and blocking the first node and the second node in response to an inverted switching control signal having an inverse logic to the switching control signal; The imaging device according to claim 1 .

12. At least one of the plurality of switches is a third transistor of the first conductivity type having a source and a drain connected to the first node and a gate to which the inverted switching control signal is input; a fourth transistor of the first conductivity type having a source and a drain connected to the second node and a gate to which the inverted switching control signal is input; a fifth transistor of a second conductivity type having a source and a drain connected to the first node and a gate to which the switching control signal is input; a sixth transistor of a second conductivity type having a source and a drain connected to the second node and a gate to which the switching control signal is input; The imaging device according to claim 11.

13. a capacitor disposed between the second node and a reference voltage node; the second node is connected to input nodes of the plurality of comparators; The imaging device according to claim 11.

14. At least one of the plurality of switches is a first transistor that switches between conducting and blocking the first node and the second node in response to a switching control signal; a voltage source that outputs a bias voltage between the third node and the fourth node; a first switch, a second switch, and a third switch connected in series between the third node and a reference voltage node; a fourth switch and a fifth switch connected in series between the fourth node and the first node; a first capacitor connected between a connection node between the first switch and the second switch and a connection node between the fourth switch and the fifth switch; a second capacitor connected between the second node and the reference voltage node; the switching control signal output from a connection node between the second switch and the third switch is input to a gate of the first transistor; When the first node and the second node are made conductive, the first switch, the third switch, and the fourth switch are cut off, and the second switch and the fifth switch are made conductive; When the first node and the second node are cut off, the first switch, the third switch, and the fourth switch are made conductive, and the second switch and the fifth switch are made conductive. The imaging device according to claim 1 .

15. At least one of the plurality of switches is a first transistor that switches between conducting and blocking the first node and the second node in response to a switching control signal; a first switch, a second switch, and a third switch connected in series between a first reference voltage node and a second reference voltage node; a fourth switch and a fifth switch connected in series between the second reference voltage node and the first node; a first capacitor connected between a connection node between the first switch and the second switch and a connection node between the fourth switch and the fifth switch; a second capacitor connected between the second node and the second reference voltage node; the switching control signal output from a connection node between the second switch and the third switch is input to a gate of the first transistor; When the first node and the second node are made conductive, the first switch, the third switch, and the fourth switch are cut off, and the second switch and the fifth switch are made conductive; When the first node and the second node are cut off, the first switch, the third switch, and the fourth switch are made conductive, and the second switch and the fifth switch are made conductive. The imaging device according to claim 1 .

16. a plurality of preamplifiers each having a plurality of source follower circuits arranged between the plurality of switches and the plurality of comparators, the preamplifiers converting impedances of the reference signals output from the plurality of switches; Each of the plurality of source follower circuits comprises: a first transistor to whose gate the reference signal output from the corresponding switch is input; a second transistor of a first conductivity type connected to a drain side of the first transistor, turned on when the corresponding switch outputs the reference signal, and turned off when the corresponding switch does not output the reference signal; a third transistor of a second conductivity type connected to a source side of the first transistor, turned on when the corresponding switch outputs the reference signal, and turned off when the corresponding switch does not output the reference signal; The imaging device according to claim 1 .

17. Each of the plurality of source follower circuits comprises: a fourth transistor acting as a current source; a fifth transistor for adjusting the voltage of the corresponding input node of the comparator; the fourth transistor, the third transistor, the fifth transistor, the first transistor, and the second transistor are connected in this order between a first reference voltage node and a second reference voltage node, or the fourth transistor, the fifth transistor, the third transistor, the first transistor, and the second transistor are connected in this order; The imaging device according to claim 16.

18. a plurality of preamplifiers each having a plurality of source follower circuits arranged between the plurality of switches and the plurality of comparators, the preamplifiers converting impedances of the reference signals output from the plurality of switches; Each of the plurality of source follower circuits comprises: a first transistor to whose gate the reference signal output from the corresponding switch is input; a second transistor of a first conductivity type connected to a drain side of the first transistor, turned on when the corresponding switch outputs the reference signal, and turned off when the corresponding switch does not output the reference signal; a third transistor connected to a source side of the first transistor and functioning as a current source; a fourth transistor for adjusting the voltage of the corresponding input node of the comparator; a fifth transistor connected to a gate of the fourth transistor and turned on when the corresponding switch outputs the reference signal to turn on the fourth transistor; a sixth transistor connected to a gate of the fourth transistor and turned on to turn off the fourth transistor when the corresponding switch does not output the reference signal; The imaging device according to claim 1 .

19. a precharge circuit that supplies a precharge signal to a source of the first transistor in a source follower circuit that does not output the reference signal from a source of the first transistor among the plurality of source follower circuits; The imaging device according to claim 16.

20. the precharge circuit further includes a replica circuit having the same circuit configuration as the plurality of source follower circuits and generating, as the precharge signal, a reference voltage of the reference signal when the plurality of comparators start a comparison operation; the precharge circuit supplies the reference voltage generated by the replica circuit to a source of the first transistor in a source follower circuit that does not input the reference signal to a corresponding comparator among the plurality of source follower circuits; 20. The imaging device according to claim 19.

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