Semiconductor substrate and method for manufacturing the same

Abstract

To provide a method for manufacturing a semiconductor substrate having a high quality, at a low cost.SOLUTION: The method for manufacturing the semiconductor substrate includes: forming a graphene layer 12 on an Si surface of an SiC single crystal substrate 11; forming an SiC epitaxial growth layer 13 on the graphene layer 12; attaching a graphite substrate 19 of a temporary substrate onto the SiC epitaxial growth layer 13 via an adhesive layer 14; generating an initial crack 71 between the graphene layer 12 and the SiC epitaxial growth layer 13; extending a crack 72 to the entire surface of an interface between the graphene layer 12 and the SiC epitaxial growth layer 13 to divide the interface; detaching the graphene layer 12 and the SiC single crystal substrate 11; forming an SiC polycrystalline growth layer 15 on the SiC epitaxial growth layer 13; and removing the graphite substrate 19.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor substrate and a method for manufacturing the same. [Background technology]

[0002] Conventionally, SiC-based devices such as Schottky barrier diodes (SBDs), MOSFETs, and IGBTs (insulated gate bipolar transistors) have been provided for power control applications. Single-crystal SiC substrates on which such SiC-based devices are formed are generally manufactured by a sublimation recrystallization method called the modified Lely method. However, this method has a problem that the efficiency of crystal growth and wafer processing is low, resulting in high manufacturing costs. Therefore, in order to reduce manufacturing costs, SiC composite substrates in which a polycrystalline β-SiC layer and a single-crystal α-SiC layer are laminated have been manufactured. Patent Document 1 describes a technology in which a polycrystalline SiC freestanding substrate and a single-crystal SiC semiconductor thinned layer are bonded to each other, and then a single-crystal SiC epitaxial growth layer is grown on the single-crystal SiC thinned layer, in which the single-crystal SiC thinned layer is attached to the polycrystalline SiC substrate with low defects. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6206786 specification Summary of the Invention [Problem to be solved by the invention]

[0004] However, in order to bond a thinned single-crystal SiC layer and a freestanding polycrystalline SiC substrate with high quality, the surface roughness Ra needs to be at least 0.5 nm or less, which can result in high polishing costs and reduced quality and yield due to void defects that occur at the substrate bonding interface.

[0005] The present disclosure has been proposed in view of the above-mentioned circumstances, and has an object to provide a low-cost, high-quality semiconductor substrate and a manufacturing method thereof. [Means for solving the problem]

[0006] The method for manufacturing a semiconductor substrate according to the present disclosure includes the steps of forming a graphene layer on the Si face of a SiC single crystal substrate, forming a SiC epitaxial growth layer on the graphene layer, attaching a temporary substrate onto the SiC epitaxial growth layer via an adhesive, generating a crack between the graphene layer and the SiC epitaxial growth layer, extending the crack over the entire interface between the graphene layer and the SiC epitaxial growth layer to divide the interface and removing the graphene layer and the SiC single crystal substrate, forming a SiC polycrystalline growth layer on the SiC epitaxial growth layer, and removing the temporary substrate. Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a low-cost, high-quality semiconductor substrate and a method for manufacturing the same. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 shows a cross-sectional view of a SiC single crystal substrate. [Figure 2A] FIG. 2A shows a plan view illustrating the crystal planes of a SiC wafer. [Figure 2B] FIG. 2B shows a side view illustrating the crystal planes of a SiC wafer. [Figure 3A] FIG. 3A shows an overhead view of a unit cell of a 4H—SiC crystal. [Figure 3B] FIG. 3B shows a schematic diagram of the two-layer portion of a 4H—SiC crystal. [Figure 3C] FIG. 3C shows a schematic diagram of a four-layer portion of a 4H—SiC crystal. [Figure 4] FIG. 4 shows a configuration diagram of the unit cell of the 4H—SiC crystal shown in FIG. 3A, viewed from directly above the (0001) plane. [Diagram 5] FIG. 5 shows a cross-sectional view of a first composite in which a graphene layer is formed on a SiC single crystal substrate. [Figure 6] FIG. 6 shows an overhead view of an example of a graphene layer having a multi-layer stacked configuration. [Figure 7] FIG. 7 shows a cross-sectional view of a second composite in which an SiC epitaxial layer is formed on the graphene layer of the first composite. [Figure 8] FIG. 8 shows a cross-sectional view of a third composite in which a graphite substrate is bonded onto the SiC epitaxial growth layer of the second composite via an adhesive layer. [Figure 9] FIG. 9 shows a cross-sectional view of a fourth composite in which epitaxially grown layers of the second composite are attached to both sides of a graphite substrate via adhesive layers. [Figure 10] FIG. 10 shows a cross-sectional view of a fourth composite in which an initial crack has occurred between the graphene layer and the SiC epitaxial layer. [Figure 11] FIG. 11 shows a schematic diagram of the fourth composite in which an initial crack was generated between the graphene layer and the SiC epitaxial growth layer by immersion in liquid nitrogen. [Figure 12] FIG. 12 shows a cross-sectional view of a fourth composite in which a crack has propagated across the entire interface between the graphene layer and the SiC epitaxial layer. [Figure 13] FIG. 13 shows a cross-sectional view of the fourth composite broken at the interface between the graphene layer and the SiC epitaxial layer. [Figure 14] FIG. 14 shows a fifth composite in which SiC epitaxial layers are laminated on both sides of a graphite substrate via adhesive layers. [Figure 15] FIG. 15 shows a cross-sectional view of a sixth composite in which a SiC polycrystalline growth layer is formed by CVD on the SiC epitaxial growth layer of the fifth composite. [Figure 16] FIG. 16 shows a cross-sectional view of a seventh composite body obtained by grinding the outer periphery of the sixth composite body. [Figure 17] FIG. 17 shows a cross-sectional view of an eighth composite obtained by removing the graphite substrate and the carbonized adhesive layer from the seventh composite by annealing treatment. [Figure 18] FIG. 18 shows a cross-sectional view of the composite SiC substrate. [Figure 19] FIG. 19 shows an overhead view of a SiC composite substrate (wafer). [Figure 20] FIG. 20 shows a cross-sectional view of a structure having a highly doped layer at the interface between a SiC epitaxial growth layer and a SiC polycrystalline growth layer. [Figure 21] FIG. 21 shows a cross-sectional view of a Schottky barrier diode. [Figure 22] FIG. 22 shows a cross-sectional view of a trench-gate TMOSFET. [Figure 23] FIG. 23 shows a cross-sectional view of a planar gate type MOSFET. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Next, an embodiment will be described with reference to the drawings. In the description of the drawings described below, the same or similar parts are given the same or similar reference numerals. The drawings are schematic. Furthermore, the embodiment shown below is an example of an apparatus or method for embodying a technical idea, and does not specify the material, shape, structure, arrangement, etc. of parts. Various modifications can be made to the embodiment.

[0010] (Method of manufacturing semiconductor substrate) A method for manufacturing a semiconductor substrate according to an embodiment will be described. FIG. 1 is a cross-sectional view of a SiC single crystal substrate (SiCSB) 11 serving as a seed substrate. There are crystallographic polymorphs of SiC, with the cubic crystal (3C) being called β-SiC and the other high-temperature stable forms being called α-SiC. The SiC single crystal substrate 11 according to the embodiment is, for example, a 4H-SiC substrate of α-SiC, and has a thickness of, for example, about 300 μm to 600 μm. In FIG. 1, [C] indicates the C-face of SiC, and [S] indicates the Si-face of SiC. The same applies to the following figures.

[0011] Fig. 2 is a diagram illustrating the crystal planes of a SiC wafer 100 applicable as a SiC single crystal substrate 11. The plan view of Fig. 2A shows a Si surface 103 of a SiC wafer 100 on which a primary orientation flat 101 and a secondary orientation flat 102 are formed. In the side view of Fig. 2B seen from the [-1100] orientation, a Si surface 103 with a

[0001] orientation is formed on the upper surface, and a C surface 104 with a [000-1] orientation is formed on the lower surface.

[0012] A schematic overhead configuration of a unit cell of a 4H-SiC crystal applicable to the embodiments is shown in Fig. 3A, a schematic configuration of a two-layer portion of a 4H-SiC crystal is shown in Fig. 3B, and a schematic configuration of a four-layer portion of a 4H-SiC crystal is shown in Fig. 3C. Also, a schematic configuration of the unit cell of the 4H-SiC crystal structure shown in Fig. 3A viewed from directly above the (0001) plane is shown in Fig. 4.

[0013] As shown in FIG. 3A to FIG. 3C, the crystal structure of 4H-SiC can be approximated by a hexagonal system, in which one Si atom is bonded to four C atoms. The four C atoms are located at the four vertices of a regular tetrahedron with a Si atom at the center. Of these four C atoms, one Si atom is located in the

[0001] axial direction relative to the C atom, and the other three C atoms are located on the [000-1] axial side relative to the Si atom. In FIG. 3A, the off-angle θ is, for example, about 4 degrees or less.

[0014] The

[0001] and [000-1] axes are aligned along the axial direction of the hexagonal prism, and the surface (top surface of the hexagonal prism) normalized to the

[0001] axis is the (0001) surface (Si surface). Meanwhile, the surface (bottom surface of the hexagonal prism) normalized to the [000-1] axis is the (000-1) surface (C surface). In addition, the directions perpendicular to the

[0001] axis and passing through non-adjacent vertices of the hexagonal prism when viewed from directly above the (0001) surface are the a1 axis [2-1-10], a2 axis [-12-10], and a3 axis [-1-120], respectively.

[0015] As shown in FIG. 4, the direction passing through the vertex between the a1 axis and the a2 axis is the [11-20] axis, the direction passing through the vertex between the a2 axis and the a3 axis is the [-2110] axis, and the direction passing through the vertex between the a3 axis and the a1 axis is the [1-210] axis. Between each of the six axes passing through each vertex of the hexagonal prism, the axes inclined at an angle of 30° to the axes on both sides and normal to each side of the hexagonal prism are, in order clockwise from between the a1 axis and the [11-20] axis, the [10-10] axis, the [1-100] axis, the [0-110] axis, the [-1010] axis, the [-1100] axis, and the [01-10] axis. Each face (side face of the hexagonal prism) having these axes as normals is a crystal face perpendicular to the (0001) and (000-1) faces.

[0016] 5, a graphene layer (GR) 12 of up to several molecular layers is laminated on the (0001) Si surface of the SiC single crystal substrate 11 to form a first composite 91. The graphene layer 12 can be formed by pyrolysis on the Si surface of the SiC single crystal substrate 11 by, for example, annealing the SiC single crystal substrate 11 at about 1700° C. in an argon gas atmosphere at atmospheric pressure. The graphene layer 12 may also be formed by laminating the graphene layer 12 on the SiC single crystal substrate 11 by CVD.

[0017] The graphene layer 12 applicable to the embodiment is shown in FIG. 6. The graphene layer 12 has a laminated structure of graphite sheets 121·122·123·...12n. The graphite sheets 121·122·123·...12n on each side of the n-layer structure have a large number of hexagonal carbon (C) covalent bonds in one laminated crystal structure, and the graphite sheets 121·122·123·...12n on each side are bonded by van der Waals forces. In the embodiment, the graphene layer 12 may have a single layer structure, or may be a 0 layer bonded to the SiC single crystal substrate 11 as a buffer layer.

[0018] As shown in Fig. 7, a second composite 92 is formed by stacking an SiC epitaxial growth layer (SiC-epi) 13 on the graphene layer 12 of a first composite 91. The SiC epitaxial growth layer 13 is formed by van der Waals epitaxial growth on the graphene layer 12 formed on the Si surface of a SiC single crystal substrate 11. The SiC epitaxial growth layer 13 is a single crystal SiC thin film made of α-SiC. The surface of the SiC epitaxial growth layer 13 in contact with the graphene layer 12 is the C-plane, and the surface of the SiC epitaxial growth layer 13 is the Si-plane.

[0019] As shown in FIG. 8 , an adhesive layer 14 is formed on SiC epitaxial growth layer 13 of second composite 92, and the coated surface of adhesive layer 14 is attached to one side of a temporary graphite substrate 19 having an outer size slightly larger than that of SiC single crystal substrate 11 to form a third composite 93.

[0020] A carbon adhesive containing a thermosetting phenolic resin as a main component and a solid carbon component is used for the adhesive layer 14. The carbon adhesive is capable of maintaining its bonding strength even at high temperatures by carbonizing the adhesive itself. Carbon adhesives are commercially available, for example, from Nisshinbo Chemical Inc. (product name ST-201). Thermosetting resins such as epoxy resin, polyimide resin, and polyester resin may be used for the adhesive layer 14 instead of the phenolic resin contained in the carbon adhesive. The third composite 93 is stored in a thermostatic bath or the like and heated to, for example, about two hundred and several tens of degrees Celsius, and the adhesive layer 14 is dried and hardened.

[0021] The graphite substrate 19 may have a glassy carbon coating on its surface. The glassy carbon coating has a strong adhesive force with a carbon adhesive, which makes it easy to separate the SiC epitaxial growth layer 13 and the graphene layer 12 in a process described later, thereby improving the yield.

[0022] As the graphite substrate 19, which is a temporary substrate with a slightly larger outer size, for example, if the SiC single crystal substrate 11 has a diameter of about 10 cm, a graphite substrate 19 with an outer size of about 11 cm, which is about 10 mm larger, is used. For example, if the SiC single crystal substrate 11 has a diameter of about 15 cm, a graphite substrate 19 with an outer size of about 16 cm is used. The temporary substrate (graphite substrate 19) which is slightly larger in size than the SiC single crystal substrate 11 has the advantage that when it is inserted and aligned in the wafer boat groove of a batch-type vertical CVD furnace, the traces of the wafer boat supports are outside the effective substrate area.

[0023] As shown in FIG. 9, the SiC epitaxial growth layer 13 of the second composite 92 may be attached to both sides of the graphite substrate 19 of the temporary substrate via the adhesive layer 14 to form a fourth composite 94. In this case, the adhesive layer 14 is also formed on the SiC epitaxial growth layer 13 of each second composite 92, and the SiC epitaxial growth layer 13 is attached to both sides of the graphite substrate 19 of the temporary substrate, which has an outer size slightly larger than that of the SiC single crystal substrate 11. For the fourth composite 94, an adhesive containing a thermosetting resin as a main component such as a carbon adhesive is used for the adhesive layer 14, and the adhesive layer 14 is dried and hardened by heating to, for example, about 200° C. in a thermostatic bath or the like. For the fourth composite 94, the graphite substrate 19 of the temporary substrate may have a glassy carbon coating on its surface, as in the third composite 93 shown in FIG. 8. In the following, the manufacturing method of a semiconductor substrate will be explained using a fourth composite 94 in which the second composite 92 is attached to both sides of a graphite substrate 19 of a temporary substrate, but the manufacturing method can also be applied to a third composite 93 in which the second composite 92 is attached to only one side of a graphite substrate 19 of a temporary substrate.

[0024] As shown in FIG. 10, the fourth composite 94 in which the adhesive layer 14 has been dried and hardened by heating is stored in a low-temperature bath and cooled, causing an initial crack 71 to occur between the graphene layer 12 and the SiC epitaxial growth layer 13. Representative values ​​of the thermal conductivity and thermal expansion coefficient of the materials constituting the fourth composite 94 are shown in Table 1 below. Since the low-temperature bath is cooled to, for example, 0° C. or less, the fourth composite 94 is rapidly cooled, and the temperature drops from the SiC single crystal substrate 11, which has a large thermal conductivity, and the temperature of the graphite substrate 19, which has a small thermal conductivity compared to the SiC single crystal substrate, increases. Due to the difference in the amount of thermal expansion caused by such a relative temperature difference, thermal stress occurs in the fourth composite 94, and the stress concentrates at the interface end between the SiC epitaxial growth layer 13 and the graphene layer 12, which are joined by van der Waals bonding, and the initial crack 71 occurs from the periphery due to the separation.

[0025] [Table 1]

[0026] In detail, a temperature gradient occurs from a portion of the SiC epitaxial growth layer 13 close to the graphite substrate 19 of the temporary substrate to the SiC single crystal substrate 11, which generates a tensile stress acting on the interface between the SiC epitaxial growth layer 13 and the graphene layer 12. Then, at the outer periphery of the bond, which is the interface end portion where the tensile stress is concentrated, an initial crack 71 occurs when the strain energy due to the maximum stress exceeds the bind energy between the SiC epitaxial growth layer 13 and the graphene layer 12. When the initial crack 71 occurs, the stress concentration is temporarily released, so that if the SiC single crystal substrate 11 is wafer-sized as in the embodiment, it will not peel off completely as it is, but in a substrate of about 1 cm square, it may peel off completely.

[0027] In addition, when the adhesive strength between the SiC single crystal substrate 11 and the graphite substrate 19 of the temporary substrate by the adhesive layer 14 is weaker than the binding energy between the SiC epitaxial growth layer 13 and the graphene layer 12, an initial crack may occur on the interface side between the graphite substrate 19 and the adhesive layer 14. In the embodiment, in order to prevent a decrease in the adhesive area ratio due to gas generation from the adhesive layer 14 as described above, the adhesive layer 14 is gradually degassed while being thermally cured according to the heat treatment conditions for drying and curing recommended by the adhesive manufacturer (constant temperature of 80°C x 8 hours → constant temperature of 120°C x 4 hours → heating to 200°C at a heating rate of 10°C / hour or less → constant temperature of 200°C x 1 hour), thereby ensuring an adhesive strength between the SiC single crystal substrate 11 and the graphite substrate 19 of the temporary substrate that is greater than the binding energy of the interface between the SiC epitaxial growth layer 13 and the graphene layer 12.

[0028] Incidentally, the binding energy between the SiC epitaxial growth layer 13 and the single-layer graphene layer 12 is 40 to 50 meV, whereas the binding energy between the SiC epitaxial growth layer 13 and the zero-layer graphene layer 12, also called the buffer layer, is 106 meV, which is 2.1 times larger than the binding energy between the SiC epitaxial growth layer 13 and the zero-layer graphene layer 12. Therefore, when the graphene layer 12 is the zero-layer, a larger peeling energy is required. The thermal expansion coefficients of the graphite substrate 19 and the SiC single crystal substrate 11, which are the temporary substrates, are 3.0 ppm and 3.9 ppm, respectively, and there is not much difference between them, so a large temperature difference is required to generate a large thermal stress. In fact, when the temperature difference ΔT between the graphite substrate 19 and the SiC single crystal substrate 11 is set to 200° C., an internal thermal stress of about 25 GPa is generated. This stress is a stress value sufficient to destroy the SiC single crystal substrate 11, and such a large stress is not necessary; however, in order to generate an initial crack 71, it is desirable to set ΔT to a temperature of 40° C. or more to approximately 60° C. in the case of a single graphene layer 12, and to a temperature of 80° C. or more to approximately 120° C. in the case of zero graphene layers 12.

[0029] As shown in FIG. 11, the fourth composite 94 of FIG. 9 may be heated to dry and harden the adhesive layer 14, and then immersed in liquid nitrogen for cooling to generate an initial crack 71 between the graphene layer 12 and the SiC epitaxial growth layer 13. When the fourth composite 94 is gravity-dropped into liquid nitrogen 78 filling a container 77 to be rapidly cooled, the internal thermal stress generated by cooling is concentrated at the interface end between the graphene layer 12 and the SiC epitaxial growth layer 13, which is a weak point of the structure, and the bond at the interface end is destroyed to generate the initial crack 71. At the moment the initial crack 71 occurs, the internal stress is released to a certain extent and reduced, so that the expansion of the initial crack 71 stops unless the thermal stress increases thereafter. Here, the heating temperature and the conditions and type of the cooling medium are appropriately set so that the initial crack 71 does not expand too much due to the thermal shock being applied more than necessary.

[0030] As shown in FIG. 12, an initial crack 71 formed between the graphene layer 12 and the SiC epitaxial growth layer 13 at the periphery of the fourth composite 94 is extended to form a crack 72 over the entire interface between the graphene layer 12 and the SiC epitaxial growth layer 13. For this purpose, an ultrasonic transducer 75 is pressed against the surface of the single crystal SiC substrate 11 of the fourth composite 94, and ultrasonic waves are irradiated so that the tip of the crack 72 extending along the interface is the focal point, and the partial heating by the focused ultrasonic waves is used as the extension stress of the crack 72. Then, the ultrasonic transducer 75 is scanned so that the crack 72 extends over the entire interface. By forming the crack 72 over the entire interface, it becomes possible to divide the fourth composite 94 at the interface between the graphene layer 12 and the SiC epitaxial growth layer 13. Here, it is preferable that the irradiation energy of the ultrasonic transducer 75 is the minimum necessary to extend the crack 72. The magnitude of the irradiation energy must be optimally determined depending on parameters such as the temperature of the SiC single crystal substrate 11, the ultrasonic irradiation angle, the irradiation area and energy density, energy absorption rate, thermal conductivity, and heat dissipation efficiency.

[0031] Instead of using ultrasonic transducer 75, a laser beam may be irradiated onto the surface of single crystal SiC substrate 11 of fourth complex 94, and the laser beam may be scanned to heat the vicinity of the tip of crack 72 propagating along the interface. Even when using laser beam instead of ultrasonic transducer 75, the irradiation energy of the laser beam must be set to the minimum necessary to propagate crack 72, and the magnitude of the irradiation energy must be optimized according to parameters such as SiC single crystal substrate 11.

[0032] As shown in FIG. 13, the fourth composite 94 is divided at the interface between the graphene layer 12 and the SiC epitaxial growth layer 13. Since the cracks 72 are formed throughout the interface between the graphene layer 12 and the SiC epitaxial growth layer 13, the graphene layer 12 can be easily divided at the interface between the graphene layer 12 and the SiC epitaxial growth layer 13. The interface between the graphene layer 12 and the SiC epitaxial growth layer 13 may peel off spontaneously, or when it does not peel off spontaneously, it may be mechanically peeled off using an adhesive peeling tape, a debonder device, or the like. When the SiC single crystal substrate 11 and the graphene layer 12 that have been divided from the fourth composite 94 are removed, a fifth composite 95 is formed.

[0033] The graphene layer 12 is removed by etching or polishing from the laminate of the SiC single crystal substrate 11 and the graphene layer 12 removed from the fourth composite 94. In the etching process of the graphene layer 12, for example, a plasma asher using oxygen plasma can be applied. Since the Si surface of the SiC single crystal substrate 11 from which the graphene layer 12 has been etched by oxygen plasma is oxidized, wet etching using hydrogen fluoride (HF) is performed. In addition, in the polishing process of the graphene layer 12, the graphene layer 12 is removed by, for example, chemical mechanical polishing (CMP). Here, the Si surface of the SiC single crystal substrate 11 has an average surface roughness Ra of, for example, about 1 nm or less due to the above-mentioned wet etching process. As a result, the SiC single crystal substrate 11 becomes reusable.

[0034] FIG. 14 shows a fifth composite 95. The fifth composite 95 is heated in an annealing furnace in a vacuum or inert gas atmosphere, and the adhesive layer 14 is carbonized. The thermosetting resin contained in the adhesive layer 14 has a different carbon residual rate after carbonization depending on the carbon content. The carbon residual rate of phenolic resin is 60% by mass or more, while that of epoxy resin, polyimide resin, and polyester resin is less than 50% by mass. If the carbon residual rate is low, pores will be generated by carbonization and the adhesive strength will decrease, so it is desirable for the carbon residual rate to be 50% or more. In epoxy resins and the like with a carbon residual rate of less than 50% by mass, it is necessary to add a solid carbon component to the adhesive to compensate for the carbon residual rate in order to suppress the generation of pores, but it is better not to add too much of the solid carbon component from the viewpoint of adhesiveness. In contrast, phenolic resins generally have a carbon residual rate of 60% or more, making them suitable as thermosetting resins.

[0035] When using phenolic resin as the thermosetting resin, it is desirable to add 15 to 40% by mass of carbon components to the adhesive. If it is less than 15% by mass, the carbonization rate of the adhesive layer is insufficient and the adhesive strength is insufficient, and if it exceeds 40% by mass, the adhesive layer 14 becomes too thick and the adhesive strength decreases. The carbon adhesive (product name: ST-201) has an additive rate of 29% solid carbon components, and appropriate adhesive strength is obtained after heat curing and carbonization treatment.

[0036] As shown in FIG. 15, a SiC polycrystalline growth layer (SiC-poly) 15 is formed on the C-face of the SiC epitaxial growth layer 13 of the fifth composite 95. The SiC polycrystalline growth layer 15 can be formed by, for example, CVD technology. The SiC polycrystalline growth layer 15 has a 3C (cubic) structure and is also called α-SiC. The SiC polycrystalline growth layer 15 is formed on the C-face of the SiC epitaxial growth layer 13 to form a substrate layer of the device wafer structure. The C-face of the SiC epitaxial growth layer 13 becomes the back surface of the device wafer structure, so the flatness of the surface is not required very much. Therefore, the SiC polycrystalline growth layer 15 can be formed by a simple polishing process.

[0037] The SiC polycrystalline growth layer 15 is deposited to a thickness that provides the necessary mechanical strength for the substrate of the SiC-based semiconductor device, forming a sixth composite 96. The thickness of the SiC polycrystalline growth layer 15 is preferably about 150 μm to 500 μm, and is adjusted as necessary so that the thickness of the completed SiC composite substrate (SiC polycrystalline growth layer 15 + SiC epitaxial growth layer 13) is about 150 μm to 500 μm. By reducing the thickness of the SiC polycrystalline growth layer 15, the thermal conductivity is improved. The deposition temperature of the SiC polycrystalline growth layer 15 is preferably in the range of 1300°C to 1600°C.

[0038] As shown in Fig. 16, the SiC polycrystalline growth layer 15 formed on the periphery of the sixth composite 96 and unnecessary portions of the graphite substrate 19 of the temporary substrate are ground and removed by an outer periphery grinding device to form a seventh composite 97 in which the SiC epitaxial growth layer 13, the adhesive layer 14, and the graphite substrate 19 are exposed. In the seventh composite 97, the graphite substrate 19 and the like are exposed, making it possible to remove the graphite substrate 19 and the like by burning. In Fig. 16, the periphery of the seventh composite 97 has a unique contour in the direction in which the layers are stacked.

[0039] 17, the seventh composite 97 is heated in a thermal annealing furnace in an air or oxygen atmosphere, and the graphite substrate 19 and the carbonized adhesive layer 14 are removed by oxidative combustion to form an eighth composite 98. The eighth composite 98 is composed of two blocks of a SiC composite substrate 10 including a SiC epitaxial growth layer 13 and a SiC polycrystalline growth layer 15 disposed on the C-plane of the SiC epitaxial growth layer 13.

[0040] Fig. 18 shows a cross-sectional view of the SiC composite substrate 10. Fig. 19 shows an overhead view of the SiC composite substrate 10. In the SiC composite substrate 10, the surface of the SiC epitaxial growth layer 13 is a Si face of α-SiC with a

[0001] orientation of 4H-SiC, and the C face is a face of 4H-SiC with a [000-1] orientation. The thickness of the SiC polycrystalline growth layer 15 is, for example, about 150 µm to about 500 µm, and the thickness of the SiC epitaxial growth layer 13 is, for example, about 4 µm to about 100 µm.

[0041] 20, in the SiC epitaxial growth layer 13, a highly doped layer 13a may be formed toward the C-face of the SiC epitaxial growth layer 13 in contact with the SiC polycrystalline growth layer 15. The highly doped layer 13a suppresses the spread of a depletion layer in the SiC epitaxial growth layer 13, and also makes it possible to easily form an ohmic contact with the SiC polycrystalline growth layer 15 formed on the C-face of the SiC epitaxial growth layer 13.

[0042] The highly doped layer 13a can be formed, for example, by using a high-dose ion implantation technique. For example, in the case of an n-type semiconductor, the highly doped layer 13a is formed by high-dose phosphorus (P) ion implantation. When formed by P ion implantation, there is an effect on the crystallinity of the P ion-implanted C-face of the SiC epitaxial growth layer 13, but the Si face that becomes the device face has already been formed, and the crystallinity of the Si face is preserved.

[0043] The highly doped layer 13a may be formed by forming a highly nitrogen (N) doped epitaxial growth layer in the early stage of forming the SiC epitaxial growth layer (SiC-epi) 13 shown in Fig. 7. Although the highly nitrogen (N) doped epitaxial growth layer has an effect on crystallinity due to mismatch of lattice constants, the process is simple since it is formed by autodoping in the early stage of epitaxial growth.

[0044] (Semiconductor Substrate) As shown in Fig. 7 as a second composite 92, the semiconductor substrate according to the embodiment is obtained by disposing a graphene layer 12 on the Si surface of a SiC single crystal substrate 11 and disposing a SiC epitaxial growth layer 13 on the graphene layer 12. As shown in Fig. 10 as a fourth composite 94, the semiconductor substrate is configured such that, when the semiconductor substrate is attached to a graphite substrate 19 of a temporary substrate via an adhesive layer 14 and cooled, an initial crack 71 occurs between the graphene layer 12 and the SiC epitaxial growth layer 13. The semiconductor substrate in which the initial crack 71 occurs is processed into a SiC composite substrate 10 as shown in Fig. 18 according to the manufacturing method of a semiconductor substrate according to the present embodiment.

[0045] Specifically, as shown in Fig. 12, the graphene layer 12 and the SiC epitaxial growth layer 13 can be divided by extending a crack 72 from the initial crack 71 to the entire surface of the interface between the graphene layer 12 and the SiC epitaxial growth layer 13. Furthermore, as shown in Fig. 13, the graphene layer 12 and the SiC single crystal substrate 11 can be removed to form a fifth composite 95 as shown in Fig. 14. Thereafter, as shown in Fig. 15, a SiC polycrystalline growth layer 15 is deposited to form a sixth composite 96, and as shown in Fig. 16, the outer periphery is ground to form a seventh composite 97. As shown in Fig. 17, the graphite substrate 19 and the adhesive layer 14 of the temporary substrate are removed to form an eighth composite 98, and the SiC composite substrate 10 shown in Fig. 18 is obtained as upper and lower blocks of the eighth composite 98.

[0046] The graphene layer 12 of the semiconductor substrate has an appropriate binding energy so that an initial crack 71 occurs between the graphene layer 12 and the SiC epitaxial growth layer 13 when the fourth composite 94 attached to the graphite substrate 19 of the temporary substrate via the adhesive layer 14 as shown in FIG. 10 is cooled. For example, the single graphene layer 12 has a binding energy of 40 to 50 meV, and the zero graphene layer has a binding energy of 106 meV. When the fourth composite 94 is cooled, a thermal stress exceeding the binding energy of the graphene layer 12 is applied between the graphene layer 12 and the SiC epitaxial growth layer 13, causing an initial crack 71 to occur.

[0047] The semiconductor substrate according to the embodiment may be a substrate having a graphite substrate 19 as a temporary substrate attached via an adhesive layer 14 onto the SiC epitaxial growth layer 13 of the second composite 92 shown in Fig. 7. The graphite substrate 19 may be a substrate having a SiC epitaxial growth layer 13 attached to one side thereof as shown as a third composite 93 in Fig. 8, or a substrate having a SiC epitaxial growth layer 13 attached to both sides thereof as shown as a fourth composite 94 in Fig. 9.

[0048] The graphite substrate 19 has an outer size slightly larger than that of the SiC single crystal substrate 11. The graphite substrate 19 is attached to the SiC epitaxial growth layer 13 by an adhesive layer 14. A carbon adhesive containing a phenolic resin as a main component and a solid carbon component and the like is used for the adhesive layer 14. The carbon adhesive is an adhesive that can maintain its bonding strength even at high temperatures by carbonizing the adhesive itself. Note that, instead of the phenolic resin contained in the carbon adhesive, a thermosetting resin such as an epoxy resin, a polyimide resin, or a polyester resin may be used for the adhesive layer 14.

[0049] The graphite substrate 19 may have a glassy carbon coating on the surface thereof. The glassy carbon coating has a strong adhesive force with a carbon adhesive, and therefore can easily peel off the SiC epitaxial growth layer 13 from the graphene layer 12. The graphite substrate 19 may have a disk-like or rectangular plate-like shape.

[0050] (Semiconductor element) The SiC composite substrate 10 manufactured by the semiconductor substrate manufacturing method according to the embodiment or the SiC composite substrate 10 manufactured from the semiconductor substrate according to the embodiment can be used, for example, in the manufacture of various SiC-based semiconductor elements. In the following, as examples thereof, a SiC-SBD, a SiC trench gate (T: Trench) type TMOSFET, and a SiC planar gate type MOSFET will be described.

[0051] (SiC-SBD) As shown in FIG. 21, the SiC-SBD 21, which is a semiconductor device fabricated using a SiC composite substrate, includes a SiC composite substrate 10 consisting of a SiC polycrystalline growth layer (SiC-poly CVD) 15 and a SiC epitaxial growth layer (SiC-epi) 13. A highly doped layer 13a may be interposed between the SiC polycrystalline growth layer 15 and the SiC epitaxial growth layer 13. The highly doped layer 13a suppresses the spread of a depletion layer in the SiC epitaxial growth layer 13, and easily forms an ohmic contact with the SiC polycrystalline growth layer 15 formed on the C-face of the SiC epitaxial growth layer 13. The SiC epitaxial growth layer 13 serves as a drift layer, the highly doped layer 13a serves as a buffer layer, and the SiC polycrystalline growth layer 15 serves as a substrate layer.

[0052] The SiC polycrystalline growth layer 15 is + type (impurity density is, for example, about 1×10 18 cm -3 ~Approx. 1×10 21 cm -3 ) and the SiC epitaxial growth layer 13 is doped with n - type (impurity density is, for example, about 5×10 14 cm -3 ~Approx. 5×10 16 cm -3 The heavily doped layer 13a is doped to a higher concentration than the SiC epitaxial growth layer 13.

[0053] Furthermore, the SiC epitaxial growth layer 13 may have any one of the crystal structures of 4H-SiC, 6H-SiC, or 2H-SiC.

[0054] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.

[0055] As the p-type doping impurity, for example, B (boron), Al (aluminum) or the like can be used.

[0056] The back surface ((000-1) C surface) of the SiC polycrystalline growth layer 15 is provided with a cathode electrode 21 so as to cover the entire area.

[0057] In addition, a surface 13b (e.g., a (0001) Si surface) of the SiC epitaxial growth layer 13 has a contact hole 23 that exposes a portion of the SiC epitaxial growth layer 13 as an active region 22, and a field insulating film 25 is formed in a field region 24 surrounding the active region 22.

[0058] The field insulating film 25 is made of SiO2 (silicon oxide), but may be made of other insulators such as silicon nitride (SiN). An anode electrode 26 is formed on the field insulating film 25, and the anode electrode 26 is connected to an anode terminal A.

[0059] A p-type JTE (Junction Termination Extension) structure 27 is formed in the vicinity of the surface 13b (surface layer portion) of the SiC epitaxial growth layer 13 so as to be in contact with the anode electrode 26. The JTE structure 27 is formed along the contour of the contact hole 23 so as to straddle the inside and outside of the contact hole 23 of the field insulating film 25.

[0060] (SiC-TMOSFET) As a semiconductor device fabricated using the SiC composite substrate 10 according to the embodiment, a trench-gate TMOSFET 30 includes a SiC composite substrate 10 including a SiC polycrystalline growth layer 15 and a SiC epitaxial growth layer 13, as shown in FIG. 22. A highly doped layer 13a may be interposed between the SiC polycrystalline growth layer 15 and the SiC epitaxial growth layer 13. The highly doped layer 13a suppresses the spread of a depletion layer in the SiC epitaxial growth layer 13, and easily forms an ohmic contact with the SiC polycrystalline growth layer 15 formed on the C-face of the SiC epitaxial growth layer 13. The SiC epitaxial growth layer 13 serves as a drift layer, the highly doped layer 13a serves as a buffer layer, and the SiC polycrystalline growth layer 15 serves as a substrate layer.

[0061] The SiC polycrystalline growth layer 15 is + type (impurity density is, for example, about 1×10 18 cm -3 ~Approx. 1×10 21 cm -3 ) and the SiC epitaxial growth layer 13 is doped with n - type (impurity density is, for example, about 5×10 14 cm -3 ~Approx. 5×10 16 cm -3 The heavily doped layer 13a is doped to a higher concentration than the SiC epitaxial growth layer 13.

[0062] Furthermore, the SiC epitaxial growth layer 13 may have any one of the crystal structures of 4H-SiC, 6H-SiC, or 2H-SiC.

[0063] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.

[0064] As the p-type doping impurity, for example, B (boron), Al (aluminum) or the like can be used.

[0065] The back surface ((000-1) C surface) of the SiC polycrystalline growth layer 15 is provided with a drain electrode 31 so as to cover the entire area.

[0066] In the vicinity (surface layer portion) of the surface 13b ((0001) Si surface) of the SiC epitaxial growth layer 13, p-type (impurity density is, for example, about 1×10 16 cm -3 ~Approx. 1×10 19 cm -3 In the SiC epitaxial growth layer 13, the portion on the SiC polycrystalline growth layer 15 side with respect to the body region 32 is maintained in the state of the SiC epitaxial growth layer 13, and n - The drain region 33(13) is of the type.

[0067] A gate trench 34 is formed in the SiC epitaxial growth layer 13. The gate trench 34 penetrates the body region 32 from the surface 13b of the SiC epitaxial growth layer 13, and its deepest portion reaches the drain region 33 (13).

[0068] A gate insulating film 35 is formed on the inner surface of the gate trench 34 and on the surface 13b of the SiC epitaxial growth layer 13 so as to cover the entire inner surface of the gate trench 34. The inside of the gate insulating film 35 is filled with, for example, polysilicon, so that a gate electrode 36 is embedded in the gate trench 34. A gate terminal G is connected to the gate electrode 36.

[0069] The surface layer of the body region 32 includes n-type GaN layers that form part of the side surface of the gate trench 34. + A source region 37 is formed.

[0070] The SiC epitaxial growth layer 13 has p + type (impurity density is, for example, about 1×10 18 cm -3 ~Approx. 1×10 21 cm -3 ) a body contact region 38 is formed.

[0071] An interlayer insulating film 41 made of SiO2 is formed on the SiC epitaxial growth layer 13. A source electrode 43 is connected to the source region 37 and the body contact region 38 via a contact hole 42 formed in the interlayer insulating film 41. A source terminal S is connected to the source electrode 43.

[0072] By applying a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) to the gate electrode 36 while a predetermined potential difference is generated between the source electrode 43 and the drain electrode 31 (between the source and drain), a channel can be formed in the body region 32 near the interface with the gate insulating film 35 by the electric field from the gate electrode 36. This allows a current to flow between the source electrode 43 and the drain electrode 31, turning the SiC-TMOSFET 31 on.

[0073] (SiC planar gate MOSFET) As a semiconductor device fabricated using the SiC composite substrate 10, a planar gate MOSFET 50 includes the SiC composite substrate 10 including a SiC polycrystalline growth layer 15 and a SiC epitaxial growth layer 13, as shown in FIG. 23. A highly doped layer 13a may be interposed between the SiC polycrystalline growth layer 15 and the SiC epitaxial growth layer 13. The highly doped layer 13a suppresses the spread of a depletion layer in the SiC epitaxial growth layer 13, and easily forms an ohmic contact with the SiC polycrystalline growth layer 15 formed on the C-face of the SiC epitaxial growth layer 13. The SiC epitaxial growth layer 13 serves as a drift layer, the highly doped layer 13a serves as a buffer layer, and the SiC polycrystalline growth layer 15 serves as a substrate layer.

[0074] The SiC polycrystalline growth layer 15 is + type (impurity density is, for example, about 1×10 18 cm -3 ~Approx. 1×10 21 cm -3 ) and the SiC epitaxial growth layer 13 is doped with n - type (impurity density is, for example, about 5×10 14 cm -3 ~Approx. 5×10 16 cm -3 ) is doped.

[0075] Furthermore, the SiC epitaxial growth layer 13 may have any one of the crystal structures of 4H-SiC, 6H-SiC, or 2H-SiC.

[0076] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.

[0077] As the p-type doping impurity, for example, B (boron), Al (aluminum) or the like can be used.

[0078] A drain electrode 51 is formed on the back surface ((000-1) C surface) of the SiC composite substrate 10 so as to cover the entire area, and a drain terminal D is connected to the drain electrode 51.

[0079] In the vicinity (surface layer portion) of the surface 13b ((0001) Si surface) of the SiC epitaxial growth layer 13, p-type (impurity density is, for example, about 1×10 16 cm -3 ~Approx. 1×10 19 cm -3 The body region 52 of the SiC epitaxial growth layer 13 is formed in a well shape. The portion of the SiC epitaxial growth layer 13 on the SiC composite substrate 10 side with respect to the body region 52 is maintained in the state after the epitaxial growth, i.e., n - The drain region 53(13) is of the type.

[0080] The surface layer of the body region 52 is + A source region 54 of the type is formed in spaced relation to the periphery of the body region 52 .

[0081] Inside the source region 54, p + type (impurity density is, for example, about 1×10 18 cm -3 ~Approx. 1×10 21 cm -3 ) is formed in the body contact region 55. The body contact region 55 penetrates the source region 54 in the depth direction and is connected to the body region 52.

[0082] A gate insulating film 56 is formed on the surface 13b of the SiC epitaxial growth layer 13. The gate insulating film 56 covers a portion of the body region 52 surrounding the source region 54 (the peripheral portion of the body region 52) and the outer periphery of the source region 54.

[0083] A gate electrode 57 made of, for example, polysilicon is formed on the gate insulating film 56. The gate electrode 57 faces the peripheral edge of the body region 52 with the gate insulating film 56 interposed therebetween. A gate terminal G is connected to the gate electrode 57.

[0084] An interlayer insulating film 58 made of SiO2 is formed on the SiC epitaxial growth layer 13. A source electrode 62 is connected to the source region 54 and the body contact region 55 via a contact hole 61 formed in the interlayer insulating film 58. A source terminal S is connected to the source electrode 62.

[0085] By applying a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) to the gate electrode 57 while a predetermined potential difference is generated between the source electrode 62 and the drain electrode 51 (between the source and drain), a channel can be formed in the body region 52 near the interface with the gate insulating film 56 by the electric field from the gate electrode 57. This allows a current to flow between the source electrode 62 and the drain electrode 51, turning the planar gate MOSFET 50 on.

[0086] As described above, according to the embodiment, before forming SiC polycrystalline growth layer 15 by CVD, SiC single crystal substrate 11 is separated and replaced with a temporary substrate made of highly heat-resistant graphite substrate 19, thereby preventing unwanted adhesion of polycrystalline SiC to SiC single crystal substrate 11 and maximizing the reusability of SiC single crystal substrate 11, thereby enabling further cost reduction.

[0087] According to the embodiment, an initial crack 71 occurs between the graphene layer 12 and the SiC epitaxial growth layer due to thermal stress caused by rapid cooling, and the interface between the graphene layer 12 and the SiC epitaxial growth layer 13 is heated by irradiating the surface of the SiC epitaxial growth layer 13 with ultrasonic waves or laser light to extend the crack 72 over the entire interface, thereby enabling the graphene layer 12 and the SiC epitaxial growth layer 13 to be separated. Therefore, there is no need to form a stress layer, and costs for its deposition, removal, and the like can be reduced.

[0088] In addition, metal contamination, which is a problem with metal stressor films that are generally used in van der Waals epitaxy and remote epitaxy, can be avoided. For example, when a metal stressor film such as a nickel / titanium laminated film is formed on the surface of the SiC epitaxial growth layer 13 to generate stress that generates cracks, the metal reacts with the SiC constituent elements on the surface of the SiC epitaxial growth layer 13 to generate nickel silicide (NiSix), titanium silicide (TiSix), or titanium carbide (TiCx), which remains on the surface of the SiC epitaxial growth layer 13 even after the metal film is removed, causing metal contamination. This metal contamination can cause quality problems when the SiC epitaxial growth layer 13 is additionally grown or when a MOSFET device or the like is formed on the surface. In the embodiment, since no metal stressor layer is provided, such metal contamination does not occur.

[0089] Furthermore, according to the embodiment, since there is no stress variation caused by the film quality or film thickness distribution of the stressor film, it is easy to accommodate larger diameter substrates. Furthermore, high temperature processes such as embrittlement annealing in ion implantation delamination method are not required, and diffusion of impurities can be prevented. Furthermore, since there is no introduction of a stressor film with a linear expansion coefficient different from that of the bulk in the next process of CVD deposition of polycrystalline β-SiC, the film stress generated during film formation is reduced, and the occurrence of cracks due to the stress can be suppressed.

[0090] According to the embodiment, by making the graphite substrate 19 one size larger than the SiC single crystal substrate 11, it becomes possible to perform single-sided or double-sided epitaxial growth using an epitaxial growth apparatus such as a batch-type vertical tubular furnace, and high throughput and low-cost production can be realized without unduly increasing the growth rate. In addition, the graphite substrate 19 and the carbonized adhesive layer 14 can be removed at low cost simply by firing them in an oxidation furnace or the like.

[0091] According to the embodiment, van der Waals epitaxial growth of SiC is performed via graphene formed on a SiC single crystal substrate, and a SiC polycrystalline growth layer is formed directly thereon by CVD, which eliminates the need for substrate bonding and eliminates defects caused by substrate bonding. In addition, since the epitaxial growth layer is formed via graphene, the SiC single crystal substrate and the epitaxial growth layer can be easily separated, simplifying the process, and eliminating the need for expensive processes such as ion implantation delamination.

[0092] According to the embodiment, after the SiC single crystal substrate is removed, the highly heat-resistant handle substrate is placed in a high-temperature LP-CVD apparatus, and a SiC polycrystalline growth layer is grown directly on the epitaxial growth layer. This eliminates the steps of transporting the epitaxial growth layer having a thickness of several μm from the handle substrate to a support substrate and bonding the epitaxial growth layer to the support substrate, thereby making it possible to avoid defects such as wrinkles, crystal transitions, and voids caused by thin film transportation and bonding.

[0093] According to the embodiment, the graphene layer formed on the SiC single crystal substrate 11 is not transferred, but epitaxial growth is performed directly on the graphene layer. This makes it possible to avoid defects such as wrinkles and cracks caused by the transfer of graphene.

[0094] According to the embodiment, since the SiC single crystal substrate 11 is used as a base, hexagonal SiC with little deterioration in crystallinity can be obtained. In addition, the SiC single crystal substrate 11 is expensive and difficult to remove by polishing or etching, but by using van der Waals epitaxial growth via the graphene layer 12, the obtained SiC epitaxial growth layer 13, which is a high-performance single crystal, can be easily separated, making removal by polishing or etching unnecessary. Since the expensive SiC single crystal substrate 11 can be reused after separation, a large cost advantage can be obtained.

[0095] Although the embodiment has been described above, it is also possible to carry out the present invention in other forms. For example, although not shown in the drawings, it is also possible to manufacture a MOS capacitor using the SiC composite substrate 10. In the MOS capacitor, the yield and reliability can be improved.

[0096] Although not shown in the drawings, a bipolar transistor can also be manufactured using the SiC composite substrate 10. In addition, the SiC composite substrate 10 according to the embodiment can also be used to manufacture SiC-pn diodes, SiCIGBTs, SiC complementary MOSFETs, etc. The SiC composite substrate 1 can also be applied to other types of devices such as LEDs (light emitting diodes) and semiconductor optical amplifiers (SOAs).

[0097] The SiC epitaxial growth layer 13 may include at least one type or a plurality of types selected from the group consisting of Group IV element semiconductors, Group III-V compound semiconductors, and Group II-VI compound semiconductors.

[0098] Furthermore, the SiC composite substrate 10 and the SiC epitaxial growth layer 13 may be made of any one of 4H-SiC, 6H-SiC, and 2H-SiC materials.

[0099] Furthermore, the SiC single crystal substrate 11 and the SiC epitaxial growth layer 13 may comprise, as a material other than SiC, at least one selected from the group consisting of GaN, BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite.

[0100] A semiconductor device including the SiC composite substrate 10 may include any of GaN-, AlN-, and gallium oxide-based IGBTs, diodes, MOSFETs, and thyristors other than SiC-based.

[0101] A semiconductor device including a SiC composite substrate 10 may have any of the following configurations: a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module.

[0102] With the SiC composite substrate 10, for example, a low-cost SiC polycrystalline growth layer 15 can be used as the substrate material instead of the high-cost SiC single crystal substrate 11.

[0103] (Appendix 1) The method for manufacturing the semiconductor substrate includes the steps of forming a graphene layer 12 on the Si surface of the SiC single crystal substrate 11, forming a SiC epitaxial growth layer 13 on the graphene layer 12, attaching a graphite substrate 19 of a temporary substrate to the SiC epitaxial growth layer 13 via an adhesive layer 14, generating an initial crack 71 between the graphene layer 12 and the SiC epitaxial growth layer 13, extending the crack 72 over the entire interface between the graphene layer 12 and the SiC epitaxial growth layer 13 to divide the interface, and removing the graphene layer 12 and the SiC single crystal substrate 11, forming a SiC polycrystalline growth layer 15 on the SiC epitaxial growth layer 13, and removing the graphite substrate 19. There is no need to form a stress layer, and the costs for its deposition and removal can be reduced.

[0104] (Appendix 2) In the method for manufacturing a semiconductor substrate according to Appendix 1, the adhesive layer 14 may contain a thermosetting resin. The thermosetting resin is cured by heating and can be further carbonized.

[0105] (Appendix 3) In the method for producing a semiconductor substrate according to appended claim 2, the thermosetting resin may contain a phenol resin. The phenol resin can have an appropriate carbon residual rate by carbonization.

[0106] (Appendix 4) In the method for manufacturing a semiconductor substrate according to any one of Supplementary Note 1 to 3, the step of attaching the graphite substrate 19 of the temporary substrate includes a step of drying and curing the adhesive layer 14 by heating. By drying and curing by heating, the adhesive layer 14 can be reliably bonded.

[0107] (Appendix 5) In the method for manufacturing a semiconductor substrate according to appendix 4, the step of heating the adhesive layer 14 includes a step of storing the adhesive layer 14 in a constant temperature bath and heating the adhesive layer 14. The heating temperature can be controlled with high accuracy.

[0108] (Appendix 6) In the method for manufacturing a semiconductor substrate according to any one of claims 1 to 4, the step of generating the initial crack 71 includes a step of generating thermal stress by cooling from a surface of at least one of the SiC epitaxial growth layer 13 and the graphite substrate 19 of the temporary substrate. This eliminates the need to provide a stress layer for applying stress.

[0109] (Appendix 7) In the method for producing a semiconductor substrate according to claim 6, the step of cooling includes a step of storing in a low-temperature bath at 0° C. or lower. The heating temperature can be controlled with high accuracy.

[0110] (Appendix 8) In the method for producing a semiconductor substrate according to claim 6, the step of cooling includes a step of immersing in liquid nitrogen. Liquid nitrogen is easily available and easy to handle.

[0111] (Appendix 9) In the method for manufacturing a semiconductor substrate according to any one of Supplementary Note 1 to 8, the step of propagating the crack 72 includes a step of heating the interface between the graphene layer 12 and the SiC epitaxial growth layer 13. The crack can be propagated along the interface.

[0112] (Appendix 10) In the method for manufacturing a semiconductor substrate according to Supplementary Note 9, the step of heating the interface includes a step of scanning the surface of the SiC single crystal substrate 11 with an ultrasonic transducer. The interface can be heated by ultrasonic waves irradiated from the ultrasonic transducer.

[0113] (Appendix 11) In the method for manufacturing a semiconductor substrate according to Supplementary Note 9, the step of heating the interface includes the step of scanning with laser light the surface of the SiC single crystal substrate 11. The interface can be heated by scanning with the laser light.

[0114] (Appendix 12) The method for manufacturing a semiconductor substrate according to any one of appendices 1 to 11 further includes, after the step of extending the cracks 72 to divide the interface and before the step of forming the SiC polycrystalline growth layer 15, a step of carbonizing the adhesive layer 14 by heating. In the step of forming the SiC polycrystalline growth layer 15, evaporation of the adhesive layer 14 is prevented.

[0115] (Appendix 13) In the method for manufacturing a semiconductor substrate according to any one of Supplementary Note 1 to 12, the graphite substrate 19 serving as the temporary substrate has a disk-like or rectangular plate-like shape. The shape can be adjusted according to the shape of the SiC single crystal substrate 11 or the CVD furnace.

[0116] (Appendix 14) In the method for manufacturing a semiconductor substrate according to any one of appendices 1 to 13, the graphite substrate 19 serving as a temporary substrate has an outer size larger than that of the SiC single crystal substrate 11. When the graphite substrate 19 is inserted into a wafer boat groove in a batch-type vertical CVD furnace and aligned, the marks of the wafer boat support pillars can be positioned outside the effective substrate area.

[0117] (Appendix 15) In the method for manufacturing a semiconductor substrate according to any one of appendices 1 to 14, the graphite substrate 19 of the temporary substrate contains graphite. It can be removed by burning.

[0118] (Appendix 16) In the method for manufacturing a semiconductor substrate according to any one of claims 1 to 15, the graphite substrate 19 of the temporary substrate includes a glassy carbon coating formed on the surface thereof. The glassy carbon coating has a strong adhesive force with the carbon adhesive of the adhesive layer 14.

[0119] (Appendix 17) In the method for manufacturing a semiconductor substrate according to any one of appendices 1 to 16, the step of removing the graphite substrate 19 of the temporary substrate includes burning and removing the graphite substrate 19. The graphite substrate 19 can be burned and removed in an air atmosphere or the like.

[0120] (Appendix 18) The method for producing a semiconductor substrate according to claim 17 further includes a step of burning and removing the adhesive layer 14. The adhesive layer 14 can be burned and removed together with the graphite substrate 19 in an air atmosphere or the like.

[0121] (Appendix 19) The method for manufacturing a semiconductor substrate according to any one of appendices 1 to 18 further includes, after the step of forming the SiC polycrystalline growth layer 15 and before the step of removing the graphite substrate 19 of the temporary substrate, a step of grinding the graphite substrate 19 and the SiC polycrystalline growth layer 15 formed on the outer periphery of the SiC epitaxial growth layer 13 to expose the graphite substrate 19. By exposing the graphite substrate 19, it becomes possible to burn it.

[0122] (Appendix 20) The method for manufacturing a semiconductor substrate according to any one of appendices 1 to 19 further includes a step of forming a highly-doped layer 13a having a higher impurity concentration than the SiC epitaxial growth layer 13 on a C-face of the SiC epitaxial growth layer 13 that is in contact with the SiC polycrystalline growth layer 15. The highly-doped layer 13a suppresses the spread of a depletion layer in the SiC epitaxial growth layer 13, and easily forms an ohmic contact with the SiC polycrystalline growth layer 15 formed on the C-face of the SiC epitaxial growth layer 13.

[0123] (Appendix 21) In the method for manufacturing a semiconductor substrate according to any one of appendices 1 to 20, in the step of attaching the graphite substrate 19 as a temporary substrate, the SiC epitaxial growth layer 13 is attached only to one surface of the graphite substrate 19. Both the SiC single crystal substrate 11 and the graphite substrate 19 can be cooled.

[0124] (Appendix 22) In the method for manufacturing a semiconductor substrate according to any one of appendices 1 to 20, in the step of attaching the graphite substrate 19 as a temporary substrate, the SiC epitaxial growth layers 13 are attached to both sides of the graphite substrate 19. By attaching the SiC epitaxial growth layers 13 to both sides of the graphite substrate 19, the graphite substrate 19 can be efficiently utilized.

[0125] (Appendix 23) In the method for producing a semiconductor substrate according to any one of appendices 1 to 22, the step of forming the graphene layer 12 forms a single graphene layer 12. Since the graphene layer 12 is secured, it can be easily peeled off.

[0126] (Appendix 24) In the method for producing a semiconductor substrate according to any one of appendices 1 to 22, the step of forming the graphene layer 12 forms 0 graphene layers 12. Since the graphene layer 12 is bonded to the SiC single crystal substrate 11, epitaxial growth via the graphene layer 12 becomes easy.

[0127] (Appendix 25) The semiconductor substrate includes a SiC single crystal substrate 11, a graphene layer 12 formed on the Si face of the SiC single crystal substrate 11, and a SiC epitaxial growth layer 13 formed on the graphene layer 12, and is configured such that when a graphite substrate 19 serving as a temporary substrate is attached onto the SiC epitaxial growth layer 13 via an adhesive layer 14 and cooled, a crack occurs between the graphene layer 12 and the SiC epitaxial growth layer 13. No stress layer is required, and costs associated with its formation, removal, and the like can be reduced.

[0128] (Appendix 26) The semiconductor substrate according to claim 25, further comprising a graphite substrate 19 as a temporary substrate attached onto the SiC epitaxial growth layer 13 via an adhesive layer 14. The SiC epitaxial growth layer 13 attached to the graphite substrate 19 can be separated from the graphene layer 12.

[0129] (Appendix 27) The semiconductor substrate according to claim 25, wherein the graphite substrate 19 of the temporary substrate contains graphite. It can be removed by burning.

[0130] (Appendix 28) In the semiconductor substrate according to any one of appendices 25 to 27, the adhesive layer 14 contains a thermosetting resin and can be reliably bonded by drying and curing the resin by heating.

[0131] (Appendix 29) The thermosetting resin according to Appendix 28, comprising a phenolic resin. The phenolic resin can obtain an appropriate carbon residual rate by carbonization.

[0132] (Appendix 30) A semiconductor device formed from the semiconductor substrate according to any one of appendices 26 to 29, in which a semiconductor element structure is formed on the C-face of the SiC epitaxial growth layer 13 of the SiC composite substrate 10 having a SiC polycrystalline growth layer 15 formed on the Si-face of the SiC epitaxial growth layer 13. By using the low-cost SiC composite substrate 10, the semiconductor device can also be provided at low cost.

[0133] (Appendix 31) In the semiconductor device according to claim 30, the semiconductor element includes at least one of a SiC Schottky barrier diode, a SiC-MOSFET, a SiC bipolar transistor, a SiC diode, a SiC thyristor, and a SiC insulated gate bipolar transistor. Various useful SiC-based semiconductor elements can be provided.

[0134] (Other embodiments) As described above, several embodiments have been described, but the descriptions and drawings forming part of the disclosure are illustrative and should not be understood as limiting. From this disclosure, various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art. Thus, the embodiments include various embodiments not described herein. [Industrial Applicability]

[0135] The present disclosure can be used in various semiconductor module technologies, such as IGBT modules, diode modules, and MOS modules (SiC, GaN, AlN, gallium oxide), and can be applied to a wide range of application fields, such as power modules for inverter circuits that drive electric motors used as power sources for electric vehicles (including hybrid vehicles), trains, industrial robots, etc., and power modules for inverter circuits that convert power generated by solar cells, wind turbines, and other power generation devices (especially private power generation devices) into power from commercial power sources. [Explanation of symbols]

[0136] 10 SiC composite substrate 11 SiC single crystal substrate 11c Hydrogen ion implantation layer 11d Thinned SiC single crystal layer 12 Graphene layers 13. SiC epitaxial growth layer 14 Adhesive layer 15 SiC polycrystalline growth layer 19 Graphite Substrate

Claims

1. forming a graphene layer on a Si surface of a SiC single crystal substrate; forming a SiC epitaxial growth layer on the graphene layer; attaching a temporary substrate onto the SiC epitaxial growth layer via an adhesive; generating cracks between the graphene layer and the SiC epitaxial growth layer; extending the crack over the entire interface between the graphene layer and the SiC epitaxial growth layer to divide the interface, and removing the graphene layer and the SiC single crystal substrate; forming a SiC polycrystalline growth layer on the SiC epitaxial growth layer; removing the temporary substrate; A method for manufacturing a semiconductor substrate comprising the steps of:

2. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the adhesive contains a thermosetting resin.

3. The method for manufacturing a semiconductor substrate according to claim 2 , wherein the thermosetting resin includes a phenolic resin.

4. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the step of attaching the temporary substrate includes a step of drying and curing the adhesive by heating.

5. The method for manufacturing a semiconductor substrate according to claim 4 , wherein the step of heating the adhesive includes a step of storing the adhesive in a constant temperature chamber and heating the adhesive.

6. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the step of generating cracks includes the step of generating thermal stress by cooling from a surface of at least one of the SiC epitaxial growth layer and the temporary substrate.

7. The method for manufacturing a semiconductor substrate according to claim 6 , wherein the cooling step includes a step of storing the substrate in a low-temperature bath at 0° C. or lower.

8. The method for manufacturing a semiconductor substrate according to claim 6 , wherein the step of cooling includes the step of immersing in liquid nitrogen.

9. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the step of propagating the crack includes the step of heating an interface between the graphene layer and the SiC epitaxial growth layer.

10. The method for manufacturing a semiconductor substrate according to claim 9 , wherein the step of heating the interface includes the step of scanning the surface of the SiC single crystal substrate with an ultrasonic transducer.

11. The method for manufacturing a semiconductor substrate according to claim 9 , wherein the step of heating the interface includes the step of scanning a surface of the SiC single crystal substrate with a laser beam.

12. 2. The method for manufacturing a semiconductor substrate according to claim 1, further comprising the step of carbonizing the adhesive by heating after the step of extending the crack to separate the interface and before the step of forming the SiC polycrystalline growth layer.

13. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the temporary substrate has a disk-like or rectangular plate-like shape.

14. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the temporary substrate has an outer size larger than that of the SiC single crystal substrate.

15. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the temporary substrate includes graphite.

16. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the temporary substrate includes a glassy carbon coating formed on a surface thereof.

17. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the step of removing the temporary substrate comprises burning the temporary substrate to remove it.

18. The method for manufacturing a semiconductor substrate according to claim 17 , wherein the step of removing the temporary substrate comprises burning off the adhesive and removing the adhesive together.

19. 2. The method for manufacturing a semiconductor substrate according to claim 1, further comprising the step of: after the step of forming the SiC polycrystalline growth layer, and before the step of removing the temporary substrate, grinding the SiC polycrystalline growth layer formed on the outer periphery of the temporary substrate and the SiC epitaxial growth layer to expose the temporary substrate.

20. 2. The method for manufacturing a semiconductor substrate according to claim 1, wherein the step of forming the SiC epitaxial growth layer further includes the step of growing a highly doped layer having a higher impurity concentration than the SiC epitaxial growth layer on a C-face of the SiC epitaxial growth layer that is in contact with the SiC polycrystalline growth layer.

21. A SiC single crystal substrate; A graphene layer formed on a Si surface of the SiC single crystal substrate; a SiC epitaxial growth layer formed on the graphene layer; Including, The semiconductor substrate is configured such that, when a temporary substrate is attached onto the SiC epitaxial growth layer via an adhesive and cooled, a crack occurs between the graphene layer and the SiC epitaxial growth layer.

22. The semiconductor substrate of claim 21 , wherein the temporary substrate comprises graphite.

23. The semiconductor substrate of claim 21 , wherein the adhesive comprises a thermosetting resin.

24. The semiconductor substrate of claim 23 , wherein the thermosetting resin comprises a phenolic resin.

25. 25. A semiconductor device in which a semiconductor element structure is formed on the C surface of a SiC epitaxial growth surface of a SiC composite substrate formed from the semiconductor substrate according to any one of claims 21 to 24, in which a SiC polycrystalline growth layer is formed on the Si surface of a SiC epitaxial growth layer.

26. 26. The semiconductor device according to claim 25, wherein the semiconductor element includes at least one of a SiC Schottky barrier diode, a SiC MOSFET, a SiC bipolar transistor, a SiC diode, a SiC thyristor, and a SiC insulated gate bipolar transistor.

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