Active clamp flyback converter and control IC

Abstract

To provide an ACF converter capable of performing a zero-voltage switching operation by reducing fluctuation in an operating frequency that accompanies changes in an output voltage and an output current.SOLUTION: An ACF converter 10 includes a transformer T having a secondary winding Ns electromagnetically coupled to a primary winding Np, a first series circuit in which the primary winding Np and a main switch QL are connected in series to both ends of a DC power source Vin, a second series circuit in which a switch QH and a capacitor Cac are connected in series to both ends of the primary winding Np, a control unit 100a that turns the main switch QL and the switch QH on and off, a rectifying and smoothing circuit for the secondary winding, and an output voltage detection unit that detects an output voltage of the circuit. The control unit has a first drive signal for turning the main switch on and off, and a second drive signal and a third drive signal that turn the switch QH on and off while the main switch is in an off-period, and controls a first off-period from off-time of the first drive signal until on-time of the second drive signal, and a second off-period from off-time of the second drive signal until on-time of the third drive signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an active clamp flyback converter and a control IC. [Background technology]

[0002] Flyback converters have been proposed as power supply circuits for isolated DC-DC converters. When the main switch is on, a flyback converter passes current through the primary winding of a transformer, storing energy in the inductance of the transformer. When the main switch is off, the energy stored in the excitation inductance is extracted from the secondary winding of the transformer, transmitting power from the primary side to the secondary side.

[0003] Also, to improve the efficiency of flyback converters, active clamp flyback converters (ACF converters) have been proposed, in which the RCD snubber circuit is composed of a clamp switch and a clamp capacitor. The RCD snubber circuit suppresses surge voltages by recovering leakage energy with a capacitor and dissipating it through a resistor.

[0004] The ACF converter is capable of recovering the leakage energy stored in the leakage inductance of the transformer, and can also realize ZVS (zero volt switching), which reduces the switching loss of the main switch.

[0005] As an example of this ACF converter, a non-complementary control ACF is described in Patent Document 1. The non-complementary control ACF disclosed in Patent Document 1 does not operate the main switch and the clamp switch complementarily, but turns on the clamp switch once for a set fixed time before the main switch is turned on and after the transformer excitation current has fallen to zero.

[0006] In a non-complementary control ACF, when the load current decreases, the current in the leakage inductance decreases, and the voltage drop in the voltage resonant capacitor due to the short resonance period between the voltage resonant capacitor and the leakage inductance becomes small, making ZVS impossible. In the non-complementary control ACF shown in Patent Document 1, the peak current of the excitation inductance is controlled to be almost constant even when the load current decreases, and the off (oscillation) period is lengthened according to the decrease in the load current, thereby realizing ZVS even when the output current decreases. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] China Patent Publication No. 101572490 Summary of the Invention [Problem to be solved by the invention]

[0008] However, in the power conversion device described in Patent Document 1, because the current of the excitation inductance is controlled to be constant, there are problems in that, under light loads, energy consumption decreases, the off period becomes longer, and the frequency drops to the audible range. Therefore, it is necessary to reduce the excitation inductance current according to the load current and to lower the operating frequency.

[0009] The present invention has been made in consideration of the problems inherent in the conventional techniques, and an object of the present invention is to provide an active clamp flyback converter and a control IC that are capable of reducing the fluctuation in operating frequency caused by changes in output voltage and output current and maintaining zero-voltage switching operation. [Means for solving the problem]

[0010] An active clamp flyback converter and control IC according to an embodiment of the present invention includes a first series circuit in which a main switch and a primary winding are connected in series across a DC power supply, a second series circuit in which a clamp switch and a clamp capacitor are connected in series across the primary winding, a transformer having a secondary winding electromagnetically coupled to the primary winding, a control unit that turns the main switch and the clamp switch on and off, a rectifying and smoothing circuit that rectifies and smoothes the voltage of the secondary winding, and an output voltage detection unit that detects the output voltage of the rectifying and smoothing circuit, wherein the control unit has a first drive signal that turns the main switch on and off, a second drive signal that turns the clamp switch on and off while the main switch is off, and a third drive signal that turns the clamp switch on and off after the second drive signal, and controls a first off period in which both the main switch and the clamp switch are off from the off time of the first drive signal to the on time of the second drive signal, and a second off period in which both the main switch and the clamp switch are off from the off time of the second drive signal to the on time of the third drive signal. Effect of the Invention

[0011] According to the present invention, it is possible to provide an active clamp flyback converter and a control IC that are capable of reducing fluctuations in operating frequency that accompany changes in output voltage and output current and maintaining zero-voltage switching operation. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing the configuration of an ACF converter according to the first embodiment. [Diagram 2] FIG. 2 is a diagram showing the configuration of a control unit of the ACF converter according to the first embodiment. [Diagram 3] FIG. 3 is a diagram showing a configuration of an enable signal generating means of the ACF converter according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing operational waveforms of the enable signal generating means according to the first embodiment. [Diagram 5] FIG. 5 is a diagram showing characteristics of the enable signal generating means according to the first embodiment. [Figure 6A] FIG. 6A is a diagram showing an example of an operation waveform of the ACF converter in the first embodiment. [Figure 6B] FIG. 6B is a diagram showing an example of an operation waveform of the ACF converter in the first embodiment. [Figure 6C] FIG. 6C is a diagram showing an example of an operation waveform of the ACF converter in the first embodiment. [Figure 6D] FIG. 6D is a diagram showing an example of an operation waveform of the ACF converter in the first embodiment. [Figure 7] FIG. 7 is a diagram showing the configuration of the excitation current detection means. [Figure 8] FIG. 8 is a diagram showing an example of an operational waveform when the output voltage is varied in the ACF converter in the first embodiment. [Figure 9] FIG. 9 is a diagram showing the configuration of an ACF converter according to the second embodiment. [Figure 10] FIG. 10 is a diagram showing a configuration of an enable signal generating means of an ACF converter according to the second embodiment. [Figure 11] FIG. 11 is a diagram showing an example of an operational waveform of the enable signal generating means according to the second embodiment. [Figure 12] FIG. 12 is a diagram showing the characteristics of the enable signal generating means according to the second embodiment. [Figure 13] FIG. 13 is a diagram showing an example of an operation waveform of the ACF converter in the second embodiment. [Figure 14] FIG. 14 is a diagram showing an example of an operation waveform of the ACF converter in the first and second embodiments. [Figure 15] FIG. 15 is a diagram showing fluctuations in operating frequency with respect to output current in the first and second embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an active clamp flyback converter (ACF converter 10) according to some embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts in the drive circuit according to each embodiment will be denoted by the same reference numerals and their description will be omitted. In this embodiment, the active clamp flyback converter corresponds to the ACF converter 10.

[0014] The present invention relates to a configuration of an ACF and a control method thereof in ACF control (hybrid ACF control) in which a clamp switch QH (see FIG. 1) is turned on and off twice during an off period of a main switch QL (see FIG. 1) of an ACF converter 10.

[0015] (About ACF Converter 10) A flyback converter is one of the power circuit topologies for isolated DC-DC converters. When the main switch is on, the flyback converter passes current through the primary winding of the transformer and stores energy in the inductance of the transformer. When the main switch is off, the energy stored in the excitation inductance is extracted from the secondary winding of the transformer, transmitting power from the primary side to the secondary side.

[0016] However, there is uncoupled leakage inductance between the primary and secondary windings of the transformer. In a flyback converter, when the main switch is on, a current also flows through this leakage inductance, and energy is stored in it.

[0017] The leakage energy stored in this leakage inductance cannot be transmitted from the secondary winding to the secondary side because no back electromotive force is generated in the direction that would turn on the rectifier connected to the secondary winding after the main switch is turned off. Therefore, the back electromotive force of the leakage inductance generates a high surge voltage across both ends of the turned-off main switch, which could destroy the main switch.

[0018] For example, if a MOSFET is used for the main switch, if this surge voltage exceeds the withstand voltage of the MOSFET, it may cause an avalanche breakdown and destroy the MOSFET. Normally, an RCD snubber circuit consisting of a capacitor, resistor, and diode is connected across the primary winding of the transformer to suppress this surge voltage.

[0019] The RCD snubber circuit suppresses surge voltage by recovering leakage energy with a capacitor and dissipating it with a resistor. Therefore, one of the challenges in improving efficiency in flyback converters is the regeneration of leakage energy.

[0020] Another challenge to improving efficiency in a flyback converter is the reduction of switching losses. For example, when a flyback converter uses a MOSFET as the main switch, the parasitic capacitance Coss of the MOSFET exists between the drain and source of the MOSFET. When the MOSFET turns on, if there is a voltage Vds(0) across the drain and source, the parasitic capacitance Coss is 1 / 2Coss × Vds(0). 2 of energy is stored.

[0021] When the MOSFET turns on, this energy is lost in the on-resistance of the MOSFET. Zero-Volt Switching (ZVS), which sets the voltage across the switch to zero volts when the switch turns on, is known as a method for reducing this switching loss. ZVS sets the voltage across the switch, Vds(0), to zero volts when the switch turns on, so 1 / 2Coss × Vds(0) 2 Therefore, ZVS is one of the challenges to improve efficiency in flyback converters.

[0022] In order to improve the efficiency of flyback converters, an active clamp flyback converter (ACF converter) has been proposed, in which an RCD snubber circuit is composed of a clamp switch and a clamp capacitor.

[0023] The first advantage of the ACF converter is that it can regenerate the leakage energy stored in the leakage inductance of the transformer. The second advantage of the ACF converter is that it can achieve ZVS for the main switch. Therefore, the ACF converter is effective as a topology for high-efficiency power supply circuits.

[0024] The ACF converter recovers leakage energy by temporarily transferring the leakage energy accumulated while the main switch is on to a clamp capacitor after the main switch is turned off. When the clamp switch is turned on, the energy transferred to the clamp capacitor is applied to the primary winding of the transformer. The voltage applied to the primary winding is in the direction that causes the diode connected to the secondary winding to conduct, so the leakage energy can be recovered to the output.

[0025] ZVS also requires discharging the capacitance component that is equivalently connected across the main switch. The capacitance component corresponds to the respective Coss when the main switch or clamp switch is a MOSFET, the coupling capacitance when the secondary rectifier is a diode, the interwinding capacitance of the transformer, etc.

[0026] In an ACF converter, turning on the clamp switch makes it possible to apply the voltage of the clamp capacitor to the primary winding of the transformer in the opposite direction to the power supply voltage, allowing a negative current to flow through the excitation inductance and leakage inductance. This current flowing through the negative excitation inductance and leakage inductance can discharge the voltage resonant capacitor, making ZVS possible.

[0027] However, when the clamp switch of an ACF converter is turned on, resonance occurs between the leakage inductance and the clamp capacitor with a resonance period Tcalk, and the difference between this resonance current and the excitation current flows from the secondary winding as a secondary-side current. Therefore, various issues arise due to the relationship between this resonance period Tcalk and the on-period of the clamp switch.

[0028] The ACF converter 10 according to this embodiment solves the above-mentioned problems, and further reduces the fluctuation in operating frequency that accompanies changes in output voltage and output current, making it possible to maintain zero-voltage switching operation.

[0029] (First embodiment) Fig. 1 is a diagram showing the configuration of an ACF converter 10 according to the first embodiment. Fig. 2 is a block diagram of a control unit 100a that controls the ACF converter 10. The control unit 100a corresponds to a control IC.

[0030] The ACF converter 10 according to the first embodiment includes a first series circuit in which a main switch QL and a primary winding Np of a transformer T are connected in series across a DC power source Vin. The ACF converter 10 also includes a second series circuit in which a clamp switch QH and a clamp capacitor Cac are connected in series across the primary winding Np.

[0031] The main switch QL and the clamp switch QH are made of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and each has a body diode BDL, BDH between its drain and source.

[0032] In addition, the MOSFET has a parasitic capacitance Coss between the drain and source, and this capacitance appears in the resonant operation. To simplify the explanation of the operation, Fig. 1 shows an example in which the parasitic capacitance Coss is connected to both ends of the main switch QL as a voltage resonant capacitor Cv, but it is not necessary to attach a capacitor other than the parasitic capacitance Coss of the MOSFET.

[0033] Furthermore, the main switch QL and the clamp switch QH may be switch elements made of compound semiconductors such as GaN (gallium nitride) and SiC (silicon carbide). The main switch QL and the clamp switch QH may be configured with IGBTs (insulated gate bipolar transistors). If the element structure does not have a body diode, it can be replaced by separately adding BDL and BDH. For convenience of explanation, the main switch QL and the clamp switch QH are described in this specification as MOSFETs.

[0034] The ACF converter 10 further includes a transformer T having a primary winding Np and a secondary winding Ns electromagnetically coupled to the primary winding Np. The transformer T is configured so that the primary winding Np has an excitation inductance Lm and a leakage inductance Llk, and the coupling coefficient between the primary winding Np and the secondary winding Ns is less than 1. A rectifier element Ds and an output capacitor Co are connected in series to both ends of the secondary winding Ns, and a first rectifier circuit that rectifies and smoothes the voltage of the secondary winding Ns is connected to the both ends of the secondary winding Ns. The first rectifier circuit corresponds to a rectifier smoothing circuit.

[0035] Furthermore, the transformer T has an auxiliary winding Na, and both ends of the auxiliary winding Na are connected to a second rectifier circuit in which a rectifier element Da and a capacitor Ca are connected in series.

[0036] The ACF converter 10 also includes an output voltage detection unit 200 that detects the output capacitor voltage, a winding voltage detection means that detects the winding voltage, and an Id detection means Rs that detects the current of the main switch QL.

[0037] Furthermore, the ACF converter 10 includes a control unit 100a that controls the main switch QL and the clamp switch QH. The control unit 100a controls the main switch QL and the clamp switch QH based on a Vfb signal detected by the output voltage detection unit 200, a voltage Vcc detected by the winding voltage detection means, and an ISense signal that is an output signal detected by the Id detection means Rs. Specifically, the control unit 100a turns the main switch QL on and off, and turns the clamp switch QH on and off twice with a first pulse and a second pulse during an off period of the main switch QL.

[0038] The control unit 100a has a current source Icc, and generates a Vfb signal indicating a feedback voltage based on the output signal of the output voltage detection unit 200. The control unit 100a also includes a comparator 114 that compares the ISense signal with the Vfb signal.

[0039] The comparator 114 is connected so that the ISense signal goes High when the value of the Vfb signal exceeds the value of the Vfb signal, and outputs the signal to an R terminal of an SR-FF 115 (SR flip-flop). A P0S signal is input to an S terminal of the SR-FF 115, and the comparator 114 outputs a P0 signal that sets the output of the SR-FF 115 to High at the falling edge of the P0S signal and sets the output of the SR-FF 115 to Low.

[0040] The control unit 100a also includes a first driving means 151 that receives the P0 signal and generates a signal to drive the main switch QL. The first driving means 151 controls the ON width of a driving signal VgsL for the main switch QL to control the output voltage to a constant voltage. The driving signal VgsL corresponds to the first driving signal.

[0041] Furthermore, the control unit 100a has an output voltage detection means 111 that receives the auxiliary winding voltage Vna, generates a VoD signal indicating a voltage proportional to the output voltage, and outputs the VoD signal to the P1 threshold generation means 144. The VoD signal corresponds to a second voltage signal.

[0042] The control unit 100a also includes a zero-cross detection means 112 that receives the auxiliary winding voltage Vna and outputs a ZCD signal, which is a pulse signal that detects a zero voltage at which the voltage of the auxiliary winding Na changes from a negative voltage to a positive voltage, to the P2 delay means 143. The ZCD signal corresponds to a zero-cross signal.

[0043] Furthermore, the control unit 100a has an excitation current detection means 113 that receives the auxiliary winding voltage Vna, generates an LmC signal indicating a voltage proportional to the excitation current, and outputs the LmC signal to the P1 generation means 121. The LmC signal corresponds to a first voltage signal.

[0044] The P1 threshold generating means 144 generates a threshold signal Vth1 by multiplying the VoD signal, which is the output of the output voltage detecting means 111, by a preset ratio so that the threshold becomes a value indicated by a threshold signal Vth1 described later, and outputs the generated signal to the P1 generating means 121. That is, when the value of the VoD signal increases or decreases, the value of the threshold signal Vth1 also increases or decreases proportionally. The P1 threshold generating means 144 corresponds to a first pulse threshold generating means.

[0045] The P1 generating means 121 sets the signal P1 to High based on the LmC signal of the excitation current detecting means 113 and the threshold signal Vth1 of the P1 threshold generating means 144, and sends out a signal with a preset pulse width. The P1 generating means 121 corresponds to a first pulse generating means.

[0046] Here, the preset ratio in the P1 threshold generating means 144 and the preset pulse width in the P1 generating means 121 are determined as follows: The time when the excitation current becomes zero is defined as time tz.

[0047] The timing at which the P1 signal generated by the P1 generating means 121 becomes High is 0.5×Tcalk to 1.22×Tcalk before the time tz. In this embodiment, Tcalk indicates the resonance period. The P1 signal corresponds to the first pulse signal.

[0048] The timing at which the P1 signal goes low is set to be earlier than time tz. Furthermore, the pulse width of the P1 signal is set to 0.5×Tcalk or more. The threshold signal Vth1 of the P1 threshold generating means 144 and the pulse width of the P1 generating means 121 are determined so that a P1 signal with such a pulse width is generated.

[0049] By setting as above, even if the output voltage changes, the timing when the P1 signal goes High is 1.22×Tcalk before the above-mentioned 0.5×Tcalk, and the timing when the P1 signal goes Low is before the time tz when the excitation current becomes zero. If the output voltage does not change, the threshold signal Vth1 may be a threshold voltage that is predetermined to have the timing described above. The predetermined threshold voltage corresponds to the third voltage signal.

[0050] Furthermore, the control unit 100a includes a disable signal generating means 142. The disable signal generating means 142 outputs to a P2 delay means 143 a disable signal Dis that goes High in response to a P0S signal, receives a P1 signal, and goes Low after a preset delay time has elapsed.

[0051] The control unit 100a also includes a P2 delay means 143. The P2 delay means 143 is reset by a P0S signal, and outputs to the P2 delay means 143 an Enb signal, which is a pulse signal based on a Vfb signal indicating a feedback voltage.

[0052] Furthermore, the P2 delay means 143 receives the Dis signal, the Enb signal, and the ZCD signal, and when the Dis signal is Low and the Enb signal is High, it uses the ZCD signal as a trigger to output a P2Dy signal to the P2 generation means 122. The P2 delay means 143 corresponds to a second pulse delay means.

[0053] Furthermore, the control unit 100a has a P2 generating means 122 that receives a P2Dy signal, outputs a P2 signal having a preset pulse width, and outputs the P2 signal to the second driving means 152. The P2 generating means 122 corresponds to a second pulse generating means. The P2 signal corresponds to a second pulse signal.

[0054] Furthermore, the control unit 100a has a second driving means 152 that receives the P1 signal and the P2 signal and outputs a driving signal VgsH twice to drive the clamp switch QH of the ACF converter 10. The first driving signal VgsH is output based on the P1 signal. The second driving signal VgsH is output based on the P2 signal. The first driving signal VgsH corresponds to the second driving signal, and the second driving signal VgsH corresponds to the third driving signal.

[0055] 3 is a diagram showing the configuration of the enable signal generating means 130a of the control unit 100a according to the first embodiment. The enable signal generating means 130a includes a reference voltage Vosc and a subtraction circuit 131 that outputs a voltage VT obtained by subtracting the value of a Vfb signal indicating a feedback voltage from the reference voltage Vosc.

[0056] The enable signal generating means 130a also includes a VRamp circuit, which includes a reference current Iosc, a capacitor Cosc that is charged by the reference current Iosc, and a switch Sosc that resets the capacitor Cosc, which are connected in parallel to each other.

[0057] When the P0S signal becomes L, the VRamp circuit generates the ramp voltage VR by charging the capacitor Cosc with the reference current Iosc. The enable signal generating means 130a includes a comparator COMosc having VT connected to its negative terminal (negative terminal) and the ramp voltage VR connected to its positive terminal (positive terminal), and outputs the Enb signal, which is a pulse signal that becomes High when the ramp voltage VR exceeds the voltage VT.

[0058] FIG. 4 is a diagram showing operational waveforms of the enable signal generating means 130a.

[0059] In Fig. 4, (a) to (d) show operational waveforms when the output current increases toward the right side of the drawing. In the example shown in Fig. 4, it is shown that the value of the Vfb signal increases as the output current increases due to the configuration of the output voltage detection unit 200 and the control unit 100a.

[0060] Since the reference current Iosc is a preset current source, the slope of the ramp voltage VR increases at a constant rate as shown in Figure 4. As the output current increases, the value of the Vfb signal rises, and when the difference with the reference voltage Vosc becomes smaller, the voltage VT decreases, and the time it takes for the Enb signal to go high becomes shorter. When the value of the Vfb signal becomes higher than the reference voltage Vosc, it goes high when the P0S signal goes low.

[0061] Fig. 5 is a diagram showing the characteristics of the enable signal generating means 130a of Fig. 3. The horizontal axis is the value of the Vfb signal indicating the feedback voltage, and the vertical axis is the time Enb_Delay from when the switch Sosc is turned off until the Enb signal goes High.

[0062] As described above, the reference current Iosc is a preset current source, and the slope of the ramp voltage VR increases at a constant rate. The voltage VT is the difference between the preset reference voltage Vosc and the value of the Vfb signal. Therefore, as shown in FIG. 5, the characteristics of the enable signal generating means 130a are controlled so that the time Enb_Delay from when the switch Sosc is turned off until the Enb signal goes High is proportional to the negative value of the Vfb signal. The time Enb_Delay is expressed by the following formula (1). Note that a and b are values ​​that satisfy the conditions a<0, B>0, and are expressed by the following formulas (2) and (3).

[0063] [Number 1] Enb_Delay = a × Vfb + b (1) [Number 2] a = -(Cosc / Iosc) (2) [Number 3] b = Cosc (Vosc / Iosc) (3)

[0064] Figures 6A to 6D are diagrams showing operational waveforms of the ACF converter 10 according to the first embodiment. Figures 6A to 6D also show operational waveforms when the output current decreases from Figure 6A to Figure 6D. Due to the configuration of the output voltage detection unit 200 and the control unit 100a, the value of the Vfb signal indicating the feedback voltage decreases as the output current decreases.

[0065] FIG. 6A shows an example in which the output current is large, and illustrates the operating waveforms when the value of the Vfb signal is higher than the reference voltage Vosc.

[0066] In the period T1, at time t1, the P0S signal goes from High to Low, setting SR-FF 115. In addition, when the P0 signal goes High, the drive signal VgsL goes High, and the main switch QL turns on, the current of the main switch QL increases, and the value of the ISense signal rises.

[0067] When the value of the ISense signal reaches the value of the Vfb signal at time t2, the output of the comparator 114 goes High, the SR-FF 115 is reset, the P0 signal goes Low, the drive signal VgsL goes Low, and the main switch QL turns off.

[0068] During the period T1, the DC power supply Vin is connected to a series circuit of the leakage inductance Llk and the excitation inductance Lm, so that the current Itran of the primary winding Np of the transformer T is expressed by the following equation (4) and increases over time. Both the leakage inductance Llk and the excitation inductance accumulate the current Itran. [Number 4] Itran is Itran={Vin / (Lm+Llk)}×t ···(4)

[0069] Furthermore, the auxiliary winding voltage Vna generates a negative voltage proportional to the input voltage.

[0070] Fig. 7 is a diagram showing the excitation current detection means 113 configured with an operational amplifier. If configured with an integrating circuit as shown in Fig. 7, the auxiliary winding voltage Vna is integrated, and the excitation current detection means 113 outputs an LmC signal indicating a voltage proportional to the excitation current.

[0071] In the example shown in FIGS. 6A to 6D, the auxiliary winding voltage Vna crosses zero from negative to positive at time t2.

[0072] 6A, the value of the Vfb signal is higher than the reference voltage Vosc, so the voltage VT of the enable signal generating means 130a is zero, and the Enb signal indicating enable is high. However, the Dis signal indicating disable is high, so the output of the P2 delay means 143 remains at zero.

[0073] In the period T2, when the main switch QL is turned off at time t2, the energy stored in the magnetizing inductance Lm and the leakage inductance Llk generates a back electromotive voltage.

[0074] Since the leakage inductance Llk is not coupled to the secondary winding Ns, it is not output from the secondary winding Ns to the first rectifier circuit, and is charged into the clamp capacitor Cac together with a portion of the energy of the excitation inductance Lm.

[0075] On the other hand, since the excitation inductance Lm is an inductance coupled with the secondary winding Ns, the back electromotive force is generated in a direction that causes the rectifier element Ds, which is a diode connected to the secondary winding Ns of the transformer T, to conduct. In addition, the remaining energy of the excitation inductance Lm that is charged to the clamp capacitor Cac is output to the first rectifier circuit. Then, when the leakage energy is completely charged to the clamp capacitor Cac at time t3, all the energy of the excitation inductance Lm is output to the secondary side.

[0076] In conventional complementary control, the clamp switch QH is turned on in the period T2. However, in the ACF converter 10 of the present embodiment, the clamp switch QH is not turned on in the period T2, which is different from conventional complementary control.

[0077] However, when the load current decreases and the value of the Vfb signal decreases, the period T1 becomes shorter. As a result, when the maximum value of the LmC signal approaches the value of the threshold signal Vth1, the clamp switch QH may be turned on in the period T2. However, such an operation is also included in the scope of this embodiment.

[0078] In the period T3, the energy stored in the leakage inductance Llk becomes zero at time t3, and the energy stored in the excitation inductance Lm is output from the secondary winding Ns to the first rectifier circuit.

[0079] During periods T2 and T3, the energy stored in the excitation inductance Lm is output from the secondary winding Ns to the first rectifier circuit, so that a voltage proportional to the output voltage is generated in the auxiliary winding voltage Vna, and the output of the excitation current detection means 113 decreases in proportion to the excitation current.

[0080] During the period T4, at time t4, the value of the LmC signal decreases, and when it becomes equal to the value of the threshold signal Vth1, the P1 generating means 121 turns on the clamp switch QH.

[0081] Since the energy of the magnetizing inductance Lm is output to the secondary side, when the clamp switch QH is turned on, a resonant current flows between the clamp capacitor Cac and the leakage inductance Llk.

[0082] Therefore, the P1 generating means 121 has an ON width of at least 1 / 2 of Tcalk, which indicates the resonance period of the clamp capacitor Cac and the leakage inductance Llk. In addition, the P1 threshold generating means 144 sets the threshold signal Vth1 and the P1 generating means 121 sets the pulse width of the P1 signal so that the OFF time of the P1 signal is between (tz-0.72Tcalk) and time tz, where t6, when the excitation current becomes zero, is time tz.

[0083] In period T5, after 1 / 2Tcalk has elapsed since the clamp switch QH was turned on, the resonant current is limited by the excitation current and flows through the clamp switch QH to the clamp capacitor Cac. By generating the P1 signal as described above and turning on the clamp switch QH, no resonant current flows when the clamp switch QH is turned on for the second time.

[0084] During period T5, a current flows from the source to the drain of the clamp switch QH.

[0085] The P1 signal is generated under the above conditions, so the P1 signal turns off during period T5. Even if the clamp switch QH turns off during this period, the current path does not change after it is turned off because it is commutated to the body diode BDH. Period T5 ends when the excitation current becomes zero at time t6.

[0086] In period T6, the excitation current becomes zero at time t6, but because the clamp switch QH is off, the excitation current does not flow in the negative direction as in complementary control. Therefore, resonance occurs between the voltage resonant capacitor Cv and the excitation inductance Lm and leakage inductance Llk of the primary winding Np of the transformer T. As a result, the voltages of the main switch QL, the clamp switch QH, and each winding oscillate with the resonant period Tcvlm.

[0087] The disable signal generating means 142 is set to become Low after a preset delay time from the off time of the P1 signal. In this embodiment, the preset delay time is set so that the first zero crossing after the excitation current becomes zero can be detected, since the off time of the P1 signal is generated based on the time when the excitation current becomes zero. In the example shown in Figs. 6A to 6D, the delay time is set so that it occurs immediately after time t6 when the excitation current becomes zero.

[0088] In FIG. 6A, since the value of the Vfb signal indicating the feedback voltage is higher than the reference voltage Vosc, the voltage VT of the enable signal generating means 130a is zero and the Enb signal is already High.

[0089] The P2 delay means 143 receives the ZCD signal after the Enb signal is High and the Dis signal is Low, and outputs a signal with a preset pulse width. Therefore, in FIG. 6A, the P2 delay means 143 outputs a signal P2Dy with a preset pulse width based on the ZCD signal after the Dis signal is Low. The signal P2Dy corresponds to the second pulse delay signal.

[0090] Here, the preset pulse width means that the ZCD signal detects the negative to positive zero crossing of the auxiliary winding voltage Vna, which oscillates with a period of Tcvlm, so the pulse width of the P2Dy signal is set to Tcvlm / 4 in advance. As a result, the time t7 of the edge of the pulse signal of the P2Dy signal becomes the minimum value of the voltage across the clamp switch QH.

[0091] In this example, the case has been described where the zero-cross detection means 112 detects the zero-cross of the auxiliary winding voltage Vna going from negative to positive, and the P2Dy signal is Tcvlm / 4. Even if the zero-cross detection means 112 detects the zero-cross of the auxiliary winding voltage Vna going from positive to negative, and the pulse width of the P2Dy signal is (3 / 4)×Tcvlm, the edge of the pulse signal of the P2Dy signal occurs at time t7. In addition, the edge of the pulse signal of the P2Dy signal becomes the minimum value of the voltage across the clamp switch QH. In other words, the P2 delay means 143 sets the pulse width of the P2 signal in accordance with the polarity of the ZCD signal.

[0092] The clamp switch QH is turned on during the period T7, causing a negative excitation current to flow. The time t7 is the edge of the P2Dy signal, and the P2 generating means 122 generates a signal P2 having a pulse width set in advance at the edge of the P2Dy signal, and outputs the signal P2 to the second driving means 152.

[0093] Here, the preset pulse width refers to the energy stored by passing a negative current through the primary winding inductance of the transformer T during period T7, and is set so that all of the energy charged in the voltage resonant capacitor Cv can be discharged.

[0094] The on-timing of the clamp switch QH of the ACF converter 10 according to the first embodiment is the same as that of general non-complementary control, but no resonant current flows. Therefore, the on-width Ton2 of the P2 signal for the voltage resonant capacitor Cv to become zero is expressed by the following equation (5), where Vac is the voltage of the clamp capacitor Cac.

number

[0095] Here, when the minimum value of the input voltage is Vinmin and the maximum value is Vinmax, Ton2max when the input voltage is at the maximum value is given by the following equation (6).

number

[0096] As a result, the P2 generating means 122 generates a P2 signal with a preset pulse width Ton2max at the edge of the P2Dy signal and outputs it to the second driving means 152, thereby enabling ZVS even if the input voltage drops.

[0097] Note that the above is just one example of settings, and the on-width given by the above formula when the input voltage is Vintyp, which is smaller than Vinmax, may be preset as Ton2typ. In this case, when the input voltage is at its maximum value, ZVS is not used and the on-state occurs at the minimum voltage point, but this has the advantage that the negative current can be reduced and higher efficiency is achieved when the input voltage is equal to or lower than Vtyp.

[0098] In addition, the voltage Vac of the clamp capacitor is the turn ratio N=Np / Ns times the output voltage Vo, so Vac=N·Vo, and Ton2 is expressed by the following equation (7).

number

[0099] Therefore, by incorporating a means for detecting the input voltage and output voltage and correcting Ton2 based on the input / output conditions into the P2 generating means 122, optimal ZVS becomes possible, and a highly efficient power supply can be configured by changing the input voltage.

[0100] In a period T8, the P0 timing generating means 141 sends out a P0S signal with a preset pulse width from the edge of the P2 signal. The P0 signal goes High at the edge of the P0S signal, turning on the main switch QL, and the period ends.

[0101] When the clamp switch QH is turned off at time t8, a period begins in which the voltage resonant capacitor Cv is discharged by a negative current flowing through the inductance of the primary winding Np.

[0102] During this period T8, the inductance component of the primary winding Np and the voltage resonant capacitor Cv resonate. The voltage of the main switch QL drops due to voltage resonance, and the time DT from when the clamp switch QH turns off to when the resonant voltage reaches its minimum point is expressed by the following equation (8), where Tcvlm is the resonant period.

number

[0103] Here, Vac=N·Vo, and if Vo=20V, Vin=300V, and N=7, then DT=Tcvlm / 3, and the P0 timing generation means 141 outputs a P0S signal with a pulse width of Tcvlm / 3 that is preset from the edge of the P2 signal, thereby achieving ZVS.

[0104] In addition, since Vac=N·Vo, the P0 timing generation means 141 can incorporate means for detecting the input voltage and output voltage and correcting the pulse width of the P0S signal based on the input / output conditions, thereby enabling optimal ZVS and enabling the input voltage to change, resulting in the configuration of a highly efficient power supply.

[0105] 6B and 6C show an example in which the output current is smaller than that in FIG. 6A, and are operational waveforms in which the value of the Vfb signal is slightly lower than the reference voltage Vosc.

[0106] The lower the value of the Vfb signal, the lower the IdL current peak becomes, and the shorter the period T1 becomes. Furthermore, the peak value of the LmC signal of the excitation current detection means 113 also becomes lower, and the period from time t2 to time t6, which is the discharge period of the excitation current, becomes shorter.

[0107] Because the value of the Vfb signal is smaller than the reference voltage Vosc, the enable signal generating means 130a outputs a voltage VT based on the difference between the reference voltage Vosc and the value of the Vfb signal. In Fig. 6A, the Enb signal was High at time t1, but in Fig. 6B, the Enb signal goes High after time t3, which is the time Enb_Delay after time t1. However, the P1 signal has not been sent at this time, and the Dis signal is released after the P1 signal, so in Fig. 6B, the clamp switch QH is turned on at the timing when the voltage oscillation first reaches its maximum value after the Dis signal goes Low.

[0108] Even if the output current changes, the resonance period Tcvlm, the leakage inductance Llk, and the resonance period Tcalk of the clamp capacitor Cac do not change.

[0109] Period T2 is approximately 1 / 4 of Tcalk, period T4 is 1 / 2 of Tcalk, and period T6 is Tcvlm, which remains almost unchanged even if the output current changes. In addition, the pulse width of the P2 signal and the P0S signal, and period T5 are also preset times and do not change, but periods T1 and T3 become shorter and the operating frequency increases.

[0110] 6C shows an example of an operation waveform in which the output current is further reduced compared to the example shown in FIG 6B, and the value of the Vfb signal is further lower than the reference voltage Vosc. The IdL current peak is further reduced and the period T1 is further shortened by the amount of the Vfb signal being lowered.

[0111] However, since the value of the Vfb signal becomes smaller than the reference voltage Vosc, the enable signal generating means 130a increases the voltage VT based on the difference between the reference voltage Vosc and the value of the Vfb signal, and the Enb_Delay time increases. Also, Enb becomes High after the time when the Dis signal becomes Low. Therefore, based on the ZCD signal after the Enb signal becomes High, the P2Dy signal is sent, and the ON P2 signal is output, and in the example shown in FIG. 6C, the clamp switch QH is turned on at the maximum value of the third voltage oscillation. Therefore, the periods T1 and T3 become shorter, but the period T6 becomes longer, and the operating frequency decreases.

[0112] FIG. 6D shows an example in which the output current is even smaller than that in FIG. 6C, and illustrates the operation waveforms when the value of the Vfb signal is even lower than the reference voltage Vosc.

[0113] As the value of the Vfb signal becomes lower, the IdL current peak becomes lower, the period T1 becomes shorter, and the periods T1 and T3 become shorter. However, the period T6 becomes longer and the operating frequency becomes lower.

[0114] As described above, when the value of the Vfb signal decreases with a decrease in output current, the active clamp converter and its control IC of the present invention control the on-width of the main switch as in the conventional control technology, and also control the first off-period from time t2 when the main switch QL is turned off to time t4 (on-time) when the clamp switch QH is turned on. They also control the second off-period from time t5 when the clamp switch QH is turned off to time t7 when the clamp switch QH is turned on. Note that during the first and second off-periods, both the main switch QL and the clamp switch QH are off.

[0115] Therefore, when the output current is lowered compared to the conventional ACF with non-complementary control, it becomes possible to reduce the frequency while lowering the IdL peak current, thereby suppressing frequency fluctuation.

[0116] Furthermore, the ACF converter 10 turns on the clamp switch QH for the second time to perform ZVS on the main switch QL, but is not affected by the resonant current of Tcalk, which indicates the resonant period. Therefore, the ACF converter 10 can control the second on width according to the input and output voltages, using the input and output voltages. That is, the ACF converter 10 according to this embodiment has the advantage of being able to perform ZVS over a wide input range, and to realize a highly efficient, low-noise power supply.

[0117] (Modification) Furthermore, the ACF converter 10 according to this embodiment proposes control that enables ZVS even in a power supply device with a variable output voltage. Fig. 8 shows the operating waveforms when the output voltage is increased or decreased without changing the output current in the first embodiment.

[0118] (b) in Fig. 8 shows the same conditions as in Fig. 6B. (a) in Fig. 8 shows the operating waveforms when the output voltage is doubled. (c) in Fig. 8 shows the operating waveforms when the output voltage is halved.

[0119] When the output voltage increases or decreases, the slope of the falling edge of the LmC signal, which is the output voltage of the excitation current detection means 113, also increases or decreases in proportion to the output voltage.

[0120] However, since the P1 threshold generating means 144 generates the threshold signal Vth1 by multiplying the VoD signal indicating the output of the output voltage detecting means 111 by a preset ratio, when the value of the VoD signal, which is the output voltage, increases or decreases, the value of the threshold signal Vth1 also increases or decreases proportionally. Therefore, even if the value of the VoD signal, which is the output voltage, changes, the P1 generating means 121 turns the clamp switch QH on and off at the same timing.

[0121] In the enable signal generating means 130a of the first embodiment, as shown in (c) of Fig. 8, the output voltage becomes lower and the power transmitted to the secondary side becomes smaller, so Vfb becomes lower, the peak value of IdL becomes smaller, and the power transmitted to the secondary side is adjusted. Also, since the value of the Vfb signal becomes lower, Enb_Delay becomes longer.

[0122] The drop in output voltage shortens the period T1 and lengthens the period T3, but the longer time Enb_Delay makes the period T6 unnecessarily longer, resulting in a drop in frequency. In other words, a low operating frequency means that components such as capacitors and transformers become larger, so it is desirable for the operating frequency to fluctuate as little as possible. Therefore, in a power supply device that requires a variable output voltage, it is required that the operating frequency fluctuate as little as possible.

[0123] Second Embodiment The enable signal generating means 130b (see FIG. 9) of the second embodiment realizes control with little fluctuation in operating frequency in response to changes in output voltage, and realizes the configuration of a small-sized, highly efficient power supply.

[0124] Fig. 9 is a configuration diagram of a control unit 100b of an ACF converter 10 according to the second embodiment. The difference from Fig. 2 is that a VoD signal is added as an input to an enable signal generating means 130b. That is, the enable signal generating means 130b according to the second embodiment obtains the value of the VoD signal.

[0125] FIG. 10 is a diagram showing the configuration of an enable signal generating means 130b of a control unit 100b according to the second embodiment.

[0126] The enable signal generating means 130a, 130b in Fig. 10 differs from the enable signal generating means 130b in Fig. 3 in that the reference voltage Vosc is a voltage k·VoD proportional to the value of the VoD signal and Voffset, and the enable signal generating means 130a, 130b differs from the enable signal generating means 130b in that the reference current Iosc is a current source proportional to the reference voltage Vosc, n·Vosc=n·(k·VoD+Voffset).

[0127] A reference voltage Vosc, which is compared with the value of the Vfb signal, and a reference current Iosc are controlled by a VoD signal from an output voltage detection means 111.

[0128] Fig. 11 shows the operating waveforms of the enable signal generating means of Fig. 10. Fig. 11(a) to (c) show the operating waveforms when the value of the Vfb signal is zero. Fig. 11(a) shows the operating waveforms when the output voltage is 2×Vo, Fig. 16(b) shows the operating waveforms when the output voltage is Vo, and Fig. 16(c) shows the operating waveforms when the output voltage is Vo / 2.

[0129] The reference voltage Vosc is the sum of the voltage of the VoD signal multiplied by k and the Voffset voltage. The ramp voltage VR charges the capacitor Cosc with a current source proportional to the reference voltage Vosc, so the higher the reference voltage Vosc, the greater the slope.

[0130] When the value of the Vfb signal is zero, the voltage VT is equal to the reference voltage Vosc, so the time it takes for the ramp voltage VR to become equal to the voltage VT does not change even if the output voltage changes. Also, the value of the Vfb signal at the timing when the time Enb_Delay becomes zero is when the voltage VT is zero, so the lower the value of the VoD signal, i.e., the lower the output voltage Vo, the lower the Vfb signal value becomes.

[0131] Therefore, the characteristics of the enable signal generating means 130b in Fig. 10 are as shown in Fig. 12. Fig. 12 is a diagram showing the characteristics of the enable signal generating means 130b, where the horizontal axis is the value of the Vfb signal and the vertical axis is the time Enb_Delay.

[0132] As shown in FIG. 12, the enable signal generating means 130b according to the second embodiment has the following characteristics.

[0133] The time Enb_Delay from when the switch Sosc turns off until the Enb signal goes high is controlled to be negatively proportional to the value of the Vfb signal. Also, the time Enb_Delay when the value of the Vfb signal is zero is constant even if the output voltage changes, and the absolute value of the proportionality coefficient is controlled to become smaller as the output voltage increases.

[0134] FIG. 13 shows operational waveforms when the output voltage is increased or decreased without changing the output current in the control unit 100b according to the second embodiment of FIG.

[0135] Figure 13(b) shows the operating waveforms when the output voltage is Vo, the same as Figure 8(b). Figure 13(a) shows the operating waveforms when the output voltage is 2Vo, the same as Figure 8(a). Figure 13(c) shows the operating waveforms when the output voltage is Vo / 2, the same as Figure 8(c).

[0136] In Fig. 13(a), the output voltage is doubled, so the reference voltage Vosc is higher than in Fig. 13(b). Compared with Fig. 8(a) in the first embodiment, in Fig. 8(a), the value of the Vfb signal is higher than the reference voltage Vosc, so the time Enb_Delay is zero. On the other hand, in Fig. 13(a), the value of the Vfb signal is lower than the reference voltage Vosc, so the voltage VT increases, and the slope of the ramp voltage VR increases, but the frequency is reduced because the time Enb_Delay is longer.

[0137] In FIG. 13(c), the output voltage is halved, so the reference voltage Vosc is lower than in FIG. 13(b).

[0138] Compared to (c) of FIG. 8 in the first embodiment, the difference between the value of the Vfb signal and the reference voltage Vosc is smaller, so the slope of the ramp voltage VR is smaller, but the voltage VT is lower, so the time Enb_Delay is shorter and the frequency increases.

[0139] Therefore, the frequency fluctuation when the output voltage changes is suppressed, and a highly efficient and compact power supply device can be realized.

[0140] 14 is a diagram showing the operation of the ACF converter 10 and the control units 100a and 100b in the first and second embodiments of the present invention. As the output current increases, the value of the Vfb signal increases, lowering the voltage VT and shortening the time Enb_Delay of the Enb signal, which is an enable signal. As a result, the period T6 becomes shorter and the frequency increases.

[0141] If the output current is further increased, the time Enb_Delay becomes shorter than the edge of the Dis signal. Without the Dis signal, control becomes impossible, but the Dis signal determines the upper limit of the frequency, and the clamp switch QH turns on at the first maximum point in the resonant oscillation of Tcvlm. If the output current is further increased, the periods T1 and T3 become longer, and the frequency decreases.

[0142] Therefore, in the first and second embodiments, the change in the operating frequency when the output current changes is as shown in Fig. 15. When the output current decreases from the maximum output current, the frequency increases, and after reaching the maximum frequency, when the output current decreases, the frequency decreases.

[0143] As is already widely known, there is a problem that high-frequency sound waves are generated from the power supply circuit when the operating frequency falls below an audible frequency, so the burst mode may be switched to before the operating frequency reaches an audible frequency.

[0144] As described above, the control method of the ACF converter 10 according to this embodiment improves the drawbacks of complementary control and non-complementary control, enables ZVS over a wide output voltage and current range, and realizes highly efficient and low-noise ACF operation.

[0145] (Other embodiments) Although the embodiments have been described in detail with reference to the drawings, the present embodiments are not limited to the contents described in the above embodiments. The components described above include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the configurations described above can be appropriately combined. Various omissions, substitutions, or modifications of the configurations can be made without departing from the spirit of the embodiments.

[0146] The features of the active clamp flyback converter and its control IC are described below.

[0147] The active clamp flyback converter and control IC according to the first aspect includes a first series circuit in which a main switch QL and a primary winding Np are connected in series to both ends of a DC power source Vin, and a second series circuit in which a clamp switch QH and a clamp capacitor Cac are connected in series to both ends of the primary winding Np. The active clamp flyback converter and control IC also includes a transformer T having a secondary winding Ns electromagnetically coupled to the primary winding Np, and a control unit 100a that turns the main switch QL and the clamp switch QH on and off. The active clamp flyback converter and control IC also includes a rectifying and smoothing circuit that rectifies and smoothes the voltage of the secondary winding Ns, and an output voltage detection unit 200 that detects the output voltage of the rectifying and smoothing circuit. The control unit 100a has a first drive signal that turns the main switch QL on and off, a second drive signal that turns the clamp switch QH on and off during a period in which the main switch QL is off, and a third drive signal that turns the clamp switch QH on and off after the second drive signal. The control unit also controls a first off period during which both the main switch QL and the clamp switch QH are off from the off time of the first drive signal to the on time of the second drive signal, and a second off period during which both the main switch QL and the clamp switch QH are off from the off time of the second drive signal to the on time of the third drive signal.

[0148] This configuration enables the ACF converter 10 to reduce fluctuations in operating frequency that accompany changes in output voltage and output current, and to maintain zero-voltage switching operation.

[0149] A control unit 100a of the active clamp flyback converter and control IC according to the second aspect may include an excitation current detection means 113 that detects an excitation current of a transformer T and outputs a first voltage signal proportional to the excitation current, and an output voltage detection means 111 that outputs a second voltage signal proportional to an output voltage. The control unit 100a may set an ON timing of the second drive signal based on the first voltage signal and a threshold value set based on the second voltage signal, thereby controlling the first drive signal and the first OFF period based on a feedback voltage detected by the output voltage detection unit.

[0150] With this configuration, in the ACF converter 10, in frequency control when the load current decreases, ZVS is possible even if the frequency is reduced while decreasing the peak current of the excitation inductance, and it is possible to realize highly efficient, low-noise ACF operation over the entire load range.

[0151] The control unit 100a of the active clamp flyback converter and control IC according to the third aspect may include an excitation current detection means 113 that detects an excitation current of a transformer T and outputs a first voltage signal proportional to the excitation current, and a predetermined third voltage signal. The control unit 100a may also control the first drive signal and the first off period based on the feedback voltage detected by the output voltage detection unit 200 by setting the on-timing of the second drive signal based on the first voltage signal and the third voltage signal.

[0152] With this configuration, the ACF converter 10 can reduce the number of components since the threshold value for comparison with the excitation current can be constant in a power supply whose output voltage does not change.

[0153] The control unit 100a of the active clamp flyback converter and control IC according to the fourth aspect may include enable signal generating means 130a for generating an enable signal based on the feedback voltage detected by the output voltage detecting unit 200, and disable signal generating means 142 for generating a disable signal based on the second drive signal. The control unit 100a may also control the second off period by controlling the third drive signal based on the enable signal and the disable signal.

[0154] This configuration enables the ACF converter 10 to reduce fluctuations in operating frequency that accompany changes in output voltage and output current, and to maintain zero-voltage switching operation.

[0155] A control unit 100a of an active clamp flyback converter and control IC according to a fifth aspect may include output voltage detection means 111 that outputs a second voltage signal proportional to an output voltage, enable signal generation means 130a that generates an enable signal based on the second voltage signal and a feedback voltage detected by the output voltage detection unit 200, and disable signal generation means 142 that generates a disable signal based on the second drive signal. The control unit 100a may also control the second off period by controlling a third drive signal based on the enable signal and the disable signal.

[0156] With this configuration, the ACF converter 10 realizes control with little fluctuation in operating frequency in response to changes in output voltage, enabling the realization of a small, highly efficient power supply configuration. For example, power supply devices and the like that require the output voltage to be changed require little fluctuation in operating frequency, and the ACF converter 10 is well suited to such a configuration.

[0157] The enable signal generating means 130a of the active clamp flyback converter and control IC according to the sixth aspect may be controlled so that the time Enb_Delay from when the main switch QL is turned on until the Enb signal becomes High is proportional to a negative value of the Vfb signal.

[0158] This configuration enables the ACF converter 10 to reduce fluctuations in operating frequency that accompany changes in output voltage and output current, and to maintain zero-voltage switching operation.

[0159] In the enable signal generating means 130a of the active clamp flyback converter and control IC according to the seventh aspect, the time Enb_Delay from when the main switch QL is turned on until the Enb signal becomes High may be controlled to be negatively proportional to the Vfb signal, and the absolute value of the proportionality coefficient may be controlled to become smaller as the output voltage increases.

[0160] This configuration enables the ACF converter 10 to reduce fluctuations in operating frequency that accompany changes in output voltage and output current, and to maintain zero-voltage switching operation. [Explanation of symbols]

[0161] Vin DC power supply QL Main Switch QH Clamp Switch T transformer Np primary winding Ns Secondary winding Na Auxiliary Winding Lm Excitation inductance Llk Leakage inductance Cac Clamp Capacitor Cv Voltage Resonant Capacitor BDL, BDH Body diode Ds Rectifier Co Output capacitor Ca capacitor Ra1, Ra2 resistors Rs Id Detection Method VgsL, VgsH drive signals 10 ACF Converter 100a, 100b Control section 111 Output voltage detection means 112 Zero cross detection means 113 Excitation current detection means 114, COMosc comparator 115 SR Latch 121 P1 generation means 122 P2 generation means 130a, 130b Enable signal generating means 131 Subtraction Circuit 141 P0 timing generation means 142 Disable signal generating means 143 P2 Delay Measures 144 P1 threshold generation means 151 First driving means 152 Second driving means 200 Output voltage detection section

Claims

1. a first series circuit in which a main switch and a primary winding are connected in series across a DC power source; a second series circuit in which a clamp switch and a clamp capacitor are connected in series across the primary winding; a transformer having a secondary winding electromagnetically coupled to the primary winding; A control unit that turns on and off the main switch and the clamp switch; a rectifying and smoothing circuit that rectifies and smoothes the voltage of the secondary winding; an output voltage detection unit that detects an output voltage of the rectifying and smoothing circuit, The control unit is a first drive signal for turning on and off the main switch, a second drive signal for turning on and off the clamp switch while the main switch is off, and a third drive signal for turning on and off the clamp switch after the second drive signal; a first off period during which both the main switch and the clamp switch are off from an off time of the first drive signal to an on time of the second drive signal; a second off period during which both the main switch and the clamp switch are off from the off time of the second drive signal to the on time of the third drive signal.

2. the control unit includes an excitation current detection means for detecting an excitation current of the transformer and outputting a first voltage signal proportional to the excitation current, and an output voltage detection means for outputting a second voltage signal proportional to the output voltage, 2. The active clamp flyback converter and control IC according to claim 1, wherein the control unit sets an on timing of the second drive signal based on the first voltage signal and a threshold value set based on the second voltage signal, thereby controlling the first drive signal and the first off period based on a feedback voltage detected by the output voltage detection unit.

3. the control unit includes an excitation current detection unit that detects an excitation current of the transformer and outputs a first voltage signal proportional to the excitation current, and a predetermined third voltage signal; 2. The active clamp flyback converter and control IC according to claim 1, wherein the control unit sets an on-timing of the second drive signal based on the first voltage signal and the third voltage signal, thereby controlling the first drive signal and the first off-period based on a feedback voltage detected by the output voltage detection unit.

4. the control unit includes an enable signal generating means for generating an enable signal based on the feedback voltage detected by the output voltage detection unit, and a disable signal generating means for generating a disable signal based on the second drive signal, the control unit controls the third drive signal based on the enable signal and the disable signal, thereby controlling the second off period.

2. The active clamp flyback converter and control IC of claim 1.

5. the control unit includes an output voltage detection means for outputting a second voltage signal proportional to the output voltage, an enable signal generation means for generating an enable signal based on the second voltage signal and a feedback voltage detected by the output voltage detection means, and a disable signal generation means for generating a disable signal based on the second drive signal; the control unit controls the third drive signal based on the enable signal and the disable signal, thereby controlling the second off period.

2. The active clamp flyback converter and control IC of claim 1.

6. 5. The active clamp flyback converter and control IC according to claim 4, wherein the enable signal generating means is controlled so that a time Enb_Delay from when the main switch is turned on until the Enb signal goes High is proportional to a negative value of the Vfb signal.

7. The enable signal generating means controls a time Enb_Delay from when the main switch is turned on until the Enb signal becomes High to be negatively proportional to a Vfb signal, and controls an absolute value of a proportionality coefficient to be smaller as the output voltage increases.

6. An active clamp flyback converter and control IC according to claim 5.

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