Peaking adjustment circuit

Abstract

To stabilize the frequency characteristics of an output signal in peaking adjustment.SOLUTION: A driver IC 5 comprises: a differential amplifier 11 including a node N1 to which an input signal is input and an output node N2; a peak adjustment circuit 13 including an output node N3, an inductor 41a connected between the output node N2 and the output node N3, and a series circuit 60a which is connected between the output node N3 and a ground line GL and in which a capacitor 80a and a variable resistive element 32a are connected in series to each other; and a follower circuit 15 including an output node N4 and a source follower circuit 70a connected between the output node N3 and the output node N4. The variable resistive element 32a includes a first resistance value changing with a first setting signal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a peaking adjustment circuit. [Background technology]

[0002] Patent Document 1 describes a circuit that controls peaking in a circuit that transmits a high-frequency signal. This circuit has a peaking detection unit that monitors the signal at the output unit to detect the amount of peaking, and a control signal generation unit that varies the circuit parameters of an inductor peaking circuit based on the amount of peaking detected by the peaking detection unit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2007 / 110915 [Patent Document 2] JP 2014-7578 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional circuit, the peak frequency is not stable when the amount of peaking is adjusted, and the frequency characteristics of the output signal tend to vary significantly due to the adjustment.

[0005] An object of the present disclosure is to provide a peaking adjustment circuit that is capable of stabilizing the frequency characteristics of an adjusted output signal. [Means for solving the problem]

[0006] In order to solve the above problem, a peaking adjustment circuit according to one aspect of the present disclosure includes an amplifier circuit including a first node to which a first input signal is input and a second node which is an output node, an adjustment circuit including a third node which is the output node, a first inductor connected between the second node and the third node, and a first series circuit connected between the third node and a ground wiring and in which a first capacitor and a first variable resistance element are connected in series to each other, and a follower circuit including a fourth node which is the output node and a first source follower circuit connected between the third node and the fourth node, wherein the first variable resistance element has a first resistance value which changes in response to a first setting signal. Effect of the Invention

[0007] According to the present disclosure, it is possible to stabilize the frequency characteristics of an output signal in peaking adjustment. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a configuration of an optical transmission module 1 according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a circuit diagram showing a detailed configuration of the driver IC 5 of FIG. [Diagram 3] FIG. 3 is a circuit diagram showing a configuration example of the variable resistance elements 32a and 32b of FIG. [Figure 4] FIG. 4 is a graph showing frequency characteristics of small signal responses at output nodes N3 and N7 in driver IC5 of this embodiment. [Diagram 5] FIG. 5 is a graph showing frequency characteristics of small signal responses at output nodes N3 and N7 in a driver IC according to a comparative example. [Figure 6] FIG. 6 is a graph showing frequency characteristics of small signal responses at output nodes N3 and N7 in driver IC5 of this embodiment. [Figure 7] FIG. 7 is a circuit diagram showing a configuration of a driver IC 105 according to a modified example of the present disclosure. [Figure 8]FIG. 8 is a circuit diagram showing a configuration of a driver IC 5A according to a modified example of the present disclosure. [Figure 9] FIG. 9 is a circuit diagram showing a configuration of a driver IC 105A according to a modified example of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A peaking adjustment circuit according to a first aspect of the present disclosure comprises an amplifier circuit including a first node to which a first input signal is input and a second node which is an output node, an adjustment circuit including a third node which is the output node, a first inductor connected between the second node and the third node, and a first series circuit connected between the third node and a ground wiring and in which a first capacitor and a first variable resistance element are connected in series to each other, and a follower circuit including a fourth node which is the output node and a first source follower circuit connected between the third node and the fourth node, wherein the first variable resistance element has a first resistance value which changes in response to a first setting signal.

[0010] According to the first aspect, a first input signal input to a first node is amplified by an amplifier circuit, and is generated as a first output signal at a third node via a second node, a first inductor, and a first series circuit. Furthermore, the first output signal is output from a fourth node via a first source follower circuit. In such a configuration, a first variable resistance element in the first series circuit is set to a variable first resistance value by a first setting signal. This makes it possible to stabilize the peak frequency of the first output signal while adjusting the peak amount of the signal. As a result, it is possible to stabilize the frequency characteristic of the output signal adjusted by the peaking adjustment circuit of this embodiment.

[0011] A peaking adjustment circuit according to a second aspect of the present disclosure is the above-mentioned first aspect, in which the first series circuit is a circuit in which the first capacitor and the first variable resistance element are connected in this order between the third node and the ground wiring. In this case, the voltage of the setting signal for setting the resistance value of the first variable resistance element can be stabilized with respect to the ground potential of the ground wiring, thereby suppressing fluctuations in the resistance value. As a result, stabilization of the frequency characteristics of the output signal can be easily achieved.

[0012] A peaking adjustment circuit according to a third aspect of the present disclosure is the above-mentioned second aspect, wherein the first variable resistance element is configured by a field effect transistor having a drain connected to the first capacitor, a source connected to a ground wiring, and a gate to which a first setting signal is input. In this case, by grounding the source and inputting a setting signal to the gate, it is possible to easily realize a first variable resistance element whose drain-source resistance value can be variably set according to the voltage of the setting signal. As a result, it is possible to easily realize stabilization of the frequency characteristics of the output signal.

[0013] Also, in a peaking adjustment circuit according to a fourth aspect of the present disclosure, in any one of the first to third aspects, the follower circuit further includes a first emitter follower circuit cascade-connected to the first source follower circuit between the first source follower circuit and the fourth node. With this configuration, the circuit connected to the output of the peaking adjustment circuit can be driven stably against changes in operating temperature, and the intensity of the output signal can be stabilized.

[0014] Furthermore, a peaking adjustment circuit according to a fifth aspect of the present disclosure includes an amplifier circuit including a first node to which a first input signal is input, a fifth node to which a second input signal is input, and second and sixth nodes that are output nodes, a third node and a seventh node that are output nodes, a first inductor connected between the second node and the third node, a first series circuit connected between the third node and a ground wiring and in which a first capacitor and a first variable resistance element are connected in series to each other, a second inductor connected between the sixth node and the seventh node, The input / output circuit includes an adjustment circuit including a second series circuit connected between the node and a ground wiring, in which a second capacitor and a second variable resistance element are connected in series to each other, and a follower circuit including a fourth node and an eighth node which are output nodes, a first source follower circuit connected between the third node and the fourth node, and a second source follower circuit connected between the seventh node and the eighth node, wherein the first variable resistance element has a first resistance value which changes in response to a first setting signal, and the second variable resistance element has a second resistance value which changes in response to a second setting signal.

[0015] According to the fifth aspect, a first input signal input to a first node and a second input signal input to a fifth node are amplified by an amplifier circuit, and are generated as a first output signal at a third node via a second node, a first inductor, and a first series circuit, and are generated as a second output signal at a seventh node via a sixth node, a second inductor, and a second series circuit. Furthermore, the first output signal is output from a fourth node via a first source follower circuit, and the second output signal is output from an eighth node via a second source follower circuit. In such a configuration, the first variable resistance element in the first series circuit is set to a variable first resistance value by a first setting signal, and the second variable resistance element in the second series circuit is set to a variable second resistance value by a second setting signal. This makes it possible to stabilize the peak frequencies of the first output signal and the second output signal while adjusting the peak amounts of these signals. As a result, it is possible to stabilize the frequency characteristics of the output signal adjusted by the peaking adjustment circuit of this embodiment.

[0016] A peaking adjustment circuit according to a sixth aspect of the present disclosure is the above fifth aspect, in which the first series circuit is a circuit in which a first capacitor and a first variable resistance element are connected in this order between a third node and a ground wiring, and the second series circuit is a circuit in which a second capacitor and a second variable resistance element are connected in this order between a seventh node and a ground wiring. With this configuration, the voltage of a setting signal (first setting signal) for setting a resistance value (first resistance value) of the first variable resistance element is stabilized with respect to the ground potential of the ground wiring, thereby suppressing fluctuations in the first resistance value. Also, the voltage of a setting signal (second setting signal) for setting a resistance value (second resistance value) of the second variable resistance element is stabilized with respect to the ground potential of the ground wiring, thereby suppressing fluctuations in the second resistance value. As a result, stabilization of the frequency characteristics of the output signal can be easily achieved.

[0017] A peaking adjustment circuit according to a seventh aspect of the present disclosure is the same as that of the sixth aspect, in which the first variable resistance element is configured by a field effect transistor having a drain connected to the first capacitor, a source connected to a ground wiring, and a gate to which a first setting signal is input, and the second variable resistance element is configured by a field effect transistor having a drain connected to the second capacitor, a source connected to a ground wiring, and a gate to which a second setting signal is input. In this configuration, a first variable resistance element can be easily realized in which the resistance value between the drain and source (first resistance value) can be variably set according to the voltage of the first setting signal by grounding the source and inputting the first setting signal to the gate. Also, a second variable resistance element can be easily realized in which the resistance value between the drain and source (second resistance value) can be variably set according to the voltage of the second setting signal by grounding the source and inputting the second setting signal to the gate. As a result, stabilization of the frequency characteristics of the output signal can be easily achieved.

[0018] Also, in the peaking adjustment circuit according to an eighth aspect of the present disclosure, in any one of the fifth to seventh aspects, the follower circuit further includes a first emitter follower circuit cascade-connected to the first source follower circuit between the first source follower circuit and the fourth node, and a second emitter follower circuit cascade-connected to the second source follower circuit between the second source follower circuit and the eighth node. With this configuration, the circuit connected to the output of the peaking adjustment circuit can be driven stably against changes in operating temperature, and the intensity of the output signal can be stabilized.

[0019] Also, a peaking adjustment circuit according to a ninth aspect of the present disclosure is, in any one of the fifth to eighth aspects, an inductance of the first inductor and an inductance of the second inductor are set equal, a capacitance value of the first capacitor and a capacitance value of the second capacitor are set equal, and a resistance value of the first variable resistance element and a resistance value of the second variable resistance element are set equal. With this configuration, the peak amounts and peak frequencies of the first output signal and the second output signal can be matched, and the characteristics of the pair of output signals (i.e., one differential signal) adjusted by the peaking adjustment circuit can be stabilized.

[0020] A peaking adjustment circuit according to a tenth aspect of the present disclosure includes an amplifier circuit including a first node to which a first input signal is input and a second node which is an output node, and which generates an amplified signal having peaking characteristics at the output node in response to the first input signal; an adjustment circuit including a third node and a first series circuit connected between the third node and a ground wiring, in which a first capacitor and a first variable resistance element are connected in series to each other; and a follower circuit including a fourth node which is the output node and a first source follower circuit connected between the third node and the fourth node, wherein the first variable resistance element has a first resistance value which changes in response to a first setting signal.

[0021] According to the tenth aspect, a first input signal input to a first node is amplified by an amplifier circuit so as to have a peaking characteristic, and is generated as a first output signal at a third node via a second node and a first series circuit. Furthermore, the first output signal is output from a fourth node via a first source follower circuit. In such a configuration, a first variable resistance element in the first series circuit is set to a variable first resistance value by a first setting signal. This makes it possible to stabilize the peak frequency of the first output signal while adjusting the peak amount of the signal. As a result, it is possible to stabilize the frequency characteristic of the output signal adjusted by the peaking adjustment circuit of this embodiment.

[0022] A peaking adjustment circuit according to an eleventh aspect of the present disclosure includes an amplifier circuit including a first node to which a first input signal is input, a fifth node to which a second input signal is input, and second and sixth nodes that are output nodes, and that generates an amplified signal having peaking characteristics at the output node in response to the first input signal and the second input signal, a third node and a seventh node that are output nodes, a first series circuit connected between the third node and a ground wiring, in which a first capacitor and a first variable resistance element are connected in series with each other, and a third node and a seventh node that are output nodes. the first variable resistance element has a first resistance value that changes in response to a first setting signal, and the second variable resistance element has a second resistance value that changes in response to a second setting signal.

[0023] According to the eleventh aspect, a first input signal input to a first node and a second input signal input to a fifth node are amplified by an amplifier circuit so as to have a peaking characteristic, and are generated as a first output signal at a third node via a second node and a first series circuit, and are generated as a second output signal at a seventh node via a sixth node and a second series circuit. Furthermore, the first output signal is output from a fourth node via a first source follower circuit, and the second output signal is output from an eighth node via a second source follower circuit. In such a configuration, the first variable resistance element in the first series circuit is set to a variable first resistance value by a first setting signal, and the second variable resistance element in the second series circuit is set to a variable second resistance value by a second setting signal. This makes it possible to stabilize the peak frequencies of the first output signal and the second output signal while adjusting the peak amounts of these signals. As a result, it is possible to stabilize the frequency characteristics of the output signal adjusted by the peaking adjustment circuit of this embodiment.

[0024] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same elements are given the same reference numerals, and duplicated description will be omitted.

[0025] (Configuration of optical transmission module)

[0026] 1 is a block diagram showing a schematic configuration of an optical transmission module 1 according to an embodiment of the present disclosure. The optical transmission module 1 is a module that converts an electrical signal into an optical signal for optical signal transmission.

[0027] 1, the optical transmission module 1 includes a package 3, two signal pads PA, PB, and an optical connector CN provided in the package 3, and a driver IC (Integrated Circuit) 5, an optical modulator 7, and an optical coupling component 9 mounted in the package 3. A positive-phase signal (first input signal) and a negative-phase signal (second input signal), which are analog signals, are applied from the outside to the two signal pads PA, PB, respectively. The positive-phase signal and the negative-phase signal are signals of equal amplitude and opposite phase to each other, that is, so-called differential signals.

[0028] The signal pad PA is electrically connected to a node (first node) N1, which is a terminal of the driver IC5, via a transmission line TLA and a wire W1A inside the package 3, and the signal pad PB is electrically connected to a node (fifth node) N5, which is a terminal of the driver IC5, via a transmission line TLB and a wire W1B inside the package 3. The positive phase signal applied to the signal pad PA is input to the node N1, and the negative phase signal applied to the signal pad PB is input to the node N5.

[0029] The optical modulator 7 is a circuit that generates an optical signal based on two current signals that are differential signals output from the driver IC5. For example, a Mach-Zehnder modulator is used as the optical modulator 7. The optical modulator 7 has two nodes INA and INB as input terminals, the node INA is electrically connected to an output node OUTA that is an output terminal of the driver IC5 via a wire W2A, and the node INB is electrically connected to an output node OUTB that is an output terminal of the driver IC5 via a wire W2B. A current signal that is a positive-phase signal output from the output node OUTA is input to the node INA, and a current signal that is a negative-phase signal output from the output node OUTB is input to the node INB. The optical signal generated by the optical modulator 7 is output to the outside via an optical coupling component 9 and an optical connector CN.

[0030] FIG. 2 is a circuit diagram showing a detailed configuration of the driver IC 5.

[0031] 2, the driver IC 5 includes a differential amplifier (amplification circuit) 11, a peak adjustment circuit (also simply referred to as an adjustment circuit) 13, a follower circuit 15, and a buffer circuit 17. The differential amplifier 11, the peak adjustment circuit 13, and the follower circuit 15 configure the peaking adjustment circuit of this embodiment.

[0032] The differential amplifier 11 is an integrated circuit that modulates an output current based on a pair of differential signals input from two nodes N1 and N5. The differential amplifier 11 includes bipolar transistors 20a, 20b, 21a, and 21b, resistive elements 30a, 30b, 31a, and 31b, inductors 40a and 40b, a current source 50, an output node (second node) N2, and an output node (sixth node) N6.

[0033] The bipolar transistors 20a and 20b have their bases connected to the nodes N1 and N5, their collectors connected to the emitters of the bipolar transistors 21a and 21b, and their emitters connected to one end of the current source 50 via the resistor elements 30a and 30b. These bipolar transistors 20a and 20b modulate the collector currents with the input differential signals. The bipolar transistors 21a and 21b have their bases set to a predetermined DC voltage, their emitters connected to the collectors of the bipolar transistors 20a and 20b, and their collectors connected to a power supply line L1 to which a predetermined power supply potential (e.g., 3.3V) is applied via the resistor elements 31a and 31b and the inductors 40a and 40b. These bipolar transistors 21a and 21b are cascode transistors to which a DC voltage is applied. The resistor elements 30a and 30b are degeneration resistors that enable the linear input range of the driver IC5 to be expanded. The current source 50 has one end connected to the emitters of the bipolar transistors 20a and 20b via the resistive elements 30a and 30b and the other end connected to a ground line (ground wiring) GL set to a ground potential, and supplies the emitter currents of the bipolar transistors 20a and 20b. The resistive elements 31a and 31b are loads for converting the collector currents modulated by the bipolar transistors 20a and 20b into voltage signals.

[0034] According to the differential amplifier 11 having such a configuration, the collector currents of the bipolar transistors 20a and 20b are modulated by the differential signals input from the nodes N1 and N5, respectively, so that two output signals, which are differential signals, are generated at the output nodes N2 and N6 connected to the collectors of the bipolar transistors 21a and 21b.

[0035] The peak adjustment circuit 13 is a circuit that adjusts the frequency characteristics of two output signals generated at the output nodes N2 and N6. The peak adjustment circuit 13 includes an output node (third node) N3, an output node (seventh node) N7, control nodes NCa and NCb, an inductor (first inductor) 41a, an inductor (second inductor) 41b, a series circuit (first series circuit) 60a configured with a capacitor (first capacitor) 80a and a variable resistance element (first variable resistance element) 32a, and a series circuit (second series circuit) 60b configured with a capacitor (second capacitor) 80b and a variable resistance element (second variable resistance element) 32b.

[0036] The inductor 41a is connected between the output node N2 and the output node N3. The inductor 41a has the effect of generating a peaking characteristic, which will be described later, in the signal generated at the output node N3. That is, the maximum amount of peaking in the peaking adjustment can be set by changing the inductance of the inductor 41a. The series circuit 60a is a circuit configured by connecting a capacitor 80a and a variable resistance element 32a in series in this order between the output node N3 and the ground line GL. The variable resistance element 32a is an element configured such that its resistance value (first resistance value) can be variably adjusted in response to a first setting signal input from the outside via a control node NCa.

[0037] The inductor 41b is connected between the output node N6 and the output node N7. The inductor 41b has the effect of generating a peaking characteristic, which will be described later, in the signal generated at the output node N7. That is, the maximum amount of peaking in the peaking adjustment can be set by changing the inductance of the inductor 41b. The series circuit 60b is a circuit configured by connecting a capacitor 80b and a variable resistance element 32b in series in this order between the output node N7 and the ground line GL. The variable resistance element 32b is an element configured such that its resistance value (second resistance value) can be variably adjusted in response to a second setting signal input from the outside via a control node NCb.

[0038] In the peak adjustment circuit 13 configured as described above, the inductance of inductor 41a is set to be equal to the inductance of inductor 41b, the capacitance (capacitance value) of capacitor 80a is set to be equal to the capacitance of capacitor 80b, and the resistance value of variable resistance element 32a is set to be always equal to the resistance value of variable resistance element 32b.

[0039] 3 is a circuit diagram showing a configuration example of the variable resistance elements 32a and 32b. The variable resistance elements 32a and 32b are, for example, configured by field effect transistors (FETs). In the variable resistance element 32a, which is an FET, the drain is connected to the capacitor 80a, the source is connected to the ground line GL, and the gate is connected to the control node NCa, and a first setting signal, which is a voltage signal, is applied to the gate. In the variable resistance element 32b, which is an FET, the drain is connected to the capacitor 80b, the source is connected to the ground line GL, and the gate is connected to the control node NCb, and a second setting signal, which is a voltage signal, is applied to the gate. As described above, in order to set the resistance value of the variable resistance element 32a and the resistance value of the variable resistance element 32b to be equal, the size of the FET constituting the variable resistance element 32a is set to be equal to the size of the FET constituting the variable resistance element 32b, and the voltage value of the first setting signal and the voltage value of the second voltage signal are set to be equal to each other.

[0040] 2, the follower circuit 15 is a circuit that generates two output signals that follow two output signals generated at the output nodes N3 and N7. The follower circuit 15 includes an output node (fourth node) N4, an output node (eighth node) N8, a source follower circuit (first source follower circuit) 70a, an emitter follower circuit (first emitter follower circuit) 71a, and an emitter follower circuit 72a that are cascaded in this order between the output node N3 and the output node N4, and a source follower circuit (second source follower circuit) 70b, an emitter follower circuit (second emitter follower circuit) 71b, and an emitter follower circuit 72b that are cascaded in this order between the output node N7 and the output node N8.

[0041] The source follower circuit 70a includes an FET 22a and a current source 50a. In the FET 22a, the gate is connected to the output node N3, the drain is connected to the power supply line L1, and the source is connected to the ground line GL via the current source 50a. The source follower circuit 70b includes an FET 22b and a current source 50b. In the FET 22b, the gate is connected to the output node N7, the drain is connected to the power supply line L1, and the source is connected to the ground line GL via the current source 50b. These FETs 22a and 22b generate signals following the two output signals output from the output nodes N3 and N7, respectively, and output them from their respective sources. The current sources 50a and 50b supply source currents for the FETs 22a and 22b, respectively.

[0042] The emitter follower circuit 71a includes a bipolar transistor 23a and a current source 51a. In the bipolar transistor 23a, the base is connected to the source of the FET 22a, the collector is connected to the power supply line L1, and the emitter is connected to the ground line GL via the current source 51a. The emitter follower circuit 71b includes a bipolar transistor 23b and a current source 51b. In the bipolar transistor 23b, the base is connected to the source of the FET 22b, the collector is connected to the power supply line L1, and the emitter is connected to the ground line GL via the current source 51b. These bipolar transistors 23a and 23b generate signals following the two output signals output from the FETs 22a and 22b, respectively, and output them from their respective emitters. The current sources 51a and 51b supply the emitter currents of the bipolar transistors 23a and 23b, respectively.

[0043] The emitter follower circuit 72a includes a bipolar transistor 24a and a current source 52a. In the bipolar transistor 24a, the base is connected to the emitter of the bipolar transistor 23a, the collector is connected to the power supply line L1, and the emitter is connected to the ground line GL via the current source 52a and to the output node N4. The emitter follower circuit 72b includes a bipolar transistor 24b and a current source 52b. In the bipolar transistor 24b, the base is connected to the emitter of the bipolar transistor 23b, the collector is connected to the power supply line L1, and the emitter is connected to the ground line GL via the current source 52b and to the output node N8. These bipolar transistors 24a and 24b generate signals following the two output signals output from the bipolar transistors 23a and 23b, respectively, and output them from their respective emitters. Current sources 52a and 52b supply emitter currents to bipolar transistors 24a and 24b, respectively.

[0044] The buffer circuit 17 is a circuit that generates two current signals, which are differential signals for driving the optical modulator 7, based on the two output signals output from the output nodes N4 and N8. The buffer circuit 17 includes output nodes OUTA and OUTB, bipolar transistors 25a, 25b, 26a, and 26b, resistive elements 33a and 33b, inductors 42a and 42b, and a current source 53.

[0045] The bipolar transistors 25a and 25b have their bases connected to the output nodes N4 and N8, their collectors connected to the emitters of the bipolar transistors 26a and 26b, and their emitters connected to one end of the resistor elements 33a and 33b. The bipolar transistors 25a and 25b modulate their collector currents with the output signals output from the output nodes N4 and N8.

[0046] In the bipolar transistors 26a and 26b, the bases are set to a predetermined DC voltage, the emitters are connected to the collectors of the bipolar transistors 25a and 25b, and the collectors are connected to the output nodes OUTB and OUTA via the inductors 42a and 42b. These bipolar transistors 26a and 26b are cascode transistors. The presence of the cascode transistors makes it possible to widen the bandwidth of the output current and improve the voltage gain of the buffer circuit 17.

[0047] The resistor elements 33a and 33b have one end connected to the emitters of the bipolar transistors 25a and 25b, respectively, and the other end connected to the ground line GL via a current source 53. These resistor elements 33a and 33b are degeneration resistors, and enable the linear input range of the buffer circuit 17 to be expanded.

[0048] By the driver IC5 described above, the positive-phase signal input to the node N1 and the negative-phase signal input to the node N5 are amplified by the differential amplifier 11, and are generated as an output signal at the output node N3 via the output node N2, the inductor 41a, and the series circuit 60a, and are also generated as an output signal at the output node N7 via the output node N6, the inductor 41b, and the series circuit 60b. Furthermore, the output signal output to the output node N3 is output from the output node N4 via the source follower circuit 70a, and the output signal output from the output node N7 is output from the output node N8 via the source follower circuit 70b. In this configuration, the variable resistance element 32a in the series circuit 60a is set to a variable first resistance value by the first setting signal, and the variable resistance element 32b in the series circuit 60b is set to a variable second resistance value by the second setting signal. This makes it possible to stabilize the peak frequencies of the two output signals while adjusting the peak amounts of those signals. As a result, it is possible to stabilize the frequency characteristics of the output signal adjusted by the driver IC5 of this embodiment.

[0049] In this embodiment, the series circuits 60a, 60b are configured as circuits in which the capacitors 80a, 80b and the variable resistance elements 32a, 32b are connected in this order between the output nodes N3, N7 and the ground line GL. The voltage of a setting signal (first setting signal) for setting the resistance value (first resistance value) of the variable resistance element 32a is stabilized with respect to the ground potential of the ground wiring, thereby suppressing fluctuations in the first resistance value. In addition, the voltage of a setting signal (second setting signal) for setting the resistance value (second resistance value) of the variable resistance element 32b is stabilized with respect to the ground potential of the ground wiring, thereby suppressing fluctuations in the second resistance value. As a result, stabilization of the frequency characteristics of the output signal of the driver IC5 can be easily achieved.

[0050] In this embodiment, the variable resistance elements 32a and 32b are composed of FETs. In the FET constituting the variable resistance element 32a, the source is grounded and a first setting signal is input to the gate, so that a first variable resistance element can be easily realized in which the resistance value between the drain and source (first resistance value) can be variably set according to the voltage of the first setting signal. In the FET constituting the variable resistance element 32b, the source is grounded and a second setting signal is input to the gate, so that a second variable resistance element can be easily realized in which the resistance value between the drain and source (second resistance value) can be variably set according to the voltage of the second setting signal. As a result, it is possible to easily realize stabilization of the frequency characteristics of the output signal of the driver IC5.

[0051] In this embodiment, the follower circuit 15 further includes emitter follower circuits 71a, 71b, 72a, and 72b connected in cascade to the source follower circuits 70a and 70b, respectively, between the source follower circuits 70a and 70b and the output nodes N4 and N8. With this configuration, the load of the peak adjustment circuit 13 becomes the source follower circuit. The inventors of the present application have found that when the source follower circuits 70a and 70b are connected to the peak adjustment circuit 13 as in this embodiment, the temperature dependency of the input impedance seen from the peak adjustment circuit 13 becomes smaller than when an emitter follower circuit is connected to the peak adjustment circuit 13, and the temperature dependency of the peak adjustment circuit can be suppressed as described later. In addition, by connecting the emitter follower circuits 71a and 71b in cascade to the source follower circuits 70a and 70b, the buffer circuit 17, which is a large load, can be driven at high speed. The load driving capability can be increased by cascading emitter follower circuits 72a and 72b to the emitter follower circuits 71a and 71b, thereby improving the stability of the output signal strength of the driver IC5 and achieving high-speed operation.

[0052] In this embodiment, the inductance of the inductor 41a is equal to the inductance of the inductor 41b, the capacitance of the capacitor 80a is equal to the capacitance of the capacitor 80b, and the resistance value of the variable resistance element 32a is equal to the resistance value of the variable resistance element 32b. In this case, the peak amount and peak frequency of one signal in a pair of output signals (differential signals) of the peak adjustment circuit 13 can be made to match the peak amount and peak frequency of the other signal, thereby suppressing the occurrence of in-phase components and enabling stable operation of the driver IC 5 and the optical transmission module 1.

[0053] FIG. 4 is a graph showing the frequency characteristics of the small signal response at the output nodes N3 and N7 in the driver IC5 of this embodiment, and FIG. 5 is a graph showing the frequency characteristics of the small signal response at the output nodes N3 and N7 in a comparative example in which the source follower circuits 70a and 70b are removed from the driver IC5. A pair of complementary signals (differential signals) are generated at the output nodes N3 and N7, and each graph shows the frequency characteristics of the differential signals. In FIG. 4, each frequency characteristic shows a characteristic in which the gain reaches a maximum value (peak value) at a frequency of 70 GHz, and when the frequency is greater than 70 GHz, the gain decreases with increasing frequency. Such a frequency characteristic is also called a peaking characteristic. In each graph, G1 shows the frequency characteristic normalized by the gain at 1 GHz at an environmental temperature of -5°C, G2 shows the frequency characteristic normalized by the gain at 1 GHz at an environmental temperature of 45°C, and G3 shows the frequency characteristic normalized by the gain at 1 GHz at an environmental temperature of 95°C. In the frequency characteristics shown in each graph, the peak value is called the peaking amount, and the frequency at which the gain reaches the peak value is called the peak frequency. For example, changing the peaking amount of the output signal is called peak adjustment or peaking adjustment. From a comparison between FIG. 4 and FIG. 5, it was found that in this embodiment, the temperature dependency of the small signal response is suppressed to a low level due to the presence of the source follower circuits 70a and 70b. For example, in order to perform stable signal transmission, it is preferable that the temperature dependency of the small signal response is small.

[0054] 6 is a graph showing the frequency characteristics of the small signal response at the output nodes N3 and N7 in the driver IC5 of this embodiment. In this graph, G4, G5, and G6 show frequency characteristics when the resistance values ​​of the variable resistance elements 32a and 32b are set to increase in three stages in order to adjust the amount of peaking. At low frequencies (60 GHz or less) lower than the peak frequency (approximately 70 GHz), the impedance of the capacitors 80a and 80b is large, so the change in gain with respect to the change in the resistance values ​​of the variable resistance elements 32a and 32b connected in series thereto is relatively small. At high frequencies (80 GHz or more) higher than the peak frequency, the input impedance of the source follower circuits 70a and 70b as viewed from the peak adjustment circuit 13 is small, so the change in gain with respect to the change in the resistance values ​​of the variable resistance elements 32a and 32b is relatively small. On the other hand, in the frequency characteristics G4, G5, and G6 at the peak frequency, the change in gain with respect to the change in the resistance values ​​of the variable resistance elements 32a and 32b is relatively large compared to the low and high frequencies. In particular, as is clear from the frequency characteristics G4, G5, and G6, it was found that this embodiment can match the peak frequencies while changing the peak amount (peaking amount). Here, "matching the peak frequencies" means matching to a degree that allows a frequency error in the frequency range of ±5 GHz.

[0055] The preferred range of the circuit parameters in the peak adjustment circuit 13 of this embodiment is as follows. For the capacitors 80a and 80b, the upper limit of the capacitance is set to a value that reduces the dependency of the impedance of the series circuits 60a and 60b on the variable resistance elements 32a and 32b at low frequencies. The lower limit of the capacitance is set to a value that causes the impedance of the series circuits 60a and 60b to change according to the variable resistance elements 32a and 32b near the peak frequency. Specifically, the capacitance of the capacitors 80a and 80b is set to, for example, 10 fF or more and 100 fF or less. For the variable resistance elements 32a and 32b, the lower limit of the resistance value is set to a value that does not deteriorate the band of the output signal due to an increase in the load capacitance. Specifically, the resistance value of the variable resistance elements 32a and 32b is set to, for example, 50 Ω or more.

[0056] In addition, according to the simulation results of the input capacitance of the follower circuit 15, it was found that the input capacitance of the driver IC5 of this embodiment is in the range of 6.3 fF to 6.8 fF at a frequency of 70 GHz at an environmental temperature of -5°C to 95°C. On the other hand, in a modified example in which the source follower circuits 70a and 70b are removed from the configuration of the driver IC5, it was found that the input capacitance is in the range of 9.0 fF to 11.5 fF at a frequency of 70 GHz at an environmental temperature of -5°C to 95°C. According to the simulation results, it was found that the influence of the temperature dependency of the input capacitance of the emitter follower circuits 71a and 71b can be reduced by inserting the source follower circuits 70a and 70b, whose input capacitance has a low temperature dependency, in the rear stage of the peak adjustment circuit 13 and in the front stage of the emitter follower circuits 71a and 71b in the driver IC5, and the fluctuation of the peak frequency of the output signal output from the driver IC5 can be effectively suppressed.

[0057] Although the principles of the present disclosure have been illustrated and described in the above preferred embodiments, those skilled in the art will recognize that the present invention may be modified in arrangement and detail without departing from such principles. For example, the source follower circuits 70a and 70b, the emitter follower circuits 71a and 71b, and the emitter follower circuits 72a and 72b may further include elements (resistive elements and transistors) for adjusting the DC potential. The present invention is not limited to the specific configurations disclosed in the present embodiment. Accordingly, we claim the right to all modifications and variations that come within the scope and spirit of the appended claims.

[0058] 7 is a circuit diagram showing a configuration of a driver IC 105 according to a modified example of the present disclosure. The driver IC 105 is an embodiment in which the driver IC 5 is changed to a single-phase circuit.

[0059] That is, the driver IC 105 has a node N1, bipolar transistors 20a and 21a, resistive elements 30a and 31a, an inductor 40a, and an amplifier (amplifying circuit) 111 including an output node N2.

[0060] The driver IC 105 also includes, as a peak adjustment circuit 113, an output node N3, an inductor 41a, and a series circuit 60a configured with a capacitor 80a and a variable resistance element 32a.

[0061] The driver IC 105 also includes, as a follower circuit 115, an output node N4, and a source follower circuit 70a, an emitter follower circuit 71a, and an emitter follower circuit 72a cascade-connected in this order between the output node N3 and the output node N4.

[0062] The driver IC 105 also includes an output node OUTB, bipolar transistors 25a and 26a, a resistive element 33a, and an inductor 42a as a buffer circuit 117. The single-phase signal input to the node N1 is output from the output node OUTB as a single-phase signal.

[0063] According to such a modified example, even in a configuration in which a subsequent circuit is driven by a single-phase signal, it is possible to stabilize the frequency characteristics of the output signal adjusted by the driver IC 105.

[0064] 8 is a circuit diagram showing a configuration of a driver IC5A according to a modified example of the present disclosure. The driver IC5A is an embodiment in which the driver IC5 is modified so that the differential amplifier 11 has a function of generating a peaking characteristic.

[0065] That is, the driver IC 5A includes a differential amplifier (amplifying circuit) 11, a peak adjustment circuit 13, a follower circuit 15, and a buffer circuit 17. The differential amplifier 11, the peak adjustment circuit 13, and the follower circuit 15 configure the peaking adjustment circuit of this modified example.

[0066] The differential amplifier 11 is an integrated circuit that modulates an output current based on a pair of differential signals input from two nodes N1 and N5. The differential amplifier 11 includes bipolar transistors 20a, 20b, 21a, and 21b, resistive elements 30a, 30b, 31a, and 31b, inductors 40a and 40b, a current source 50, inductors 41a and 41b, an output node (second node) N2, and an output node (sixth node) N6.

[0067] The bipolar transistors 20a and 20b have their bases connected to the nodes N1 and N5, their collectors connected to the emitters of the bipolar transistors 21a and 21b, and their emitters connected to one end of the current source 50 via the resistor elements 30a and 30b. These bipolar transistors 20a and 20b modulate the collector currents with the input differential signal. The bipolar transistors 21a and 21b have their bases set to a predetermined DC voltage, their emitters connected to the collectors of the bipolar transistors 20a and 20b, and their collectors connected to a power supply line L1 to which a predetermined power supply potential (e.g., 3.3V) is applied via the resistor elements 31a and 31b and the inductors 40a and 40b. These bipolar transistors 21a and 21b are cascode transistors to which a DC voltage is applied to the bases.

[0068] The inductors 40a and 40b are inductors for shunt peaking and are also called shunt inductors. The inductors 40a and 40b enable the differential amplifier 11 to have a wide bandwidth. The inductors 41a and 41b are connected between the collectors of the bipolar transistors 21b and 21a and the output nodes N2 and N6, respectively. The inductors 41a and 41b are inductors for series peaking and are also called series inductors. The inductors 41a and 41b enable the differential amplifier 11 to have a wide bandwidth, similar to the shunt inductors. The differential amplifier 11 has at least one of the inductors 40a and 40b and the inductors 41a and 41b, and the other may be omitted. As a result, the frequency response of the differential amplifier 11 has a peak shape with a higher gain in a specific frequency range than in other frequency ranges. That is, the differential amplifier 11 generates a differential signal having a peaking characteristic in response to the differential signal input at the output nodes N2 and N6.

[0069] The resistor elements 30a and 30b are degeneration resistors that enable the linear input range of the driver IC 5A to be expanded. One end of the current source 50 is connected to the emitters of the bipolar transistors 20a and 20b via the resistor elements 30a and 30b, and the other end is connected to a ground line (ground wiring) GL set to a ground potential, and supplies the emitter currents of the bipolar transistors 20a and 20b. The resistor elements 31a and 31b are loads for converting the collector currents modulated by the bipolar transistors 20a and 20b into voltage signals.

[0070] According to the differential amplifier 11 having such a configuration, the collector currents of the bipolar transistors 20a and 20b are modulated by the differential signals input from the nodes N1 and N5, respectively, so that two output signals, which are differential signals, are generated at the output nodes N2 and N6 connected to the collectors of the bipolar transistors 21a and 21b.

[0071] The peak adjustment circuit 13 is a circuit that adjusts the frequency characteristics of two output signals generated at the output nodes N2 and N6. The peak adjustment circuit 13 includes an output node (third node) N3, an output node (seventh node) N7, control nodes NCa and NCb, a series circuit (first series circuit) 60a configured with a capacitor (first capacitor) 80a and a variable resistance element (first variable resistance element) 32a, and a series circuit (second series circuit) 60b configured with a capacitor (second capacitor) 80b and a variable resistance element (second variable resistance element) 32b.

[0072] By the driver IC5A, the positive-phase signal input to the node N1 and the negative-phase signal input to the node N5 are amplified by the differential amplifier 11 so as to have peaking characteristics, and are generated as an output signal at the output node N3 via the output node N2 and the series circuit 60a, and are also generated as an output signal at the output node N7 via the output node N6 and the series circuit 60b. Furthermore, the output signal output to the output node N3 is output from the output node N4 via the source follower circuit 70a, and the output signal output from the output node N7 is output from the output node N8 via the source follower circuit 70b. In this configuration, the variable resistance element 32a in the series circuit 60a is set to a variable first resistance value by the first setting signal, and the variable resistance element 32b in the series circuit 60b is set to a variable second resistance value by the second setting signal. This makes it possible to stabilize the peak frequencies of the two output signals while adjusting the peak amounts of those signals. As a result, it is possible to stabilize the frequency characteristics of the output signal adjusted by the driver IC5A of this modification.

[0073] 9 is a circuit diagram showing a configuration of a driver IC 105A according to a modified example of the present disclosure. The driver IC 105A is an embodiment in which the driver IC 105 is modified so that an amplifier 111 has a function of generating a peaking characteristic.

[0074] That is, the driver IC 105A has a node N1, and an amplifier 111 including bipolar transistors 20a and 21a, resistive elements 30a and 31a, an inductor 40a, an inductor 41A, and an output node N2. The amplifier 111 has at least one of the inductor 40a and the inductor 41a, and the other may be omitted. The amplifier 111 generates a single-phase signal having a peaking characteristic in response to the single-phase signal input at the output node N2.

[0075] The driver IC 105A also includes, as a peak adjustment circuit 113, an output node N3 and a series circuit 60a configured with a capacitor 80a and a variable resistance element 32a.

[0076] In such a modified example, even in a configuration in which a subsequent circuit is driven by a single-phase signal, it is possible to stabilize the frequency characteristics of the output signal adjusted by the driver IC 105A. [Explanation of symbols]

[0077] 1...Optical transmitter module 3. Package 5,105,5A,105A…Driver IC 7...Optical modulator 9...Optical coupling parts 11...Differential amplifier (amplifier circuit) 13,113…Peak adjustment circuit (adjustment circuit) 15,115…Follower circuit 17,117…Buffer circuit 32a...variable resistance element (first variable resistance element) 32b...variable resistance element (second variable resistance element) 41a...inductor (first inductor) 41b...inductor (second inductor) 60a...series circuit (first series circuit) 60b…Series circuit (second series circuit) 70a...source follower circuit (first source follower circuit) 70b...Source follower circuit (second source follower circuit) 71a...Emitter follower circuit (first emitter follower circuit) 71b...Emitter follower circuit (second emitter follower circuit) 72a, 72b...Emitter follower circuit 80a...capacitor (first capacitor) 80b...capacitor (second capacitor) 111...Amplifier (amplifier circuit) GL...Ground line (ground wiring) N1...node (first node) N2: Output node (second node) N3: Output node (third node) N4: Output node (fourth node) N5...node (5th node) N6: Output node (6th node) N7: Output node (7th node) N8: Output node (8th node) OUTA, OUTB...Output nodes

Claims

1. an amplifier circuit including a first node to which a first input signal is input and a second node which is an output node; an adjustment circuit including a third node which is an output node, a first inductor connected between the second node and the third node, and a first series circuit connected between the third node and a ground wiring, in which a first capacitor and a first variable resistance element are connected in series with each other; a follower circuit including a fourth node that is an output node, and a first source follower circuit connected between the third node and the fourth node; The first variable resistance element has a first resistance value that changes in response to a first setting signal. Peaking adjustment circuit.

2. the first series circuit is a circuit in which the first capacitor and the first variable resistance element are connected in this order between the third node and the ground wiring; 2. The peaking adjustment circuit of claim 1.

3. the first variable resistance element is configured by a field effect transistor having a drain connected to the first capacitor, a source connected to the ground wiring, and a gate to which the first setting signal is input; 3. The peaking adjustment circuit according to claim 2.

4. the follower circuit further includes a first emitter follower circuit cascade-connected to the first source follower circuit between the first source follower circuit and the fourth node; The peaking adjustment circuit according to any one of claims 1 to 3.

5. an amplifier circuit including a first node to which a first input signal is input, a fifth node to which a second input signal is input, and second and sixth nodes which are output nodes; an adjustment circuit including: a third node and a seventh node which are output nodes; a first inductor connected between the second node and the third node; a first series circuit connected between the third node and a ground wiring and in which a first capacitor and a first variable resistance element are connected in series to each other; a second inductor connected between the sixth node and the seventh node; and a second series circuit connected between the seventh node and the ground wiring and in which a second capacitor and a second variable resistance element are connected in series to each other; a follower circuit including a fourth node and an eighth node which are output nodes, a first source follower circuit connected between the third node and the fourth node, and a second source follower circuit connected between the seventh node and the eighth node; the first variable resistance element has a first resistance value that changes in response to a first setting signal; The second variable resistance element has a second resistance value that changes in response to a second setting signal. Peaking adjustment circuit.

6. the first series circuit is a circuit in which the first capacitor and the first variable resistance element are connected in this order between the third node and the ground wiring, the second series circuit is a circuit in which the second capacitor and the second variable resistance element are connected in this order between the seventh node and the ground wiring; 6. The peaking adjustment circuit according to claim 5.

7. the first variable resistance element is configured by a field effect transistor having a drain connected to the first capacitor, a source connected to the ground wiring, and a gate to which the first setting signal is input, the second variable resistance element is configured by a field effect transistor having a drain connected to the second capacitor, a source connected to the ground wiring, and a gate to which the second setting signal is input; 7. The peaking adjustment circuit according to claim 6.

8. The follower circuit includes: a first emitter follower circuit cascade-connected to the first source follower circuit between the first source follower circuit and the fourth node; a second emitter follower circuit cascade-connected to the second source follower circuit between the second source follower circuit and the eighth node; Further comprising: The peaking adjustment circuit according to any one of claims 5 to 7.

9. the inductance of the first inductor is equal to the inductance of the second inductor, The capacitance value of the first capacitor is equal to the capacitance value of the second capacitor, a resistance value of the first variable resistance element and a resistance value of the second variable resistance element are set to be equal to each other; The peaking adjustment circuit according to any one of claims 5 to 7.

10. an amplifier circuit including a first node to which a first input signal is input and a second node serving as an output node, the amplifier circuit generating an amplified signal having a peaking characteristic at the output node in response to the first input signal; an adjustment circuit including a third node and a first series circuit connected between the third node and a ground wiring, in which a first capacitor and a first variable resistance element are connected in series with each other; a follower circuit including a fourth node that is an output node, and a first source follower circuit connected between the third node and the fourth node; The first variable resistance element has a first resistance value that changes in response to a first setting signal.

11. an amplifier circuit including a first node to which a first input signal is input, a fifth node to which a second input signal is input, and second and sixth nodes which are output nodes, and which generates an amplified signal having peaking characteristics at the output node in response to the first input signal and the second input signal; an adjustment circuit including: a third node and a seventh node which are output nodes; a first series circuit connected between the third node and a ground wiring, in which a first capacitor and a first variable resistance element are connected in series; and a second series circuit connected between the seventh node and the ground wiring, in which a second capacitor and a second variable resistance element are connected in series; a follower circuit including a fourth node and an eighth node which are output nodes, a first source follower circuit connected between the third node and the fourth node, and a second source follower circuit connected between the seventh node and the eighth node; the first variable resistance element has a first resistance value that changes in response to a first setting signal; The second variable resistance element has a second resistance value that changes in response to a second setting signal. Peaking adjustment circuit.

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