Semiconductor device

Abstract

To provide a semiconductor device capable of improving reliability.SOLUTION: A semiconductor device according to an embodiment includes a first electrode, a second electrode facing the first electrode in a first direction, a semiconductor portion provided between the first electrode and the second electrode, a metal silicide layer provided between the second electrode and the semiconductor portion, and a metal layer provided between the metal silicide layer and the second electrode. The metal silicide layer includes a recess that is recessed toward the semiconductor portion. The metal layer contacts the bottom and side surfaces of the recess.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In power semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), p + Type semiconductor region and n + In known structures, a metal silicide layer and a metal layer may be provided between the source electrode and the semiconductor region.

[0003] In the above-mentioned power semiconductor device, when a reverse current flows between the drain electrode and the source electrode, thermal stress occurs due to the difference in thermal expansion coefficient between the metal silicide layer and the metal layer. If the thermal stress reduces the adhesion between the metal silicide layer and the metal layer, metal peeling and metal cracks are likely to occur. As a result, reliability may decrease. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 7243094 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device capable of improving reliability. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment includes a first electrode, a second electrode facing the first electrode in a first direction, a semiconductor portion provided between the first electrode and the second electrode, a metal silicide layer provided between the second electrode and the semiconductor portion, and a metal layer provided between the metal silicide layer and the second electrode. The metal silicide layer has a recess that is recessed toward the semiconductor portion. The metal layer contacts the bottom and side surfaces of the recess. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of the semiconductor device according to the first embodiment cut in the vertical direction. [Diagram 2] 1 is a perspective view showing a structure of a main part of a semiconductor device 1 according to a first embodiment. [Diagram 3] FIG. 11 is a cross-sectional view taken in the vertical direction of a semiconductor device according to a comparative example. [Figure 4] FIG. 11 is a perspective view showing a structure of a main part of a semiconductor device according to a comparative example. [Diagram 5] 1 is a cross-sectional view of a semiconductor device according to a second embodiment taken along a vertical direction. [Figure 6] FIG. 11 is a perspective view showing a structure of a main part of a semiconductor device according to a second embodiment. [Figure 7] FIG. 13 is a perspective view showing a structure of a main part of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiment.

[0009] (First embodiment) FIG. 1 is a vertical cross-sectional view of the semiconductor device according to the first embodiment. The semiconductor device 1 according to this embodiment is a MOSFET having a planar gate structure. In the following description, the arrangement and configuration of each part of the semiconductor device may be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually orthogonal and represent the X-direction (second direction), the Y-direction (third direction), and the Z-direction (first direction), respectively. In addition, the Z-direction may be described as upward and the opposite direction as downward. In this embodiment, the X-direction and the Y-direction represent in-plane directions parallel to the semiconductor device 1 according to this embodiment, and the Z-direction represents an out-of-plane direction perpendicular to the semiconductor device 1.

[0010] Also, p, p + The notation means that the p-type impurity concentration increases in this order. - , n + The notation indicates that the n-type impurity concentration increases in this order.

[0011] The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, SCM (Scanning Capacitance Microscopy). The distance, such as the depth of the semiconductor region, can also be obtained by, for example, SIMS.

[0012] The semiconductor device 1 according to this embodiment includes a semiconductor portion 10, a drain electrode 20, a source electrode 30, a gate electrode 40, a metal silicide layer 50, and a metal layer 60. The drain electrode 20 and the source electrode 30 correspond to a first electrode and a second electrode, respectively.

[0013] As shown in FIG. + A p-type semiconductor region 11 and + a p-type semiconductor region 12, a p-type semiconductor region 13, and an n - and a type semiconductor region 14. + The p-type semiconductor region 11 corresponds to the first semiconductor region.+ The p-type semiconductor region 12 corresponds to a second semiconductor region, and the p-type semiconductor region 13 corresponds to a third semiconductor region.

[0014] n + The n-type semiconductor region 11 is in contact with the metal silicide 50 on its top surface or side surface. + The n-type semiconductor region 11 is electrically connected to the source electrode 30 via the metal silicide 50 and the metal layer 60. + The n-type semiconductor region 11 can be formed, for example, by ion-implanting a high concentration of n-type impurities from the surface of the semiconductor portion 10.

[0015] p + The p-type semiconductor region 12 is in contact with the metal silicide 50 on its upper surface. + The p-type semiconductor region 12 is electrically connected to the source electrode 30 via the metal silicide 50 and the metal layer 60. + The p-type semiconductor region 12 can be formed, for example, by ion-implanting a high concentration of p-type impurities from the surface of the semiconductor portion 10.

[0016] Now, referring to FIG. 2, + Type semiconductor region 11 and p + The layout of the semiconductor region 12 will now be described.

[0017] 2 is a perspective view showing a structure of a main part of the semiconductor device 1 according to the first embodiment. + type semiconductor region 11 and p + The n-type semiconductor regions 12 are arranged in the X direction. + type semiconductor region 11 and p + The type semiconductor regions 12 are alternately arranged adjacent to each other along the Y direction.

[0018] The p-type semiconductor region 13 is + type semiconductor region 11 and p +The p-type semiconductor region 13 is in contact with each of the semiconductor regions so as to surround the p-type semiconductor region 12. The p-type semiconductor region 13 can be formed, for example, by ion implantation of a low concentration of p-type impurities from the surface of the semiconductor portion 10.

[0019] Returning to Figure 1, - The n-type semiconductor region 14 is a drift region disposed in the bottom layer of the semiconductor portion 10. - The type semiconductor region 14 is made of, for example, epitaxially grown SiC (silicon carbide).

[0020] n - The n-type semiconductor region 14 is depleted by a drain voltage applied between the drain electrode 20 and the source electrode 30 when the semiconductor device 1 is turned off. - The thickness of the type semiconductor region 14 is designed to satisfy a predetermined withstand voltage condition.

[0021] In the semiconductor portion 10, various semiconductor layers are formed into a p-type semiconductor region 13 and an n-type semiconductor region 14. - 1 and 2, nothing is shown in the region between the two p-type semiconductor regions 13 arranged side by side along the X direction, but this region can be, for example, a Schottky barrier diode region.

[0022] The drain electrode 20 is - The source electrode 30 is provided on the back surface of the type semiconductor region 14. The source electrode 30 is disposed to face the drain electrode 20 in the Z direction with the semiconductor portion 10 in between. The source electrode 30 is electrically insulated from the gate electrode 40 by an interlayer insulating film 70. The drain electrode 20 and the source electrode 30 can be formed using a metal such as aluminum. The interlayer insulating film 70 is, for example, a silicon oxide film (SiO2).

[0023] The gate electrode 40 faces the p-type semiconductor region 13 via the gate insulating film 41. The gate electrode 40 can be formed using, for example, a polysilicon film. The gate insulating film 41 is, for example, a silicon oxide film (SiO2). In this embodiment, the gate electrode 40 is a planar type, but may be a trench type.

[0024] The metal silicide layer 50 is n + The metal silicide layer 50 is provided on the p-type semiconductor region 11. + The metal silicide layer 50 is also provided on the type semiconductor region 12. The metal silicide layer 50 includes nickel silicon (NiSi).

[0025] When forming the metal silicide layer 50, first, the silicon film is + On the p-type semiconductor region 11 and + A metal film made of nickel or the like is then formed on the silicon film by, for example, sputtering. Thereafter, the silicon and the metal are reacted by, for example, annealing to form a metal silicide layer 50. Here, the structure of the metal silicide layer 50 will be described with reference to FIG. 2.

[0026] As shown in FIG. 2, the metal silicide layer 50 includes the semiconductor portion 10 (n + 11, p-type semiconductor region + The n-type semiconductor region 12 has a recess 51 recessed therein. The recess 51 is formed in a groove shape that extends continuously along the Y direction. + type semiconductor region 11 and p + In the type semiconductor region 12 , the region in contact with the metal silicide layer 50 is recessed to conform to the shape of the outer circumferential surface of the recess 51 .

[0027] Returning to FIG. 1, the metal layer 60 contacts the inner side and bottom surfaces of the recess 51. That is, the bottom surface of the metal layer 60 is convex so as to be in close contact with the inner circumferential surface of the recess 51 of the metal silicide 50. The upper surface of the metal layer 60 is concave toward the metal silicide 50. Therefore, the bottom surface of the source electrode 30 in contact with the metal layer 60 is convex along the concave of the metal layer 60. The metal layer 60 can be formed by vapor deposition of a metal such as titanium.

[0028] Now, a comparative example to be compared with this embodiment will be described with reference to FIGS.

[0029] Fig. 3 is a vertical cross-sectional view of the semiconductor device according to the comparative example. Fig. 4 is a perspective view showing the structure of the main part of the semiconductor device according to the comparative example. In Figs. 3 and 4, the same components as those in the semiconductor device 1 described above are given the same reference numerals, and detailed description thereof will be omitted.

[0030] In the semiconductor device 100 according to this comparative example, the metal silicide layer 50 is formed in a flat plate shape, as shown in Fig. 4. Therefore, only the upper surface of the metal silicide layer 50 is in contact with the metal layer 60, as shown in Fig. 4.

[0031] In the semiconductor device 100 configured as described above, when a reverse current flows, for example from the source electrode 30 to the drain electrode 20, + A large current is concentrated in the p-type semiconductor region 12. + The p-type semiconductor region 12 generates heat. + The metal silicide layer 50 in contact with the type semiconductor region 12 and the metal layer 60 in contact with the metal silicide layer 50 are then propagated.

[0032] p +The thermal expansion coefficients of the metal silicide layer 50 and the metal layer 60 in contact with the type semiconductor region 12 are different. Therefore, thermal stress caused by the difference in thermal expansion coefficient occurs at the interface between the metal silicide layer 50 and the metal layer 60. This thermal stress can reduce adhesion at the interface between the metal silicide layer 50 and the metal layer 60. When this adhesion is reduced, metal peeling, in which the metal layer 60 peels off from the metal silicide layer 50, and metal cracking, in which cracks occur in the metal layer 60, are more likely to occur.

[0033] Therefore, in this embodiment, n + type semiconductor region 11 or p + A recess is formed in the type semiconductor region 12 by etching or the like, and a metal film made of nickel or the like is sputtered to form the recess 51. A metal layer 60 is also formed so as to adhere to the inner side and bottom surface of the recess 51. As a result, the adhesion between the metal silicide layer 50 and the metal layer 60 is strengthened by the anchor effect. Therefore, metal peeling and metal cracks in the metal layer 60 are less likely to occur, improving reliability.

[0034] In this embodiment, the source electrode 30 contains aluminum. Aluminum is a relatively flexible metal. Therefore, the source electrode 30 penetrates into the recess 51 and functions as a cushion that relieves thermal stress caused by the difference in thermal expansion coefficient between the metal silicide layer 50 and the metal layer 60. This makes it even more difficult for metal peeling or metal cracks to occur in the metal layer 60, further improving reliability.

[0035] In the semiconductor device 1 according to this embodiment, when a predetermined voltage is applied between the gate electrode 20 and the source electrode 30, a channel is formed in the p-type semiconductor region 13. This causes a forward current to flow from the drain electrode 20 to the source electrode 30. At this time, if the current value is large, n + Thermal stress occurs at the interface between the metal silicide layer 50 in contact with the type semiconductor region 11 and the metal layer 60 in contact with this metal silicide layer 50. Therefore, there is concern that the adhesion between these two layers may decrease.

[0036] However, in this embodiment, p + Not only the metal silicide layer 50 in contact with the n-type semiconductor region 12 but also + A recess 51 is also formed in the metal silicide layer 50 in contact with the n-type semiconductor region 11. + The adhesion between the metal silicide layer 50 in contact with the p-type semiconductor region 11 and the metal layer 60 in contact with the metal silicide layer 50 is thus strengthened. + Not only the n-type semiconductor region 12 but also + Since metal peeling and metal cracks are less likely to occur on the side of the mold semiconductor region 11, the reliability can be further improved.

[0037] Second embodiment Fig. 5 is a vertical cross-sectional view of the semiconductor device according to the second embodiment. Fig. 6 is a perspective view showing the structure of the main part of the semiconductor device according to the second embodiment. In Fig. 5 and Fig. 6, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0038] The semiconductor device 2 according to this embodiment is different from the first embodiment in the shape of the metal silicide layer 50. In the metal silicide layer 50 according to the first embodiment described above, n + A first portion 50a in contact with the p-type semiconductor region 11; + The depth from the surface of the semiconductor portion 10 to the bottom end of the metal silicide layer 50 is the same between the second portion 50b that is in contact with the type semiconductor region 12 and the second portion 50b.

[0039] 5 and 6, in the metal silicide layer 50 according to this embodiment, the depth from the surface of the semiconductor portion 10 to the lower end of the metal silicide layer 50 differs between the first portion 50a and the second portion 50b. Specifically, the depth d2 of the second portion 50b is greater than the depth d1 of the first portion 50a. As the depth increases, the anchor effect between the metal silicide layer 50 and the metal layer 60 increases.

[0040] In order to form the metal silicide layer 50 having the first portion 50a and the second portion 50b, in this embodiment, as shown in FIG. + The p-type semiconductor region 11 is etched to a depth d1. + The type semiconductor region 12 is etched to a depth d2.

[0041] In the semiconductor device 2 according to this embodiment, similarly to the first embodiment, when a current flows in the reverse direction between the drain electrode 20 and the source electrode 30, the current + The thermal stress is concentrated in the type semiconductor region 12. Therefore, the thermal stress may occur at the interface between the metal silicide layer 50 and the metal layer 60.

[0042] However, in the metal silicide layer 50 according to this embodiment, p + The depth d2 of the second portion 50b in contact with the n-type semiconductor region 12 is + The depth d1 of the second portion 50b is greater than the depth d1 of the first portion 50a that contacts the type semiconductor region 11. Therefore, the anchor effect of the second portion 50b is higher than that of the first embodiment. Therefore, the adhesion between the metal silicide layer 50 and the metal layer 60 is further strengthened. Therefore, it is possible to further improve the reliability.

[0043] In this embodiment, the depth d2 of the second portion 50b is greater than the depth d1 of the first portion 50a, but the depth relationship may be changed as appropriate depending on the magnitude of the current. For example, when a large current flows in the forward direction between the drain electrode 20 and the source electrode 30, the adhesion between the first portion 50 and the metal layer 60 is likely to decrease.

[0044] In the above case, the depth d1 of the first portion 50a may be made larger than the depth d2 of the second portion 50b. This strengthens the adhesion between the first portion 50 and the metal layer 60. This makes it possible to further improve the reliability.

[0045] Third embodiment Fig. 7 is a perspective view showing the structure of the main part of the semiconductor device according to the third embodiment. In Fig. 7, the same components as those in the first embodiment are given the same reference numerals, and detailed description is omitted. Note that the cross-sectional structure of the semiconductor device 3 according to this embodiment is similar to that of the first embodiment shown in Fig. 1, and therefore illustration and description are omitted.

[0046] The semiconductor device 3 according to this embodiment is different from the first embodiment in the structure of the metal silicide layer 50. + A first portion 50a in contact with the p-type semiconductor region 11; + The first portions 50a and the second portions 50b in contact with the first semiconductor region 12 are arranged in a lattice pattern along the X direction and the Y direction. In other words, the first portions 50a and the second portions 50b are arranged intermittently and alternately along the X direction and the Y direction.

[0047] The first portion 50a is + The second portion 50b is formed in a concave shape that is concave toward the p-type semiconductor region 11. + The metal silicide layer 50 is formed in a concave shape recessed toward the type semiconductor region 12. The metal layer 60 is embedded without any gaps along the concave shapes of the first portion 50a and the second portion 50b. Therefore, the adhesion between the metal silicide layer 50 and the metal layer 60 is strengthened by the anchor effect. As a result, even if forward and reverse currents flow between the drain electrode 20 and the source electrode 30, problems such as peeling or cracking of the metal layer 60 are unlikely to occur.

[0048] Therefore, according to this embodiment, it is possible to improve reliability in the same way as in the first embodiment.

[0049] In this embodiment, as shown in FIG. 7, between the first portion 50a and the second portion 50b arranged along the Y direction, + The n-type semiconductor region 11 is interposed. + The area of ​​the type semiconductor region 11 is larger than that of the first embodiment, which makes it possible to reduce the on-resistance.

[0050] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0051] 1, 2, 3: Semiconductor device 10: Semiconductor department 11:n + Type semiconductor region (first semiconductor region) 12:p + Type semiconductor region (second semiconductor region) 13: p-type semiconductor region (third semiconductor region) 20: Drain electrode (first electrode) 30: Source electrode (second electrode) 40: Gate electrode 50: Metal silicide layer 50a: 1st part 50b:Second part 51: Recess 60: Metal layer

Claims

1. A first electrode; a second electrode facing the first electrode in a first direction; A semiconductor portion provided between the first electrode and the second electrode; a metal silicide layer provided between the second electrode and the semiconductor portion; a metal layer provided between the metal silicide layer and the second electrode; the metal silicide layer has a recess that is recessed toward the semiconductor portion, The metal layer contacts a bottom surface and a side surface of the recess. Semiconductor device.

2. The semiconductor portion is 2. The semiconductor device according to claim 1, further comprising a first semiconductor region of a first conductivity type in contact with said metal silicide layer.

3. the semiconductor portion includes a second semiconductor region of a second conductivity type; 3. The semiconductor device according to claim 2, wherein said metal silicide layer has a first portion in contact with said first semiconductor region and a second portion in contact with said second semiconductor region.

4. The semiconductor device according to claim 3 , wherein the first semiconductor region and the second semiconductor region are arranged side by side along a second direction perpendicular to the first direction.

5. The semiconductor device according to claim 4 , wherein the first semiconductor regions and the second semiconductor regions are alternately arranged adjacent to each other along a third direction perpendicular to the first direction and the second direction.

6. The semiconductor device according to claim 5 , wherein the recess has a groove shape that extends continuously in the third direction.

7. 4. The semiconductor device according to claim 3, wherein a depth from a surface of said semiconductor portion to a lower end of said metal silicide layer differs between said first portion and said second portion.

8. The semiconductor device according to claim 5 , wherein the first portions and the second portions are arranged in a lattice pattern along the second direction and the third direction.

9. a third semiconductor region of a second conductivity type in contact with the first semiconductor region and the second semiconductor region; a gate electrode facing the third semiconductor region via a gate insulating film; The semiconductor device according to claim 3 , further comprising:

10. the second electrode comprises aluminum; the metal silicide layer comprises nickel silicon (NiSi); the metal layer comprises titanium; The semiconductor device according to claim 1 .

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