Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of reducing the variation in the amount of gate-drain charge and a manufacturing method thereof.SOLUTION: A gate electrode includes a first side portion facing a region including at least a second semiconductor portion on a side surface of a mesa portion of a semiconductor layer, a second side portion located on the opposite side of the first side portion in the second direction, a bottom portion inclined with respect to the first side portion and the second side portion and connecting the first side portion and the second side portion, a first corner portion located between the first side portion and the bottom portion, and a second corner portion located between the second side portion and the bottom portion. When a straight line passing through the first corner portion and extending in the first direction is defined as a first straight line, and a straight line passing through the first corner portion and the second corner portion is defined as a second straight line, the angle formed by the first straight line and the second straight line is 60° or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices having a trench gate structure in which a gate electrode is provided in a trench formed in a semiconductor layer are widely used for, for example, power control. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-62502 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device capable of reducing variations in the amount of gate-drain charge and a method for manufacturing the same. [Means for solving the problem]

[0005] According to an embodiment, a semiconductor device includes a semiconductor layer having a first semiconductor portion of a first conductivity type, a second semiconductor portion of a second conductivity type provided on the first semiconductor portion, and a third semiconductor portion of the first conductivity type provided on the second semiconductor portion, the semiconductor layer including a part of the first semiconductor portion, the second semiconductor portion, and the third semiconductor portion and having a mesa portion extending in a first direction, a gate electrode facing a side surface of the mesa portion, and a first insulating portion provided between the gate electrode and the side surface of the mesa portion, the gate electrode insulating at least the second semiconductor portion on the side surface of the mesa portion. a first side portion facing a region including the first side portion, a second side portion located on the opposite side of the first side portion in a second direction perpendicular to the first direction, a bottom portion inclined with respect to the first side portion and the second side portion and connecting the first side portion and the second side portion, a first corner portion located between the first side portion and the bottom, and a second corner portion located between the second side portion and the bottom, wherein a first line is a line passing through the first corner portion and extending in the first direction, and a second line is a line passing through the first corner portion and the second corner portion, the angle formed by the first line and the second line is 60° or less. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Diagram 2] FIG. 13 is a graph showing the results of a simulation of the sensitivity of the variation in Qgd to the variation in the position of the first corner portion of the gate electrode. [Diagram 3] 2A to 2C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 2A to 2C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Diagram 5] 2A to 2C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 2A to 2C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 2A to 2C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 8]2A to 2C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 2A to 2C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals. In the following embodiments, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0008] As shown in FIG. 1, the semiconductor device of the embodiment includes a semiconductor layer 10 and a trench structure portion 100.

[0009] The semiconductor layer 10 has a first surface 10A and a second surface 10B located on the opposite side of the first surface 10A in a first direction Z. The first direction Z is a direction that connects the first surface 10A and the second surface 10B in the shortest distance. In FIG. 1, a direction perpendicular to the first direction Z is defined as a second direction X. A direction perpendicular to the first direction Z and the second direction X is defined as a third direction Y. In the first direction Z, a direction toward the first surface 10A is defined as an upward direction, and a direction toward the second surface 10B is defined as a downward direction.

[0010] The semiconductor layer 10 may be made of, for example, silicon. Alternatively, the semiconductor layer 10 may be made of, for example, silicon carbide, gallium nitride, or the like.

[0011] The semiconductor layer 10 has an n-type first semiconductor portion 11, a p-type second semiconductor portion 12 provided on the first semiconductor portion 11, and an n-type third semiconductor portion 13 provided on the second semiconductor portion 12. The n-type impurity concentration of the third semiconductor portion 13 is higher than the n-type impurity concentration of the first semiconductor portion 11.

[0012] The semiconductor layer 10 also includes a part of the first semiconductor portion 11, the second semiconductor portion 12, and the third semiconductor portion 13, and has a mesa portion 10C extending in the first direction Z. The first surface 10A includes an upper surface of the mesa portion 10C. The upper surface of the mesa portion 10C includes an upper surface of the third semiconductor portion 13. The mesa portion 10C extends in the third direction Y. For example, the multiple mesa portions 10C are arranged apart from each other in the second direction X. Alternatively, multiple columnar mesa portions 10C may be arranged side by side in the second direction X and the third direction Y.

[0013] The trench structure 100 is located in the semiconductor layer 10 on the first surface 10A side. For example, the trench structure 100 extends in the third direction Y. For example, a plurality of trench structures 100 are arranged in the semiconductor layer 10 apart from each other in the second direction X. Alternatively, a plurality of columnar trench structures 100 may be arranged in the second direction X and the third direction Y.

[0014] For example, mesa portions 10C of the semiconductor layer 10 and trench structures 100 are alternately arranged in the second direction X. The trench structures 100 are adjacent to the mesa portions 10C in the second direction X. The trench structures 100 are located between adjacent mesa portions 10C in the second direction X. The mesa portions 10C are located between adjacent trench structures 100 in the second direction X.

[0015] The trench structure 100 includes a gate electrode 30 and an insulating member 40 .

[0016] The gate electrode 30 faces a side surface of the mesa portion 10C in the second direction X. The side surface of the mesa portion 10C includes a part of a side surface of the first semiconductor portion 11, a side surface of the second semiconductor portion 12, and a side surface of the third semiconductor portion 13. As a material for the gate electrode 30, for example, polycrystalline silicon having electrical conductivity can be used.

[0017] The gate electrode 30 has a first side portion 31, a second side portion 32, a bottom portion 33, a first corner portion C1, and a second corner portion C2.

[0018] 1, the position of the upper end of the first side portion 31 in the first direction Z is located on the third semiconductor portion 13 side relative to the boundary between the second semiconductor portion 12 and the third semiconductor portion 13.

[0019] The second side surface portion 32 is located on the opposite side to the first side surface portion 31 in the second direction X. The length of the second side surface portion 32 in the first direction Z is longer than the length of the first side surface portion 31 in the first direction Z.

[0020] The bottom portion 33 is inclined with respect to the first side portion 31 and the second side portion 32, and connects the first side portion 31 and the second side portion 32. In a cross-sectional view, the shape of the bottom portion 33 is not limited to being linear, and may be curved, convex, concave, or a combination of two or more of these shapes.

[0021] The first corner C1 is located between the first side surface portion 31 and the bottom portion 33. For example, the angle formed between the first side surface portion 31 and the bottom portion 33 on the inner side of the gate electrode 30 (the interior angle of the first corner C1) is greater than 90°.

[0022] The second corner C2 is located between the second side surface portion 32 and the bottom portion 33. For example, the angle formed between the second side surface portion 32 and the bottom portion 33 on the inner side of the gate electrode 30 (the interior angle of the second corner C2) is smaller than 90°. The position of the second corner C2 in the first direction Z is located lower than the position of the first corner C1 in the first direction Z.

[0023] The insulating member 40 has a first insulating portion 41 provided between the gate electrode 30 and a side surface of the mesa portion 10C of the semiconductor layer 10. The maximum thickness in the second direction X of the first insulating portion 41 between the first side portion 31 of the gate electrode 30 and the side surface of the mesa portion 10C is smaller than the maximum thickness in the second direction X of the first insulating portion 41 between the bottom portion 33 of the gate electrode 30 and the side surface of the mesa portion 10C.

[0024] The trench structure 100 may further include a conductive member 50. The conductive member 50 faces the second side portion 32 of the gate electrode 30 in the second direction X and extends downward in the first direction Z beyond the bottom portion 33 of the gate electrode 30. As a material for the conductive member 50, for example, polycrystalline silicon having conductivity can be used.

[0025] One trench structure 100 has, for example, two gate electrodes 30 located apart from each other in the second direction X. For example, the conductive member 50 is located between the second side portions 32 of the two gate electrodes 30. The conductive member 50 extends downward from a portion located between the two gate electrodes 30.

[0026] The conductive member 50 is electrically connected to a first electrode 21, which will be described later. Alternatively, a potential lower than that of a second electrode 22, which will be described later and to which a higher potential is applied than that of the first electrode 21, may be applied to the conductive member 50. The conductive member 50 can reduce the electric field (vertical electric field) applied in the first direction Z, and can improve the withstand voltage.

[0027] The insulating member 40 is located between the gate electrode 30 and the semiconductor layer 10, between the conductive member 50 and the semiconductor layer 10, and between the gate electrode 30 and the conductive member 50. The insulating member 40 may be made of, for example, silicon oxide.

[0028] The insulating member 40 further includes a second insulating portion 42, a third insulating portion 43, and a fourth insulating portion 44 in addition to the first insulating portion 41 described above.

[0029] The second insulating portion is located between the second side portion 32 of the gate electrode 30 and the conductive member 50 in the second direction X.

[0030] The third insulating portion 43 is provided between the conductive member 50 and the first semiconductor portion 11 of the semiconductor layer 10.

[0031] The fourth insulating portion 44 is located in the first direction X between the gate electrode 30 and the first electrode 21 and between the conductive member 50 and the first electrode 21.

[0032] The semiconductor device of the embodiment further includes a first electrode 21 provided on the first surface 10A and a second electrode 22 provided on the second surface 10B. The first electrode 21 contacts the third semiconductor portion 13 and is electrically connected to the third semiconductor portion 13. The first electrode 21 contacts the second semiconductor portion 12 and is electrically connected to the second semiconductor portion 12.

[0033] The semiconductor layer 10 may further include an n-type fourth semiconductor portion 14 provided between the second electrode 22 and the first semiconductor portion 11. The n-type impurity concentration of the fourth semiconductor portion 14 is higher than the n-type impurity concentration of the first semiconductor portion 11. The fourth semiconductor portion 14 is electrically connected to the second electrode 22.

[0034] The semiconductor device according to the embodiment has, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. For example, the first electrode 21 functions as a source electrode, the second electrode 22 functions as a drain electrode, the first semiconductor portion 11 functions as a drift layer, the second semiconductor portion 12 functions as a base layer, the third semiconductor portion 13 functions as a source layer, and the fourth semiconductor portion 14 functions as a drain layer.

[0035] When a first potential (e.g., ground potential) is applied to the first electrode 21, a second potential (e.g., positive potential) higher than the first potential is applied to the second electrode 22, and a gate voltage equal to or greater than a threshold value is applied to the gate electrode 30, an n-type inversion layer (channel) is formed in a portion of the second semiconductor portion 12 facing the first side portion 31 of the gate electrode 30. Then, a current flows between the second electrode 22 (drain electrode) and the first electrode 21 (source electrode) via the fourth semiconductor portion 14 (drain layer), the channel, and the third semiconductor portion 13 (source layer).

[0036] According to this embodiment, if a straight line passing through the first corner C1 of the gate electrode 30 and extending in the first direction Z is defined as a first straight line L1, and a straight line passing through the first corner C1 and the second corner C2 is defined as a second straight line L2, the angle θ1 formed between the first straight line L1 and the second straight line L2 is 60° or less.

[0037] FIG. 2 is a graph showing the results of a simulation of the sensitivity of the variation in Qgd to the variation in the position of the first corner C1 of the gate electrode 30 in the first direction Z when the angle θ1 is changed to 20°, 30°, 40°, 60°, and 80°.

[0038] The horizontal axis represents the position Z in the first direction Z of the first corner C1 of the gate electrode 30. C1 The position Z of the first corner C1 when the on-resistance is the same for each of the angles θ1 of 20°, 30°, 40°, 60°, and 80° represents the variation in the on-resistance. C1 is set to 100%. In order to obtain the same on-resistance, the smaller the angle θ1, the greater the difference in the position Z C1 is located on the side closer to the first surface 10A (upper side).

[0039] The vertical axis represents the variation in the amount of charge Qgd between the gate electrode 30 and the first semiconductor portion 11 (hereinafter also referred to as the gate-drain charge amount). C1 When is 100%, Qgd is 100%.

[0040] Qgd is one of the parameters that affect the characteristics of the semiconductor device, and affects the switching loss when the semiconductor device is turned on and off by switching the gate voltage applied to the gate electrode 30. Therefore, it is required that Qgd is within a predetermined range. In order to reduce the switching loss, C1 When the variation in Qgd is ±10%, the variation in Qgd must be kept within ±25%.

[0041] From the results in Figure 2, by setting the angle θ1 between the first line L1 and the second line L2 to 60° or less, the variation in Qgd can be reduced to ±25% or less. Also, by setting the angle θ1 to 40° or less, the variation in Qgd can be reduced to less than ±25%.

[0042] Next, a method for manufacturing the semiconductor device of the embodiment will be described with reference to FIGS.

[0043] 3, the method for manufacturing the semiconductor device according to the embodiment includes a step of forming a first trench T1 and a mesa portion 10C in the semiconductor layer 10. The first trench T1 is formed by, for example, a reactive ion etching (RIE) method.

[0044] The first trench T1 extends in a first direction Z from the first surface 10A of the semiconductor layer 10. The mesa portion 10C is adjacent to the first trench T1 in the second direction X. For example, a plurality of first trenches T1 and a plurality of mesa portions 10C are alternately arranged in the second direction X.

[0045] 4 to 9, which show subsequent steps, show an enlarged view of a portion on the first surface 10A side where the first trench T1 and the mesa portion 10C are adjacent to each other.

[0046] The manufacturing method of the semiconductor device according to the embodiment includes a step of forming an insulating member 40 in the first trench T1. As shown in FIG. 4, the insulating member 40 covers the side surface (side wall of the first trench T1) and the first surface 10A of the mesa portion 10C. The insulating member 40 also covers the bottom wall of the first trench T1. The insulating member 40 is formed along two side walls and the bottom wall of the first trench T1 that face each other in the second direction X. In the case of a semiconductor device including a conductive member 50, a space is left between the insulating members 40 located on the two side walls of the first trench T1, and the conductive member 50 is formed in the space.

[0047] The method for manufacturing a semiconductor device according to the embodiment includes a step of forming a second trench T2 in an insulating member 40, as shown in FIG. 5. The second trench T2 is formed by dry etching. The second trench T2 is formed by, for example, an RIE method. During the RIE, conditions are set such that the sputtered material is easily deposited on the sidewall of the second trench T2. As a result, the sidewall of the second trench T2 is inclined with respect to the first direction Z so that the width in the second direction X becomes smaller toward the bottom of the second trench T2.

[0048] The second trench T2 has a first sidewall T2a facing the side surface of the mesa portion 10C in the second direction X, a second sidewall T2b located on the opposite side of the first sidewall T2a in the second direction X, and a bottom wall T2c connecting the first sidewall T2a and the second sidewall T2b. The variation in the depth of the first sidewall T2a when forming the second trench T2 is caused by the difference in the position Z in the first direction Z of the first corner portion C1 of the gate electrode 30 described above. C1 This corresponds to the variation in and affects the variation in Qgd.

[0049] The second sidewall T2b is located closer to the interface between the conductive member 50 and the insulating member 40 in the second direction X than the first sidewall T2a. In the state shown in FIG. 4 before the second trench T2 is formed, the thickness in the first direction Z of the insulating member 40 on the mesa portion 10C side is thicker than the thickness in the first direction Z of the insulating member 40 on the conductive member 50 side. Therefore, as shown in FIG. 5, in the second trench T2, the depth in the first direction Z on the mesa portion 10C side is shallower than the depth in the first direction Z on the conductive member 50 side. That is, the position in the first direction Z of the lower end of the second sidewall T2b is located lower than the position in the first direction Z of the lower end of the first sidewall T2a.

[0050] Therefore, the bottom wall T2c is inclined with respect to the first side wall T2a and the second side wall T2b. The second trench T2 has a third corner C3 located between the first side wall T2a and the bottom wall T2c, and a fourth corner C4 located between the second side wall T2b and the bottom wall T2c. The position of the fourth corner C4 in the first direction Z is lower than the position of the third corner C3 in the first direction Z.

[0051] If a line passing through the third corner C3 of the second trench T2 and extending in the first direction Z is defined as a third line L3, and a line passing through the third corner C3 and the fourth corner C4 is defined as a fourth line L4, the angle θ2 between the third line L3 and the fourth line L4 is 60° or less. Since a gate electrode 30 is formed in the second trench T2 as described below, the angle θ2 of the second trench T2 corresponds to the angle θ1 of the gate electrode 30 described above.

[0052] The method for manufacturing the semiconductor device according to the embodiment includes a step of forming a gate electrode 30 in the second trench T2, as shown in FIG. 8. The gate electrode 30 is formed by, for example, a chemical vapor deposition (CVD) method. The gate electrode 30 is also deposited above the first surface 10A in the first direction Z, and then etched back by, for example, a chemical dry etching (CDE) method. As a result, the upper surface of the gate electrode 30 recedes to a predetermined position in the second trench T2, as shown in FIG. 9.

[0053] In the step of forming the second trench T2 described above, as shown in FIG. 5, a part 40a of the insulating member 40 is left between the first sidewall T2a and the side surface of the mesa portion 10C. The method for manufacturing the semiconductor device of the embodiment may include a step of removing the part 40a of the insulating member 40 between the first sidewall T2a and the side surface of the mesa portion 10C after forming the second trench T2, and exposing the side surface of the mesa portion 10C at the first sidewall T2a, as shown in FIG. 6. Furthermore, the method for manufacturing the semiconductor device of the embodiment may include a step of forming a first insulating portion 41 on the exposed side surface of the mesa portion 10C, as shown in FIG. 7. This allows the first insulating portion 41, which is not damaged by RIE, to be used as a gate insulating film, instead of the part 40a of the insulating member 40 damaged by RIE when forming the second trench T2.

[0054] For example, the part 40a of the insulating member 40 between the first sidewall T2a and the side surface of the mesa portion 10C can be removed by wet etching. This can reduce damage to the semiconductor layer 10 compared to removing the part 40a of the insulating member 40 by dry etching. In addition, the first insulating portion 41 can be formed by thermal oxidation treatment of the exposed side surface of the mesa portion 10C.

[0055] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0056] 10...semiconductor layer, 10A...first surface, 10B...second surface, 11...first semiconductor portion, 12...second semiconductor portion, 13...third semiconductor portion, 14...fourth semiconductor portion, 21...first electrode, 22...second electrode, 30...gate electrode, 31...first side portion, 32...second side portion, 33...bottom portion, 40...insulating member, 41...first insulating portion, 42...second insulating portion, 43... Third insulating portion, 44...fourth insulating portion, 50...conductive member, 100...trench structure portion, C1...first corner portion, C2...second corner portion, C3...third corner portion, C4...fourth corner portion, L1...first straight line, L2...second straight line, L3...third straight line, L4...fourth straight line, T1...first trench, T2...second trench, T2a...first side wall, T2b...second side wall, T2c...bottom wall

Claims

1. a semiconductor layer having a first semiconductor section of a first conductivity type, a second semiconductor section of a second conductivity type provided on the first semiconductor section, and a third semiconductor section of the first conductivity type provided on the second semiconductor section, the semiconductor layer having a mesa section including a part of the first semiconductor section, the second semiconductor section, and the third semiconductor section and extending in a first direction; a gate electrode facing a side surface of the mesa portion; a first insulating portion provided between the gate electrode and the side surface of the mesa portion; Equipped with The gate electrode is a first side surface portion facing a region of the side surface of the mesa portion that includes at least the second semiconductor portion; a second side portion located on an opposite side of the first side portion in a second direction perpendicular to the first direction; a bottom portion inclined with respect to the first side portion and the second side portion and connecting the first side portion and the second side portion; a first corner portion located between the first side portion and the bottom portion; a second corner portion located between the second side portion and the bottom portion; having If a straight line passing through the first corner portion and extending in the first direction is defined as a first straight line, and a straight line passing through the first corner portion and the second corner portion is defined as a second straight line, The angle between the first straight line and the second straight line is 60° or less.

2. The semiconductor device according to claim 1 , wherein the angle between the first straight line and the second straight line is equal to or smaller than 40°.

3. a conductive member facing the second side portion of the gate electrode in the second direction and extending downward in the first direction below the bottom portion of the gate electrode; a second insulating portion located between the conductive member and the second side surface portion; The semiconductor device according to claim 1 , further comprising:

4. a first electrode provided on the mesa portion and electrically connected to the third semiconductor portion; The semiconductor device according to claim 3 , wherein the conductive member is electrically connected to the first electrode.

5. forming a first trench extending in the first direction from a first surface of a semiconductor layer having a first surface and a second surface located on an opposite side of the first surface in the first direction, and a mesa portion of the semiconductor layer adjacent to the first trench in a second direction perpendicular to the first direction; forming an insulating member in the first trench; a step of forming a second trench in the insulating member by dry etching, the second trench having a first sidewall facing a side surface of the mesa portion in the second direction, a second sidewall located on the opposite side of the first sidewall in the second direction, a bottom wall inclined with respect to the first sidewall and the second sidewall and connecting the first sidewall and the second sidewall, a third corner located between the first sidewall and the bottom wall, and a fourth corner located between the second sidewall and the bottom wall, wherein a third straight line is a line passing through the third corner and extending in the first direction, and a fourth straight line is a line passing through the third corner and the fourth corner, the angle formed by the third straight line and the fourth straight line is 60° or less; forming a gate electrode in the second trench; A method for manufacturing a semiconductor device comprising the steps of:

6. In the step of forming the second trench, a part of the insulating member is left between the first sidewall and the side surface of the mesa portion; after forming the second trench, removing the portion of the insulating member between the first sidewall and the side surface of the mesa portion to expose the side surface of the mesa portion at the first sidewall; forming a first insulating portion on the exposed side surface of the mesa portion; The method for manufacturing a semiconductor device according to claim 5 , further comprising:

7. The method for manufacturing a semiconductor device according to claim 6 , wherein the portion of the insulating member between the first sidewall and the side surface of the mesa portion is removed by wet etching.

8. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the first insulating portion is formed by a thermal oxidation treatment on the exposed side surface of the mesa portion.

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