Detection circuit, semiconductor integrated circuit, semiconductor device, and control method

Abstract

To provide a detection circuit suitable for appropriately protecting a power device from overcurrent.SOLUTION: According to one embodiment, there is provided a detection circuit having a comparison circuit and a signal generation circuit. The comparison circuit has a first input node, a second input node, and an output node. The first input node is connected to one end of the power device. The second input node is connected to a threshold voltage. The signal generation circuit has a first input node and an output node. The first input node is connected to the output node of the comparison circuit. The output node is connected to a control node of a protection circuit of the power device.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present embodiment relates to a detection circuit, a semiconductor integrated circuit, a semiconductor device, and a control method. [Background technology]

[0002] A semiconductor device connected to a control terminal of a power device drives the power device. The power device is connected to a load through which a relatively large current flows and is used to switch the load. In the semiconductor device, it is desirable to appropriately protect the power device from overcurrent. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2018 / 0097515 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a detection circuit, a semiconductor integrated circuit, a semiconductor device, and a control method suitable for appropriately protecting a power device from an overcurrent. [Means for solving the problem]

[0005] According to one embodiment, a detection circuit is provided having a comparison circuit and a signal generation circuit. The comparison circuit has a first input node, a second input node, and an output node. The first input node is connected to one end of a power device. The second input node is connected to a threshold voltage. The signal generation circuit has a first input node and an output node. The first input node is connected to an output node of the comparison circuit. The output node is connected to a control node of a protection circuit for the power device. [Brief description of the drawings]

[0006] [Figure 1] 1 is a circuit diagram showing a configuration of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing the concept of DESAT in an embodiment. [Diagram 3] 5 is a waveform diagram showing the operation of the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a circuit diagram showing a configuration of a semiconductor device according to a first modified example of the embodiment. [Diagram 5] FIG. 4 is a circuit diagram showing a configuration of a time history generating circuit according to a first modified example of the embodiment. [Figure 6] FIG. 11 is a waveform diagram showing the operation of the time history generating circuit according to the first modified example of the embodiment. [Figure 7] FIG. 11 is a circuit diagram showing a configuration of a semiconductor device according to a second modified example of the embodiment. [Figure 8] FIG. 11 is a circuit diagram showing a configuration of a semiconductor device according to a third modified example of the embodiment. [Figure 9] FIG. 11 is a circuit diagram showing a configuration of a semiconductor device according to a fourth modified example of the embodiment. [Figure 10] FIG. 13 is a circuit diagram showing a configuration of a semiconductor device according to a fifth modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the embodiment.

[0008] (Embodiment) The semiconductor device according to the embodiment is connected to a control terminal of a power device to drive the power device, and is designed to appropriately protect the power device from an overcurrent.

[0009] The semiconductor device 1 may be connected to a control terminal G of a power device PT as shown in Fig. 1 to drive the power device PT. Fig. 1 is a circuit diagram showing the configuration of the semiconductor device 1.

[0010] The power device PT is connected to a load LD that operates with a relatively large current, and is used to switch the load LD. The load LD may include a resistive component LDa and an inductive component LDb. For example, the load LD may be a part of a DC motor and its drive circuit (e.g., an H-bridge circuit), and the power device PT may be another part of the drive circuit. Alternatively, the load LD may be a part of an AC motor and its drive circuit (e.g., an inverter circuit), and the power device PT may be another part of the drive circuit.

[0011] The power device PT may be any device capable of handling a relatively large current. The power device PT may be an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or a bipolar transistor. The substrate used in the element structure of the power device PT may be a SiC substrate or a Si substrate.

[0012] When a fault such as a short circuit occurs in the load LD, an overcurrent may flow through the power device PT. In order to protect the power device PT from an overcurrent, it is effective to detect when an overcurrent starts to flow through the power device PT and perform a protective operation to turn off the power device PT accordingly. The start of an overcurrent flowing through the power device PT can be detected by detecting DESAT (hereinafter referred to as DESAT detection).

[0013] DESAT can be defined as shown in Figure 2. Figure 2 is a diagram for explaining DESAT.

[0014] For example, when the power device PT is an N-type IGBT, one end of the power device PT is a collector C, the other end is an emitter E, and the control terminal is a gate G, as shown in FIG. 2(a).

[0015] As shown in Figure 2(b), the power device PT operates with a voltage V between the gate G and emitter E. CE When the voltage V between the collector C and the emitter E exceeds a certain value and turns on, in the region RG1, CE As the current I flows from collector C to emitter E, C In the higher voltage region RG2, the voltage V CE With increasing current I C will increase gradually.

[0016] As shown by the white arrow in Figure 2(b), the current I C The current I C The transition to the region RG2, where the transition is gradual, is called DESAT. Region RG1 is sometimes called the saturation region. Region RG2 is sometimes called the active region.

[0017] In addition, when the power device PT is a P-type IGBT, the polarity of the voltage between the gate G and emitter E that is turned on is reversed, and the collector current flows in the direction from the emitter E to the collector C, except that the power device PT is the same as when it is an N-type IGBT.

[0018] Alternatively, when the power device PT is an N-type power MOSFET, one end of the power device PT is a drain D, the other end is a source S, and the control terminal is a gate G, as shown in FIG. 2(c).

[0019] As shown in Figure 2(d), the power device PT has a gate G-source S voltage V GS When the voltage V between the drain D and source S exceeds a certain value and turns on, in the region RG11, DS As the current I of the drain D increases D In the higher voltage region RG12, the voltage V DS With increasing current I D will increase gradually.

[0020] As shown by the white arrow in Fig. 2(d), the current I DThe current I D The transition to the region RG12 where the slope is gentle is called DESAT. The region RG11 is sometimes called the linear region. The region RG12 is sometimes called the saturation region.

[0021] When the power device PT is a P-type power MOSFET, the polarity of the voltage between the gate G and source S that is turned on is reversed, and the drain current flows in the direction from the source S to the drain D. Except for this, the power device PT is the same as when it is an N-type power MOSFET.

[0022] Although not shown, if the power device PT is a bipolar transistor, one end of the power device PT is the collector, the other end is the emitter, and the control terminal is the base. The transition from the region where the current at both ends is steep to the region where the current at both ends is gentle is called DESAT.

[0023] The following explanation focuses on the case where the power device PT is an N-type power MOSFET. One end, the other end, and the control terminal of the power device PT are represented by D, S, and G, respectively. The following explanation can also be applied to cases where the power device PT is of other types.

[0024] The semiconductor device 1 shown in Fig. 1 has input nodes 1a to 1c and an output node 1d. The input node 1a is connected to the outside (for example, a higher-level controller) and receives an input signal INPUT from the outside. The input node 1b is connected to one end D of the power transistor PT and one end of the load LD. The input node 1c is connected to one end D of the power transistor PT and one end of the load LD. The output node 1d is connected to a control terminal G of the power transistor PT.

[0025] The power device PT has one end D connected to the input nodes 1b, 1c of the semiconductor device 1 and one end of the load LD, the other end S connected to the ground potential GND, and a control terminal G connected to the output node 1d of the semiconductor device 1.

[0026] The semiconductor device 1 includes a semiconductor integrated circuit 2 and a rectifier D DESAT , capacitance element C DESAT , resistor element R DESAT , rectifier D DET , resistor element R DET has.

[0027] The semiconductor integrated circuit 2 may be configured as a single chip, or may be configured by dividing it into multiple chips. The semiconductor integrated circuit 2 is provided with a terminal INPUT, a terminal VDDET, a terminal DESAT, and a terminal GATE_DRIVE.

[0028] Rectifier D DESAT is connected between the terminal DESAT and one end D of the power device PT. DESAT The direction from the terminal DESAT to the terminal D is the forward direction. DESAT may be a diode.

[0029] Capacitive element C DESAT One end is connected to the terminal DESAT and the rectifier element D DESAT and the other end is connected to the ground potential. DESAT The capacitance value of the capacitance element C can be determined in advance according to the operating characteristics required for the protection circuit 4. DESAT The capacitance value of the capacitance element C required for DESAT detection of the power device PT is DESAT may be predetermined depending on the charging characteristics of the current source 43 (eg, the RC time constant or the charging time by the current source 43).

[0030] Resistance element R DESAT terminal DESAT and rectifier element D DESAT A resistor element R DESAT The resistance value of the resistor element R can be determined in advance according to the characteristics required for the protection circuit 4. DESAT The resistance value of the resistor element R can be determined in advance depending on the operating characteristics required for the protection circuit 4. DESAT The resistance value of the capacitance element C required for DESAT detection of the power device PT DESAT This can be predetermined depending on the charging characteristics (eg, RC time constant) of the battery.

[0031] Rectifier D DET is connected between the terminal VDDET and one end D of the power device PT. DET The forward direction of the rectifier is from the terminal VDDET to the terminal D. DET may be a diode.

[0032] Resistance element R DET is the terminal VDDET and the rectifier D DET A resistor element R DET The resistance value of the resistor element R can be determined in advance according to the operating characteristics required for the detection circuit 3. DET The resistance value of the resistor element R required to detect the falling edge of the voltage at one end D of the power device PT is DET The resistance characteristics (eg, transient current limiting) of the resistors may be predetermined.

[0033] The semiconductor integrated circuit 2 includes a detection circuit 3, a protection circuit 4, and a drive circuit 5.

[0034] The detection circuit 3 is connected between the terminal INPUT, the protection circuit 4, and the terminal VDDET. The detection circuit 3 is capable of detecting a falling edge of the voltage at one end D of the power device PT via the terminal VDDET. When the detection circuit 3 detects a falling edge of the voltage at one end D, it generates a signal for enabling the protection circuit 4 and supplies the signal to the protection circuit 4.

[0035] The detection circuit 3 includes a comparison circuit 31, a voltage source 32, a current source 33, a capacitance element , a switch 35, and a control unit (signal generation circuit) .

[0036] The comparison circuit 31 has an input node 31a, an input node 31b, and an output node 31c. The input node 31a is connected to a terminal VDDET, a resistor element R DET and rectifier D DET to one end D of the power device PT via an input node 31b. The input node 31b is connected to a voltage source 32. The output node 31c is connected to the control unit .

[0037] The voltage source 32 has one end connected to the input node 31b of the comparison circuit 31 and the other end connected to the ground potential. The voltage source 32 may be a constant voltage source, and generates a reference voltage corresponding to the threshold voltage Vth1. The threshold voltage Vth1 is a voltage V D This corresponds to the falling edge of the waveform (see Figure 3).

[0038] For example, the comparator circuit 31 detects the voltage V VDDET is compared with the threshold voltage Vth1.

[0039] When input node 31a is a non-inverting input node and input node 31b is an inverting input node, comparison circuit 31 detects a voltage V VDDET is higher than the threshold voltage Vth1, the comparison result is output as a H level, and the voltage V VDDET If is lower than the threshold voltage Vth1, the comparison result is output at L level.

[0040] When input node 31a is an inverting input node and input node 31b is a non-inverting input node, comparison circuit 31 detects a voltage V VDDET is higher than the threshold voltage Vth1, the comparison result is output at L level, and the voltage V VDDET If is lower than the threshold voltage Vth1, the comparison result of H level is output.

[0041] The current source 33 has one end connected to a power supply potential and the other end connected to a node between the input node 31a of the comparison circuit 31 and the terminal VDDET. The current source 33 may be a constant current source and is capable of supplying a constant current to the capacitive element 34. The constant current supplied by the current source 33 can be determined in advance according to the operating characteristics required for the detection circuit 3. The constant current supplied by the current source 33 can be determined in advance according to the charging characteristics of the capacitive element 34 required for detecting the falling edge of the voltage at one end D of the power device PT.

[0042] The capacitive element 34 has one end connected to a node between the input node 31a of the comparison circuit 31 and the terminal VDDET, and the other end connected to a ground potential. The capacitance value of the capacitive element 34 can be determined in advance according to the operating characteristics required for the detection circuit 3. The capacitance value of the capacitive element 34 can be determined in advance according to the charging characteristics of the capacitive element 34 required for detecting the falling edge of the voltage at one end D of the power device PT.

[0043] The switch 35 is connected between one end of the capacitive element 34 and the ground potential. One end of the switch 35 is connected to a node between the input node 31a of the comparison circuit 31 and the terminal VDDET, the other end is connected to the ground potential, and a control terminal is connected to the control unit 36.

[0044] When switch 35 receives a control signal MASK1 of a non-active level (for example, L level) from control unit 36, it turns off to disconnect one end of capacitance element 34 from ground potential and make capacitance element 34 chargeable. When switch 35 receives a control signal MASK1 of an active level (for example, H level) from control unit 36, it turns on to connect one end of capacitance element 34 to ground potential, draws charge from one end of capacitance element 34, sets input node 31a of comparison circuit 31 to ground potential, and disables the function of the detection circuit.

[0045] The control unit 36 ​​has an input node 36 a connected to the terminal INPUT, an input node 36 b connected to the comparison circuit 31 , an output node 36 d connected to the switch 35 , and an output node 36 e connected to the protection circuit 4 .

[0046] The control unit 36 ​​generates a control signal MASK in response to the input signal INPUT and supplies the control signal MASK to the switch 35 .

[0047] The control unit 36 ​​generates a control signal EN_DESAT for enabling the protection circuit 4 in response to the inversion of the comparison result of the comparison circuit 31, and supplies the control signal EN_DESAT to the protection circuit 4.

[0048] When the input node 31a of the comparison circuit 31 is a non-inverting input node and the input node 31b is an inverting input node, the control unit 36 ​​supplies a non-active level control signal EN_DESAT to the protection circuit 4 during a period TP1 in which the comparison circuit 31 outputs an H-level comparison result. The control unit 36 ​​supplies an active level control signal EN_DESAT to the protection circuit 4 during a period TP2 in which the comparison circuit 31 outputs an L-level comparison result.

[0049] When the input node 31a of the comparison circuit 31 is an inverting input node and the input node 31b is a non-inverting input node, the control unit 36 ​​supplies a non-active level control signal EN_DESAT to the protection circuit 4 during a period TP11 in which the comparison circuit 31 outputs an L level comparison result. The control unit 36 ​​supplies an active level control signal EN_DESAT to the protection circuit 4 during a period TP12 in which the comparison circuit 31 outputs an H level comparison result.

[0050] The protection circuit 4 is connected between the terminal INPUT, the detection circuit 3, the drive circuit 5, and the terminal DESAT. The protection circuit 4 can detect the DESAT of the power device PT via the terminal DESAT. When the protection circuit 4 detects the DESAT of the power device PT, it supplies a signal OFF_CTR to the drive circuit 5 to instruct the drive circuit 5 to shut down the power device PT.

[0051] The protection circuit 4 includes a comparison circuit 41, a voltage source 42, a current source 43, a switch 45, a filter 47, and a control unit (signal generating circuit) 46.

[0052] The comparison circuit 41 has an input node 41a, an input node 41b, and an output node 41c. The input node 41a is connected to a terminal DESAT, a resistor element R DESAT and rectifier D DESAT The input node 41b is connected to one end D of the power device PT via a filter 47. The input node 41b is connected to a voltage source 42. The output node 41c is connected to the control unit 46 via a filter 47.

[0053] The filter 47 is connected between the comparator circuit 41 and the control unit 46. The filter 47 rejects a short pulse signal when the comparison result of the comparator circuit 41 is erroneously determined, and supplies the same to the control unit 46.

[0054] The voltage source 42 has one end connected to the input node 41b of the comparison circuit 41 and the other end connected to the ground potential. The voltage source 42 may be a constant voltage source, and generates a reference voltage corresponding to the threshold voltage Vth2. The threshold voltage Vth2 is a voltage V D This corresponds to the rising edge of the waveform (see Figure 3).

[0055] For example, the comparator circuit 41 detects the voltage V DESAT is compared with the threshold voltage Vth2.

[0056] When the input node 41a is a non-inverting input node and the input node 41b is an inverting input node, the comparison circuit 41 detects a voltage V DESAT is higher than the threshold voltage Vth2, the comparison result of the H level is output, and the voltage V DESAT If is lower than the threshold voltage Vth2, the comparison result of the L level is output.

[0057] When the input node 41a is an inverting input node and the input node 41b is a non-inverting input node, the comparison circuit 41 detects a voltage V DESAT is higher than the threshold voltage Vth2, the comparison result of the L level is output, and the voltage V DESAT If is lower than the threshold voltage Vth2, the comparison result of the H level is output.

[0058] The current source 43 has one end connected to a power supply potential and the other end connected to a node between the input node 41a of the comparison circuit 41 and the terminal DESAT. The current source 43 may be a constant current source, and supplies a constant current to the capacitance element C via the terminal DESAT. DESAT The constant current supplied by the current source 43 can be determined in advance according to the operating characteristics required for the protection circuit 4. The constant current supplied by the current source 43 can be determined in advance according to the operating characteristics required for the protection circuit 4. DESATThe charging characteristic of the battery may be predetermined.

[0059] The switch 45 is a capacitance element C DESAT The switch 45 has one end connected to a node between the input node 41a of the comparison circuit 41 and the terminal DESAT, the other end connected to the ground potential, and a control terminal connected to the control unit 46.

[0060] When the switch 45 receives a control signal MASK2 of a non-active level (for example, L level) from the control unit 46, the switch 45 turns off to disconnect one end of the capacitance element 34 from the ground potential and make the capacitance element 34 chargeable. When the switch 45 receives a control signal MASK2 of an active level (for example, H level) from the control unit 46, the switch 45 turns on to connect one end of the capacitance element 34 to the ground potential and make the capacitance element 34 chargeable. K The charge is extracted from one end and discharged to the ground potential.

[0061] The control unit 46 has an input node 46a connected to the terminal INPUT, an input node 46b connected to the comparison circuit 41 via a filter 47, a control node 46c connected to the detection circuit 3, an output node 46d connected to the switch 45, and an output node 46e connected to the drive circuit 5.

[0062] The control unit 46 generates a control signal OFF_CTR instructing the drive circuit 5 to shut down the power device PT in response to an inversion of the comparison result of the comparator circuit 41.

[0063] When the input node 41a of the comparison circuit 41 is a non-inverting input node and the input node 41b is an inverting input node, the control unit 46 supplies an active-level control signal OFF_CTR to the drive circuit 5 during a period TP21 in which the comparison circuit 41 outputs an H-level comparison result. The control unit 46 supplies a non-active-level control signal OFF_CTR to the drive circuit 5 during a period TP22 in which the comparison circuit 41 outputs an L-level comparison result.

[0064] When the input node 41a of the comparison circuit 41 is an inverting input node and the input node 41b is a non-inverting input node, the control unit 46 supplies an active-level control signal OFF_CTR to the drive circuit 5 during a period TP11 in which the comparison circuit 41 outputs an L-level comparison result. The control unit 46 supplies a non-active-level control signal OFF_CTR to the drive circuit 5 during a period TP12 in which the comparison circuit 41 outputs an H-level comparison result.

[0065] The drive circuit 5 has an input node 5a, an output node 5b, and a control node 5c. The input node 5a is connected to a terminal INPUT. The output node 5b is connected to a control terminal G of the power transistor PT. The control node 5c is connected to the protection circuit 4.

[0066] While the drive circuit 5 is receiving the control signal Shutdown at a non-active level, it generates a drive signal DRV for switching in response to the input signal IN and supplies the drive signal DRV to the control terminal G of the power transistor PT. This allows the switching of the power transistor PT to be controlled.

[0067] When the drive circuit 5 receives the active-level control signal Shutdown, it generates a drive signal DRV to maintain the power transistor PT in the off state regardless of the input signal IN, and supplies the drive signal DRV to the control terminal G of the power transistor PT. This maintains the power transistor PT in the off state. This allows the power transistor PT to be protected from an overcurrent generated in the load LD.

[0068] In the semiconductor device 1 shown in Fig. 1, DESAT detection is performed during a period from timing t4 to t8 as shown in Fig. 3. Fig. 3 is a waveform diagram showing the operation of the semiconductor device 1.

[0069] In the period from timing t4 to t8, the protection circuit 4 is enabled, and DESAT detection by the protection circuit 4 is enabled. The DESAT detection period (t4 to t8) is within the period from timing t4 to t10 in which the power device PT is in the ON state.

[0070] In the DESAT detection, in response to an excessive current flowing into the power device PT in the ON state, the protection circuit 4 detects the voltage V D In FIG. 3, during the period from timing t4 to t8, the voltage V D is maintained below the threshold voltage Vth2, and the voltage V D 10. An example is a case where an increase exceeding the threshold voltage Vth2 is not detected.

[0071] Although not shown, the voltage V D When an increase exceeding the threshold voltage Vth2 of the protection circuit 4 is detected, the protection circuit 4 transitions the control signal OFF_CTR to an active level and supplies it to the drive circuit 5. In response to this, the drive circuit 5 supplies the drive signal V GATE_DRIVE to a non-active level (for example, L level), and the power device PT is turned off. This performs the off control of the power device PT.

[0072] The timing when DESAT detection is enabled starts when the input signal INPUT becomes active (for example, H level), and the drive signal V GATE_DRIVE The timing t1 at which the driving signal V becomes active (for example, H level) is used as a trigger. GATE_DRIVE The period from timing t1 to t8 during which the signal is maintained at the active level is represented as an "ON control signal."

[0073] At this time, as shown in FIG. 3, the drive signal V GATE_DRIVE After the voltage V of the control terminal G becomes active, G The delay time Td1 according to the dead time until the voltage V starts to rise, G There is a delay time Td2 corresponding to the switching time from when the potential starts to rise until the power device PT transitions to the on state.

[0074] Here, the dead time and switching time are measured in advance, and the delay time from the trigger timing t1 to the start timing of "DESAT valid" (= dead time + switching time) is set as the blanking time T BLANK It is conceivable to experimentally determine in advance and set it in the protection circuit 4 as a fixed value.

[0075] For example, in the protection circuit 4, a blanking time T BLANK A predetermined value corresponding to the time t1 may be set. In this case, immediately before timing t1, the protection circuit 4 sets the count value of the timer 461 to an initial value and sets the control signal MASK2 to an active level. When the protection circuit 4 detects a rising edge of the waveform of the input signal INPUT, it starts the counting operation of the timer 461, and when the count value reaches a predetermined value, it sets the control signal MASK2 to a non-active level to turn off the switch 45, thereby enabling DESAT detection.

[0076] However, of the dead time and the switching time, at least the switching time tends to vary due to manufacturing variations in the power devices PT, the effects of environmental temperature, and the like.

[0077] Fixed blanking time T BLANK is longer than the actual "dead time + switching time", the power device PT transitions to the on state and the blanking time T BLANK During this period, if an excessive current flows into the power device PT in the on state, the power device PT may be damaged. In other words, it may be difficult to perform DESAT detection properly.

[0078] Fixed blanking time T BLANK is shorter than the actual "dead time + switching time", the power device PT is in the off state but the blanking time T BLANKDuring this period, even though no excessive current flows into the power device PT, the power device PT is in the off state, so the voltage V at one end D D If the threshold voltage Vth is exceeded, it may be erroneously detected that DESAT has occurred, which may make it difficult to properly perform DESAT detection.

[0079] For this reason, in the semiconductor device 1, the voltage V D The falling edge of the signal is detected by the detection circuit 3, and the protection circuit 4 is made to enable DESAT detection in accordance with the detection timing, thereby optimizing the timing at which DESAT is enabled.

[0080] For example, immediately before timing t1, the detection circuit 3 sets the control signal MASK1 to an active level and keeps the switch 35 in the on state. This disables the detection of the falling edge of the waveform by the detection circuit 3. The detection circuit 3 sets the control signal EN_DESAT to a non-active level. The protection circuit 4 sets the control signal MASK2 to an active level and keeps the switch 45 in the on state. This disables the DESAT detection by the protection circuit 4.

[0081] At timing t1, when the rising edge of the waveform of the input signal INPUT is detected, the drive circuit 5 generates the drive signal V GATE_DRIVE to the active level.

[0082] Furthermore, when detecting a rising edge of the waveform of the input signal INPUT, the detection circuit 3 sets the control signal MASK1 to a non-active level to turn off the switch 35. In response to this, the detection circuit 3 detects the voltage V D That is, the detection circuit 3 detects the falling edge of the voltage V D The falling edge of the waveform can now be detected.

[0083] At this time, the power device PT is off, and the voltage VD is maintained at a predetermined level (for example, H level). In response to this, the rectifying element D DET is cut off, the current of the current source 33 charges the capacitance element 34, the voltage of the terminal VDDET becomes higher than the threshold voltage Vth1, and the comparison result V 31 Until the control signal EN_DESAT of an active level arrives from the detection circuit 3, the protection circuit 4 sets the control signal MASK2 to an active level and maintains the switch 45 in an on state. Therefore, the voltage of the terminal DESAT is lower than the threshold voltage Vth2, and the comparison result V of the comparison circuit 41 is 41 is at L level.

[0084] At time t2, the voltage V of the control terminal G G begins to rise, and in response, the power device PT begins to turn on. At timing t3, the voltage V D begins to fall.

[0085] At time t4, the voltage V at one end D D When the comparison result V 31 In other words, the detection circuit 3 detects the voltage V D In response to this, the detection circuit 3 sets the control signal EN_DESAT to an active level and supplies it to the protection circuit 4.

[0086] In response to the control signal EN_DESAT at an active level, the protection circuit 4 sets the control signal MASK2 to a non-active level and turns off the switch 45. In response to this, the protection circuit 4 enables DESAT detection. That is, the protection circuit 4 is in a state where it can detect DESAT of the power device PT. In FIG. 3, the blanking period from timing t1 to t4 is denoted as "Blanking".

[0087] At timing t5 immediately thereafter, the transition of the power device PT to the on state is completed.

[0088] At time t7, the voltage V of the control terminal G G reaches a predetermined level (eg, H level) and is maintained there.

[0089] At timing t8, when the falling edge of the waveform of the input signal INPUT is detected, the drive circuit 5 outputs the drive signal V GATE_DRIVE In Figure 3, the drive signal V GATE_DRIVE The period from timing t1 to t8 during which the signal is maintained at the active level is referred to as an "ON control signal."

[0090] Furthermore, upon detecting a falling edge of the waveform of the input signal INPUT, the detection circuit 3 sets the control signal MASK1 to an active level and turns on the switch 35. This again disables detection of falling edges of the waveform by the detection circuit 3. The detection circuit 3 sets the control signal EN_DESAT to a non-active level and supplies it to the protection circuit 4. The protection circuit 4 sets the control signal MASK2 to an active level and turns on the switch 45. This again disables DESAT detection by the protection circuit 4. In FIG. 3, the period from timing t4 to t8 during which DESAT detection is enabled is denoted as "DESAT enabled".

[0091] At timing t9, the voltage V of the control terminal G G begins to fall, and in response, at timing t10 ​​immediately thereafter, the power device PT begins to turn off, and the voltage V D starts to rise. In Fig. 3, the period from timing t5 to t10 during which the power device PT is maintained in the ON state is represented as "power device ON state."

[0092] At timing t11, the voltage V at one end D D reaches a predetermined level (eg, H level) and is maintained there.

[0093] At the subsequent timing t12, the voltage V of the control terminal G G falls to a reference level (for example, L level), and the transition of the power device PT to the off state is completed.

[0094] As shown in FIG. 3, the timing of the transition of the power device PT to the on state is determined by the voltage V D This is the timing to enable DESAT detection, and is determined from the detection result of the falling edge of the waveform of the power device PT. This makes it possible to end the blanking time and start enabling DESAT detection at a timing close to the completion of the transition to the on state of the power device PT, without being affected by the manufacturing variation or temperature dependency of the power device PT.

[0095] As described above, in the semiconductor device 1 according to the embodiment, the voltage V D The falling edge of the signal is detected by the detection circuit 3, and the protection circuit 4 enables DESAT detection according to the detection timing. This makes it possible to optimize the timing at which DESAT is enabled. Also, there is no need to design a margin for the timing at which DESAT detection is enabled in the system, which reduces the system design load and enables the system design to be QTAT.

[0096] 1, the capacitance element 34 may be omitted. In this case, the current source 33 charges the parasitic capacitance of the line connecting the comparison circuit 31 and the terminal VDDET with its current.

[0097] In the semiconductor device 1 shown in FIG. DESAT may be omitted. In this case, the current source 43 of the protection circuit 4 charges the parasitic capacitance of the line connecting the comparison circuit 41 and the terminal DESAT with its current.

[0098] 1 sets the control signal MASK2 to an active level in response to the control signal EN_DESAT received from the detection circuit 3 without using the timer 461. For this reason, the timer 461 may be omitted in the control unit 46.

[0099] (First Modification of the Embodiment) In addition, the voltage V at one end D of the power device PTD When DESAT detection is enabled by detecting the falling edge of D Therefore, the voltage V at one end D may not fall. D A history of the time when the signal falls may be recorded, and DESAT detection may be enabled based on the history of the time.

[0100] In the semiconductor device 1i, the detection circuit 3i of the semiconductor integrated circuit 2i may have a control unit 36i instead of the control unit 36 ​​(see FIG. 1) as shown in Fig. 4. Fig. 4 is a diagram showing a configuration of the semiconductor device 1i according to a first modified example of the embodiment. The control unit 36i has a time history generating unit 361i.

[0101] In the control unit 36i, the time history generating unit 361i calculates the comparison result V 31 The time history generating unit 361i measures the time until the input signal INPUT is inverted and holds the measured time Δt. The time history generating unit 361i generates a control signal EN_DESAT for enabling the protection circuit 4 and supplies it to the protection circuit 4 in response to the passage of a predetermined time period corresponding to the time Δt (see FIG. 3) measured from the rising edge of the waveform of the input signal INPUT. The predetermined time period is calculated by multiplying the history time Δt by an offset time t offset The offset time t offset Any time greater than 0 may be used.

[0102] The time history generating unit 361i may be configured as shown in Fig. 5. Fig. 5 is a circuit diagram showing the configuration of the time history generating unit 361i in a first modified example of the embodiment.

[0103] The time history generating unit 361i includes a counter 361i1, a latch circuit 361i2, an adder 361i3, a setting circuit 361i4, and a timer 361i5.

[0104] The counter 361i1 has a node S connected to the terminal INPUT and a node S of the counter 361i1, a node E connected to the comparator circuit 31, and a node O connected to a node D of the latch circuit 36ii2. D Count the fall time of the voltage V at one end D. D The fall time is the time from the transition of the input signal INPUT from L level to H level to the voltage V D That is, the counter 361i1 starts counting in response to the rising edge of the input signal INPUT received at the node S, and the comparison result V of the comparator circuit 31 received at the node E 31 The counter 361i1 ends the counting operation in response to an inversion of the signal. The counter 361i1 outputs the count value to the latch circuit 361i2. The count value indicates the time Δt measured by the counter 361i1.

[0105] In the latch circuit 361i2, a node CK is connected to a terminal INPUT, and a node Q is connected to an adder 361i3. The voltage VD fall time at one end counted by the counter 361i1 is held in the latch circuit 361i2 at the transition timing of the input signal INPUT from H level to L level. That is, the latch circuit 361i2 latches the count value of the counter 361i1 in response to the fall of the input signal INPUT received at the node CK, and outputs the latched value from the node Q to the adder 361i3.

[0106] The setting circuit 361i4 has an output node connected to the adder 361i3. The setting circuit 361i4 sets the offset time t offset The setting circuit 361i4 sets the offset time t offset The adder 361i3 outputs a value indicating this.

[0107] The adder 361i3 has a first input node connected to the latch circuit 361i2, a second input node connected to the setting circuit 361i4, and an output node connected to a node E of the timer 361i5. The adder 361i3 calculates the latched value (i.e., a value indicating the measured time Δt) and the offset time toffset The value indicating the sum is added to the value indicating the sum, and the value of the sum is output to the timer 361i5. The value of the sum is offset Shows.

[0108] The timer 361i5 has a node O connected to the protection circuit 4. The timer 361i5 receives the value of the addition result at a node G. In a reset state, the timer 361i5 outputs a non-active level control signal EN_DESAT from the node O to the protection circuit 4. The timer 361i5 starts counting in response to the rising edge of the input signal INPUT received at a node S, and when the count value reaches the value of the addition result received at node G, it ends the counting operation and transitions the control signal EN_DESAT to an active level to supply it to the protection circuit 4.

[0109] For example, the time history generating unit 361i may operate as shown in Fig. 6. Fig. 6 is a waveform diagram showing the operation of the time history generating unit 361i in the first modified example of the embodiment.

[0110] At timing t21, the counter 361i1 of the time history generating unit 361i starts counting the time Δt in response to the rising edge of the input signal INPUT. The timer 361i5 starts counting the time (Δt0+t offset ) count operation is started. Δt0 is the time measured previously as Δt. The comparison circuit 31 starts counting the comparison result V 31 starts outputting.

[0111] At timing t22, the counter 361i1 receives the comparison result V 31 In response to the inversion of the signal from H level to L level, the count operation of the time Δt ends, and the count value of the measured time Δt=Δt1 is output to the latch circuit 361i2.

[0112] A predetermined time from timing t21 (Δt0+t offset At timing t23 after the lapse of a predetermined time (Δt0+toffset ) depending on the

[0113] Immediately thereafter, at timing t24, the timer 361i5 sets the control signal EN_DESAT to an active level and supplies it to the protection circuit 4. In response to this, in the protection circuit 4, DESAT is enabled.

[0114] At timing t25, the latch circuit 361i2 latches the count value of the counter 361i1 in response to the falling edge of the input signal INPUT, and starts outputting the latched value to the adder 361i3. In response to this, the adder 361i3 starts outputting a value obtained by adding an offset to the latched value. The value resulting from the addition by the adder 361i3 is output to the timer 361i5, and is set as the value to be counted by the timer 361i5.

[0115] In response to the falling edge of the input signal INPUT, the timer 361i5 sets the control signal EN_DESAT to a non-active level and supplies it to the protection circuit 4. In response to this, in the protection circuit 4, DESAT is disabled.

[0116] At timing t26, the counter 361i1 of the time history generating unit 361i starts counting the time Δt in response to the rising edge of the input signal INPUT. The timer 361i5 starts counting the time (Δt1+t offset ) count operation is started. Δt1 is the time measured previously as Δt. The comparison circuit 31 starts counting the comparison result V 31 starts outputting.

[0117] At timing t27, the counter 361i1 receives the comparison result V 31 In response to the inversion of the signal from H level to L level, the count operation of the time Δt ends, and the count value of the measured time Δt=Δt2 is output to the latch circuit 361i2.

[0118] A predetermined time from timing t26 (Δt1+t offsetAt timing t28 after the lapse of a predetermined time (Δt1+t offset ) depending on the

[0119] Immediately thereafter, at timing t29, the timer 361i5 sets the control signal EN_DESAT to an active level and supplies it to the protection circuit 4. In response to this, in the protection circuit 4, DESAT is enabled.

[0120] At timing t30, the latch circuit 361i2 latches the count value of the counter 361i1 in response to the falling edge of the input signal INPUT, and starts outputting the latched value to the adder 361i3. In response to this, the adder 361i3 starts outputting a value obtained by adding an offset to the latched value. The value resulting from the addition by the adder 361i3 is output to the timer 361i5, and is set as the value to be counted by the timer 361i5.

[0121] In response to the falling edge of the input signal INPUT, the timer 361i5 sets the control signal EN_DESAT to a non-active level and supplies it to the protection circuit 4. In response to this, in the protection circuit 4, DESAT is disabled.

[0122] In this manner, in the semiconductor device 1i, the detection circuit 3i detects the voltage V D The detection circuit 4 keeps a history of the time when the falling edge of the signal is detected, and enables DESAT detection based on the past time history. For example, the detection circuit 4 enables DESAT detection using a predetermined time obtained by adding an offset to offset, which takes fluctuations into consideration, to the immediately preceding measured time Δt. This also makes it possible to optimize the start timing of DESAT enablement.

[0123] (Second Modification of the Embodiment) Alternatively, the operation of the embodiment and the operation of the first modification may be combined with respect to the start timing of "DESAT enabled" at which DESAT detection is possible. For example, the start timing of "DESAT enabled" may be determined by determining whether or not the voltage VD at one end D of the power transistor PT falls and whether or not a predetermined time (Δt+t offset ) has elapsed, whichever is earlier.

[0124] In this case, in the semiconductor device 1j, the detection circuit 3j of the semiconductor integrated circuit 2j may have a control unit 36j instead of the control unit 36i (see FIG. 4) as shown in Fig. 7. Fig. 7 is a diagram showing a configuration of a semiconductor device 1j according to a second modified example of the embodiment.

[0125] The control unit 36j receives the comparison result V 31 or the input signal INPUT waveform rises after a certain time (Δt+t offset ) has elapsed, the control unit 36j generates a control signal EN_DESAT for enabling the protection circuit 4. For example, the control unit 36j generates the control signal EN_DESAT for enabling the protection circuit 4 in response to the comparison result V 31 The timing at which the input signal INPUT is inverted and the time from the rising edge of the input signal INPUT waveform (Δt+t offset ) has elapsed, whichever is earlier. In this case, the control signal EN_DESAT for enabling the protection circuit 4 may be generated.

[0126] The control unit 36j may further include an operator 362j. The operator 362j has a first input node connected to the output node 31c of the comparison circuit 31, a logical inversion of a second input node connected to the output node of the time history generation unit 361i, and an output node connected to the protection circuit 4.

[0127] The logical sum operator 362j is the comparison result V 31The control signal EN_DESAT is generated as a result of the operation by calculating the logical inversion of the voltage VD at one end D of the power transistor PT and the logical sum of the control signal EN_DESAT (see FIG. 5) output by the time history generating unit 361i. offset ), whichever is earlier. As a result, the start timing of "DESAT enabled" is determined based on the time between the falling edge of the voltage VD at one end D of the power transistor PT and the predetermined time (Δt+t offset ) whichever is earlier.

[0128] In this manner, in the semiconductor device 1j, the detection circuit 3j detects the comparison result V 31 or the input signal INPUT waveform rises after a certain time (Δt+t offset ) has elapsed, the control signal EN_DESAT for enabling the protection circuit 4 is generated. This also makes it possible to optimize the timing for starting to enable DESAT.

[0129] (Third Modification of the Embodiment) The semiconductor device 1k may have a simplified configuration as shown in Fig. 8. Fig. 8 is a diagram showing the configuration of a semiconductor device 1k according to a third modified example of the embodiment.

[0130] In the semiconductor integrated circuit 2k of the semiconductor device 1k, the detection circuit 3 and the protection circuit 4 (see FIG. 1) are merged to form a protection circuit 4k including the detection circuit 3k. The detection circuit 3k does not include the current source 33, the capacitive element 34, the switch 35, and the control unit 36. The protection circuit 4k has a control unit 46k instead of the control unit 46 (see FIG. 1).

[0131] The control unit 46k has an additional function of the control unit 36. When the comparison result of the comparison circuit 31 is inverted, the control unit 46k enables the protection circuit 4k, and enables DESAT detection by the protection circuit 4k.

[0132] The semiconductor device 1k also includes a capacitance element C DESAT (see FIG. 1) is omitted, and instead, the protection circuit 4k includes a capacitive element C DESAT1 is added. Capacitive element C DESAT1 The capacitance value of the capacitance element C required to detect the falling edge of the voltage at one end D of the power device PT is DESAT1 The charging characteristic of the battery may be predetermined.

[0133] In this manner, the protection circuit 4k including the detection circuit 3k is configured in the semiconductor integrated circuit 2k of the semiconductor device 1k, and the configuration is simplified. This allows the circuit scale of the semiconductor integrated circuit 2k to be reduced, thereby saving the space of the semiconductor device 1k and reducing the cost of the semiconductor device 1k.

[0134] In the configuration shown in FIG. DESAT1 may be omitted. In this case, the current source 43 of the protection circuit 4k charges the parasitic capacitance of the line connecting the comparison circuit 41 and the terminal DESAT with its current.

[0135] (Fourth Modification of the Embodiment) The configuration of the semiconductor device 1n may be simplified as shown in Fig. 9. Fig. 9 is a diagram showing the configuration of a semiconductor device 1n according to a fourth modified example of the embodiment.

[0136] In the semiconductor integrated circuit 2n of the semiconductor device 1n, the detection circuit 3i and the protection circuit 4 (see FIG. 4) are merged to form a protection circuit 4n including the detection circuit 3n. The detection circuit 3n does not include the current source 33, the capacitance element 34, the switch 35, and the control unit 36i. The protection circuit 4n has a control unit 46n instead of the control unit 46i (see FIG. 4).

[0137] The control unit 46n has the functions of the control unit 36i added thereto. The control unit 46n performs a process of detecting a rise in the waveform of the input signal INPUT after a predetermined time (Δt+t offsetFor example, the control unit 46n enables the protection circuit 4n in response to the passage of a predetermined time (Δt+t offset ) has elapsed. This puts the protection circuit 4n into a state in which it is possible to perform DESAT detection for the power transistor PT.

[0138] The semiconductor device 1n also includes a capacitance element C DESAT (see FIG. 1) is omitted, and instead, the protection circuit 4k includes a capacitive element C DESAT1 is added. Capacitive element C DESAT1 The capacitance value of the capacitance element C required to detect the falling edge of the voltage at one end D of the power device PT is DESAT1 The charging characteristic of the battery may be predetermined.

[0139] In this way, the protection circuit 4n including the detection circuit 3n is configured in the semiconductor integrated circuit 2n of the semiconductor device 1n, and the configuration is simplified. This allows the circuit scale of the semiconductor integrated circuit 2n to be reduced, thereby saving the space of the semiconductor device 1n and reducing the cost of the semiconductor device 1n.

[0140] In the configuration shown in FIG. DESAT1 may be omitted. In this case, the current source 43 of the protection circuit 4n charges the parasitic capacitance of the line connecting the comparison circuit 41 and the terminal DESAT with its current.

[0141] (Fifth Modification of the Embodiment) The configuration of the semiconductor device 1p may be simplified as shown in Fig. 10. Fig. 10 is a diagram showing the configuration of a semiconductor device 1p according to a fifth modified example of the embodiment.

[0142] In the semiconductor integrated circuit 2p of the semiconductor device 1p, the detection circuit 3j and the protection circuit 4 (see FIG. 7) are merged to form a protection circuit 4p including the detection circuit 3p. The detection circuit 3p does not include the current source 33, the capacitive element 34, the switch 35, and the control unit 36j. The protection circuit 4p has a control unit 46p instead of the control unit 46j (see FIG. 7).

[0143] The control unit 46p has the additional function of the control unit 36j. The control unit 46p detects whether the comparison result of the comparator circuit 31 is inverted or whether a predetermined time (Δt+t offset ) has elapsed, the control unit 46p enables the protection circuit 4p and enables DESAT detection by the protection circuit 4p. For example, the control unit 46p enables the protection circuit 4p when a predetermined time (Δt+t offset ), for example, the control unit 46p determines that the start timing of “DESAT effective” is the timing of the fall of the voltage VD of the one end D of the power transistor PT and the predetermined time (Δt+t offset ) whichever is earlier. This puts the protection circuit 4p into a state in which it is possible to perform DESAT detection for the power transistor PT.

[0144] The semiconductor device 1k also includes a capacitance element C DESAT (see FIG. 1) is omitted, and instead, the protection circuit 4k includes a capacitive element C DESAT1 is added. Capacitive element C DESAT1 The capacitance value of the capacitance element C required to detect the falling edge of the voltage at one end D of the power device PT is DESAT1 The charging characteristic of the battery may be predetermined.

[0145] In this manner, the protection circuit 4p including the detection circuit 3p is configured in the semiconductor integrated circuit 2p of the semiconductor device 1p, and the configuration is simplified. This allows the circuit scale of the semiconductor integrated circuit 2p to be reduced, thereby saving the space of the semiconductor device 1p and reducing the cost of the semiconductor device 1p.

[0146] In the configuration shown in FIG. DESAT1 may be omitted. In this case, the current source 43 of the protection circuit 4p charges the parasitic capacitance of the line connecting the comparison circuit 41 and the terminal DESAT with its current.

[0147] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0148] 1,1i,1j,1k,1n,1p semiconductor devices, 2,2i,2j,2k,2n,2p semiconductor integrated circuits, 3,3i,3j,3k,3n,3p detection circuits, 4,4k,4n,4p protection circuits.

Claims

1. a comparator circuit having a first input node connected to one end of the power device, a second input node connected to a threshold voltage corresponding to a falling edge of a waveform, and an output node; a signal generating circuit having a first input node connected to an output node of the comparison circuit and an output node connected to a control node of the power device protection circuit; A detection circuit comprising:

2. The signal generating circuit generates a control signal for enabling the protection circuit in response to an inversion of the comparison result of the comparator circuit.

2. The detection circuit of claim 1.

3. The signal generating circuit supplies the control signal at a non-active level to the protection circuit during a first period in which the comparator circuit outputs a first comparison result, and supplies the control signal at an active level to the protection circuit during a second period in which the comparator circuit outputs a second comparison result that is an inversion of the first comparison result.

3. The detection circuit of claim 2.

4. The signal generating circuit further includes a second input node connected to the input terminal.

2. The detection circuit of claim 1.

5. The signal generating circuit measures the time from the rising edge of the waveform of the input signal supplied to the input terminal to the inversion of the comparison result of the comparator, and generates a signal for enabling the protection circuit in response to the passage of a predetermined time corresponding to the measured time from the rising edge of the waveform of the input signal.

5. The detection circuit of claim 4.

6. The signal generating circuit generates a signal for enabling the protection circuit in response to an inversion of the comparison result of the comparator circuit or the lapse of the predetermined time from a rising edge of the waveform of the input signal.

6. The detection circuit according to claim 5.

7. A detection circuit according to any one of claims 1 to 6; a protection circuit having an input node connected to one end of a power device and a control node and an output node connected to an output node of the detection circuit; a drive circuit having an input node connected to an input terminal, a control node connected to an output node of the protection circuit, and an output node connected to a control terminal of the power device; A semiconductor integrated circuit comprising:

8. a drive circuit having an input node, a control node, and an output node connected to a control terminal of the power device; a first comparison circuit having a first input node connected to one end of the power device, a second input node connected to a first threshold voltage corresponding to a falling edge of a waveform, and an output node; a second comparator circuit having a first input node connected to one end of the power device, a second input node connected to a second threshold voltage corresponding to a rising edge of a waveform, and an output node; a signal generating circuit having a first input node connected to an output node of the first comparison circuit, a first output node, and a second output node connected to a control node of the drive circuit; A semiconductor integrated circuit comprising:

9. the semiconductor integrated circuit further includes a switch having a first node connected to the first input node of the second comparison circuit, a second node connected to a reference potential, and a control node; The signal generating circuit generates a signal for enabling a protection circuit in response to an inversion of a comparison result of the first comparing circuit.

9. The semiconductor integrated circuit according to claim 8.

10. the semiconductor integrated circuit further includes a switch having a first node connected to the first input node of the second comparison circuit, a second node connected to a reference potential, and a control node; The signal generating circuit measures the time from the rising edge of the waveform of the input signal to the drive circuit to the falling edge of the waveform of the voltage at one end of the power device, and generates a signal for enabling a protection circuit in response to the passage of a predetermined time corresponding to the measured time from the rising edge of the waveform of the input signal.

9. The semiconductor integrated circuit according to claim 8.

11. The signal generating circuit generates a signal for enabling the protection circuit in response to an inversion of a comparison result of the first comparing circuit or the lapse of the predetermined time from a rising edge of a waveform of the input signal. The semiconductor integrated circuit according to claim 10.

12. A semiconductor integrated circuit according to claim 7; a first rectifying element connected between a detection circuit and one end of the power device; a second rectifying element connected between a protection circuit and one end of the power device; A semiconductor device comprising:

13. A semiconductor integrated circuit according to any one of claims 8 to 11, a rectifying element connected between a first input node of the second comparison circuit and one end of the power device; A semiconductor device comprising:

14. comparing a voltage at one end of the power device with a threshold voltage; activating a protection circuit for the power device in response to a result of the comparison being inverted; A control method comprising:

15. measuring a time from a rising edge of a waveform of an input signal to a falling edge of a waveform of a voltage at one end of the power device in response to an inversion of a result of the comparison; The protection circuit is enabled by and activating the protection circuit in response to at least one of the inversion of the result of the comparison and the lapse of a predetermined time corresponding to the measured time from the rising edge of the waveform of the input signal. The control method according to claim 14.

Images