Semiconductor device

Abstract

To provide a semiconductor device capable of appropriately changing the voltage amplitude of a differential signal without using any resistor.SOLUTION: A semiconductor device includes a first upper and lower arm including a first switch element on a first potential side and a second switch element on a second potential side that is connected in series to the first switch element, a second potential being lower than a first potential, and outputting a first signal by the first switch element and the second switch element operating in a complementary manner, a second upper and lower arm including a third switch element on the first potential side arranged in parallel with the first upper and lower arm, and a fourth switch element on the second potential side that is connected in series to the third switch element, and generating and outputting a second signal whose potential changes complementarily with respect to the first signal by the third switch element and the fourth switch element operating in the complementary manner, and a voltage control circuit that is connected to the first upper and lower arm and the second upper and lower arm, and limits the voltage amplitude of the first signal and the second signal based on a bias voltage.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a driver circuit that uses an LVDS (Low Voltage Differential Signal) interface to achieve high-speed data transfer (see FIG. 1 of Patent Document 1). A pair of transmission lines that transmit differential signals to a receiving circuit is connected to the driver circuit. The pair of transmission lines is provided with resistors that are termination resistors for setting the voltage amplitude of the differential signals. When a current from a current source flows through the resistors, a potential difference occurs between the pair of transmission lines. In the prior art, the voltage amplitude of the differential signals is set by changing the value of the resistor or the value of the current source. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-031810 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional technology, a resistor provided on the receiving circuit side is used to set the voltage amplitude of the differential signal using a resistor provided outside the driver circuit, which may complicate the configuration of the system including the receiving circuit and reduce the yield. In addition, the resistor may hinder the need to shorten the manufacturing time of the system including the receiving circuit. In addition, simply changing the value of the current source on the driver circuit side without replacing the resistor may not provide an appropriate voltage amplitude of the differential signal. Thus, in the conventional technology, there is room for improvement in terms of appropriately changing the voltage amplitude of the differential signal.

[0005] In consideration of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can appropriately change the voltage amplitude of a differential signal without using a resistor. [Means for solving the problem]

[0006] In order to solve the above problems, the semiconductor device disclosed herein is an AC-coupled receiving circuit having a first input terminal for inputting a first signal transmitted via a first capacitive element and a second input terminal for inputting a second signal transmitted via a second capacitive element and having a potential that changes complementarily to the first signal, and is equipped with a signal output circuit that outputs a first logic signal corresponding to the potential of the first signal and a second logic signal corresponding to the potential of the second signal, and a signal supply circuit that supplies a first guarantee signal of a potential corresponding to the value of the first logic signal to the first input terminal as a signal that guarantees the potential of the first signal, and supplies a second guarantee signal of a potential that changes complementarily to the first guarantee signal to the second input terminal as a signal that guarantees the potential of the second signal. Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a semiconductor device that can appropriately change the voltage amplitude of a differential signal without using a resistor. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a configuration of a display device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram illustrating a configuration of a communication system according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is a diagram illustrating a configuration of a transmission circuit according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a timing chart for explaining the operation of the transmission circuit. [Diagram 5] FIG. 5 is a diagram showing a configuration of a transmission circuit according to a first modified example. [Figure 6] FIG. 6 is a diagram showing a configuration of a transmission circuit according to the second modified example. [Figure 7]FIG. 7 is a timing chart for explaining the operation of the transmission circuit according to the second modified example. [Figure 8] FIG. 8 is a diagram showing a configuration of a transmission circuit according to the third modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and the description thereof will be omitted as appropriate.

[0010] [Embodiment] (display device) 1 is a diagram showing a configuration of a display device according to an embodiment of the present disclosure. The display device 100 may be interpreted as a vehicle display device mounted on an automobile or the like. The display device 100 includes a display panel 10, a timing controller 11, a driver IC (Integrated Circuit) 12, and a gate driver 13.

[0011] The display panel 10 may be construed as an image display device such as a liquid crystal display panel or an organic EL (Electro Luminescence) panel.

[0012] The timing controller 11 may control the display timing of an image on the display panel 10 by controlling a plurality of driver ICs 12 and a gate driver 13. The timing controller 11 may generate a clock signal and supply it to the driver ICs 12. The timing controller 11 may supply a scanning control signal synchronized with video data to the gate driver 13. The timing controller 11 may be interpreted as a semiconductor device including a transmission circuit described later. The transmission circuit may be interpreted as a driver circuit.

[0013] The driver IC 12 may control the lighting state of a plurality of light-emitting elements provided in the display panel 10. The gate driver 13 may generate a gate signal based on a signal supplied from the timing controller 11 and supply the gate signal to the display panel 10.

[0014] The timing controller 11 and the driver IC 12 may constitute a communication system 200. The communication system 200 may be interpreted as a system to which mini-LVDS is applied.

[0015] Next, a configuration of a communication system 200 will be described with reference to Fig. 2. Fig. 2 is a diagram showing a configuration of a communication system according to an embodiment of the present disclosure. The communication system 200 includes a timing controller 11 and a signal output circuit 12. The timing controller 11 and the signal output circuit 12 are communicatively connected via a transmission path 20.

[0016] The timing controller 11 includes a transmission circuit 111. The transmission circuit 111 may be interpreted as a semiconductor device that outputs a differential signal 23. The transmission circuit 111 may be interpreted as a circuit that transmits data using the differential signal 23. The transmission circuit 111 may be applied to devices other than the timing controller 11.

[0017] The differential signal 23 includes two signals that change in a complementary manner. Specifically, the differential signal 23 includes a first signal 24 transmitted via a first capacitive element 21 arranged on the transmission line 20, and a second signal 25 transmitted via a second capacitive element 22 arranged on the transmission line 20. The second signal 25 may be interpreted as a signal whose potential changes in a complementary manner with respect to the first signal 24.

[0018] The signal output circuit 12 includes a receiving circuit 121. The receiving circuit 121 may be interpreted as an AC-coupled data receiving circuit to which a differential signal 23 transmitted via a capacitive element is supplied. The AC-coupling method may be interpreted as a method for removing a DC component of an input signal and transmitting only an AC component to the receiving circuit 121. The receiving circuit 121 has a first input terminal IN1 for inputting a first signal 24 and a second input terminal IN2 for inputting a second signal 25. The first input terminal IN1 may be interpreted as a positive terminal (+ terminal), and the second input terminal IN2 may be interpreted as a negative terminal (- terminal).

[0019] The receiving circuit 121 outputs a first logic signal 26 corresponding to the potential of the first signal 24 and a second logic signal 27 corresponding to the potential of the second signal 25. Specifically, the receiving circuit 121 may amplify the first signal 24 and the second signal 25, and output the first logic signal 26 and the second logic signal 27 having higher voltage levels than the first signal 24 and the second signal 25. The first logic signal 26 is transmitted to the display panel 10 shown in FIG. 1 via a first output terminal OUT1, and the second logic signal 27 is transmitted to the display panel 10 shown in FIG. 1 via a second output terminal OUT2.

[0020] Next, a specific configuration of the transmission circuit 111 will be described with reference to Fig. 3. Fig. 3 is a diagram showing the configuration of the transmission circuit according to an embodiment of the present disclosure. The transmission circuit 111 includes a first upper and lower arm 31, a second upper and lower arm 32, and a voltage control circuit 6.

[0021] (First upper and lower arm) The first upper and lower arm 31 may be interpreted as a circuit including a first switch element 1 and a second switch element 2 connected in series. Specifically, the first upper and lower arm 31 may be interpreted as a circuit including a first switch element 1 on a first potential side, and a second switch element 2 on a second potential side lower than the first potential, connected in series to the first switch element 1. The first upper and lower arm 31 may output the first signal 24 by the first switch element 1 and the second switch element 2 operating in a complementary manner.

[0022] The first potential may be interpreted as the potential of the power supply VDD, and the second potential may be interpreted as the potential of the ground GND. Each of the first switch element 1 and the second switch element 2 may be interpreted as a transistor.

[0023] (Second upper and lower arms) The second upper and lower arm 32 may be interpreted as a circuit arranged in parallel with the first upper and lower arm 32, and may be interpreted as a circuit including a third switch element 3 and a fourth switch element 4 connected in series. Specifically, the second upper and lower arm 32 may be interpreted as a circuit including a third switch element 3 on a first potential side, and a fourth switch element 4 on a second potential side lower than the first potential, which is connected in series to the third switch element 3. The second upper and lower arm 32 may output the second signal 25 by the third switch element 3 and the fourth switch element 4 operating in a complementary manner. Each of the third switch element 3 and the fourth switch element 4 may be interpreted as a transistor.

[0024] The on / off operation of each of the first switch element 1 to the fourth switch element 4 is controlled by a control circuit (not shown).

[0025] 3, the first switch element 1 and the fourth switch element 4 are in an ON state, and the second switch element 2 and the third switch element 3 are in an OFF state. In this case, a current from the current source 5 flows in the order of the first switch 1, the first input terminal IN1, the second input terminal IN2, the fourth switch 4, and the ground GND.

[0026] In contrast, when the first switch element 1 and the fourth switch element 4 are in the off state and the second switch element 2 and the third switch element 3 are in the on state, the current from the current source 5 flows in the following order: the fourth switch 4, the second input terminal IN2, the first input terminal IN1, the second switch 2, and the ground GND.

[0027] (Voltage control circuit) The voltage control circuit 6 may be interpreted as a control circuit that controls the voltage amplitude of the differential signal 23. The voltage control circuit 6 may be interpreted as a circuit that is connected to the first upper and lower arms 31 and the second upper and lower arms 32 and limits the voltage amplitudes of the first signal 24 and the second signal 25 based on the bias voltage Vbias.

[0028] Specifically, the voltage control circuit 6 may be interpreted as a transistor connected between a current source 5 provided at a first potential (power supply VDD) and the first switch element 1, and further connected between the current source 5 and the third switch element 3.

[0029] More specifically, the voltage control circuit 6 may be interpreted as an enhancement-type P-channel transistor having a gate G to which a bias voltage Vbias is applied, a drain D to which is grounded, and a source S to which the current source 5, one end of the first switch element 1, and one end of the third switch element 3 are connected.

[0030] The bias voltage Vbias may be interpreted as a voltage generated by a voltage generating circuit (not shown). The bias voltage Vbias may be interpreted as a voltage that defines the voltage amplitude of each of the first signal 24 and the second signal 25. The bias voltage Vbias may be interpreted as a voltage that limits the voltage applied to the first upper and lower arms 31 and the second upper and lower arms 32 to a specific potential.

[0031] (Transmitter circuit operation) Next, the operation of the transmission circuit 111 will be described with reference to Fig. 4. Fig. 4 is a timing chart for explaining the operation of the transmission circuit. Fig. 4 shows a clock signal (φ) input to the first arm or the second arm from a control circuit (not shown), a clock signal ( / φ) input to the first arm or the second arm from a control circuit (not shown), a first signal 24 input to the first input terminal IN1, and a second signal 25 input to the second input terminal IN2. The clock signal ( / φ) may be interpreted as a signal whose potential changes complementarily to the clock signal (φ).

[0032] At time t1, the first switch element 1 and the fourth switch element 4 are turned on by the clock signal φ, and the second switch element 2 and the third switch element 3 are turned off by the clock signal / φ. As a result, the voltage of the first signal 24 increases and the voltage of the second signal 25 decreases.

[0033] When the voltage of the first signal 24 reaches a specific voltage at time t2, a certain time after time t1, a current flows in the voltage control circuit 6, suppressing an increase in the voltage amplitude of the first signal 24. The specific voltage may be interpreted as a voltage obtained by adding the gate-source voltage Vgs of the transistor in the voltage control circuit 6 to the bias voltage Vbias. The specific voltage may be interpreted as a voltage for causing a current from the current source 5 to flow in the voltage control circuit 6, that is, for diverting the current to the voltage control circuit 6. The voltage amplitude of the first signal 24 can be changed by changing the bias voltage.

[0034] At time t3 after a certain time has elapsed from time t2, the first switch element 1 and the fourth switch element 4 are turned off by the clock signal φ, and the second switch element 2 and the third switch element 3 are turned on by the clock signal / φ. As a result, the voltage of the second signal 25 increases and the voltage of the first signal 24 decreases.

[0035] When the voltage of the second signal 25 reaches a specific voltage at time t4, a certain time after time t3, a current flows through the voltage control circuit 6, suppressing an increase in the voltage amplitude of the second signal 25. As described above, the specific voltage may be interpreted as a voltage obtained by adding the gate-source voltage Vgs to the bias voltage Vbias, or as a voltage that causes a current from the current source 5 to flow through the voltage control circuit 6. By changing the bias voltage, the voltage amplitude of the second signal 25 can be changed.

[0036] In this way, the transmission circuit 111 of the present disclosure can change the voltage amplitude of the differential signal by setting the bias voltage Vbias. In contrast, the conventional technology sets the voltage amplitude of the differential signal by providing a resistor outside the driver circuit corresponding to the transmission circuit 111. This may complicate the configuration of the system including the reception circuit, and may reduce the yield. In addition, the resistor may hinder the need to shorten the manufacturing time of the system including the reception circuit. In addition, there is a possibility that the appropriate voltage amplitude of the differential signal cannot be obtained by simply changing the value of the current source on the driver circuit side without replacing the resistor.

[0037] (Action and effect) The transmitter circuit 111 of the present disclosure includes a voltage control circuit 6 that limits the voltage amplitude of the differential signal based on a bias voltage. This configuration makes it possible to change the voltage amplitude of the differential signal without providing a resistor outside the driver circuit. Therefore, high-speed communication with limited voltage amplitude of the differential signal is possible while simplifying the configuration of the system including the receiver circuit.

[0038] In addition, since the configuration of the system including the receiving circuit is simplified, the yield can be improved. In addition, the manufacturing time of the system including the receiving circuit can be shortened. In addition, the voltage amplitude of the differential signal can be easily changed without replacing resistors. In addition, the voltage amplitude of the differential signal can be easily changed without changing the current of the current source 5.

[0039] (First Modification) Fig. 5 is a diagram showing the configuration of a transmission circuit according to a first modified example. The difference from the transmission circuit 111 shown in Fig. 3 is that the transmission circuit 111A according to the first modified example includes a voltage control circuit 6A that includes a first voltage control circuit 6A1 and a second voltage control circuit 6A2.

[0040] The first voltage control circuit 6A1 may be interpreted as a transistor connected between the third switch element 3 and the fourth switch element 4. Specifically, the first voltage control circuit 6A1 may be interpreted as an enhancement type P-channel transistor in which a bias voltage Vbias is applied to a gate G, a drain D is grounded, and a source S is connected to the other end of the third switch element 3 and one end of the fourth switch element 4.

[0041] The second voltage control circuit 6A2 may be interpreted as a transistor connected between the first switch element 1 and the second switch element 2. Specifically, the second voltage control circuit 6A2 may be interpreted as an enhancement type P-channel transistor having a gate G to which a bias voltage Vbias is applied, a drain D to which is grounded, and a source S to which the other end of the first switch element 1 and one end of the second switch element 2 are connected.

[0042] The transmission circuit 111A according to the first modification can operate in the same manner as the transmission circuit 111 shown in FIG. 3. That is, when the voltage of the first signal 24 reaches a specific voltage at time t2 shown in FIG. 4, a current flows through the second voltage control circuit 6A2, suppressing an increase in the voltage amplitude of the first signal 24. The specific voltage may be interpreted as a voltage obtained by adding the gate-source voltage Vgs of the transistor constituting the second voltage control circuit 6A2 to the bias voltage Vbias. The specific voltage may be interpreted as a voltage for causing a current from the current source 5 to flow through the second voltage control circuit 6A2, that is, for diverting the current to the second voltage control circuit 6A2. The voltage amplitude of the first signal 24 can be changed by changing the bias voltage.

[0043] 4, when the voltage of the second signal 25 reaches a specific voltage, a current flows through the first voltage control circuit 6A1, suppressing an increase in the voltage amplitude of the second signal 25. As described above, the specific voltage may be interpreted as a voltage obtained by adding the bias voltage Vbias to the gate-source voltage Vgs of the transistor that constitutes the first voltage control circuit 6A1, or as a voltage that causes a current from the current source 5 to flow through the first voltage control circuit 6A1. By changing the bias voltage, the voltage amplitude of the second signal 25 can be changed.

[0044] So far, examples of the configuration of a transmission circuit for defining an upper limit of the voltage amplitude of a differential signal have been described. Below, examples of the configuration of a transmission circuit that also defines a lower limit of the voltage amplitude (second and third variants) will be described.

[0045] (Second Modification) Fig. 6 is a diagram showing the configuration of a transmission circuit according to a second modified example. The difference from the transmission circuit 111 shown in Fig. 3 is that the transmission circuit 111B according to the second modified example includes a voltage control circuit 6B that includes a first voltage control circuit 6B1 and a second voltage control circuit 6B2. In the transmission circuit 111B, the other end of the second switch element 2 and the other end of the fourth switch element 4 are connected to a current source 5a on the second potential side.

[0046] The first voltage control circuit 6B1 includes a first conductivity type transistor. The first conductivity type transistor may be interpreted as a transistor connected between a first current source provided at a first potential and the first switch element 1, and also connected between the first current source and the third switch element 3. The first current source may be interpreted as a current source 5. Specifically, the first voltage control circuit 6B1 may be interpreted as a transistor connected between a current source 5 provided at a first potential and the first switch element 1, and also connected between the current source 5 and the third switch element 3. More specifically, the first voltage control circuit 6B1 may be interpreted as an enhancement type P-channel transistor having a gate G to which a bias voltage Vbiasp is applied, a drain D grounded, and a source S connected to the current source 5, one end of the first switch element 1, and one end of the second switch element 2.

[0047] The second voltage control circuit 6B2 includes a second conductivity type transistor. The second conductivity type transistor may be interpreted as a transistor connected between a second current source provided at the second potential and the second switch element 2, and also connected between the second current source and the fourth switch element 4. The second current source may be interpreted as the current source 5a. Specifically, the second voltage control circuit 6B2 may be interpreted as a transistor connected between a current source 5a provided at the second potential and the second switch element 2, and also connected between the current source 5a and the fourth switch element 4. More specifically, the second voltage control circuit 6B2 may be interpreted as an enhancement type N-channel transistor having a gate G to which a bias voltage Vbiasn is applied, a drain D connected to a power supply VDD, and a source S connected to the current source 5a, the other end of the second switch element 2, and the other end of the fourth switch element 4.

[0048] (Operation of the Transmission Circuit According to the Second Modification) Next, the operation of the transmission circuit 111B will be described with reference to Fig. 7. Fig. 7 is a timing chart for explaining the operation of the transmission circuit according to the second modified example. Fig. 7 shows a clock signal (φ) input to the first arm or the second arm from a control circuit (not shown), a clock signal ( / φ) input to the first arm or the second arm from a control circuit (not shown), a first signal 24 input to the first input terminal IN1, and a second signal 25 input to the second input terminal IN2.

[0049] At time t1, the first switch element 1 and the fourth switch element 4 are turned on by the clock signal φ, and the second switch element 2 and the third switch element 3 are turned off by the clock signal / φ. As a result, the voltage of the first signal 24 increases and the voltage of the second signal 25 decreases.

[0050] When the voltage of the first signal 24 reaches the specific voltage at time t2 after a certain time has elapsed from time t1, a current flows through the first voltage control circuit 6B1, suppressing an increase in the voltage amplitude of the first signal 24. The specific voltage may be interpreted as a voltage obtained by adding the gate-source voltage Vgsp of the transistor of the first voltage control circuit 6B1 to the bias voltage Vbiasp to the first voltage control circuit 6B1. The specific voltage may be interpreted as a voltage for causing the current from the current source 5 to flow through the first voltage control circuit 6B1, that is, for diverting the current to the first voltage control circuit 6B1. The voltage amplitude of the first signal 24 can be changed by changing the bias voltage Vbiasp.

[0051] At time t3 after a certain time has elapsed from time t2, the first switch element 1 and the fourth switch element 4 are turned off by the clock signal φ, and the second switch element 2 and the third switch element 3 are turned on by the clock signal / φ. As a result, the voltage of the second signal 25 increases and the voltage of the first signal 24 decreases.

[0052] When the voltage of the second signal 25 reaches a specific voltage at time t4, a certain time after time t3, a current flows through the second voltage control circuit 6B2, suppressing a drop in the voltage amplitude of the second signal 25. As described above, the specific voltage may be interpreted as a voltage obtained by adding the gate-source voltage Vgsn to the bias voltage Vbiasn applied to the second voltage control circuit 6B2, or as a voltage that causes a current from the current source 5 to flow through the second voltage control circuit 6B2. The voltage amplitude of the second signal 25 can be changed by changing the bias voltage Vbiasn.

[0053] The transmission circuit 111B can change the upper and lower limits of the voltage amplitude of the differential signal by changing the bias voltage Vbiasp and the bias voltage Vbiasn. According to the transmission circuit 111B, the voltage amplitude of the differential signal can be set more finely, and therefore faster data transmission can be realized.

[0054] (Third Modification) Fig. 8 is a diagram showing the configuration of a transmission circuit according to a third modified example. A transmission circuit 111C according to the third modified example differs from the transmission circuit 111B shown in Fig. 6 in that a voltage control circuit 6C includes a first transistor pair 61 and a second transistor pair 62. Specifically, the voltage control circuit 6C includes a first voltage control circuit 6C1, a second voltage control circuit 6C2, a third voltage control circuit 6C3, and a fourth voltage control circuit 6C4.

[0055] The first transistor pair 61 includes a first conductivity type transistor and a second conductivity type transistor connected in series between a first potential and a second potential, and may be interpreted as a transistor pair connected between the third switch element 3 and the fourth switch element 4. The second transistor pair 62 includes a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and a second potential, and may be interpreted as a transistor pair connected between the first switch element 1 and the second switch element 2.

[0056] The first voltage control circuit 6C1 may be interpreted as a transistor connected between the third switch element 3 and the fourth switch element 4. Specifically, the first voltage control circuit 6C1 may be interpreted as an enhancement type N-channel transistor having a gate G to which a bias voltage Vbiasp is applied, a drain D connected to a power supply VDD, a source S connected to the other end of the third switch element 3 and one end of the fourth switch element 4, and a source S connected to the source S of the second voltage control circuit 6C2.

[0057] The second voltage control circuit 6C2 may be interpreted as a transistor connected between the third switch element 3 and the fourth switch element 4. Specifically, the second voltage control circuit 6C2 may be interpreted as an enhancement type P-channel transistor having a gate G to which a bias voltage Vbiasn is applied, a drain D grounded, a source S connected to the other end of the third switch element 3 and one end of the fourth switch element 4, and a source S connected to the source S of the first voltage control circuit 6C1.

[0058] The third voltage control circuit 6C3 may be interpreted as a transistor connected between the first switch element 1 and the second switch element 2. Specifically, the third voltage control circuit 6C3 may be interpreted as an enhancement type N-channel transistor having a gate G to which a bias voltage Vbiasp is applied, a drain D connected to a power supply VDD, a source S connected to the other end of the third switch element 3 and one end of the fourth switch element 4, and a source S connected to the source S of the fourth voltage control circuit 6C4.

[0059] The fourth voltage control circuit 6C4 may be interpreted as a transistor connected between the first switch element 1 and the second switch element 2. Specifically, the fourth voltage control circuit 6C4 may be interpreted as an enhancement type P-channel transistor having a gate G to which a bias voltage Vbiasn is applied, a drain D grounded, a source S connected to the other end of the third switch element 3 and one end of the fourth switch element 4, and a source S connected to the source S of the third voltage control circuit 6C3.

[0060] The transmission circuit 111C according to the third modification can operate in the same manner as the transmission circuit 111B shown in FIG. 6. That is, when the voltage of the first signal 24 reaches a specific voltage at time t2 shown in FIG. 7, a current flows through the fourth voltage control circuit 6C4, suppressing an increase in the voltage amplitude of the first signal 24. The specific voltage may be interpreted as a voltage obtained by adding the gate-source voltage Vgsn of the transistor constituting the fourth voltage control circuit 6C4 to the bias voltage Vbiasn. The specific voltage may be interpreted as a voltage for causing the current from the current source 5 to flow through the fourth voltage control circuit 6C4, that is, for diverting the current to the fourth voltage control circuit 6C4. By changing the bias voltage, the upper limit of the voltage amplitude of the first signal 24 can be changed.

[0061] 7, when the voltage of the second signal 24 reaches the specific voltage, a current flows through the first voltage control circuit 6C1, suppressing a drop in the voltage amplitude of the second signal 25. The specific voltage may be interpreted as a voltage obtained by adding the gate-source voltage Vgsp of the transistor constituting the first voltage control circuit 6C1 to the bias voltage Vbiasp. The specific voltage may be interpreted as a voltage for causing the current from the current source 5a to flow through the first voltage control circuit 6C1, that is, for diverting the current to the first voltage control circuit 6C1. By changing the bias voltage, the lower limit of the voltage amplitude of the second signal 25 can be changed.

[0062] 7, when the voltage of the first signal 24 reaches the specific voltage, a current flows through the third voltage control circuit 6C3, suppressing a drop in the voltage amplitude of the first signal 24. The specific voltage may be interpreted as a voltage obtained by adding the gate-source voltage Vgsp of the transistor constituting the third voltage control circuit 6C3 to the bias voltage Vbiasp. The specific voltage may be interpreted as a voltage for causing the current from the current source 5a to flow through the third voltage control circuit 6C3, that is, for diverting the current to the third voltage control circuit 6C3. By changing the bias voltage, the lower limit of the voltage amplitude of the first signal 24 can be changed.

[0063] 7, when the voltage of the second signal 24 reaches the specific voltage, a current flows through the second voltage control circuit 6C2, suppressing an increase in the voltage amplitude of the second signal 25. The specific voltage may be interpreted as a voltage obtained by adding the gate-source voltage Vgsn of the transistor constituting the second voltage control circuit 6C2 to the bias voltage Vbiasn. The specific voltage may be interpreted as a voltage for causing the current from the current source 5 to flow through the second voltage control circuit 6C2, that is, for diverting the current to the second voltage control circuit 6C2. By changing the bias voltage, the upper limit of the voltage amplitude of the second signal 25 can be changed.

[0064] In addition, the following supplementary notes are provided in relation to the above description.

[0065] (Appendix 1) A semiconductor device that outputs a differential signal, a first upper and lower arm including a first switch element on a first potential side and a second switch element on a second potential side lower than the first potential connected in series to the first switch element, the first switch element and the second switch element operating complementarily to output a first signal; a second upper and lower arm including a third switch element on the first potential side arranged in parallel with the first upper and lower arm and a fourth switch element on the second potential side connected in series to the third switch element, the second upper and lower arm generating and outputting a second signal whose potential changes complementarily to the first signal as a result of the third switch element and the fourth switch element operating complementarily; a voltage control circuit connected to the first upper and lower arms and the second upper and lower arms, the voltage control circuit limiting a voltage amplitude of the first signal and the second signal based on a bias voltage; A semiconductor device comprising: (Appendix 2) The voltage control circuit includes: 2. The semiconductor device according to claim 1, wherein the first switch element is connected between a current source provided at the first potential and the first switch element, and the third switch element is connected between the current source and the third switch element. (Appendix 3) The voltage control circuit includes: 3. The semiconductor device according to claim 1, further comprising: a first voltage control circuit connected between the third switch element and the fourth switch element; and a second voltage control circuit connected between the first switch element and the second switch element. (Appendix 4) The voltage control circuit includes: a first voltage control circuit including a first conductivity type transistor connected between a first current source provided at the first potential and the first switch element, and connected between the first current source and the third switch element; and a second voltage control circuit including a second conductivity type transistor connected between a second current source provided at the second potential and the second switch element, and connected between the second current source and the fourth switch element. (Appendix 5) The voltage control circuit includes: a first transistor pair including a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, the first transistor pair being connected between the third switch element and the fourth switch element; 5. The semiconductor device according to claim 1, further comprising: a second transistor pair including a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, the second transistor pair being connected between the first switch element and the second switch element. [Explanation of symbols]

[0066] 1 First switch element 2 Second switch element 3 Third switch element 4 Fourth switch element 5 Current source 5a current source 6 Voltage control circuit 6A voltage control circuit 6A1 First voltage control circuit 6A2 Second voltage control circuit 6B Voltage control circuit 6B1 First voltage control circuit 6B2 Second voltage control circuit 6C Voltage control circuit 6C1 First voltage control circuit 6C2 Second voltage control circuit 6C3 Third voltage control circuit 6C4 4th voltage control circuit 10 Display Panel 11 Timing Controller 12 Signal output circuit 13 Gate Driver 20 Transmission Line 21 First Capacitor 22 Second Capacitor 23 Differential Signal 24 First Signal 25 2nd Signal 26 First logic signal 27 Second logic signal 31 First upper and lower arm 32 Second upper and lower arm 61 First transistor pair 62 Second transistor pair 100 display device 111 Transmitting circuit 111A Transmitting circuit 111B Transmitting circuit 111C Transmitting circuit 121 Receiver circuit 200 Communication Systems

Claims

1. A semiconductor device that outputs a differential signal, a first upper and lower arm including a first switch element on a first potential side and a second switch element on a second potential side lower than the first potential connected in series to the first switch element, the first switch element and the second switch element operating complementarily to output a first signal; a second upper and lower arm including a third switch element on the first potential side arranged in parallel with the first upper and lower arm and a fourth switch element on the second potential side connected in series to the third switch element, the second upper and lower arm generating and outputting a second signal whose potential changes complementarily to the first signal as a result of the third switch element and the fourth switch element operating complementarily; a voltage control circuit connected to the first upper and lower arms and the second upper and lower arms, the voltage control circuit limiting a voltage amplitude of the first signal and the second signal based on a bias voltage; A semiconductor device comprising:

2. The voltage control circuit includes:

2. The semiconductor device according to claim 1, connected between a current source provided at said first potential and said first switch element, and also connected between said current source and said third switch element.

3. The voltage control circuit includes:

2. The semiconductor device according to claim 1, further comprising: a first voltage control circuit connected between said third switch element and said fourth switch element; and a second voltage control circuit connected between said first switch element and said second switch element.

4. The voltage control circuit includes: a first voltage control circuit including a first conductivity type transistor connected between a first current source provided at the first potential and the first switch element, and connected between the first current source and the third switch element; 2. The semiconductor device according to claim 1, further comprising: a second voltage control circuit including a second conductivity type transistor connected between a second current source provided at the second potential and the second switch element, and connected between the second current source and the fourth switch element.

5. The voltage control circuit includes: a first transistor pair including a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, the first transistor pair being connected between the third switch element and the fourth switch element; 2. The semiconductor device according to claim 1, further comprising: a second transistor pair including a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, the second transistor pair being connected between the first switch element and the second switch element.

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