Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device driving at high speed.SOLUTION: In a predetermined cross-sectional view, a semiconductor device includes a transistor in which a gate electrode surrounds an upper surface, a lower surface, and side surfaces of a metal oxide layer. The metal oxide layer includes one or more layers that overlap with the gate electrode, and in the predetermined cross-sectional view, each of a lower surface, an upper surface, and side surfaces of that layer is surrounded by the gate electrode that includes a plurality of layers overlapping with the metal oxide layer. The metal oxide layer can include the plurality of layers overlapping with the gate electrode. In this case, the layer included in the gate electrode and the layer included in the metal oxide layer and overlapping with the gate electrode are provided alternately. In addition, the metal oxide layer includes a region not overlapping with the gate electrode in a plan view. Outside that region, a source electrode and a drain electrode of the transistor are provided. The source electrode and the drain electrode are provided to face each other with the layer included in the gate electrode interposed therebetween.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of a semiconductor device. Also, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs (Large Scale Integration), CPUs (Central Processing Units), memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of the components in various electronic devices.

[0006] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but metal oxides are also attracting attention as other materials.

[0007] It is also known that transistors using metal oxides have an extremely small leakage current in an off state. For example, Patent Document 1 discloses a low-power consumption CPU or the like that utilizes the property of low leakage current of transistors using metal oxides. In addition, for example, Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using metal oxides.

[0008] In addition, in recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for further density of integrated circuits. In addition, there is a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology for increasing density of integrated circuits by stacking a first transistor using a metal oxide film and a second transistor using a metal oxide film to provide multiple memory cells in a superimposed manner. In addition, Patent Document 4 discloses a technology for increasing density of integrated circuits by vertically arranging the channel of a transistor using a metal oxide film. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A [Patent Document 3] International Publication No. 2021 / 053473 [Patent Document 4] JP 2013-211537 A [Non-patent literature]

[0010] [Non-Patent Document 1] M.Oota et.al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53 Summary of the Invention [Problem to be solved by the invention]

[0011] As integrated circuits become denser and more multifunctional, there is a demand for high-speed operation of semiconductor devices including integrated circuits. For example, in a memory device in which memory cells are densely arranged and capable of storing a large amount of data, there is a demand for writing and reading a large amount of data in a short time. Therefore, there is a demand for writing and reading data in a short time.

[0012] An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed and a manufacturing method thereof.Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current and a manufacturing method thereof.Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof.Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption and a manufacturing method thereof.Another object of one embodiment of the present invention is to provide a novel semiconductor device and a manufacturing method thereof.

[0013] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description of the specification, drawings, and claims. [Means for solving the problem]

[0014] One embodiment of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, an insulating layer, and a first metal oxide layer, the second conductive layer being provided on the first conductive layer, the third conductive layer having a region in contact with a first side surface of the first conductive layer and a second side surface of the second conductive layer, the fourth conductive layer having a third side surface of the first conductive layer facing the first side surface, and a region in contact with a fourth side surface of the second conductive layer facing the second side surface, the insulating layer having, in a region between the first conductive layer and the second conductive layer, a region in contact with a top surface of the first conductive layer, a region in contact with a bottom surface of the second conductive layer, a region in contact with a side surface of the third conductive layer, and a region in contact with a side surface of the fourth conductive layer, the first metal oxide layer has a first region surrounded by the first to fourth conductive layers with an insulating layer therebetween, a second region facing the seventh side with the insulating layer therebetween, and a third region facing the eighth side with the insulating layer therebetween; the fifth conductive layer has the second region and a region facing the seventh side with the insulating layer therebetween, and is provided so as to be electrically connected to the first metal oxide layer; and the sixth conductive layer has the third region and a region facing the eighth side with the insulating layer therebetween, and is provided so as to be electrically connected to the first metal oxide layer.

[0015] Alternatively, in the above aspect, the semiconductor device has a seventh conductive layer, the seventh conductive layer is provided on the second conductive layer, a ninth side of the seventh conductive layer has a region in contact with the third conductive layer, a tenth side of the seventh conductive layer opposite to the ninth side has a region in contact with the fourth conductive layer, an upper surface of the second conductive layer, a lower surface of the seventh conductive layer, a side of the third conductive layer, and a side of the fourth conductive layer each have a region in contact with an insulating layer in a region between the second conductive layer and the seventh conductive layer, and an eleventh side of the seventh conductive layer, The twelfth side opposite the eleventh side each has a region in contact with an insulating layer, the first metal oxide layer has a fourth region surrounded by the second to fourth conductive layers and the seventh conductive layer across the insulating layer, a fifth region opposite the eleventh side across the insulating layer, and a sixth region opposite the twelfth side across the insulating layer, the fifth conductive layer has the fifth region and a region opposite the eleventh side across the insulating layer, and the sixth conductive layer has the sixth region and a region opposite the twelfth side across the insulating layer.

[0016] Alternatively, in the above embodiment, the fifth conductive layer may have a shape that follows the side surface of the first metal oxide layer that includes the second region and a shape that follows the side surface of the first metal oxide layer that includes the fifth region, and the sixth conductive layer may have a shape that follows the side surface of the first metal oxide layer that includes the third region and a shape that follows the side surface of the first metal oxide layer that includes the sixth region.

[0017] Alternatively, in the above aspect, the semiconductor device may have a second metal oxide layer and a third metal oxide layer, the second metal oxide layer being provided between the first metal oxide layer and a fifth conductive layer, the third metal oxide layer being provided between the first metal oxide layer and a sixth conductive layer, the second metal oxide layer having a shape that follows the side surface including the second region and the side surface including the fifth region of the first metal oxide layer, the third metal oxide layer having a shape that follows the side surface including the third region and the side surface including the sixth region of the first metal oxide layer, the second metal oxide layer having a region in contact with the fifth conductive layer, and the third metal oxide layer having a region in contact with the sixth conductive layer.

[0018] Alternatively, in the above embodiment, the third conductive layer and the fourth conductive layer may each have the same material as the second conductive layer.

[0019] Alternatively, in the above embodiment, the film thickness of the third conductive layer and the film thickness of the fourth conductive layer may be equal to or greater than the film thickness of at least one of the first conductive layer and the second conductive layer.

[0020] Alternatively, in the above aspect, the third conductive layer may have a first layer having a region in contact with the second side surface and a second layer provided outside the first layer, and the fourth conductive layer may have a third layer having a region in contact with the fourth side surface and a fourth layer provided outside the third layer, and the first layer and the third layer may each have the same material as the second conductive layer.

[0021] Alternatively, in the above embodiment, the first metal oxide layer may have one or more selected from indium, zinc, and element M, and element M may be one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The electrical conductivity of the second metal oxide layer and the third metal oxide layer may be equal to or higher than that of the first metal oxide layer, and each may contain indium.

[0022] Alternatively, one embodiment of the present invention includes forming a first conductive layer, a first sacrificial layer over the first conductive layer, and a second conductive layer over the first sacrificial layer; forming a third conductive layer so as to have a region in contact with a first side surface of the first conductive layer, a region in contact with a second side surface of the second conductive layer, a region in contact with a third side surface opposed to the first side surface, and a region in contact with a fourth side surface opposed to the second side surface and located on the second conductive layer; removing the first sacrificial layer; a metal oxide layer is formed to cover the insulating layer; a fourth conductive layer is formed on the metal oxide layer; a fifth conductive layer and a sixth conductive layer facing the fifth conductive layer with the metal oxide layer sandwiched therebetween are formed by planarizing the fourth conductive layer; and a seventh conductive layer and an eighth conductive layer facing the seventh conductive layer with the second conductive layer sandwiched therebetween are formed by planarizing the third conductive layer.

[0023] Alternatively, in the above aspect, before forming the third conductive layer, a second sacrificial layer on the second conductive layer and a ninth conductive layer on the second sacrificial layer are formed, the third conductive layer is formed to have a region in contact with a fifth side of the ninth conductive layer and a region in contact with a sixth side opposite the fifth side, and a region located on the ninth conductive layer, the second sacrificial layer is removed in the same process as the removal of the first sacrificial layer, and an insulating layer is formed to cover the ninth conductive layer.

[0024] Alternatively, in the above embodiment, before forming the third conductive layer, a third sacrificial layer may be formed on the ninth conductive layer, the third conductive layer may be formed to have a region located on the third sacrificial layer, and a planarization treatment for the third sacrificial layer may be performed in parallel with the planarization treatment for the third conductive layer and the planarization treatment for the fourth conductive layer.

[0025] Alternatively, in the above aspect, a third sacrificial layer may be formed having a first layer and a second layer on the first layer, and the film thickness of the first layer is equal to or less than the film thickness of the second layer, and the planarization process for the third sacrificial layer may be performed until at least the upper surface of the first layer is exposed.

[0026] Alternatively, in the above embodiment, the third conductive layer may be formed to have a thickness equal to or greater than the thickness of the ninth conductive layer.

[0027] Alternatively, in the above embodiment, the metal oxide layer may be formed using an ALD method. Effect of the Invention

[0028] According to one embodiment of the present invention, a semiconductor device with high operating speed and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a novel semiconductor device and a manufacturing method thereof can be provided.

[0029] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief description of the drawings]

[0030] [Figure 1] 1A to 1D are perspective views showing configuration examples of a semiconductor device. [Diagram 2] Fig. 2A is a plan view showing a configuration example of a semiconductor device, and Figs. 2B to 2E are cross-sectional views showing the configuration example of the semiconductor device. [Diagram 3] 3A and 3B are cross-sectional views showing configuration examples of a semiconductor device. [Figure 4] 4A and 4B are cross-sectional views showing configuration examples of a semiconductor device. [Diagram 5] Fig. 5(A) is a perspective view showing a configuration example of a semiconductor device, Fig. 5(B) is a plan view showing a configuration example of a semiconductor device, Fig. 5(C) and Fig. 5(D) are cross-sectional views showing the configuration example of a semiconductor device. [Figure 6] Fig. 6A is a circuit diagram showing a configuration example of a memory cell, Fig. 6B and Fig. 6C are cross-sectional views showing a configuration example of a memory device. [Figure 7] 7A and 7B are cross-sectional views showing configuration examples of a memory device. [Figure 8] Fig. 8A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 8B and Fig. 8C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device. [Figure 9] Fig. 9A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 9B and Fig. 9C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device. [Figure 10] Fig. 10A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 10B and Fig. 10C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device. [Figure 11] Fig. 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 11B and Fig. 11C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device. [Figure 12] 12A to 12C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 13] 13A to 13D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 14] Fig. 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 14B and Fig. 14C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device. [Figure 15] Fig. 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 15B and Fig. 15C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device. [Figure 16] Fig. 16A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 16B and Fig. 16C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device. [Figure 17] Fig. 17A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 17B and Fig. 17C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device. [Figure 18]Fig. 18A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 18B to Fig. 18E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 19] 19A and 19B are cross-sectional views showing an example of a method for manufacturing a memory device. [Figure 20] 20A and 20B are cross-sectional views showing an example of a method for manufacturing a memory device. [Figure 21] FIG. 21 is a block diagram showing an example of the configuration of a storage device. [Figure 22] Fig. 22A is a schematic diagram showing a configuration example of a memory device, and Fig. 22B is a schematic diagram and a circuit diagram showing a configuration example of a memory device. [Diagram 23] 23(A) and 23(B) are schematic diagrams showing configuration examples of a storage device. [Figure 24] 24A to 24C are circuit diagrams showing configuration examples of memory devices. [Diagram 25] FIG. 25 is a circuit diagram showing a configuration example of a storage device. [Figure 26] FIG. 26 is a cross-sectional view showing a configuration example of a storage device. [Figure 27] FIG. 27 is a cross-sectional view showing a configuration example of a storage device. [Figure 28] 28(A) and 28(B) are diagrams showing an example of a semiconductor device. [Figure 29] 29(A) and 29(B) are diagrams showing an example of an electronic component. [Diagram 30] Figures 30(A) and 30(B) are diagrams showing an example of an electronic device, and Figures 30(C) to 30(E) are diagrams showing an example of a mainframe computer. [Diagram 31] FIG. 31 is a diagram showing an example of space equipment. [Diagram 32] FIG. 32 is a diagram illustrating an example of a storage system applicable to a data center. [Diagram 33] 33(A) and 33(B) are perspective views showing configuration examples of a display device. [Diagram 34]FIG. 34 is a cross-sectional view showing a configuration example of a display device. [Diagram 35] FIG. 35 is a cross-sectional view showing a configuration example of a display device. [Diagram 36] FIG. 36 is a cross-sectional view showing a configuration example of a display device. [Figure 37] Fig. 37(A) is a plan view showing a configuration example of a display device, and Fig. 37(B) and Fig. 37(C) are cross-sectional views showing a configuration example of a display device. [Figure 38] 38(A) and 38(B) are cross-sectional views showing configuration examples of a display device. [Figure 39] 39A to 39D are diagrams illustrating examples of electronic devices. [Diagram 40] 40(A) to 40(F) are diagrams showing examples of electronic devices. [Diagram 41] 41(A) to 41(G) are diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0032] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

[0033] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0034] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). In addition, an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.

[0035] A transistor is a type of semiconductor element and can realize a function of amplifying a current or a voltage, a switching operation of controlling conduction or non-conduction, etc. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).

[0036] In this specification and the like, a transistor using a metal oxide for a semiconductor layer and a transistor having a metal oxide for a channel formation region may be referred to as an OS transistor, and a transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0037] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region (also called a channel formation region) in which a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) is provided, and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0038] In addition, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current changes during circuit operation, etc. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0039] Note that impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. The inclusion of impurities can, for example, increase the defect level density of the semiconductor or reduce the crystallinity. When the semiconductor is a metal oxide, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the metal oxide. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V O In some cases, a junction (also referred to as a junction) may be formed.

[0040] In this specification and the like, an oxynitride refers to a material having a composition containing more oxygen than nitrogen, and a nitride oxide refers to a material having a composition containing more nitrogen than oxygen.

[0041] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used to analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in the film. When the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more), XPS is suitable. On the other hand, when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less), SIMS is suitable. When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

[0042] In addition, the words "film" and "layer" can be interchanged depending on the case or situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer".

[0043] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0044] In this specification, "electrically connected" includes a case where a connection is made via "something having some electrical action." Here, "something having some electrical action" is not particularly limited as long as it enables transmission and reception of an electrical signal between the objects to be connected. For example, "something having some electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistors, coils, capacitors, and other elements having various functions.

[0045] In this specification, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also called the non-conducting state or cut-off state). Unless otherwise specified, the off-state refers to the voltage V between the gate and the source in an n-channel transistor. gs is the threshold voltage V th (For p-channel transistors, V th The term "higher" refers to a state of being.

[0046] In this specification, the normally-on characteristic refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the normally-off characteristic refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0047] In this specification, the term "tapered shape" refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0048] In this specification, when it is stated that A is located on B, at least a part of A is located on B. Therefore, for example, it can be rephrased as A has an area located on B. Similarly, when it is stated that A contacts B or A overlaps B, at least a part of A contacts B or overlaps B. Therefore, it can be rephrased as A has an area contacting B or A has an area overlapping B, respectively. Similarly, in this specification, when it is stated that A covers B, at least a part of A covers B. Therefore, for example, it can be rephrased as A has an area covering B.

[0049] In addition, for example, in the drawings related to this specification, arrows indicating the X direction, Y direction, and Z direction may be added. In addition, in this specification, the "X direction" is the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." In addition, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0050] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

[0051] A semiconductor device according to one embodiment of the present invention includes a transistor in which a gate electrode surrounds an upper surface, a lower surface, and a side surface of a semiconductor layer (also referred to as a metal oxide layer) containing a metal oxide in a cross-sectional view. A transistor having such a structure is also referred to as a transistor having a gate all around (GAA) structure. Note that a conductive layer containing a metal oxide can also be referred to as a metal oxide layer.

[0052] The metal oxide layer has one or more layers (also referred to as regions) overlapping with the gate electrode, and in a predetermined cross-sectional view, the bottom surface, top surface, and side surface of the layer are each surrounded by a gate electrode having a plurality of layers overlapping with the metal oxide layer. The metal oxide layer can have a plurality of layers overlapping with the gate electrode, and in this case, the layers included in the gate electrode and the layers included in the metal oxide layer overlapping with the gate electrode are alternately provided. Specifically, the layers included in the gate electrode are provided in the bottom layer and the top layer, and a layer included in the metal oxide layer and overlapping with the gate electrode is provided between these layers. Thus, when the gate electrode has n layers (n is an integer of 2 or more), the metal oxide layer has n-1 layers. A channel is formed in the layer included in the metal oxide layer and overlapping with the gate electrode. Here, the layer in which the channel is formed can have a flat top surface. Thus, the transistor included in the semiconductor device of one embodiment of the present invention can be said to be a transistor with a nanosheet structure.

[0053] A gate insulating layer is provided so as to cover the gate electrode. The metal oxide layer has a region that does not overlap with the gate electrode in a planar view, for example. The region of the metal oxide layer and the side surface of the layer of the gate electrode face each other via the gate insulating layer. A source electrode and a drain electrode of the transistor are provided outside the region of the metal oxide layer (the opposite side to the layer of the gate electrode). The source electrode and the drain electrode are provided so as to face each other with the layer of the gate electrode sandwiched therebetween. The source electrode and the drain electrode have a shape that follows the side surface of the metal oxide layer in the region that does not overlap with the gate electrode.

[0054] In a transistor included in a semiconductor device of one embodiment of the present invention, a gate electrode can surround a bottom surface, a top surface, and a side surface of a metal oxide layer in a predetermined cross-sectional view in a region between a source electrode and a drain electrode. This allows an electric field for inducing a channel in the metal oxide layer to be applied more effectively than when the gate electrode covers, for example, only the top surface of the metal oxide layer, covers only the top surface and the side surfaces, or covers only the top surface and the bottom surface. Thus, the transistor included in the semiconductor device of one embodiment of the present invention can be a transistor with a large on-state current. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device with high operating speed.

[0055] Furthermore, the larger the number of layers that the metal oxide layer has and that overlap with the gate electrode, that is, the larger n, the larger the volume of a region surrounded by the gate electrode of the metal oxide layer can be without increasing the channel length of the transistor. As a result, the on-state current of the transistor can be increased. Therefore, the operating speed of the semiconductor device of one embodiment of the present invention can be increased. On the other hand, the larger n is, the more manufacturing steps of the semiconductor device are required. Thus, the manufacturing cost of the semiconductor device may increase, and for example, the price of the semiconductor device may become high. Therefore, it is preferable to determine n in consideration of the performance and price of the semiconductor device.

[0056] An example of a manufacturing method of a transistor included in a semiconductor device of one embodiment of the present invention in which n is 2 will be described below. First, a first conductive layer, a sacrificial layer, and a second conductive layer are formed in this order over a substrate. The first conductive layer and the second conductive layer can be formed by, for example, an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, or the like. The first conductive layer and the second conductive layer can be formed using, for example, titanium nitride. The sacrificial layer can be formed using, for example, aluminum oxide.

[0057] Then, the second conductive layer, the sacrificial layer, and the first conductive layer are processed. For example, the second conductive layer, the sacrificial layer, and the first conductive layer are processed in order using photolithography and etching. This processing is called the first processing. The second conductive layer, the sacrificial layer, and the first conductive layer can be processed using the same mask pattern. Here, the thinner the film thickness of the first conductive layer and the second conductive layer, the more preferable it is because the first conductive layer and the second conductive layer can be prevented from being processed in the horizontal direction.

[0058] Next, a third conductive layer is formed so as to cover the first conductive layer, the sacrificial layer, and the second conductive layer. The third conductive layer can be formed by, for example, a CVD method, an ALD method, or the like. When the same material as that used for the first conductive layer and the second conductive layer is used for the third conductive layer, it is preferable that the third conductive layer is easily adhered to the first conductive layer and the second conductive layer. In particular, when the same material as that used for the second conductive layer is used for the third conductive layer, it is preferable that the third conductive layer is easily adhered to the second conductive layer, and the second conductive layer can be prevented from falling off when the sacrificial layer is removed in a later process. For example, when titanium nitride is used for the first conductive layer and the second conductive layer, it is preferable that titanium nitride is also used for the third conductive layer.

[0059] Then, the third conductive layer is processed. For example, the third conductive layer is processed using a photolithography method and an etching method. This processing is called the second processing. The third conductive layer is formed to have a region in contact with the first side surface, which is a side surface of the first conductive layer, a region in contact with the second side surface, which is a side surface of the second conductive layer, a region in contact with the third side surface, which is a side surface opposite to the first side surface, and a region in contact with the fourth side surface, which is a side surface opposite to the second side surface, and to have a region located on the second conductive layer. In addition, the third conductive layer can be formed so as not to be in contact with the side surfaces other than the first and second side surfaces of the first conductive layer and the side surfaces other than the third and fourth side surfaces of the second conductive layer.

[0060] Unlike the first processing, the second processing does not require processing of multiple layers, for example, multiple conductive layers overlapping with a sacrificial layer, with the same mask pattern. Therefore, the film thickness of the third conductive layer can be equal to or greater than the film thickness of at least one of the first conductive layer and the second conductive layer. The film thickness of the third conductive layer can be greater than the film thickness of the first conductive layer and the film thickness of the second conductive layer, for example. In addition, the first conductive layer and the second conductive layer can be formed as a single layer structure, and the third conductive layer can be formed as a laminated structure of two or more layers.

[0061] Next, the sacrificial layer is removed. For example, the sacrificial layer is removed by using a wet etching method. As described above, if the second conductive layer and the third conductive layer have the same material, the third conductive layer can be easily attached to the second conductive layer, and the second conductive layer can be prevented from falling off, which is preferable.

[0062] Subsequently, a gate insulating layer is formed so as to cover the first to third conductive layers. The gate insulating layer can be formed so as to cover at least the upper surface of the first conductive layer and the side surface not in contact with the third conductive layer, the lower surface of the second conductive layer and the side surface not in contact with the third conductive layer, and the upper surface and side surface of the third conductive layer. The gate insulating layer is preferably formed by a method having high coverage. In particular, it is preferable to form the gate insulating layer by the ALD method, since it can cover the first to third conductive layers, including the lower surface of the second conductive layer, with good coverage.

[0063] Next, a metal oxide layer is formed so as to cover the gate insulating layer. The metal oxide layer is preferably formed by a method that provides high coverage, for example, by using an ALD method. This allows the metal oxide layer to be formed with good coverage in the region surrounded by the first to third conductive layers.

[0064] The metal oxide layer preferably contains at least indium (In) or zinc (Zn). For example, indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO) can be used for the metal oxide layer.

[0065] Here, for example, a semiconductor layer containing silicon is difficult to form using the ALD method. On the other hand, in order to form a semiconductor layer so as to cover the lower surface of the gate insulating layer with good coverage, it is preferable to use the ALD method. Therefore, it is preferable to use a metal oxide layer that can be formed using the ALD method as the semiconductor layer. Note that if the semiconductor layer can be formed using the ALD method, it is not necessary to use a metal oxide layer as the semiconductor layer.

[0066] Subsequently, a fourth conductive layer is formed on the metal oxide layer. The fourth conductive layer can be formed by, for example, a CVD method, an ALD method, or a sputtering method. The fourth conductive layer can be made of, for example, titanium nitride or tungsten. The fourth conductive layer can have a laminated structure of, for example, a layer containing titanium nitride and a layer containing tungsten.

[0067] Subsequently, the fourth conductive layer and the metal oxide layer are processed. For example, the fourth conductive layer and the metal oxide layer are processed in order using a photolithography method and an etching method. The fourth conductive layer and the metal oxide layer can be processed using the same mask pattern.

[0068] Next, an interlayer insulating layer is formed on the gate insulating layer and the fourth conductive layer. The interlayer insulating layer can be formed by, for example, a CVD method. The interlayer insulating layer can be made of, for example, silicon oxide.

[0069] Next, a planarization process is performed on the interlayer insulating layer, the fourth conductive layer, the metal oxide layer, the gate insulating layer, and the third conductive layer. For example, the planarization process is performed using a chemical mechanical polishing (CMP) method. The planarization process can be performed until the top surface of the second conductive layer is exposed, for example.

[0070] A fifth conductive layer and a sixth conductive layer facing the fifth conductive layer with the metal oxide layer sandwiched therebetween can be formed in a region not overlapping with the first to third conductive layers by planarization treatment of the fourth conductive layer. The fifth conductive layer and the sixth conductive layer can be formed to have a shape along the side surface of the metal oxide layer in the region not overlapping with the first to third conductive layers. The fifth conductive layer functions as one of the source and drain electrodes of the transistor. The sixth conductive layer functions as the other of the source and drain electrodes of the transistor.

[0071] A seventh conductive layer and an eighth conductive layer facing the seventh conductive layer with the first and second conductive layers interposed therebetween can be formed by planarizing the third conductive layer. The seventh conductive layer can be formed to have a region in contact with a first side surface, which is a side surface of the first conductive layer, and a region in contact with a second side surface, which is a side surface of the second conductive layer. The eighth conductive layer can be formed to have a third side surface facing the first side surface, and a region in contact with a fourth side surface facing the second side surface. The first conductive layer, the second conductive layer, the seventh conductive layer, and the eighth conductive layer function as gate electrodes of transistors.

[0072] The boundaries (interfaces) of the first conductive layer, the second conductive layer, the seventh conductive layer, and the eighth conductive layer may not be clearly identified. For example, when the first conductive layer, the second conductive layer, the seventh conductive layer, and the eighth conductive layer are made of the same material, the boundaries (interfaces) of these conductive layers may not be clearly identified.

[0073] Through the above steps, a transistor included in a semiconductor device of one embodiment of the present invention can be manufactured.

[0074] <Configuration Example 1 of Semiconductor Device> Fig. 1(A) is a perspective view showing a configuration example of a semiconductor device of one embodiment of the present invention. In Fig. 1(A), directions parallel to a surface of a substrate (not shown) are the X direction and the Y direction, and a direction perpendicular to the surface is the Z direction. The X direction, the Y direction, and the Z direction are perpendicular to each other. The above also applies to subsequent drawings unless otherwise specified.

[0075] Figures 1(B), 1(C), and 1(D) are perspective views of a portion of the configuration shown in Figure 1(A). Figure 1(B) shows a cross section in the XZ plane and a cross section in the YZ plane. Figure 1(C) shows a cross section in the XZ plane. Figure 1(D) shows a cross section in the YZ plane.

[0076] Fig. 2(A) is a plan view showing the configuration of the semiconductor device shown in Fig. 1(A) as viewed from the Z direction. Fig. 2(B) is a cross-sectional view taken along dashed line A1-A2 in Fig. 2(A). Fig. 2(C) is a cross-sectional view taken along dashed line B1-B2 in Fig. 2(A). Fig. 2(A) can also be said to show the configuration in the XY plane. Fig. 2(B) can also be said to show the configuration in the XZ plane. Fig. 2(C) can also be said to show the configuration in the YZ plane.

[0077] In the perspective views shown in Figures 1(A) to 1(D) and the plan view shown in Figure 2(A), some elements are omitted for clarity of the drawings. The same applies to the subsequent perspective views and plan views.

[0078] 1A to 1D and 2A to 2C include an insulating layer 101 over a substrate (not shown), a transistor 11 and an insulating layer 131 over the insulating layer 101, an insulating layer 133 over the insulating layer 131, an insulating layer 135 over the transistor 11, the insulating layer 131, and the insulating layer 133, and an insulating layer 137 over the insulating layer 135. The insulating layer 101, the insulating layer 133, and the insulating layer 137 function as interlayer insulating layers.

[0079] 3A and 3B are enlarged views of the transistor 11 shown in FIG. 2B and FIG. 2C, respectively. In addition to the transistor 11, insulating layers 101, 131, and 133 are also shown in FIG. 3A and FIG.

[0080] The transistor 11 includes a conductive layer 111 <1> and the conductive layer 111 <2> and the conductive layer 111 <3> The conductive layer 111 includes a conductive layer 112a, a conductive layer 112b, a semiconductor layer 113, a conductive layer 115a, a conductive layer 115b, and an insulating layer 105. <2> is a conductive layer 111 <1> A conductive layer 111 is provided on the <3> is a conductive layer 111 <2> is provided on top.

[0081] For example, as shown in FIG. <1> , conductive layer 111 <2> , and the conductive layer 111 <3> In this case, the conductive layer 111 may be a hexahedron having four sides, as shown in FIG. <1> Side 141a <1> and side 141b <1> and side 142a <1> and side 142b <1> and the side surface 141b <1> Side 141a <1> and side 142b <1> Side 142a <1> It is the side opposite to.

[0082] Side 141a <1> , and side 141b <1> , respectively, side 142a <1> and can be in contact with one side of side 142b. <1> For example, the conductive layer 111 can contact one side of the conductive layer 111. <1> When the rectangular parallelepiped is used, the side surface 141a <1> , and side 141b <1> , side 142a <1> and a side perpendicular to side 142b. <1> In addition, in Figs. 1(A) to 1(D), 2(B), 2(C), 3(A), and 3(B), the side surface 141a <1> , side 141b <1> , side 142a <1> , and side 142b <1> 1 is perpendicular to the upper surface of the insulating layer 101, <1> , side 141b <1> , side 142a <1> , and side 142b <1> may have a tapered shape.

[0083] Conductive layer 111 <2> , side 141a <2> and side 141b <2> and side 142a <2> and side 142b <2> The conductive layer 111 <3> , side 141a <3> and side 141b <3> and side 142a <3> and side 142b <3> The side surface 141a <2> , side 141b <2> , side 142a <2> , and side 142b <2> Regarding aspect 141a <1> , side 141b <1> , side 142a <1> , and side 142b <1> Similarly, the above description of the side surface 141a can be referred to. <3> , side 141b <3> , side 142a <3> , and side 142b <3> Regarding aspect 141a <1> , side 141b <1> , side 142a <1> , and side 142b <1> Please refer to the above explanation for.

[0084] In the following, the conductive layer 111 <1> , conductive layer 111 <2> , and the conductive layer 111 <3> When describing matters common to all of the above, the term may simply be referred to as the conductive layer 111. The same applies to other elements marked with the identification symbols "< >".

[0085] The conductive layer 112a is <1> Side 141a, which is a side of <1> The conductive layer 111 <2> Side 141a, which is a side of <2> and the conductive layer 111 <3> Side 141a, which is a side of <3> The conductive layer 112b has a region in contact with the side surface 141a. <1> Side 141b, which is the side opposite to <1> The area adjacent to the side surface 141a <2> Side 141b, which is the side opposite to <2> and the side surface 141a <3> Side 141b, which is the side opposite to <3> Conductive layer 112a has a region along side surface 141a and a region along the upper surface of insulating layer 101. Conductive layer 112b has a region along side surface 141b and a region along the upper surface of insulating layer 101.

[0086] As a result, the transistor 11 includes the conductive layer 111 <1> , conductive layer 111 <2> A region surrounded by the conductive layers 112a and 112b and a region surrounded by the conductive layer 111 <2> , conductive layer 111 <3> , a region surrounded by the conductive layer 112a, and a region surrounded by the conductive layer 112b.

[0087] The insulating layer 105 is a conductive layer 111 <1> , conductive layer 111 <2> , conductive layer 111 <3> The insulating layer 105 is provided to cover at least a part of the conductive layer 111, the conductive layer 112a, and the conductive layer 112b. <1> On the top surface of the conductive layer 111 <2> The lower surface of the conductive layer 111 <2> On the top surface of the conductive layer 111 <3> The lower surface of the conductive layer 111 <1> Conductive layer 111 <3> The side surface of the conductive layer 111 that is not in contact with the conductive layer 112a and the conductive layer 111 <1> Conductive layer 111 <3> The insulating layer 112 is provided so as to cover the side surface not in contact with the conductive layer 112b.

[0088] The insulating layer 105 is a conductive layer 111 <1> and conductive layer 111 <2> Specifically, the area between the conductive layer 111 <1> , conductive layer 111 <2> In a region surrounded by the conductive layer 112a and the conductive layer 112b, the conductive layer 111 <1> the area in contact with the upper surface of the conductive layer 111 <2> The insulating layer 105 has a region in contact with the bottom surface of the conductive layer 111, a region in contact with the side surface of the conductive layer 112a, and a region in contact with the side surface of the conductive layer 112b. <2> and conductive layer 111 <3> Specifically, the area between the conductive layer 111 <2> , conductive layer 111 <3> In a region surrounded by the conductive layer 112a and the conductive layer 112b, the conductive layer 111 <2> the area in contact with the upper surface of the conductive layer 111 <3> The conductive layer 112a has a region in contact with a bottom surface of the conductive layer 112b, a region in contact with a side surface of the conductive layer 112a, and a region in contact with a side surface of the conductive layer 112b.

[0089] For example, as shown in FIG. 3B, the insulating layer 105 is a conductive layer 111. <1> Side 142a, which is a side of <1> and the side surface 142a <1> Side 142b, which is the side opposite to <1> The insulating layer 105 has a region in contact with the conductive layer 111. <2> Side 142a, which is a side of <2> and the side surface 142a <2> Side 142b, which is the side opposite to <2> Further, the insulating layer 105 has a region in contact with the conductive layer 111. <3> Side 142a, which is a side of <3> and the side surface 142a <3> Side 142b, which is the side opposite to <3> It has an area in contact with.

[0090] The insulating layer 105 has a region in contact with the side surfaces of the conductive layer 112a other than the side surface 141a and the side surfaces of the conductive layer 112b other than the side surface 141b. The insulating layer 105 has a region in contact with the upper surfaces of the conductive layers 112a and 112b other than their uppermost surfaces, in other words, the upper surfaces of the regions having a shape along the upper surface of the insulating layer 101.

[0091] In this specification, the top surface of a layer refers to the top surface that is the highest among the multiple top surfaces of the layer from a reference surface. Also, the bottom surface of a layer refers to the bottom surface that is the lowest among the multiple bottom surfaces of the layer from a reference surface. The reference surface is preferably a flat surface. The reference surface can be, for example, the surface of the substrate or the top surface of the insulating layer 101.

[0092] The semiconductor layer 113 is a conductive layer 111 with an insulating layer 105 sandwiched therebetween. <1> , conductive layer 111 <2> , the conductive layer 112a, and the conductive layer 112b. <1> The insulating layer 105 is sandwiched between the conductive layer 111 and the conductive layer 111. <2> , conductive layer 111 <3> , the conductive layer 112a, and the conductive layer 112b. <2> and. Area 143 <1> In the above, the lower surface, the upper surface, and the side surfaces of the semiconductor layer 113 are in contact with the conductive layer 111. <1> , conductive layer 111 <2> , conductive layer 112a, and conductive layer 112b. <2> In the above, the lower surface, the upper surface, and the side surfaces of the semiconductor layer 113 are in contact with the conductive layer 111. <2> , conductive layer 111 <3> , the conductive layer 112a, and the conductive layer 112b. Note that the region 143 can be said to be a layer, specifically, a layer included in the semiconductor layer 113. In this case, it can be said that the semiconductor layer 113 includes a layer overlapping with the conductive layer 111, specifically, a layer surrounded by the conductive layer 111, the conductive layer 112a, and the conductive layer 112b.

[0093] 3A, the conductive layers 111 and the regions 143 are provided alternately. Specifically, the conductive layers 111 are provided in the bottom and top layers, and the regions 143 are provided between the conductive layers 111.

[0094] The semiconductor layer 113 has a region that does not overlap with the conductive layer 111, the conductive layer 112a, and the conductive layer 112b. As shown in Figures 1(A), 1(B), 1(D), 2(A), 2(C), and 3(B), the semiconductor layer 113 has two regions that do not overlap with the conductive layer 111, the conductive layer 112a, and the conductive layer 112b, and these two regions can be said to face each other with the conductive layer 111 and the insulating layer 105 interposed therebetween.

[0095] As shown in FIG. 3B, in the above region, the semiconductor layer 113 has a side surface 142a with the insulating layer 105 interposed therebetween. <1> and the region 144a facing <1> and the side surface 142b with the insulating layer 105 interposed therebetween. <1> and the region 144b facing <1> The insulating layer 105 is sandwiched between the side surface 142a <2> and the region 144a facing <2> and the side surface 142b with the insulating layer 105 interposed therebetween. <2> and the region 144b facing <2> The insulating layer 105 is sandwiched between the side surface 142a <3> and the region 144a facing <3> and the side surface 142b with the insulating layer 105 interposed therebetween. <3> and the region 144b facing <3> Here, the bottom surface of the semiconductor layer 113 is the conductive layer 111. <1> The bottom surface of the semiconductor layer 113 may be located above the bottom surface of the conductive layer 111. <1> The insulating layer 105 may be located at a position higher than the lower surface of the insulating layer 105 by, for example, the thickness of the insulating layer 105.

[0096] From the above, the conductive layer 111 <1> Side 142a <1> Part of and side 142b <1> A part of the insulating layer 105 may be a region that does not face the semiconductor layer 113. <1> If the thickness is greater than the thickness of the semiconductor layer 113, the semiconductor layer 113 may <1> , and region 144b <1> It is possible to adopt a configuration that does not have the above.

[0097] The conductive layer 115a and the conductive layer 115b are provided outside (opposite side to the conductive layer 111) a region of the semiconductor layer 113 that does not overlap with the conductive layer 111, the conductive layer 112a, and the conductive layer 112b. The conductive layer 115a and the conductive layer 115b are provided to face each other with the conductive layer 111, the insulating layer 105, and the semiconductor layer 113 interposed therebetween. As shown in FIG. 3B, the conductive layer 115a is provided in the region 144a. <2> and the side surface 142a with the insulating layer 105 interposed therebetween. <2> and the area 144a <3> and the side surface 142a with the insulating layer 105 interposed therebetween. <3> The conductive layer 115b has a region facing the semiconductor layer 113 and is provided to be electrically connected to the semiconductor layer 113. <2> and the side surface 142b with the insulating layer 105 interposed therebetween. <2> and the area 144b <3> and the side surface 142b with the insulating layer 105 interposed therebetween. <3> and is provided so as to be electrically connected to the semiconductor layer 113.

[0098] The conductive layer 115a and the conductive layer 115b have a region having a shape along the side surface of the semiconductor layer 113 in a region that does not overlap with the conductive layer 111, the conductive layer 112a, and the conductive layer 112b, and a region along the upper surface other than the uppermost surface. <2> and region 144a <3> The conductive layer 115b has a shape along the side including the region 144b of the semiconductor layer 113. <2> and region 144b <3> The shape along the side includes:

[0099] In the semiconductor device having the above structure, the conductive layer 111, the conductive layer 112a, and the conductive layer 112b function as a gate electrode of the transistor 11. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 11. The conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor 11. The insulating layer 105 functions as a gate insulating layer of the transistor 11.

[0100] From the above, the transistor 11 can be a transistor in which the gate electrode surrounds the upper surface, lower surface, and side surface of the semiconductor layer 113 in a predetermined cross-sectional view. Therefore, the transistor 11 is a transistor with a GAA structure. Furthermore, a channel is formed in the region 143 of the semiconductor layer 113 surrounded by the gate electrode. Here, the region 143 of the semiconductor layer 113 can have a flat upper surface. Therefore, the transistor 11 can be said to be a transistor with a nanosheet structure.

[0101] 1A to 1D, 2A to 2C, 3A, and 3B can be set as a channel length direction. One of a region of the semiconductor layer 113 in contact with the conductive layer 115a and a region of the semiconductor layer 113 in contact with the conductive layer 115b can be set as a source region, and the other can be set as a drain region. For example, of two regions of the semiconductor layer 113 that do not overlap with the gate electrode and face each other with the gate electrode therebetween, one can be set as a source region, and the other can be set as a drain region.

[0102] By using the transistor 11 as a GAA transistor, an electric field for inducing a channel in the semiconductor layer 113 can be applied more effectively than when the gate electrode covers, for example, only the top surface, the top and side surfaces, or the top and bottom surfaces of the semiconductor layer 113. Thus, the transistor 11 can have a large on-state current. Therefore, the semiconductor device of one embodiment of the present invention can have a high operating speed.

[0103] Here, in the manufacturing process of the transistor 11, the conductive layer 111 and a sacrificial layer on the conductive layer 111 are alternately formed, and then a conductive film which will become the conductive layer 112a and the conductive layer 112b in a later step is formed so as to cover the conductive layer 111 and the sacrificial layer, and then the sacrificial layer is removed. Therefore, if the adhesion between the conductive layer 111 and the conductive film which will become the conductive layer 112a and the conductive layer 112b in a later step is poor, the conductive layer 111 may fall off after the sacrificial layer is removed. In the examples shown in FIGS. 1(A) to 1(D), 2(A) to 2(C), 3(A), and 3(B), the conductive layer 111 <2> , and the conductive layer 111 <3> In order to improve the adhesion between the conductive layer 111 and the conductive layers 112a and 112b, the conductive layers 112a and 112b are preferably made of the same material as the conductive layer 111. Specifically, the conductive layers 112a and 112b are preferably made of the same material as the conductive layer 111. <2> , and the conductive layer 111 <3> It is preferred that the material be the same as that of the first embodiment.

[0104] The boundaries (interfaces) of the conductive layers 111, 112a, and 112b may not be clearly identified. For example, when the conductive layers 111, 112a, and 112b are made of the same material, the boundaries (interfaces) of these conductive layers may not be clearly identified.

[0105] In addition, in the manufacturing process of the transistor 11, the conductive layer 111 and the sacrificial layer on the conductive layer 111 are alternately formed, and then these layers are processed, for example, with the same mask pattern. In this case, it is preferable that the conductive layer 111 is thinner in thickness because the conductive layer 111 can be prevented from being processed in the horizontal direction. In FIG. 3A, the conductive layer 111 <1> The thickness of the film is T111 <1> , conductive layer 111 <2> The thickness of the film is T111 <2> , conductive layer 111 <3> The thickness of the film is T111 <3> The thickness T111 is preferably 0.1 nm or more and 100 nm or less, more preferably 0.3 nm or more and 50 nm or less, more preferably 0.5 nm or more and 20 nm or less, and further preferably 0.5 nm or more and 10 nm or less.

[0106] The conductive layers 112a and 112b, which will be described in detail later, can be formed by forming a conductive film so as to cover the conductive layer 111 and the sacrificial layer, and then processing the conductive film. The processing of the conductive film differs from the processing of the conductive layer 111 in that, for example, multiple conductive layers overlapping with a sacrificial layer sandwiched therebetween do not need to be processed with the same mask pattern. Therefore, the thickness T112a of the conductive layer 112a and the thickness T112b of the conductive layer 112b are the thickness T111. <1> , thickness T111 <2> , and thickness T111 <3> The thickness T112a and the thickness T112b can be equal to or greater than at least one of the thicknesses T111 and T112b. <1> , thickness T111 <2> , and thickness T111 <3> It can be thicker. In the region of the conductive layer 112a along the side surface 141a, the thickness T112a can be the distance between the side surface of the conductive layer 112a and the side surface of the conductive layer 112a facing the side surface. Similarly, in the region of the conductive layer 112b along the side surface 141b, the thickness T112b can be the distance between the side surface of the conductive layer 112b and the side surface of the conductive layer 112b facing the side surface. By increasing the thickness T112a, the electrical resistivity of the conductive layer 112a can be reduced, and by increasing the thickness T112b, the electrical resistivity of the conductive layer 112b can be reduced.

[0107] Furthermore, in the manufacturing process of the transistor 11, after removing the sacrificial layer, the insulating layer 105 is formed so as to cover the conductive layer 111 and the conductive film that will become the conductive layer 112a and the conductive layer 112b. Then, the semiconductor layer 113 is formed so as to cover the insulating layer 105. Here, if the semiconductor layer 113 is formed by a method with high coverage, for example, the conductive layer 111 <1> and conductive layer 111 <2> and the conductive layer 111 <2> and conductive layer 111 <3> This is preferable because the semiconductor layer 113 can be formed in the region between the first and second electrodes with good coverage.

[0108] Here, for example, a semiconductor layer containing silicon is difficult to form by the ALD method. On the other hand, in order to form the semiconductor layer 113 so as to cover the insulating layer 105 including its lower surface with good coverage, it is preferable to use the ALD method. Therefore, it is preferable to use a metal oxide layer that can be formed by the ALD method as the semiconductor layer 113. Note that if the semiconductor layer 113 can be formed by the ALD method, it is not necessary to use a metal oxide layer as the semiconductor layer 113.

[0109] When the semiconductor layer 113 is a metal oxide layer, it is preferable that the semiconductor layer 113 contains at least indium (In) or zinc (Zn). For example, indium gallium zinc oxide (In-Ga-Zn oxide) can be used for the semiconductor layer 113.

[0110] In FIG. 1A to FIG. 1D, FIG. 2B, FIG. 2C, FIG. 3A, and FIG. 3B, the transistor 11 includes three conductive layers 111 (conductive layer 111 <1> , conductive layer 111 <2> , and the conductive layer 111 <3> 3A, the semiconductor layer 113 has two regions 143 (regions 143) located between the two conductive layers 111. <1> , and area 143 <2> ) is shown. Here, the transistor 11 may have two conductive layers 111. In this case, the semiconductor layer 113 may have one region 143. The transistor 11 may have four or more conductive layers 111. In this case, the semiconductor layer 113 may have three or more regions 143. When the transistor 11 has n conductive layers 111 (n is an integer of 2 or more), the semiconductor layer 113 may have n-1 regions 143.

[0111] The larger the number of regions 143 in the semiconductor layer 113, that is, the larger n, the larger the volume of the region surrounded by the gate electrode of the semiconductor layer 113 can be without increasing the channel length of the transistor 11. As a result, the on-state current of the transistor 11 can be increased. Therefore, the operating speed of the semiconductor device of one embodiment of the present invention can be increased. On the other hand, the larger n, the more manufacturing steps of the semiconductor device are required. Thus, the manufacturing cost of the semiconductor device may increase, and for example, the price of the semiconductor device may become high. Therefore, it is preferable to determine n in consideration of the performance and price of the semiconductor device.

[0112] The insulating layer 131 has a region located over the insulating layer 105, a region located over the conductive layer 115a, and a region located over the conductive layer 115b. In a region not overlapping with the conductive layer 111, the insulating layer 131 is provided to cover the insulating layer 105, the semiconductor layer 113, the conductive layer 115a, and the conductive layer 115b.

[0113] An insulating layer 133 is provided on the insulating layer 131. The insulating layer 133 may be a planarized layer. In this case, the conductive layer 111 <3> The top surface of the insulating layer 105, the top surface of the insulating layer 131, and the top surface of the insulating layer 133 can be made to have the same or approximately the same height from the reference plane as each other.

[0114] Conductive layer 111 <3> An insulating layer 135 is provided on the conductive layers 112a, 112b, 115a, 115b, the insulating layer 105, the insulating layer 131, and the insulating layer 133, and an insulating layer 137 is provided on the insulating layer 135.

[0115] The transistor 11 is covered with the insulating layer 131 and the insulating layer 135. Specifically, the semiconductor layer 113 included in the transistor 11 is covered with the insulating layer 131 and the insulating layer 135. Therefore, the insulating layer 131 and the insulating layer 135 preferably have a barrier property against impurities such as water and hydrogen. This can suppress diffusion of impurities from the outside of the transistor 11 to the transistor 11. In particular, diffusion of impurities to the semiconductor layer 113, which can be a metal oxide layer, for example, can be suppressed. This can improve the electrical characteristics of the transistor 11 and increase its reliability. Thus, the reliability of the semiconductor device of one embodiment of the present invention can be increased. Here, the insulating layer 133 provided over the insulating layer 131 and the insulating layer 137 provided over the insulating layer 135 preferably function as interlayer insulating layers as described above and are planarized.

[0116] 2D and 2E are diagrams illustrating the conductive layer 111 shown in FIG. 2B and FIG. 2C, respectively. <3> 1 is a cross-sectional view showing an example in which a sacrificial layer 123a is provided on the conductive layer 111 due to a manufacturing process of a semiconductor device described later. <3> and insulating layer 135. In this case, the upper surface of sacrificial layer 123a can be made to coincide or approximately coincide with the height from the reference plane of the uppermost surface of conductive layer 112a, the uppermost surface of conductive layer 112b, the uppermost surface of conductive layer 115a, the uppermost surface of conductive layer 115b, the uppermost surface of insulating layer 105, the uppermost surface of insulating layer 131, and the upper surface of insulating layer 133.

[0117] The sacrificial layer 123a may be made of, for example, a material shown in [Insulating Layer] described later. The sacrificial layer 123a may be made of, for example, an inorganic insulating film, specifically, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film. The sacrificial layer 123a may be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Note that the sacrificial layer 123a may be made of a semiconductor material or a conductive material.

[0118] <Materials for semiconductor devices> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that, unless otherwise specified, each layer constituting the semiconductor device of this embodiment may have a single layer structure or a multilayer structure.

[0119] [Semiconductor layer] As described above, the semiconductor layer 113 has a channel formation region. The channel formation region is i-type (intrinsic) or substantially i-type. The semiconductor layer 113 further has a source region and a drain region. The source region and the drain region are n-type regions (low resistance regions) having a higher carrier concentration than the channel formation region.

[0120] The crystallinity of a semiconductor material used for the semiconductor layer 113 is not particularly limited, and any of an amorphous semiconductor, a single crystalline semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0121] As described above, a metal oxide layer can be used as the semiconductor layer 113. In the following, materials that can be used for the semiconductor layer 113 will be described on the assumption that the semiconductor layer 113 is a metal oxide layer.

[0122] The band gap of the metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a large band gap, the off-current of a transistor can be reduced. Since the off-current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, since the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0123] Examples of metal oxides that can be used for the semiconductor layer 113 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification and the like may include metalloid elements.

[0124] The semiconductor layer 113 may be formed of, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), or the like. Indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO), etc., can be used. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0125] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0126] The metal oxide may have one or more metal elements having a large period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element having a large period number in the periodic table, the field effect mobility of the transistor may be increased. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0127] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the carrier concentration may be increased, the band gap may be narrowed, or the like, and the field effect mobility of the transistor may be increased. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, bromine, and hydrogen.

[0128] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0129] Moreover, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, a metal oxide having a large band gap can be obtained. Furthermore, formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, a shift in the threshold voltage of the transistor can be suppressed. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0130] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used for the semiconductor layer 113. Thus, by varying the composition of the metal oxide in accordance with the electrical characteristics and reliability required of a transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be provided.

[0131] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn=1:1:0.5, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:1:2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, and compositions in the vicinity thereof. The term "composition in the vicinity" includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, or the like of a transistor can be increased.

[0132] In addition, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0133] When the element M contains a plurality of metal elements, the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of the element M.

[0134] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.

[0135] In addition, when the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements of the In-Zn oxide may be, for example, In:Zn=1:1, In:Zn=2:1, In:Zn=4:1, or a composition close to these. The In-Zn oxide may also contain a trace amount of element M. For example, when the element M is Sn, the atomic ratio of the metal elements of the metal oxide may be, for example, In:Sn:Zn=2:0.1:1, In:Sn:Zn=4:0.1:1, or a composition close to these.

[0136] The composition of the metal oxide used in the semiconductor layer 113 can be analyzed by, for example, energy dispersive X-ray spectrometry (EDX), XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that, for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content. In addition, it may be difficult to quantify element M, or element M may not be detected.

[0137] The crystallinity of the semiconductor material used for the semiconductor layer 113 is not particularly limited, and any of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0138] Each of the semiconductor layers 113 preferably has a metal oxide layer having crystallinity. Examples of the structure of the metal oxide having crystallinity include a c-axis aligned crystal (CAAC) structure, a polycrystal (Poly-crystal) structure, and a nanocrystal (nc) structure. By using a metal oxide layer having crystallinity for the semiconductor layer 113, the density of defect states in the semiconductor layer 113 can be reduced, and a highly reliable semiconductor device can be realized. Note that the CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of IGZO microcrystals) have a c-axis alignment, and the plurality of microcrystals are connected without being oriented in the ab plane. In addition, when a cross section of an OS film having a CAAC structure is observed using a high-resolution TEM image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal portion. Therefore, the OS film having a CAAC structure can be said to have a structure having a layered crystal portion.

[0139] The polycrystalline structure has grain boundaries. In addition, when a heat treatment is performed after forming a metal oxide layer having a polycrystalline structure, a minute gap (also called a nanocrack or a microcrack) or a minute space (also called a nanospace or a microspace) may be formed between the crystal parts. When a minute gap or a minute space is formed in the metal oxide layer, the electric resistance of the metal oxide layer increases. This is because the electric resistance of the minute gap or minute space is very high, for example, infinite. When a metal oxide layer having a minute gap or minute space is used in a channel formation region of a transistor, the contact resistance between the metal oxide layer and one or both of the source electrode and the drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. The CAAC structure has fewer grain boundaries in the ab plane than the polycrystalline structure, and therefore can realize a highly reliable semiconductor device.

[0140] The higher the crystallinity of the semiconductor layer 113, the more the density of defect states in the semiconductor layer 113 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0141] The higher the substrate temperature (stage temperature) during the formation of the metal oxide layer, the higher the crystallinity of the metal oxide layer that can be formed. Also, the higher the ratio of the flow rate of oxygen gas to the total deposition gas used during the formation (hereinafter, also referred to as oxygen flow rate ratio), the higher the crystallinity of the metal oxide layer that can be formed.

[0142] The crystallinity of the semiconductor layer 113 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0143] The thickness of the semiconductor layer 113 is preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, further preferably 20 nm to 50 nm. In a transistor used in a finer semiconductor device, the thickness of the semiconductor layer 113 is preferably 1 nm to 20 nm, 1 nm to 15 nm, 3 nm to 12 nm, or 5 nm to 10 nm.

[0144] Hydrogen contained in the semiconductor layer 113 reacts with oxygen that bonds with metal atoms to form water, and oxygen vacancies (V O In addition, defects in which hydrogen is inserted into oxygen vacancies (hereafter referred to as V OHydrogen atoms in the metal oxide (represented as H) may function as donors and generate electrons as carriers. Some of the hydrogen atoms may bond with oxygen that bonds with metal atoms to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics (that is, a threshold voltage having a negative value). Furthermore, hydrogen in a metal oxide is easily mobile due to stress such as heat or an electric field. Therefore, if the semiconductor layer 113 contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.

[0145] V in semiconductor layer 113 O It is preferable to reduce H as much as possible and make the semiconductor layer 113 highly intrinsic or substantially highly intrinsic. O In order to obtain a metal oxide with a sufficiently reduced amount of H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes called dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to repair the oxygen vacancies. O Stable electrical characteristics can be imparted by using a metal oxide in which impurities such as H are sufficiently reduced in the channel formation region of a transistor. Note that supplying oxygen to a metal oxide to repair oxygen vacancies is sometimes referred to as oxygen addition treatment.

[0146] The carrier concentration of the metal oxide in the region that functions as the channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the region functioning as the channel formation region is not particularly limited, but is, for example, 1×10 -9 cm -3 It can be said that:

[0147] Here, the influence of each impurity in the metal oxide will be described.

[0148] When a metal oxide contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the metal oxide. Therefore, the carbon concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The silicon concentration in the metal oxide channel formation region obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The following applies.

[0149] Furthermore, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, the carrier concentration increases, and the metal oxide is likely to become n-type. As a result, a transistor using a nitrogen-containing metal oxide as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in a metal oxide, a trap level may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0150] In addition, hydrogen contained in the metal oxide reacts with oxygen that bonds to metal atoms to form water, which may form oxygen vacancies. Hydrogen entering the oxygen vacancies may generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that bonds to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using a metal oxide that contains hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen as much as possible in the channel formation region of the metal oxide. Specifically, the hydrogen concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×1018 atoms / cm 3 Less than.

[0151] In addition, when an alkali metal or an alkaline earth metal is contained in a metal oxide, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the metal oxide obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0152] By using a metal oxide with sufficiently reduced impurities for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0153] [Insulation layer] For each of the insulating layers (insulating layer 105, insulating layer 131, insulating layer 133, insulating layer 135, insulating layer 137, etc.) included in the semiconductor device, an inorganic insulating film is preferably used. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and an oxide (hafnium aluminate) film containing aluminum and hafnium. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film may be used for the insulating layer of the semiconductor device.

[0154] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a material with a high dielectric constant (high-k) for the gate insulating layer, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. It also becomes possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, by using a material with a low dielectric constant for the insulating layer that functions as an interlayer insulating layer, it is possible to reduce the parasitic capacitance that occurs between conductive layers. Therefore, it is advisable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0155] Examples of high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0156] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Examples of other inorganic insulating materials with a low relative dielectric constant include silicon oxide to which fluorine is added, silicon oxide to which carbon is added, and silicon oxide to which carbon and nitrogen are added. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0157] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. Examples of the material capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X(X is a real number greater than 0). Examples of materials that can have ferroelectricity include materials obtained by adding an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 can be set appropriately, for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Examples of materials that can have ferroelectricity include materials obtained by adding an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. Also, the ratio of the number of zirconium atoms to the number of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. In addition, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as lead zirconate titanate (PZT), strontium tantalate bismuthate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0158] In addition, examples of materials that can have ferroelectricity include metal nitrides having an element M1, an element M2, and nitrogen. Here, the element M1 is one or more selected from aluminum, gallium, and indium. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium. The ratio of the number of atoms of the element M1 to the number of atoms of the element M2 can be set appropriately. In addition, metal oxides having the element M1 and nitrogen may have ferroelectricity even if they do not contain the element M2. In addition, examples of materials that can have ferroelectricity include materials in which the element M3 is added to the above metal nitride. In addition, the element M3 is one or more selected from magnesium, calcium, strontium, zinc, and cadmium. Here, the ratio between the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0159] Moreover, examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N or BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0160] In the above description, metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto. For example, metal oxide nitrides in which nitrogen is added to the above-mentioned metal oxides, or metal nitride oxides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

[0161] As a material capable of having ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer of the semiconductor device can have a laminated structure made of a plurality of materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change not only depending on the film formation conditions but also depending on, for example, various processes. Therefore, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials capable of having ferroelectricity.

[0162] Metal oxides containing hafnium and / or zirconium can have ferroelectricity even when processed into a thin film of a few nm. Metal oxides containing hafnium and / or zirconium can have ferroelectricity even in a very small area. Therefore, by using metal oxides containing hafnium and / or zirconium, it is possible to miniaturize semiconductor devices.

[0163] In this specification, a layer of a material that may have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0164] It is believed that ferroelectricity is expressed by displacing oxygen or nitrogen in the crystals contained in the ferroelectric layer due to an external electric field. It is also presumed that the expression of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to express ferroelectricity, the insulating layer needs to contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, since ferroelectricity is expressed. The crystal structure of the crystals contained in the insulating layer may be one or more selected from a cubic crystal system, a tetragonal crystal system, an orthorhombic crystal system, a monoclinic crystal system, and a hexagonal crystal system. The insulating layer may have an amorphous structure. In this case, the insulating layer may be a composite structure having an amorphous structure and a crystalline structure.

[0165] In addition, by adding a Group 3 element (also called IIIa element) in the periodic table to a metal oxide containing either or both of hafnium and zirconium, the oxygen vacancy concentration in the oxide increases, and crystals having an orthorhombic crystal structure are easily formed. This is preferable because the proportion of crystals having an orthorhombic crystal structure increases, and the remanent polarization can be increased. On the other hand, if the amount of the Group 3 element added is too large, the crystallinity of the oxide decreases, and ferroelectricity may not be easily expressed. Therefore, the content of the Group 3 element in the metal oxide containing either or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0166] In addition, the transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer having a function of suppressing the transmission of impurities and oxygen. As the insulating layer having a function of suppressing the transmission of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specifically, as a material for the insulating layer having a function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0167] Specifically, examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include hafnium aluminate. Examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0168] In addition, an insulating layer such as a gate insulating layer that is in contact with a metal oxide layer or that is provided near a metal oxide layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, may be referred to as excess oxygen). For example, an insulating layer having a region containing excess oxygen is in contact with a metal oxide layer or is located near the metal oxide layer, whereby oxygen vacancies in the metal oxide layer can be reduced. Examples of insulating layers that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0169] Since the insulating layer 101, the insulating layer 133, and the insulating layer 137 function as interlayer insulating layers, it is preferable that the insulating layer 101, the insulating layer 133, and the insulating layer 137 have a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer insulating layer, the parasitic capacitance generated between conductive layers can be reduced. Silicon oxide and silicon oxynitride are each thermally stable, and therefore are suitable for the insulating layer 101, the insulating layer 133, and the insulating layer 137.

[0170] The concentrations of impurities such as water and hydrogen are preferably reduced in the insulating layers 101, 133, and 137. This can prevent impurities such as water and hydrogen from entering a channel formation region of the semiconductor layer 113, for example.

[0171] It is preferable to use a barrier insulating layer against impurities such as water and hydrogen as the insulating layer 131 and the insulating layer 135. In particular, it is preferable to use a barrier insulating layer against hydrogen as the insulating layer 131 and the insulating layer 135. Examples of a material for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, and the like.

[0172] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that has low permeability of a corresponding substance, or a function of suppressing the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. - In addition, impurities when described as a corresponding substance refer to impurities in the channel formation region or the semiconductor layer unless otherwise specified, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. In addition, oxygen when described as a corresponding substance refers to at least one of, for example, oxygen atoms, oxygen molecules, etc.

[0173] The insulating layer 105 preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the semiconductor layer 113 (particularly, the hydrogen concentration in the channel formation region of the transistor). O By reducing H, the channel formation region can be made i-type or substantially i-type.

[0174] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and hafnium aluminate. These metal oxides may further contain zirconium, and examples include oxides containing hafnium and zirconium. Here, in metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, so that they have a high ability to capture or fix hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, the amorphous structure may be realized by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Note that the metal oxide may have one or both of a crystalline region and a crystal grain boundary in a part.

[0175] The function of capturing or fixing a corresponding substance can also be said to have a property that makes it difficult for the corresponding substance to diffuse. Therefore, the function of capturing or fixing a corresponding substance can be rephrased as a barrier property.

[0176] The above-mentioned barrier insulating layer against hydrogen is preferably used as the insulating layer 105. By using a barrier insulating layer against hydrogen for the insulating layer 105, impurities contained in the conductive layer 111, the conductive layer 112a, and the conductive layer 112b can be prevented from diffusing into the semiconductor layer 113. For example, silicon nitride has a high barrier property against hydrogen and is therefore suitable for the insulating layer 105. Furthermore, the insulating layer 105 may include an insulating layer having a structure that is stable against heat, such as silicon oxide or silicon oxynitride.

[0177] With such a structure, a semiconductor device having good electrical characteristics, a highly reliable semiconductor device, a semiconductor device with less variation in the electrical characteristics of the transistors, and a semiconductor device with a large on-current can be provided.

[0178] Additionally, the insulating layer 105 may comprise an insulating layer of a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0179] Furthermore, the insulating layer 105 may have an insulating layer having a thermally stable structure between a pair of insulating layers having the functions of capturing and fixing hydrogen.

[0180] The insulating layer 105 preferably has a barrier insulating layer against oxygen, which can suppress oxidation of the conductive layer 111, the conductive layer 112a, the conductive layer 112b, and the like. When the insulating layer 105 has a stacked-layer structure, a layer in contact with the conductive layer 111, the conductive layer 112a, and the conductive layer 112b is preferably a barrier insulating layer against oxygen.

[0181] Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, hafnium aluminate, and hafnium silicate.

[0182] Each layer constituting the insulating layer 105 is preferably a thin film. For example, the insulating layer 105 has a thickness of 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also called S value), which is one of the transistor characteristics. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage kept constant in the subthreshold region.

[0183] The insulating layer 105 can have a two-layer structure in which a first insulating layer and a second insulating layer are stacked in this order from the semiconductor layer 113 side. In this case, the first insulating layer is preferably made of a material with a low relative dielectric constant. As the material with a low relative dielectric constant, silicon oxide or silicon oxynitride is preferably used. In this case, the first insulating layer contains at least silicon and oxygen. The first insulating layer is a layer in contact with the semiconductor layer 113. By using an oxide insulating layer for the first insulating layer, oxygen can be supplied to the semiconductor layer 113. Furthermore, by providing the second insulating layer, oxygen contained in the first insulating layer can be prevented from diffusing to the conductive layer 111, the conductive layer 112a, and the conductive layer 112b, and the conductive layer 111, the conductive layer 112a, and the conductive layer 112b can be prevented from being oxidized. Furthermore, a decrease in the amount of oxygen supplied from the first insulating layer to the semiconductor layer 113 can be prevented.

[0184] The first insulating layer preferably has a function of trapping or fixing hydrogen. When the first insulating layer has a function of trapping or fixing hydrogen, hydrogen contained in the semiconductor layer 113 can be more effectively trapped or fixed. Thus, the hydrogen concentration in the semiconductor layer 113 can be reduced. For example, hafnium silicate is preferably used for the first insulating layer. In addition, the first insulating layer preferably has an amorphous structure.

[0185] By making the first insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the film of the first insulating layer. This makes it possible to uniformize the film thickness distribution of the first insulating layer and reduce the number of parts with extremely thin film thickness, thereby improving the withstand voltage of the first insulating layer. In addition, it is possible to uniformize the film thickness distribution of the film provided on the first insulating layer.

[0186] Moreover, by suppressing the formation of grain boundaries in the first insulating layer, it is possible to reduce leakage current caused by defect levels in the grain boundaries, and therefore the first insulating layer can function as an insulating film with low leakage current.

[0187] In addition, hafnium oxide is a high-k material, so hafnium silicate can be a high-k material depending on the silicon content. Therefore, when the first insulating layer is used as a gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. In addition, it is possible to reduce the EOT.

[0188] The second insulating layer preferably includes a barrier insulating layer against hydrogen. By using a barrier insulating layer against hydrogen for the second insulating layer, impurities contained in the conductive layer 111, the conductive layer 112a, and the conductive layer 112b can be prevented from diffusing into the semiconductor layer 113. Silicon nitride is suitable for the second insulating layer because it has a high barrier property against hydrogen. When silicon nitride is used for the second insulating layer, the second insulating layer contains silicon and nitrogen.

[0189] The second insulating layer preferably has a barrier insulating layer against oxygen, which can prevent the conductive layers 111, 112a, and 112b from being oxidized. In addition, oxygen contained in the semiconductor layer 113 can be prevented from diffusing into the conductive layers 111, 112a, and 112b, which can prevent oxygen vacancies from being formed in the semiconductor layer 113.

[0190] With such a structure, a semiconductor device having good electrical characteristics, a highly reliable semiconductor device, a semiconductor device with less variation in the electrical characteristics of the transistors, and a semiconductor device with a large on-current can be provided.

[0191] The insulating layer 105 may have a three-layer structure in which a first insulating layer, a third insulating layer, and a second insulating layer are stacked in this order from the semiconductor layer 113 side. That is, the third insulating layer may be provided between the first insulating layer and the second insulating layer.

[0192] For example, it is preferable to use a material with a low relative dielectric constant for the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen for the third insulating layer. Specifically, it is preferable to use silicon oxide for the first insulating layer and hafnium oxide for the third insulating layer. In this case, the first insulating layer contains silicon and oxygen, and the third insulating layer contains hafnium and oxygen. With this structure, oxygen can be supplied to the semiconductor layer 113. In addition, hydrogen contained in the semiconductor layer 113 can be captured or fixed more effectively.

[0193] Alternatively, for example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and to use a material having a low relative dielectric constant as the third insulating layer. Specifically, it is preferable to use hafnium oxide as the first insulating layer, and silicon oxide as the third insulating layer. In this case, the first insulating layer contains hafnium and oxygen, and the third insulating layer contains silicon and oxygen. With such a structure, oxygen can be supplied to the semiconductor layer 113. In addition, hydrogen contained in the semiconductor layer 113 can be captured or fixed more effectively.

[0194] The second insulating layer may have the above-mentioned structure.

[0195] The insulating layer 105 may have a four-layer structure in which a fourth insulating layer, a first insulating layer, a third insulating layer, and a second insulating layer are stacked in this order from the semiconductor layer 113 side. That is, in the above-mentioned three-layer stacked structure, a fourth insulating layer may be added to the layer closest to the semiconductor layer 113. The fourth insulating layer may be a layer in contact with the semiconductor layer 113.

[0196] The first to third insulating layers can have the above-described configuration.

[0197] The fourth insulating layer preferably has a barrier property against oxygen. As described above, the fourth insulating layer is a layer in contact with the semiconductor layer 113. When the fourth insulating layer has a barrier property against oxygen, oxygen can be prevented from being released from the semiconductor layer 113. For the fourth insulating layer, for example, aluminum oxide can be used. In this case, the fourth insulating layer contains aluminum and oxygen. Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 113.

[0198] In order to miniaturize the transistor, it is preferable that each of the first to fourth insulating layers has a thin film thickness. The film thickness of each of the first to fourth insulating layers is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each of the first to fourth insulating layers has a region with the above film thickness in at least a part thereof.

[0199] Typically, the thicknesses of the fourth insulating layer, the first insulating layer, the third insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0200] [Conductive layer] For the conductive layers (conductive layer 111, conductive layer 112a, conductive layer 112b, conductive layer 115a, conductive layer 115b, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Alternatively, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0201] In addition, conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed. Note that examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.

[0202] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0203] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0204] In addition, when a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductive layer that functions as a gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0205] [substrate] As the substrate on which the transistor is formed, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (for example, an yttria stabilized zirconia substrate), and a resin substrate can be used. As the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be used. Furthermore, there is a semiconductor substrate having an insulating region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. As the conductive substrate, there is a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there is a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there is a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or insulator is provided on a conductive substrate, and the like. Alternatively, a substrate on which an element is provided on these substrates may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0206] <Configuration Example 2 of Semiconductor Device> The structure of a semiconductor device according to another embodiment of the present invention will be described below. Specifically, a variation of the transistor 11 will be described.

[0207] [Transistor 11A] 4A is a cross-sectional view illustrating an example in which the conductive layer 112a illustrated in FIG. 3A has a two-layer structure of a conductive layer 112a1 and a conductive layer 112a2, and the conductive layer 112b has a two-layer structure of a conductive layer 112b1 and a conductive layer 112b2. The transistor 11 illustrated in FIG. 4A is referred to as a transistor 11A.

[0208] The conductive layer 112a1 is a conductive layer 111 <1> Side 141a, which is a side of <1> The conductive layer 111 <2> Side 141a, which is a side of <2> and the conductive layer 111 <3> Side 141a, which is a side of <3> The conductive layer 112a2 is provided on the outer side of the conductive layer 112a1 (opposite side of the conductive layer 111). <1> Side 141b, which is the side opposite to <1> The area adjacent to the side surface 141a <2> Side 141b, which is the side opposite to <2> and the side surface 141a <3> Side 141b, which is the side opposite to <3> The conductive layer 112b2 is provided on the outer side of the conductive layer 112b1 (opposite side from the conductive layer 111).

[0209] It is preferable that the conductive layer 112a1 and the conductive layer 112b1 have the same material as the conductive layer 111, because this improves the adhesion between the conductive layer 111 and the conductive layer 112a and the conductive layer 112b. On the other hand, the conductive layer 112a2 can be made of a material different from that of the conductive layer 112a1, and the conductive layer 112b2 can be made of a material different from that of the conductive layer 112b1. In this case, the boundary (interface) between the conductive layer 111 and the conductive layer 112a1 and the boundary (interface) between the conductive layer 111 and the conductive layer 112b1 cannot be clearly confirmed, but the boundary (interface) between the conductive layer 112a1 and the conductive layer 112a2 and the boundary (interface) between the conductive layer 112b1 and the conductive layer 112b2 may be confirmed.

[0210] The conductive layer 111, the conductive layer 112a1, and the conductive layer 112b1 can be formed using, for example, the above-mentioned conductive material containing nitrogen, such as titanium nitride or tantalum nitride. This can prevent the conductivity of the conductive layer 111, the conductive layer 112a1, and the conductive layer 112b1 from decreasing due to oxygen contained in the insulating layer 105. The conductive layer 112a2 and the conductive layer 112b2 can be formed using a material with high conductivity, such as tungsten, copper, or aluminum.

[0211] The conductive layer 112a1 and the conductive layer 112b1, and the conductive layer 112a2 and the conductive layer 112b2 can be formed by using different film formation methods. For example, the conductive layer 112a1 and the conductive layer 112b1 are preferably formed by a method with high coverage in order to improve adhesion with the conductive layer 111. The conductive layer 112a1 and the conductive layer 112b1 can be formed by, for example, an ALD method, a CVD method, or the like. The conductive layer 112a2 and the conductive layer 112b2 are preferably formed by a film formation method with a high film formation rate. The conductive layer 112a2 and the conductive layer 112b2 can be formed by, for example, a sputtering method, a CVD method, or the like. Note that when the conductive layers 112a1 and 112b1 and the conductive layers 112a2 and 112b2 are formed by different deposition methods, the conductive layers 112a1 and 112b1 and the conductive layers 112a2 and 112b2 may be formed using the same material. For example, the conductive layer 111, the conductive layer 112a1, the conductive layer 112a2, the conductive layer 112b1, and the conductive layer 112b2 may all be formed using the same material.

[0212] Here, for example, when the conductive layers 112a1 and 112b1 are formed by the same film formation method as that used to form the conductive layer 111, the thickness T112a1 of the conductive layer 112a1 and the thickness T112b1 of the conductive layer 112b1 can be made equal to or approximately equal to the thickness T111. Also, the thickness T112a2 of the conductive layer 112a2 can be made thicker than the thickness T112a1, and the thickness T112b2 of the conductive layer 112b2 can be made thicker than the thickness T112b1.

[0213] As described above, by forming the conductive layers 112a and 112b with a stacked structure, the range of film formation methods and the range of material selection used for forming the conductive layers 112a and 112b can be increased compared to when the conductive layers 112a and 112b have a single-layer structure. On the other hand, when the conductive layers 112a and 112b have a single-layer structure, the number of manufacturing steps of the transistor 11 can be reduced compared to when the conductive layers 112a and 112b have a stacked structure. Note that the conductive layers 112a and 112b may have a stacked structure of three or more layers.

[0214] [Transistor 11B] 4B is a cross-sectional view showing an example in which the conductive layer 115a shown in FIG. 3B has a two-layer structure of a conductive layer 115a1 and a conductive layer 115a2, and the conductive layer 115b has a two-layer structure of a conductive layer 115b1 and a conductive layer 115b2. The transistor 11 shown in FIG. 4B is a transistor 11B. The conductive layer 115a1 and the conductive layer 115b1 are provided on the inner side (the semiconductor layer 113 side), and the conductive layer 115a2 and the conductive layer 115b2 are provided on the outer side (the insulating layer 131 side).

[0215] The conductive layer 115a1 and the conductive layer 115b1 can be formed using, for example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, or a conductive material containing oxygen, such as ruthenium oxide. This can prevent the conductivity of the conductive layer 115a1 and the conductive layer 115b1 from decreasing due to oxygen contained in the semiconductor layer 113. The conductive layer 115a2 and the conductive layer 115b2 can be formed using a material with high conductivity, such as tungsten, copper, or aluminum. Note that the conductive layer 115a and the conductive layer 115b may have a stacked structure of three or more layers.

[0216] [Transistor 11C] 5(A), 5(B), 5(C), and 5(D) are diagrams showing examples of the transistor 11 shown in FIG. 1(A), FIG. 2(A), FIG. 2(B), and FIG. 2(C), respectively, which includes a metal oxide layer 114a and a metal oxide layer 114b. The transistor 11 shown in FIG. 5(A) to FIG. 5(D) is referred to as a transistor 11C.

[0217] The metal oxide layer 114a is provided between the semiconductor layer 113 and the conductive layer 115a. The metal oxide layer 114b is provided between the semiconductor layer 113 and the conductive layer 115b.

[0218] The metal oxide layer 114a and the metal oxide layer 114b have a region having a shape along the side surface of the semiconductor layer 113 in a region that does not overlap with the conductive layer 111, the conductive layer 112a, and the conductive layer 112b, and a region along the upper surface other than the top surface. The metal oxide layer 114a and the metal oxide layer 114b can have a region in contact with the side surface of the semiconductor layer 113 in a region that does not overlap with the conductive layer 111, the conductive layer 112a, and the conductive layer 112b, and a region in contact with the upper surface other than the top surface. The metal oxide layer 114a can have a region in contact with the side surface of the conductive layer 115a and a region in contact with the bottom surface of the conductive layer 115a. The metal oxide layer 114b can have a region in contact with the side surface of the conductive layer 115b and a region in contact with the bottom surface of the conductive layer 115b.

[0219] The conductive layer 115a has a region having a shape that follows the side surface of the metal oxide layer 114a and a region along the upper surface other than the top surface. The conductive layer 115b has a region having a shape that follows the side surface of the metal oxide layer 114b and a region along the upper surface other than the top surface. The top surface of the metal oxide layer 114a and the top surface of the metal oxide layer 114b are each connected to the conductive layer 111. <3> The height from the reference plane can be made to match or approximately match the heights of the upper surfaces of the top surfaces of conductive layers 112a, 112b, 115a, 115b, insulating layer 105, insulating layer 131, and insulating layer 133.

[0220] The metal oxide layer 114a and the metal oxide layer 114b can be formed using a material that can be used for the semiconductor layer 113. The composition of the metal oxide layer 114a and the composition of the metal oxide layer 114b can be different from the composition of the semiconductor layer 113. When the metal oxide layer 114a and the metal oxide layer 114b are conductive, the current path between the source region and the drain region of the transistor 11 can be shortened. Thus, the on-current of the transistor 11 can be increased. Note that the metal oxide layer 114a and the metal oxide layer 114b may be included in the semiconductor layer 113. Alternatively, the metal oxide layer 114a may be included in the conductive layer 115a, and the metal oxide layer 114b may be included in the conductive layer 115b.

[0221] In this specification and the like, a metal oxide having conductivity is referred to as an oxide conductor. An oxide conductor can be used for the metal oxide layer 114a and the metal oxide layer 114b. In this case, the conductivity of the metal oxide layer 114a and the metal oxide layer 114b can be higher than or equal to the conductivity of the semiconductor layer 113.

[0222] When the semiconductor layer 113 is a metal oxide layer, the oxide conductor has lower contact resistance with the semiconductor layer 113 than, for example, a conductor not containing oxygen. This can shorten the current path between the source region and the drain region of the transistor 11. Therefore, the on-state current of the transistor 11 can be increased compared to, for example, a case in which the transistor 11 does not include the metal oxide layer 114a and the metal oxide layer 114b and the conductive layer 115a and the conductive layer 115b are in contact with the semiconductor layer 113. On the other hand, when the transistor 11 does not include the metal oxide layer 114a and the metal oxide layer 114b, the number of manufacturing steps of the transistor 11 can be reduced compared to a case in which the transistor 11 includes the metal oxide layer 114a and the metal oxide layer 114b. Note that the metal oxide layer 114a and the metal oxide layer 114b may have a stacked structure of two or more layers.

[0223] The metal oxide layer 114a and the metal oxide layer 114b preferably contain at least indium. In addition, the metal oxide layer 114a and the metal oxide layer 114b can increase the field-effect mobility of the transistor 11 by increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide. Examples of oxide conductors that can be used for the metal oxide layer 114a and the metal oxide layer 114b include ITO, ITSO, and IZO (registered trademark).

[0224] The above-described structures of the transistor 11A, the transistor 11B, and the transistor 11C can be combined as appropriate. For example, the conductive layer 112a and the conductive layer 112b may have a stacked structure of two or more layers, and the conductive layer 115a and the conductive layer 115b may have a stacked structure of two or more layers.

[0225] <Storage device configuration example> An example in which the semiconductor device of one embodiment of the present invention is applied to a memory device will be described below. Specifically, an example in which the transistor 11 is applied to a memory cell included in the memory device will be described.

[0226] 6A is a circuit diagram illustrating a configuration example of a memory cell 20 included in a memory device of one embodiment of the present invention. The memory cell 20 includes a transistor 11 and a capacitor 13.

[0227] A gate of the transistor 11 is electrically connected to a wiring 15. One of a source and a drain of the transistor 11 is electrically connected to a wiring 17. The other of the source and the drain of the transistor 11 is electrically connected to one electrode of the capacitor 13. The other electrode of the capacitor 13 is electrically connected to a wiring 19.

[0228] The wiring 15 functions as a word line. A signal for controlling the on / off state of the transistor 11 is supplied to the wiring 15.

[0229] The wiring 17 functions as a bit line. A data signal to be supplied to the memory cell 20 is supplied to the wiring 17. When the transistor 11 is on, data corresponding to the potential of the wiring 17 is written to the memory cell 20. Alternatively, data held in the memory cell 20 is output to the wiring 17 and read out. When the transistor 11 is turned off, the data written to the memory cell 20 is held. Specifically, the charge of the capacitor 13 is held.

[0230] The wiring 19 functions as a power supply line. A power supply potential, for example, a low power supply potential, is supplied to the wiring 19.

[0231] 6(B) and 6(C) are cross-sectional views showing a configuration example of a memory device having the memory cell 20 shown in FIG. 6(A). Here, FIG. 2(A) can be referred to for the planar configuration of the transistor 11 shown in FIG. 6(B) and FIG. 6(C). FIG. 6(B) is a cross-sectional view taken along dashed line A1-A2 shown in FIG. 2(A). FIG. 6(C) is a cross-sectional view taken along dashed line B1-B2 shown in FIG. 2(A). FIG. 6(C) shows a configuration example of the transistor 11 and the capacitor 13. Note that, for example, the transistor 11A, the transistor 11B, or the transistor 11C may be applied to FIG. 6(B) and FIG. 6(C). The same applies to the memory devices shown below.

[0232] The capacitor 13 has a conductive layer 115b, an insulating layer 106, and a conductive layer 116. The conductive layer 115b functions as one electrode of the capacitor 13. The conductive layer 116 functions as the other electrode of the capacitor 13. The insulating layer 106 functions as a dielectric layer of the capacitor 13. In other words, the capacitor 13 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0233] The insulating layer 106 has a region located over the insulating layer 105, a region located over the conductive layer 115a, and a region located over the conductive layer 115b. The insulating layer 106 is provided so as to cover the insulating layer 105, the semiconductor layer 113, the conductive layer 115a, and the conductive layer 115b in a region not overlapping with the conductive layer 111. The insulating layer 106 has a region having a shape along the side surface of the conductive layer 115b and a region along the upper surface other than the top surface. The insulating layer 106 can also have a region having a shape along the side surface of the conductive layer 115a and a region along the upper surface other than the top surface.

[0234] The conductive layer 116 is provided on the insulating layer 106 so as to have a region overlapping with the conductive layer 115b. The conductive layer 116 has a region having a shape along the side surface of the insulating layer 106 and a region having a shape along the top surface.

[0235] The insulating layer 131 has a region located over the insulating layer 106 and a region located over the conductive layer 116. The insulating layer 131 is provided to cover the insulating layer 106 and the conductive layer 116.

[0236] As described above, the insulating layer 133 is provided on the insulating layer 131. The insulating layer 133 may be a planarized layer. In this case, the conductive layer 111 <3> The top surface of conductive layer 112a, the top surface of conductive layer 112b, the top surface of conductive layer 115a, the top surface of conductive layer 115b, the top surface of conductive layer 116, the top surface of insulating layer 105, the top surface of insulating layer 106, the top surface of insulating layer 131, and the top surface of insulating layer 133 can be made to match or approximately match each other in height from the reference plane.

[0237] Conductive layer 111 <3> An insulating layer 135 is provided on the conductive layer 112a, the conductive layer 112b, the conductive layer 115a, the conductive layer 115b, the conductive layer 116, the insulating layer 105, the insulating layer 106, the insulating layer 131, and the insulating layer 133, and an insulating layer 137 is provided on the insulating layer 135.

[0238] Openings reaching the conductive layer 112b are provided in the insulating layers 137, 135, 133, 131, 106, and 105, and the conductive layer 151a is provided so as to have a region located inside the openings. The conductive layer 151a can be in contact with the conductive layer 112b inside the openings. Note that openings reaching the conductive layer 112a may be provided in the insulating layers 137, 135, 133, 131, 106, and 105, and the conductive layer 151a may be provided so as to have a region located inside the openings. In addition, the conductive layer 112a may be provided in the insulating layer 137 and the insulating layer 135. <3> An opening reaching the substrate 151 may be provided, and the conductive layer 151a may be provided so as to have a region located inside the opening.

[0239] An opening reaching the conductive layer 115a is provided in the insulating layer 137, the insulating layer 135, the insulating layer 133, the insulating layer 131, and the insulating layer 106, and the conductive layer 151b is provided so as to have a region located inside the opening. The conductive layer 151b can be in contact with the conductive layer 115a inside the opening. Furthermore, an opening reaching the conductive layer 116 is provided in the insulating layer 137, the insulating layer 135, the insulating layer 133, and the insulating layer 131, and the conductive layer 151c is provided so as to have a region located inside the opening. The conductive layer 151c can be in contact with the conductive layer 116 inside the opening.

[0240] The conductive layers 151a, 151b, and 151c each function as a plug, for example. Note that the conductive layers 151a, 151b, and 151c are also referred to as connection electrodes.

[0241] A conductive layer 153a is provided over the conductive layer 151a and the insulating layer 137. The conductive layer 153a can have a region in contact with a top surface of the conductive layer 151a and a region in contact with a top surface of the insulating layer 137. The conductive layer 111, the conductive layer 112a, and the conductive layer 112b are electrically connected to the conductive layer 153a through the conductive layer 151a.

[0242] A conductive layer 153b is provided over the conductive layer 151b and the insulating layer 137. The conductive layer 153b can have a region in contact with an upper surface of the conductive layer 151b and a region in contact with an upper surface of the insulating layer 137. The conductive layer 115a and the conductive layer 153b are electrically connected to each other through the conductive layer 151b.

[0243] Similarly, a conductive layer 153c is provided on the conductive layer 151c and on the insulating layer 137. The conductive layer 153c can have a region in contact with an upper surface of the conductive layer 151c and a region in contact with an upper surface of the insulating layer 137. The conductive layer 116 and the conductive layer 153c are electrically connected to each other through the conductive layer 151c.

[0244] At least a part of the conductive layer 153a can function as the wiring 15 shown in FIG. 6A. At least a part of the conductive layer 153b can function as the wiring 17 shown in FIG. 6A. At least a part of the conductive layer 153c can function as the wiring 19 shown in FIG. 6A. Note that at least a part of the conductive layer 151a may function as the wiring 15, at least a part of the conductive layer 151b may function as the wiring 17, and at least a part of the conductive layer 151c may function as the wiring 19. Alternatively, at least a part of the conductive layer 111, the conductive layer 112a, and the conductive layer 112b may function as the wiring 15, at least a part of the conductive layer 115a may function as the wiring 17, and at least a part of the conductive layer 116 may function as the wiring 19.

[0245] An insulating layer 155 is provided over the conductive layers 153a, 153b, and 153c, and over the insulating layer 137. The insulating layer 155 is provided so as to cover an upper surface and side surfaces of the conductive layer 153a, an upper surface and side surfaces of the conductive layer 153b, an upper surface and side surfaces of the conductive layer 153c, and an upper surface of the insulating layer 137. The insulating layer 155 functions as an interlayer insulating layer and can be a planarized layer.

[0246] An opening reaching the conductive layer 153a is provided in the insulating layer 155, and the conductive layer 175 is provided to have a region located inside the opening. The conductive layer 175 can be in contact with the conductive layer 153a inside the opening.

[0247] A conductive layer 177 is provided over the conductive layer 175 and the insulating layer 155. The conductive layer 177 can have a region in contact with a top surface of the conductive layer 175 and a region in contact with a top surface of the insulating layer 155. The conductive layer 111, the conductive layer 112a, and the conductive layer 112b are electrically connected to the conductive layer 177 through the conductive layer 151a, the conductive layer 153a, and the conductive layer 175.

[0248] An insulating layer 179 is provided over the conductive layer 177 and the insulating layer 155. The insulating layer 179 is provided to cover an upper surface and side surfaces of the conductive layer 177 and an upper surface of the insulating layer 155. The insulating layer 179 functions as an interlayer insulating layer and can be a planarized layer.

[0249] The conductive layer 116, the conductive layer 151a, the conductive layer 151b, the conductive layer 151c, the conductive layer 153a, the conductive layer 153b, the conductive layer 153c, the conductive layer 175, and the conductive layer 177 can each be formed using the above-mentioned materials which can be used for at least one of the conductive layer 111, the conductive layer 112a, the conductive layer 112b, the conductive layer 115a, and the conductive layer 115b. The insulating layer 155 and the insulating layer 179 can each be formed using the above-mentioned materials which can be used for at least one of the insulating layer 101, the insulating layer 133, and the insulating layer 137.

[0250] 7(A) and 7(B) show an example in which the capacitor 13 shown in FIG. 6(C) is provided on an insulating layer 137. In the example shown in FIG. 7(A), the capacitor 13 has a conductive layer 153c on a conductive layer 151c and on the insulating layer 137, an insulating layer 156 on the conductive layer 153c, and a conductive layer 157 on the insulating layer 156. The conductive layer 153c functions as one electrode of the capacitor 13. The insulating layer 156 functions as a dielectric layer of the capacitor 13. The conductive layer 157 functions as the other electrode of the capacitor 13. At least a part of the conductive layer 157 can function as the wiring 19 shown in FIG. 6(A). The capacitor 13 shown in FIG. 7(A) is a parallel plate type MIM capacitor.

[0251] 7A, the conductive layer 151c can have a region in contact with the conductive layer 115b. The conductive layer 153c can have a region in contact with a top surface of the conductive layer 151c and a region in contact with a top surface of the insulating layer 137. The conductive layer 153c is electrically connected to the conductive layer 115b through the conductive layer 151c.

[0252] The insulating layer 156 can be provided so as to have a region located over the conductive layer 153c, a region located over the conductive layer 153b, and a region located over the insulating layer 137. In this case, the insulating layer 156 can cover the top surface and side surfaces of the conductive layer 153c, the top surface and side surfaces of the conductive layer 153b, and the top surface of the insulating layer 137.

[0253] An insulating layer 159 is provided over the conductive layer 157 and the insulating layer 156. The insulating layer 159 is provided to cover an upper surface and side surfaces of the conductive layer 157 and an upper surface of the insulating layer 156. The insulating layer 159 functions as an interlayer insulating layer and can be a planarized layer. An insulating layer 179 is provided over the insulating layer 159.

[0254] The conductive layer 153c and the conductive layer 157 can be formed using a material that can be used for the conductive layer 116 shown in Figure 6C. The insulating layer 156 can be formed using a material that can be used for the insulating layer 106 shown in Figure 6C. The insulating layer 159 can be formed using a material that can be used for the insulating layer 155 shown in Figure 6C.

[0255] The memory cell 20 shown in Fig. 7A can be provided to have, for example, a region overlapping with the conductive layer 111 of the transistor 11. Therefore, the memory cell 20 shown in Fig. 7A can have a higher degree of freedom in the layout of the capacitor 13 than the memory cell 20 shown in Fig. 6C. On the other hand, the memory cell 20 shown in Fig. 6C can have a smaller number of manufacturing steps than the memory cell 20 shown in Fig. 7A.

[0256] In the example shown in FIG. 7B, the capacitor 13 is provided over the conductive layer 153c. The capacitor 13 shown in FIG. 7B includes a conductive layer 163 over the conductive layer 153c, an insulating layer 165 over the conductive layer 163, and a conductive layer 167 over the insulating layer 165. The conductive layer 163 functions as one electrode of the capacitor 13. The insulating layer 165 functions as a dielectric layer of the capacitor 13. The conductive layer 167 functions as the other electrode of the capacitor 13. At least a part of the conductive layer 167 can function as the wiring 19 shown in FIG. 6A.

[0257] In the example shown in FIG. 7B, an insulating layer 155 is provided over the conductive layer 153b, the conductive layer 153c, and the insulating layer 137. An opening reaching the conductive layer 153c is provided in the insulating layer 155. A conductive layer 163 is provided along a side surface of the opening and a top surface of the conductive layer 153c. The conductive layer 163 has a region in contact with a side surface of the insulating layer 155 in the opening and a region in contact with a top surface of the conductive layer 153c. The conductive layer 163 is electrically connected to the conductive layer 115b through the conductive layer 153c and the conductive layer 151c.

[0258] The insulating layer 165 is provided along the upper surface and side surfaces of the conductive layer 163 so as to have a region located inside the opening of the insulating layer 155. The conductive layer 167 is provided on the insulating layer 165 so as to have a region located inside the opening of the insulating layer 155. The conductive layer 167 can be provided so as to fill the opening of the insulating layer 155.

[0259] As described above, the capacitor 13 shown in FIG. 7(B) is a trench-type MIM capacitor. In the capacitor 13 shown in FIG. 7(B), the MIM structure is formed not only on the top surface of the conductive layer 163 that functions as one of the electrodes, but also along the side surface. Therefore, the capacitor 13 shown in FIG. 7(B) can have a larger capacitance value without increasing the occupied area, compared to the capacitor 13 shown in FIG. 7(A). On the other hand, the semiconductor device shown in FIG. 7(A) can be manufactured in fewer steps, compared to the semiconductor device shown in FIG. 7(B).

[0260] An insulating layer 169 is provided over the insulating layer 155 so as to cover side surfaces of the conductive layer 163, the insulating layer 165, and the conductive layer 167. The insulating layer 169 can be formed by forming an insulating film over the conductive layer 167 and the insulating layer 155, and performing planarization treatment on the insulating film until the top surface of the conductive layer 167 is exposed. Here, the conductive layer 167 may be planarized by the planarization treatment. An insulating layer 179 is provided over the conductive layer 167 and the insulating layer 169.

[0261] The conductive layer 163 can be formed using, for example, a material that can be used for the conductive layer 116 shown in FIG. 6C. The insulating layer 165 can be formed using, for example, a material that can be used for the insulating layer 106 shown in FIG. 6C. The conductive layer 167 can be formed using, for example, any of the above materials that can be used for at least one of the conductive layer 111, the conductive layer 112a, the conductive layer 112b, the conductive layer 115a, and the conductive layer 115b. The insulating layer 169 can be formed using, for example, a material that can be used for the insulating layer 137.

[0262] <Example of a method for manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. Note that, with respect to materials and formation methods of elements, descriptions of parts similar to those described above may be omitted.

[0263] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device can be formed using a sputtering method, a CVD method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0264] There are three types of sputtering: RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when forming insulating films, while DC sputtering is mainly used when forming metal conductive films. Pulsed DC sputtering is mainly used when forming films of compounds such as oxides, nitrides, or carbides by reactive sputtering.

[0265] CVD methods can be further classified into plasma CVD (PECVD) methods that use plasma, thermal CVD (TCVD) methods that use heat, and photo CVD (Photo CVD) methods that use light, etc. They can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0266] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, and elements (transistors, capacitors, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, or elements included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0267] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0268] The CVD method and the ALD method are different from the sputtering method in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent film thickness uniformity, so it is suitable for covering the surface of an opening with a high aspect ratio, for example. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0269] In addition, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming a film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0270] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0271] Furthermore, the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0272] The thin film can be processed by forming a resist mask by photolithography, for example, and then etching the thin film according to the pattern of the resist mask. Alternatively, the thin film may be processed by nanoimprinting, sandblasting, lift-off, or the like. Also, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask. Also, a photosensitive thin film can be processed by exposure and development. That is, a photosensitive thin film can be processed by photolithography.

[0273] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0274] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0275] The thin film can be etched by dry etching, wet etching, or the like.

[0276] An example of a method for manufacturing a semiconductor device including the transistor 11 illustrated in FIGS. 2A, 2B, and 2C will be described below.

[0277] First, an insulating layer 101 is formed on a substrate (not shown), and a conductive layer 111 is formed on the insulating layer 101. <1> A conductive layer 111 <1> Sacrificial layer 121 on top <1> A sacrificial layer 121 is formed. <1> Conductive layer 111 on top <2> A conductive layer 111 <2> Sacrificial layer 121 on top <2> A sacrificial layer 121 is formed. <2> Conductive layer 111 on top <3> A conductive layer 111 <3> A sacrificial layer 123 is formed on the sacrificial layer 123, and a mask layer 125 is formed on the sacrificial layer 123 (FIGS. 8(A), 8(B), and 8(C)). FIG. 8(A) is a plan view, FIG. 8(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 8(A), and FIG. 8(C) is a cross-sectional view taken along dashed line B1-B2 in FIG. 8(A).

[0278] In a later step, the semiconductor layer 113 and the insulating layer 105 covering the upper and lower surfaces of the semiconductor layer 113 in this region will be formed in the region where the sacrificial layer 121 is formed. The thickness of the sacrificial layer 121 can be, for example, 1 nm to 300 nm, preferably 5 nm to 200 nm, more preferably 10 nm to 100 nm, and further preferably 15 nm to 70 nm.

[0279] The sacrificial layer 123 can have a stacked structure of multiple layers. In Fig. 8B and Fig. 8C, an example is shown in which the sacrificial layer 123 has a two-layer stacked structure of a sacrificial layer 123a and a sacrificial layer 123b on the sacrificial layer 123a. In subsequent cross-sectional views showing an example of a method for manufacturing a semiconductor device, an example is also shown in which the sacrificial layer 123 has a two-layer stacked structure of a sacrificial layer 123a and a sacrificial layer 123b on the sacrificial layer 123a. The thickness of the sacrificial layer 123a is preferably equal to or smaller than the thickness of the sacrificial layer 123b.

[0280] Insulating layer 101, sacrificial layer 121 <1> , sacrificial layer 121 <2> The sacrificial layer 123a, the sacrificial layer 123b, and the mask layer 125 can be formed by using, for example, a CVD method, an ALD method, a sputtering method, an MBE method, or a PLD method. <1> , conductive layer 111 <2> , and the conductive layer 111 <3> The conductive layer 111 can be formed by, for example, an ALD method or a CVD method. <1> , conductive layer 111 <2> , and the conductive layer 111 <3> For example, titanium nitride can be used.

[0281] Sacrificial Layer 121 <1> , sacrificial layer 121 <2> For example, the materials shown in the above [Insulating layer] can be used for the sacrificial layers 123a and 123b. <1> , sacrificial layer 121 <2> For example, an inorganic insulating film can be used as the sacrificial layer 123a and the sacrificial layer 123b. Specifically, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used. <1> , and the sacrificial layer 121 <2> For example, aluminum oxide, aluminum nitride, aluminum oxynitride, or aluminum nitride oxide can be used as the sacrificial layer 123a and the sacrificial layer 123b. For example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide can be used as the sacrificial layer 123a and the sacrificial layer 123b. Here, it is preferable that the sacrificial layer 123b has a material different from that of the sacrificial layer 123a. Note that the sacrificial layer 121 <1> , sacrificial layer 121 <2> An organic insulating film may be used as the sacrificial layer 123a and the sacrificial layer 123b. <1> , and the sacrificial layer 121 <2> An organic insulating film may be used for the sacrificial layer 121. <1> , sacrificial layer 121 <2> The sacrificial layers 123a and 123b may be formed using a semiconductor material or a conductive material.

[0282] It is preferable to use a material for the sacrificial layer 123b different from that for the insulating layer 133 formed in a later step. Although details will be described later, after forming the insulating layer 133, for example, a planarization process is performed with the sacrificial layer 123a as the end point. In this case, the end point can be easily detected by making the material for the sacrificial layer 123b on the sacrificial layer 123a different from the material for the insulating layer 133. The sacrificial layer 123a can be made of the same material as that for the insulating layer 133. For example, when silicon oxide is used for the insulating layer 133, silicon oxide can be used for the sacrificial layer 123a and silicon nitride can be used for the sacrificial layer 123b.

[0283] The mask layer 125 is a layer that serves as a mask (also referred to as a hard mask) when processing the sacrificial layer 123, the conductive layer 111, and the sacrificial layer 121 in a later step. The mask layer 125 can be made of, for example, a metal material. The mask layer 125 can be made of, for example, tungsten. Note that the mask layer 125 may be made of a semiconductor material or an insulating material.

[0284] Next, the mask layer 125, the sacrificial layer 123b, the sacrificial layer 123a, and the conductive layer 111 are <3> , sacrificial layer 121 <2> , conductive layer 111 <2> , sacrificial layer 121 <1> , and the conductive layer 111 <1> is processed (FIGS. 9(A), 9(B), and 9(C)). This processing is referred to as, for example, a first processing. FIG. 9(A) is a plan view, FIG. 9(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 9(A), and FIG. 9(C) is a cross-sectional view taken along dashed line B1-B2 in FIG. 9(A).

[0285] For example, a resist mask is formed by photolithography, and then the mask layer 125 is processed according to the pattern of the resist mask. This processing can be performed by, for example, an etching method, and is preferably performed by dry etching since fine processing is easy. Then, the resist mask is removed. Then, the sacrificial layer 123b, the sacrificial layer 123a, and the conductive layer 111 are removed according to the pattern of the mask layer 125. <3> , sacrificial layer 121 <2> , conductive layer 111 <2> , sacrificial layer 121 <1> , and the conductive layer 111 <1> Here, the conductive layer 111 <1> Conductive layer 111 <3> The thinner the film thickness of the conductive layer 111 <1> Conductive layer 111 <3> This is preferable because it can prevent the horizontal processing.

[0286] Here, as shown in Figures 9(A), 9(B), and 9(C), it is preferable to form a dummy pattern so as to surround at least a part of the region in which the transistor 11 is to be manufactured. This makes it easier to detect the end point of a planarization process such as a CMP process performed in a later step than when a dummy pattern is not formed. In Figures 9(A) to 9(C), the conductive layer 111 and the mask layer 125 included in the dummy pattern are referred to as a conductive layer 111D and a mask layer 125D, respectively. This also applies to subsequent drawings showing examples of a method for manufacturing a semiconductor device.

[0287] Next, the conductive layer 111 <1> , sacrificial layer 121 <1> , conductive layer 111 <2> , sacrificial layer 121 <2> , conductive layer 111 <3> A conductive layer 112 is formed so as to cover the sacrificial layer 123a, the sacrificial layer 123b, and the mask layer 125 (FIGS. 10(A), 10(B), and 10(C)). FIG. 10(A) is a plan view, FIG. 10(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 10(A), and FIG. 10(C) is a cross-sectional view taken along dashed line B1-B2 in FIG. 10(A).

[0288] The conductive layer 112 can be formed by, for example, a CVD method, an ALD method, a sputtering method, or the like. <1> Conductive layer 111 <3> When the conductive layer 112 is made of the same material as that used for the conductive layer 111, <1> Conductive layer 111 <3> This is particularly preferable since it is easy to adhere the conductive layer 111 to the conductive layer 111. <2> When the conductive layer 112 is made of the same material as that used for the conductive layer 111, the conductive layer 112 is <2> This makes it easier to adhere the conductive layer 111 to the sacrificial layer 121 when removing the sacrificial layer 121 in a later process. <2> In addition, the conductive layer 111 can be prevented from falling off. <3> When the conductive layer 112 is made of the same material as that used for the conductive layer 111, the conductive layer 112 is <3> This makes it easier to adhere the conductive layer 111 to the sacrificial layer 121 when removing the sacrificial layer 121 in a later process. <3> This is preferable because it can prevent the sacrificial layer 123 and the mask layer 125 from falling off. <1> Conductive layer 111 <3> When titanium nitride is used for the conductive layer 112, it is preferable to use titanium nitride also for the conductive layer 112. When the conductive layer 112 has a laminated structure of two or more layers, the same material as the conductive layer 111 can be used for the innermost layer (the conductive layer 111 side), and a different material from the conductive layer 111 can be used for the outermost layer (the side opposite to the conductive layer 111).

[0289] Next, the conductive layer 112 is processed (FIGS. 11(A), 11(B), and 11(C)). FIG. 11(A) is a plan view, FIG. 11(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 11(A), and FIG. 11(C) is a cross-sectional view taken along dashed line B1-B2 in FIG. 11(A). This processing is also referred to as, for example, a second processing.

[0290] For example, after forming a resist mask by photolithography, the conductive layer 112 is processed according to the pattern of the resist mask. This processing can be performed by, for example, an etching method, and is preferably performed by dry etching, which facilitates fine processing. Then, the resist mask is removed.

[0291] Fig. 12 is an enlarged view of the configuration shown in Fig. 11(B) Note that dummy patterns are not shown in Fig. 12.

[0292] As shown in FIG. 12, the conductive layer 112 is <1> Side 141a, which is a side of <1> The conductive layer 111 <2> Side 141a, which is a side of <2> The conductive layer 111 <3> Side 141a, which is a side of <3> The area adjacent to the side surface 141a <1> Side 141b, which is the side opposite to <1> The area adjacent to the side surface 141a <2> Side 141b, which is the side opposite to <2> and the side surface 141a <3> Side 141b, which is the side opposite to <3> The conductive layer 112 is formed to have a region in contact with the conductive layer 111. <3> The conductive layer 112 is formed to have a region located above the sacrificial layer 145a, specifically, to have a region located above the mask layer 125. <1> Side 145a, which is the side of <1> The area in contact with the sacrificial layer 145a <2> Side 145a, which is the side of <2> a region in contact with a side surface 147a which is a side surface of the sacrificial layer 123; a region in contact with a side surface 148a which is a side surface of the mask layer 125; <1> Side 145b, which is the side opposite to <1> The area adjacent to the side 145a <2> Side 145b, which is the side opposite to <2> 1, a region contacting side 147b, which is the side opposite side 147a, and a region contacting side 148b, which is the side opposite side 148a.

[0293] For example, the conductive layer 112 is processed so that the width of the conductive layer 112 in the Y direction is smaller than the width of the conductive layer 111 in the Y direction. This allows the sacrificial layer 121 to be removed in a later step. By this processing, the conductive layer 112 is, for example, as shown in FIG. <1> Side 141a <1> and side 141b <1> The other side of the conductive layer 111 <2> Side 141a <2> and side 141b <2> The other side surfaces and the conductive layer 111 <3> Side 141a <3> and side 141b <3> The conductive layer 112 can be formed so as not to contact any other side surface than the sacrificial layer 121 as shown in FIG. <1> Side 145a <1> and side 145b <1> Other side, sacrificial layer 121 <2> Side 145a <2> and side 145b <2> The mask layer 125 can be formed so as not to come into contact with any side surfaces other than the side surfaces 147a and 147b of the sacrificial layer 123, and any side surfaces other than the side surfaces 148a and 148b of the mask layer 125.

[0294] 11(A) to 11(C) and 12, unlike the first processing in the process shown in FIG. 9(A) to 9(C), multiple layers, for example, multiple conductive layers 111 overlapping with a sacrificial layer 121 in between, do not need to be processed with the same mask pattern. Therefore, the thickness T112 of the conductive layer 112 shown in FIG. <1> , thickness T111 <2> , and thickness T111 <3> The thickness T112 can be equal to or greater than at least one of the thicknesses T111, for example. <1> , thickness T111 <2> , and thickness T111 <3> By increasing the thickness T112, the electrical resistivity of the conductive layer 112a and the conductive layer 112b to be formed in a later step can be reduced. <1> Conductive layer 111 <3> The conductive layer 112 can have a single layer structure and a stacked structure of two or more layers.

[0295] As described above, it is preferable that the thickness T123a of the sacrificial layer 123a is equal to or smaller than the thickness T123b of the sacrificial layer 123b. In a later step, the conductive layer 112 is planarized to form the conductive layers 112a and 112b shown in FIGS. 2A to 2C. The planarization is performed by, for example, CMP, with the sacrificial layer 123a as the end point. By ending the planarization at the sacrificial layer 123a, the conductive layer 112 is formed. <3> When the end point is the conductive layer 111 <3> This can prevent the upper surface from being subjected to a planarization process.

[0296] As described above, the conductive layer 111 <3> The thickness of the film is T111 <3> On the other hand, it is preferable to make the thickness T111 <3> When the conductive layer 111 is thin, <3> When the upper surface of the conductive layer 111 is planarized, <3> Therefore, the conductive layer 111 may disappear. <3> A planarization process is performed using the upper sacrificial layer 123a as an end point, so that the conductive layer 111 <3> The upper surface of the conductive layer 111 is prevented from being planarized. <3> It is possible to prevent the loss of the conductive layer 123a. On the other hand, if the thickness T123a is large, the sacrificial layer 123a may remain even after the planarization process is completed. If the remaining sacrificial layer 123a is thick, the insulating layer 133 also becomes thick. As a result, when an opening for providing a conductive layer functioning as a plug is provided in the insulating layer 133 as shown in, for example, FIG. 6B to FIG. 7B, it may be difficult to form the opening. As a result, for example, the conductive layer functioning as the source electrode, drain electrode, or gate electrode of the transistor 11 may not be electrically connected to the conductive layer functioning as a plug.

[0297] From the above, the thickness T123a is set to a value that is equal to or smaller than the thickness T123a of the conductive layer 111, and that is equal to or smaller than the thickness T123a of the conductive layer 111. <3> It is preferable that the thickness T123a is set to a value that does not cause a planarization process to be performed on the substrate. The thickness T123a is, for example, preferably 1 nm or more and 150 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 7 nm or more and 70 nm or less, more preferably 8 nm or more and 50 nm or less, more preferably 10 nm or more and 30 nm or less, and even more preferably 10 nm or more and 20 nm or less.

[0298] Next, the sacrificial layer 121 <1> , and the sacrificial layer 121 <2> As a result, the conductive layer 111 <1> , conductive layer 111 <2> , and a space 122 in the area surrounded by the conductive layer 112. <1> In addition, the conductive layer 111 <2> , conductive layer 111 <3> , and a space 122 in the area surrounded by the conductive layer 112. <2> is formed (FIGS. 13(A) and 13(B)). Here, FIG. 11(A) can be referred to for a plan view. FIG. 13(A) is a cross-sectional view taken along dashed line A1-A2 in FIG. 11(A), and FIG. 13(B) is a cross-sectional view taken along dashed line B1-B2 in FIG. 11(A).

[0299] Sacrificial Layer 121 <1> , and the sacrificial layer 121 <2> The conductive layer 111 can be removed, for example, by etching, and is preferably removed by wet etching. <2> When the conductive layer 112 has the same material, the conductive layer 112 is <2> The conductive layer 111 is easily adhered to the conductive layer 111. <2> In addition, the conductive layer 111 can be prevented from falling off. <3> When the conductive layer 112 has the same material, the conductive layer 112 is <3> The conductive layer 111 is easily adhered to the conductive layer 111. <3> This is preferable because it can prevent the sacrificial layer 123 and the mask layer 125 from falling off.

[0300] Here, in at least a part of the region where the dummy pattern is formed (also called the dummy region) that is not shown in FIG. 13(A) and FIG. 13(B), a sacrificial layer 121 is formed. <1> , and the sacrificial layer 121 <2> This makes it possible to prevent the conductive layer 111D and the mask layer 125D from falling off. For example, by adjusting the etching time, it is possible to remove the entire sacrificial layer 121 in the region surrounded by the conductive layer 111 and the conductive layer 112, and leave a part of the sacrificial layer in the dummy region.

[0301] Next, the conductive layer 111 <1> , conductive layer 111 <2> , conductive layer 111 <3> An insulating layer 105 is formed to cover the conductive layer 112, the conductive layer 111D, and the mask layer 125D (FIGS. 13(C) and 13(D)). FIG. 11(A) can be referred to for a plan view. FIG. 13(C) is a cross-sectional view taken along dashed line A1-A2 in FIG. 11(A), and FIG. 13(D) is a cross-sectional view taken along dashed line B1-B2 in FIG. 11(A).

[0302] The insulating layer 105 includes at least the conductive layer 111 <1> the upper surface of the conductive layer 111 and the side surface not in contact with the conductive layer 112, <2> The lower surface, the upper surface, and the side surface not in contact with the conductive layer 112, <3> The insulating layer 105 can be formed so as to cover the lower surface and the side surface not in contact with the conductive layer 112, the upper surface and the side surface of the conductive layer 112, and the upper surface and the side surface of the mask layer 125D. The insulating layer 105 is preferably formed by a method that provides high coverage. In particular, when the insulating layer 105 is formed by the ALD method, the conductive layer 111 <1> , conductive layer 111 <2> , conductive layer 111 <3> This is preferable because the insulating layer 105 can cover the conductive layer 112, the conductive layer 111D, and the mask layer 125D with good coverage. <2> and the conductive layer 111 <3> It can cover the entire surface including the underside with good coverage.

[0303] Next, the semiconductor layer 113 is formed so as to cover the insulating layer 105 (FIGS. 14(A), 14(B), and 14(C)). FIG. 14(A) is a plan view, FIG. 14(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 14(A), and FIG. 14(C) is a cross-sectional view taken along dashed line B1-B2 in FIG. 14(A).

[0304] The semiconductor layer 113 is preferably formed by a method that provides high coverage, for example, by an ALD method. <1> , conductive layer 111 <2> The semiconductor layer 113 can be formed with good coverage in the region surrounded by the conductive layer 111 and the conductive layer 112. <2> , conductive layer 111 <3> In addition, the semiconductor layer 113 can be formed with good coverage in a region surrounded by the conductive layer 112 .

[0305] Here, when silicon is used as the semiconductor layer 113, for example, it is difficult to form the semiconductor layer 113 by the ALD method. On the other hand, in order to form the semiconductor layer 113 so as to cover the insulating layer 105 including its lower surface with good coverage, it is preferable to use the ALD method. Therefore, it is preferable to use a metal oxide layer that can be formed by the ALD method as the semiconductor layer 113. Note that if the semiconductor layer 113 can be formed by the ALD method, it is not necessary to use a metal oxide layer as the semiconductor layer 113.

[0306] When the ALD method is used as a method for forming a metal oxide film, the amount of carbon and chlorine contained in the film can be reduced by adopting a condition of a high substrate temperature during film formation and / or by performing an impurity removal process, compared to when the ALD method is used without applying these conditions.

[0307] For example, it is preferable to perform an impurity removal treatment intermittently in an oxygen-containing atmosphere during the formation of the metal oxide film. It is also preferable to perform an impurity removal treatment in an oxygen-containing atmosphere after the formation of the metal oxide film. By performing an impurity removal treatment either during or after the formation of the metal oxide film, impurities in the film can be removed. This makes it possible to suppress impurities (such as hydrogen, carbon, and nitrogen) contained in raw materials such as precursors from remaining in the metal oxide. Therefore, it is possible to reduce the impurity concentration in the metal oxide. In addition, it is possible to increase the crystallinity of the metal oxide.

[0308] Examples of the impurity removal treatment include a plasma treatment, a microwave treatment, and a heat treatment.

[0309] When performing the plasma treatment or microwave treatment, the substrate temperature is preferably set to room temperature (e.g., 25° C.) or higher, 100° C. or higher, 200° C. or higher, 300° C. or higher, or 400° C. or higher, and 500° C. or lower, or 450° C. or lower. The heat treatment temperature is preferably set to 100° C. or higher, 200° C. or higher, 300° C. or higher, or 400° C. or higher, and 500° C. or lower, or 450° C. or lower.

[0310] The temperature for removing impurities is preferably set to a temperature equal to or lower than the maximum temperature in the manufacturing process of a transistor or a memory device, because the amount of impurities in the metal oxide can be reduced without decreasing productivity. For example, the productivity of the memory device of one embodiment of the present invention can be increased by setting the maximum temperature in the manufacturing process of the memory device to 500° C. or lower, preferably 450° C. or lower.

[0311] Here, the microwave treatment refers to, for example, a treatment using a device having a power source that generates high-density plasma using microwaves. In addition, in this specification, the microwave refers to an electromagnetic wave having a frequency of 300 MHz or more and 300 GHz or less.

[0312] In the microwave treatment, for example, it is preferable to use a microwave treatment device having a power source that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. In addition, the power of the power source that applies microwaves of the microwave treatment device is preferably 1000 W or more and 10000 W or less, and preferably 2000 W or more and 5000 W or less. In addition, the microwave treatment device may have a power source that applies RF to the substrate side. By applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the film.

[0313] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, and more preferably from 300 to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and even more preferably from 400 to 450°C.

[0314] Alternatively, after the microwave treatment or plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. to 750° C., more preferably 300° C. to 500° C., and further preferably 400° C. to 450° C.

[0315] The microwave treatment can be performed using, for example, oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than or equal to 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than or equal to 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than or equal to 10% and less than or equal to 40%. Even more preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than or equal to 10% and less than or equal to 30%.

[0316] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to set the oxygen gas to about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been desorbed. The heat treatment may be performed in an atmosphere of ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less).

[0317] By carrying out the heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. Furthermore, at the same time as the removal of the impurities, rearrangement of metal atoms and oxygen atoms can be carried out, improving the crystallinity. Therefore, a metal oxide with a highly crystalline layered crystal structure, particularly a metal oxide with the above CAAC structure, can be formed.

[0318] Furthermore, by performing the above-described treatment under an atmosphere containing oxygen, oxygen can be supplied to the semiconductor layer 113. As a result, when a metal oxide layer is used as the semiconductor layer 113, oxygen addition treatment can be performed on the semiconductor layer 113. Thus, oxygen vacancies in the semiconductor layer 113 can be repaired, and a transistor with stable electrical characteristics can be manufactured.

[0319] 5A to 5D, metal oxide films to be the metal oxide layers 114a and 114b in a later step are formed after the semiconductor layer 113. The metal oxide films can be formed by, for example, a sputtering method, an ALD method, or a CVD method.

[0320] Next, a conductive layer 115 is formed on the semiconductor layer 113 (FIGS. 15(A), 15(B), and 15(C)). FIG. 15(A) is a plan view, FIG. 15(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 15(A), and FIG. 15(C) is a cross-sectional view taken along dashed line B1-B2 in FIG. 15(A).

[0321] The conductive layer 115 can be formed by, for example, a CVD method, an ALD method, a sputtering method, or the like. The conductive layer 115 can be formed using, for example, titanium nitride or tungsten. Here, the conductive layer 115 may have a stacked structure of two or more layers. For example, when the conductive layer 115a and the conductive layer 115b to be formed in a later step have the structure shown in FIG. 4B, the conductive layer 115 can have a stacked structure of a layer to be the conductive layer 115a1 and the conductive layer 115b1 and a layer to be the conductive layer 115a2 and the conductive layer 115b2 on the layer. In this case, the layer to be the conductive layer 115a1 and the conductive layer 115b1 in a later step can be formed using, for example, titanium nitride. The layer to be the conductive layer 115a2 and the conductive layer 115b2 in a later step can be formed using, for example, tungsten.

[0322] When the conductive layer 115 has a stacked structure of two or more layers, the deposition method can be different for each layer. For example, when the conductive layer 115a and the conductive layer 115b to be formed in a later step have the structure shown in FIG. 4B, among the layers included in the conductive layer 115, the layers to be the conductive layer 115a1 and the conductive layer 115b1 can be deposited by a CVD method or an ALD method. The layers to be the conductive layer 115a2 and the conductive layer 115b2 can be deposited by a sputtering method.

[0323] Next, the conductive layer 115 and the semiconductor layer 113 are processed (FIGS. 16(A), 16(B), and 16(C)). FIG. 16(A) is a plan view, FIG. 16(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 16(A), and FIG. 16(C) is a cross-sectional view taken along dashed line B1-B2 in FIG. 16(A).

[0324] For example, after forming a resist mask by a photolithography method, the conductive layer 115 and the semiconductor layer 113 are processed according to the pattern of the resist mask. The processing can be performed by, for example, an etching method, and is preferably performed by dry etching, which facilitates fine processing. Then, the resist mask is removed. As described above, the conductive layer 115 and the semiconductor layer 113 can be processed by using the same mask pattern. Processing the conductive layer 115 and the semiconductor layer 113 by using the same mask pattern is preferable because the number of masks required for manufacturing a semiconductor device can be reduced compared to processing the conductive layer 115 and the semiconductor layer 113 by using different mask patterns. Note that when manufacturing the semiconductor device shown in FIG. 5(A) to FIG. 5(D), a metal oxide film between the conductive layer 115 and the semiconductor layer 113 is processed by using the same mask pattern as the above mask pattern.

[0325] Next, an insulating layer 131 is formed on the insulating layer 105 and the conductive layer 115, and an insulating layer 133 is formed on the insulating layer 131 (FIGS. 17(A), 17(B), and 17(C)). FIG. 17(A) is a plan view, FIG. 17(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 17(A), and FIG. 17(C) is a cross-sectional view taken along dashed line B1-B2 in FIG. 17(A). The insulating layer 131 and the insulating layer 133 can be formed by, for example, a CVD method, an ALD method, a sputtering method, an MBE method, or a PLD method. For example, silicon nitride can be used for the insulating layer 131, and silicon oxide can be used for the insulating layer 133.

[0326] Next, planarization is performed on the insulating layer 133, the insulating layer 131, the conductive layer 115, the semiconductor layer 113, the insulating layer 105, the conductive layer 112, the mask layer 125, the sacrificial layer 123b, and the sacrificial layer 123a (FIGS. 18(A), 18(B), and 18(C)). FIG. 18(A) is a plan view, FIG. 18(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 18(A), and FIG. 18(C) is a cross-sectional view taken along dashed line B1-B2 in FIG. 18(A). At least some of the planarization treatment for the insulating layer 133, the planarization treatment for the insulating layer 131, the planarization treatment for the conductive layer 115, the planarization treatment for the semiconductor layer 113, the planarization treatment for the insulating layer 105, the planarization treatment for the conductive layer 112, the planarization treatment for the mask layer 125, and the planarization treatment for the sacrificial layer 123 can be performed in parallel during at least a portion of a period.

[0327] The planarization process can be performed by, for example, a CMP method. <3> This can be done until the top surface of the

[0328] By planarization treatment on the conductive layer 115, a conductive layer 115a and a conductive layer 115b facing the conductive layer 115a with the semiconductor layer 113 interposed therebetween can be formed in a region not overlapping with the conductive layer 111 and the conductive layer 112. The conductive layer 115a and the conductive layer 115b can be formed to have a shape along the side surface of the semiconductor layer 113 in the region not overlapping with the conductive layer 111 and the conductive layer 112.

[0329] By the planarization treatment of the conductive layer 112, a conductive layer 112a and a conductive layer 112b facing the conductive layer 112a with the conductive layer 111 interposed therebetween can be formed. <1> or side surface 141a <3> The conductive layer 112b can be formed to have a region in contact with the side surface 141b shown in FIG. <1> or side surface 141b <3> The insulating layer 10 can be formed to have a region in contact with the insulating layer 10 .

[0330] Through the above steps, the transistor 11 including the conductive layer 111, the conductive layer 112a, the conductive layer 112b, the semiconductor layer 113, the conductive layer 115a, the conductive layer 115b, and the insulating layer 105 can be formed.

[0331] The planarization process for the insulating layer 133, the insulating layer 131, the conductive layer 115, the semiconductor layer 113, the insulating layer 105, the conductive layer 112, the mask layer 125, the sacrificial layer 123b, and the sacrificial layer 123a is performed by, for example, a CMP method ending at the sacrificial layer 123a. <3> When the end point is the conductive layer 111 <3> This can prevent the upper surface from being subjected to a planarization process.

[0332] As described above, the conductive layer 111 <3> It is preferable to make the film thickness of the conductive layer 111 thin. <3> When the thickness of the conductive layer 111 is small, <3> When the upper surface of the conductive layer 111 is planarized, <3> Therefore, the conductive layer 111 may disappear. <3> A planarization process is performed using the upper sacrificial layer 123a as an end point, so that the conductive layer 111 <3> The upper surface of the conductive layer 111 is prevented from being planarized. <3> This can prevent the loss of the conductive layer 111. Therefore, the semiconductor device of one embodiment of the present invention can be manufactured with a high yield. On the other hand, if the sacrificial layer 123a is thick, the sacrificial layer 123a may remain even after the planarization treatment is completed. As described above, the sacrificial layer 123a does not remain after the planarization treatment that ends at the sacrificial layer 123a, and the conductive layer 111 <3> It is preferable that the thickness is set so that the sacrificial layer 123a is not subjected to planarization treatment. Note that, as shown in Fig. 2(D) and Fig. 2(E), a part of the sacrificial layer 123a may remain. Even in this case, it is preferable that the thickness of the remaining sacrificial layer 123a is as thin as possible.

[0333] Furthermore, by forming a dummy pattern so as to surround at least a part of the region in which the transistor 11 is to be formed, the area of ​​the sacrificial layer 123a in a plan view can be increased, for example, compared to a case in which a dummy pattern is not formed. This makes it easier to detect the end point of the planarization process. Thus, the semiconductor device of one embodiment of the present invention can be manufactured with a high yield.

[0334] As described above, it is preferable to use a material different from that of the insulating layer 133 for the sacrificial layer 123b. This makes it possible to easily detect the end point, for example, when the sacrificial layer 123a is set as the end point in the planarization process. Note that the same material as that used for the insulating layer 133 can be used for the sacrificial layer 123a. For example, when silicon oxide is used as the insulating layer 133 as described above, silicon oxide can be used for the sacrificial layer 123a, and silicon nitride can be used for the sacrificial layer 123b.

[0335] In manufacturing the semiconductor device illustrated in FIGS. 5A to 5D, a metal oxide film between the conductive layer 115 and the semiconductor layer 113 is subjected to planarization treatment, so that a metal oxide layer 114a and a metal oxide layer 114b facing the metal oxide layer 114a with the semiconductor layer 113 interposed therebetween can be formed in a region not overlapping with the conductive layer 111 and the conductive layer 112. The metal oxide layer 114a and the metal oxide layer 114b can be formed to have a shape along a side surface of the semiconductor layer 113 in a region not overlapping with the conductive layer 111 and the conductive layer 112. The conductive layer 115a can be formed to have a region having a shape along a side surface of the metal oxide layer 114a and a region along an upper surface other than the top surface. The conductive layer 115b can be formed to have a region having a shape along a side surface of the metal oxide layer 114b and a region along an upper surface other than the top surface.

[0336] Next, the conductive layer 111 <3> An insulating layer 135 is formed on the conductive layer 112a, the conductive layer 112b, the conductive layer 115a, the conductive layer 115b, the insulating layer 105, the insulating layer 131, the insulating layer 133, and the conductive layer 111D, and an insulating layer 137 is formed on the insulating layer 135 (FIGS. 18(D) and 18(E)). Here, FIG. 18(A) can be referred to for a plan view. FIG. 18(D) is a cross-sectional view between the dashed dotted line A1-A2 shown in FIG. 18(A), and FIG. 18(E) is a cross-sectional view between the dashed dotted line B1-B2 shown in FIG. 18(A). The insulating layer 135 and the insulating layer 137 can be formed by using, for example, a CVD method, an ALD method, a sputtering method, an MBE method, or a PLD method. For example, silicon nitride can be used for the insulating layer 135, and silicon oxide can be used for the insulating layer 137.

[0337] In this manner, the semiconductor device shown in FIGS. 2A to 2C can be manufactured.

[0338] <Example of how to make a memory device> 6B and 6C will be described below. Note that steps different from the above <Example of Manufacturing Method of Semiconductor Device> will be mainly described, and the same steps will not be described as appropriate.

[0339] First, the same steps as those shown in Fig. 8(A) to Fig. 16(C) are performed. Then, an insulating layer 106 is formed on the insulating layer 105 and the conductive layer 115 (Fig. 19(A) and Fig. 19(B)). Fig. 19(A) is a cross-sectional view corresponding to Fig. 6(B), and Fig. 19(B) is a cross-sectional view corresponding to Fig. 6(C). The insulating layer 106 can be formed by using, for example, an ALD method, a CVD method, or the like.

[0340] Next, a conductive layer 116 is formed on the insulating layer 106 and processed (FIG. 19A and FIG. 19B). The conductive layer 116 can be formed by, for example, a CVD method, an ALD method, a sputtering method, or the like. Note that the conductive layer 116 may have a stacked structure of two or more layers. In this case, the film formation method can be different for each layer.

[0341] The conductive layer 116 can be processed according to a pattern of the resist mask after forming a resist mask by, for example, photolithography. The processing can be performed by, for example, an etching method, and is preferably performed by dry etching because fine processing is easy. Then, the resist mask is removed. The conductive layer 116 can be formed so as to overlap with the conductive layer 115, for example.

[0342] Next, an insulating layer 131 is formed over the insulating layer 106 and the conductive layer 116, and an insulating layer 133 is formed over the insulating layer 131 (FIGS. 19A and 19B). For the formation of the insulating layer 131 and the insulating layer 133, refer to the descriptions in FIGS. 17A to 17C.

[0343] Next, planarization treatment is performed on the insulating layer 133, the insulating layer 131, the conductive layer 116, the insulating layer 106, the conductive layer 115, the semiconductor layer 113, the insulating layer 105, the conductive layer 112, the mask layer 125, the sacrificial layer 123b, and the sacrificial layer 123a (FIGS. 20(A) and 20(B)). FIG. 20(A) is a cross-sectional view corresponding to FIG. 6(B), and FIG. 20(B) is a cross-sectional view corresponding to FIG. 6(C). For the planarization treatment, refer to the descriptions of FIGS. 18(A) to 18(C).

[0344] By the above planarization treatment, the transistor 11 can be formed, which includes the conductive layer 111, the conductive layer 112a, the conductive layer 112b, the semiconductor layer 113, the conductive layer 115a, the conductive layer 115b, and the insulating layer 105. In addition, the capacitor 13 can be formed, which includes the conductive layer 115b, the insulating layer 106, and the conductive layer 116.

[0345] Next, the conductive layer 111 <3> An insulating layer 135 is formed on the conductive layer 112a, the conductive layer 112b, the conductive layer 115a, the conductive layer 115b, the conductive layer 116, the insulating layer 105, the insulating layer 106, the insulating layer 131, the insulating layer 133, and the conductive layer 111D, and an insulating layer 137 is formed on the insulating layer 135. For the formation of the insulating layer 135 and the insulating layer 137, refer to the descriptions of FIGS. 18(D) and 18(E).

[0346] Next, a first opening reaching the conductive layer 112b is formed in the insulating layer 137, the insulating layer 135, the insulating layer 133, the insulating layer 131, the insulating layer 106, and the insulating layer 105. A second opening reaching the conductive layer 115a is formed in the insulating layer 137, the insulating layer 135, the insulating layer 133, the insulating layer 131, and the insulating layer 106. Furthermore, a third opening reaching the conductive layer 115b is formed in the insulating layer 137, the insulating layer 135, the insulating layer 133, and the insulating layer 131. The first to third openings can be formed in parallel.

[0347] Next, a conductive layer 151a having a region located inside the first opening, a conductive layer 151b having a region located inside the second opening, and a conductive layer 151c having a region located inside the third opening are formed. For example, a conductive film is formed to fill the first to third openings, and a planarization treatment is performed on the conductive film, thereby forming the conductive layers 151a, 151b, and 151c. The planarization treatment can be performed by, for example, a CMP method ending at the insulating layer 137.

[0348] Next, the conductive layer 153a is formed over the conductive layer 151a, the conductive layer 153b is formed over the conductive layer 151b, and the conductive layer 153c is formed over the conductive layer 151c. For example, a conductive film to be the conductive layer 153a, the conductive layer 153b, and the conductive layer 153c is formed over the conductive layer 151a, the conductive layer 151b, the conductive layer 151c, and the insulating layer 137, and the conductive film is processed to form the conductive layer 153a, the conductive layer 153b, and the conductive layer 153c.

[0349] Subsequently, an insulating layer 155 is formed over the conductive layers 153a, 153b, and 153c, and over the insulating layer 137. The insulating layer 155 can be formed by a method similar to that for the insulating layer 137.

[0350] Next, an opening reaching the conductive layer 153a is formed in the insulating layer 155. Next, a conductive layer 175 having a region located inside the opening is formed, for example, by a method similar to that of the conductive layer 151a. Next, a conductive layer 177 on the conductive layer 175 is formed, for example, by a method similar to that of the conductive layer 153a. Then, an insulating layer 179 on the conductive layer 177 and on the insulating layer 155 is formed, for example, by a method similar to that of the insulating layer 155.

[0351] Through the above steps, the memory device illustrated in FIG. 6B and FIG. 6C can be manufactured.

[0352] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0353] (Embodiment 2) In this embodiment, a memory device including a transistor of one embodiment of the present invention will be described with reference to drawings.

[0354] In this embodiment, a configuration example of a memory device using a memory cell having the transistor described in the above embodiment will be described, in which a layer having a functional circuit having a function of amplifying and outputting a data potential held in the memory cell is provided between layers having stacked memory cells.

[0355] <Storage device configuration example 1> FIG. 21 illustrates a block diagram of a storage device of one embodiment of the present invention.

[0356] 21 includes a driver circuit 621 and a memory array 620. The memory array 620 includes a plurality of memory cells 610 and a functional layer 650 including a plurality of functional circuits 651.

[0357] 21 shows an example in which a memory array 620 has a plurality of memory cells 610 arranged in a matrix of m rows and n columns (m and n are each independently an integer of 2 or more.) Also, in FIG. 21, a functional circuit 651 is provided for each wiring BL that functions as a bit line, and a functional layer 650 has a plurality of functional circuits 651 provided corresponding to the n wirings BL.

[0358] In FIG. 21, the memory cell 610 in the first row and first column is indicated as memory cell 610[1,1], and the memory cell 610 in the mth row and nth column is indicated as memory cell 610[m,n]. In addition, for example, in this embodiment, an arbitrary row may be indicated as row i. In addition, an arbitrary column may be indicated as column j. Thus, i is an integer between 1 and m, and j is an integer between 1 and n. In addition, for example, in this embodiment, the memory cell 610 in the ith row and jth column is indicated as memory cell 610[i,j]. Note that, for example, in this embodiment, when "i+α" (α is a positive or negative integer) is indicated, "i+α" is not less than 1 and does not exceed m. Similarly, when "j+α" is indicated, "j+α" is not less than 1 and does not exceed n.

[0359] The memory array 620 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. For example, in this embodiment, the first wiring WL (first row) is indicated as wiring WL[1], and the mth wiring WL (mth row) is indicated as wiring WL[m]. Similarly, the first wiring PL (first row) is indicated as wiring PL[1], and the mth wiring PL (mth row) is indicated as wiring PL[m]. Similarly, the first wiring BL (first column) is indicated as wiring BL[1], and the nth wiring BL (nth column) is indicated as wiring BL[n].

[0360] The memory cells 610 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 610 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0361] A DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory) can be applied to the memory array 620. DOSRAM is a RAM having 1T (transistor) 1C (capacitor) type memory cells, and refers to a memory in which the access transistor is an OS transistor. The current flowing between the source and drain in the off state of the OS transistor, that is, the leakage current, is extremely small. By turning off (non-conducting) the access transistor, the DOSRAM can hold a charge corresponding to the data held in the capacitance (capacitor) for a long time. Therefore, the DOSRAM can reduce the frequency of refresh operations compared to a DRAM composed of a transistor (Si transistor) having silicon in the channel formation region. As a result, it is possible to reduce power consumption. In addition, since the frequency characteristic of the OS transistor is high, reading and writing of the storage device can be performed at high speed. This makes it possible to provide a storage device with a high operating speed.

[0362] In addition, by using an OS transistor with low off-state current for a memory cell, stored contents can be retained for a long time. That is, a refresh operation is not required or is performed very rarely, and thus the power consumption of the memory device can be sufficiently reduced. Note that in a typical DRAM, the frequency of the refresh operation needs to be about once per 60 msec. However, in a memory device of one embodiment of the present invention, the frequency of the refresh operation can be about once per 10 sec, which is 10 times or more or 100 times or more the frequency of the refresh operation. Note that in the memory device of one embodiment of the present invention, the frequency of the refresh operation can be set to once per 1 sec to 100 sec, preferably once per 5 sec to 50 sec.

[0363] 21, a plurality of memory arrays 620[1] to 620[m] can be stacked. The memory arrays 620[1] to 620[m] of the memory array 620 are arranged in a vertical direction to the substrate surface on which the driver circuit 621 is provided, thereby improving the memory density of the memory cells 610.

[0364] The wiring BL functions as a bit line for writing and reading data, the wiring WL functions as a word line for controlling the on / off (conducting state or non-conducting state) of an access transistor functioning as a switch, and the wiring PL functions as a constant potential line connected to a capacitance.

[0365] The memory cells 610 included in each of the memory arrays 620[1] to 620[m] are connected to the functional circuit 651 via wirings BL. The wirings BL can be arranged in a direction perpendicular to the substrate surface on which the driver circuit 621 is provided. By providing the wirings BL extending from the memory cells 610 included in the memory arrays 620[1] to 620[m] in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 620 and the functional circuit 651 can be shortened. Therefore, the signal propagation distance between two circuits connected to the bit line can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay. In addition, the memory cells 610 can be operated even if the capacitance value of the capacitance is reduced.

[0366] The functional circuit 651 has a function of amplifying a data potential held in the memory cell 610 and outputting it to a sense amplifier 646 of the driver circuit 621 through a wiring GBL (not shown) described later. With this configuration, a slight potential difference of the wiring BL can be amplified when reading data. The wiring GBL can be arranged in a vertical direction to the substrate surface on which the driver circuit 621 is provided, similar to the wiring BL. By providing the wiring BL and the wiring GBL extending from the memory cell 610 included in the memory arrays 620[1] to 620[m] in a vertical direction to the substrate surface, the length of the wiring between the functional circuit 651 and the sense amplifier 646 can be shortened. Therefore, the signal propagation distance between two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL can be significantly reduced, thereby realizing reduction in power consumption and signal delay.

[0367] Note that the wiring BL is provided in contact with a semiconductor layer of a transistor included in the memory cell 610. Alternatively, the wiring BL is provided in contact with a region that functions as a source or drain of a semiconductor layer of a transistor included in the memory cell 610. Alternatively, the wiring BL is provided in contact with a conductive layer provided in contact with a region that functions as a source or drain of a semiconductor layer of a transistor included in the memory cell 610. In other words, the wiring BL can be said to be a wiring for electrically connecting one of the source and the drain of a transistor included in a memory cell 610 in each layer of the memory array 620 to the functional circuit 651 in the vertical direction.

[0368] The memory array 620 can be provided overlapping the drive circuit 621. By providing the drive circuit 621 and the memory array 620 overlapping, the signal propagation distance between the drive circuit 621 and the memory array 620 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 621 and the memory array 620 can be reduced, and the power consumption and signal delay can be reduced. In addition, the storage device 600 can be made smaller.

[0369] The functional circuit 651 can be freely arranged on a circuit using Si transistors, similar to the memory arrays 620[1] to 620[m], by using OS transistors similar to the transistors in the memory cell 610 of the DOSRAM, and can be easily integrated. By configuring the functional circuit 651 to amplify signals, for example, the sense amplifier 646, which is a subsequent circuit, can be made smaller. Therefore, the memory device 600 can be made smaller.

[0370] The drive circuit 621 includes a PSW 622 (power switch), a PSW 623, and a peripheral circuit 631. The peripheral circuit 631 includes a peripheral circuit 641, a control circuit 632, and a voltage generating circuit 633.

[0371] In the storage device 600, each circuit, each signal, and each voltage can be appropriately selected or omitted as necessary. Or, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0372] Moreover, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 632.

[0373] The control circuit 632 is a logic circuit having a function of controlling the overall operation of the memory device 600. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 600. Alternatively, the control circuit 632 generates a control signal for the peripheral circuit 641 so that this operation mode is executed.

[0374] The voltage generating circuit 633 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 633. For example, when an H-level signal is provided to the signal WAKE, the signal CLK is input to the voltage generating circuit 633, and the voltage generating circuit 633 generates a negative voltage.

[0375] The peripheral circuit 641 is a circuit for writing and reading data to and from the memory cell 610. The peripheral circuit 641 is also a circuit for outputting various signals for controlling the functional circuit 651. The peripheral circuit 641 has a row decoder 642, a row driver 643, a column decoder 644, a column driver 645, a sense amplifier 646, an input circuit 647, and an output circuit 648.

[0376] The row decoder 642 and the column decoder 644 have a function of decoding the signal ADDR. The row decoder 642 is a circuit for specifying a row to be accessed, and the column decoder 644 is a circuit for specifying a column to be accessed. The row driver 643 has a function of selecting the wiring WL specified by the row decoder 642. The column driver 645 has a function of writing data to the memory cell 610, a function of reading data from the memory cell 610, a function of holding the read data, and the like.

[0377] The input circuit 647 has a function of holding a signal WDA. The data held by the input circuit 647 is output to the column driver 645. The output data of the input circuit 647 is data (Din) to be written to the memory cell 610. The data (Dout) read from the memory cell 610 by the column driver 645 is output to the output circuit 648. The output circuit 648 has a function of holding Dout. In addition, the output circuit 648 has a function of outputting Dout to the outside of the memory device 600. The data output from the output circuit 648 is a signal RDA.

[0378] The PSW622 has a function of controlling the supply of VDD to the peripheral circuit 631. The PSW623 has a function of controlling the supply of VHM to the row driver 643. Here, the high power supply voltage of the memory device 600 is VDD, and the low power supply voltage is GND (ground potential). Also, VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD. The on / off of the PSW622 is controlled by a signal PON1, and the on / off of the PSW623 is controlled by a signal PON2. In FIG. 21, the number of power supply domains to which VDD is supplied in the peripheral circuit 631 is one, but it may be multiple. In this case, a power switch may be provided for each power supply domain.

[0379] The memory array 620 including the memory arrays 620[1] to 620[m] (m is an integer of 2 or more) and the functional layer 650 can be provided by stacking multiple layers of the memory arrays 620 on a driver circuit 621. By stacking multiple layers of the memory arrays 620, the memory density of the memory cells 610 can be increased. FIG. 22A shows a perspective view of a storage device 600 including a functional layer 650 and five layers (m=5) of memory arrays 620[1] to 620[5] stacked on a driver circuit 621.

[0380] In Fig. 22(A), the memory array 620 provided in the first layer is shown as memory array 620[1], the memory array 620 provided in the second layer is shown as memory array 620[2], and the memory array 620 provided in the fifth layer is shown as memory array 620[5]. Fig. 22(A) also shows wiring WL and wiring PL extending in the X direction, and wiring BL extending in the Z direction (the direction perpendicular to the substrate surface on which the driving circuit is provided). Note that, in order to make the drawing easier to understand, the wiring WL and wiring PL of each memory array 620 are partially omitted.

[0381] 22B is a schematic diagram illustrating a configuration example of a functional circuit 651 connected to the wiring BL illustrated in FIG. 22A and memory cells 610 included in memory arrays 620[1] to 620[5] connected to the wiring BL. FIG. 22B also illustrates a wiring GBL provided between the functional circuit 651 and the driver circuit 621. Note that a configuration in which multiple memory cells (memory cells 610) are electrically connected to one wiring BL is also referred to as a "memory string." Note that in the drawings, the wiring GBL may be illustrated with a thick line to improve visibility.

[0382] 22B illustrates an example of a circuit configuration of a memory cell 610 connected to a wiring BL. The memory cell 610 includes a transistor 611 and a capacitor 612. The transistor 611, the capacitor 612, and each wiring (wiring BL, wiring WL, etc.) may also be referred to as wiring BL[1] and wiring WL[1], etc. Here, the memory cell 610, the transistor 611, and the capacitor 612 correspond to the memory cell 20, the transistor 11, and the capacitor 13 shown in the above embodiment, respectively.

[0383] In the memory cell 610, one of a source and a drain of a transistor 611 is connected to a wiring BL. The other of the source and the drain of the transistor 611 is connected to one electrode of a capacitor 612. The other electrode of the capacitor 612 is connected to a wiring PL. A gate of the transistor 611 is connected to a wiring WL. The wiring PL is a wiring that applies a constant potential to hold the potential of the capacitor 612.

[0384] 22B is provided so as to electrically connect the driver circuit 621 and the functional layer 650. Fig. 23A is a schematic diagram of a memory device 600 including a functional circuit 651 and memory arrays 620[1] to 620[m] as a structure 670. Note that although one wiring GBL is illustrated in Fig. 23A, the wiring GBL may be appropriately provided depending on the number of functional circuits 651 provided in the functional layer 650.

[0385] Note that the wiring GBL is provided in contact with a semiconductor layer of a transistor included in the functional circuit 651. Alternatively, the wiring GBL is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 651. Alternatively, the wiring GBL is provided in contact with a conductive layer provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 651. In other words, the wiring GBL can be said to be a wiring for electrically connecting one of the source and the drain of a transistor included in the functional circuit 651 in the functional layer 650 to the driver circuit 621 in the vertical direction.

[0386] 23B. The wiring GBL is connected to the functional layer 650 of the structure 670. The wiring GBL may be provided as appropriate depending on the number of functional circuits 651.

[0387] In one embodiment of the present invention, OS transistors are stacked, and wirings functioning as bit lines are arranged in a direction perpendicular to the surface of the substrate on which the driver circuit 621 is provided. By providing the wirings functioning as bit lines extending from the memory array 620 in a direction perpendicular to the surface of the substrate, the length of the wiring between the memory array 620 and the driver circuit 621 can be shortened. As a result, the parasitic capacitance of the bit lines can be significantly reduced.

[0388] In one embodiment of the present invention, a functional layer 650 including a functional circuit 651 having a function of amplifying and outputting a data potential held in a memory cell 610 is provided in a layer in which the memory array 620 is provided. With this structure, a slight potential difference of a wiring BL functioning as a bit line when reading data can be amplified to drive a sense amplifier 646 included in a driver circuit 621. Since circuits such as a sense amplifier can be miniaturized, the memory device 600 can be miniaturized. Furthermore, the memory device 600 can be operated even if the capacitance of a capacitor 612 included in the memory cell 610 is reduced.

[0389] Although the above describes a memory device having memory arrays 620[1] to 620[m], the semiconductor device according to the present invention can also be used for a single-layer memory device having only memory array 620[1].

[0390] In the above, an example in which the memory cell 610 has a 1T (transistor) 1C (capacitor) configuration has been described, but the present invention is not limited to this. For example, as shown in FIG. 24A, a 3T1C type memory cell may be used in the storage device. The memory cell shown in FIG. 24A has a transistor 611a, a transistor 611b, a transistor 611c, and a capacitor 612a. Here, the transistors 611a, 611b, and 611c can have the same configuration as the transistor 611, and the capacitor 612a can have the same configuration as the capacitor 612. A RAM having such a configuration may be called a NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM).

[0391] 24A, one of the source and drain of the transistor 611a is electrically connected to one electrode of the capacitor 612a and the gate of the transistor 611b. One of the source and drain of the transistor 611b is electrically connected to one of the source and drain of the transistor 611c. Note that wirings may be provided as appropriate for the gate of the transistor 611a, the other of the source and drain of the transistor 611a, the other of the source and drain of the transistor 611b, the gate of the transistor 611c, the other of the source and drain of the transistor 611c, and the other electrode of the capacitor 612a. The structure of the memory device can also be modified as appropriate in accordance with these wirings.

[0392] Alternatively, as shown in FIG. 24B, the transistor 611c may not be provided, and only the transistors 611a and 611b and the capacitor 612a may be used.

[0393] In addition, when the parasitic capacitances of the transistors 611a and 611b are sufficiently large, the capacitor 612a may not be provided as shown in Fig. 24C. In this case, the memory cell is formed only by the transistors 611a and 611b.

[0394] <Configuration example of memory array and functional circuit> 25, a configuration example of the functional circuit 651 described in FIG. 21 to FIG. 23 and a configuration example of the sense amplifier 646 included in the memory array 620 and the driver circuit 621 will be described. FIG. 25 illustrates a driver circuit 621 connected to wirings GBL (wirings GBL_A and GBL_B) connected to a functional circuit 651 (functional circuit 651A and functional circuit 651B) connected to memory cells 610 (memory cell 610A and memory cell 610B) connected to different wirings BL (wirings BL_A and BL_B). As the driver circuit 621 illustrated in FIG. 25, in addition to the sense amplifier 646, a precharge circuit 671A, a precharge circuit 671B, a switch circuit 672A, a switch circuit 672B, and a write / read circuit 673 are illustrated.

[0395] Transistors 652a, 652b, 653a, 653b, 654a, 654b, 655a, and 655b are illustrated as the functional circuits 651A and 651B. The transistors 652a, 652b, 653a, 653b, 654a, 654b, 655a, and 655b illustrated in Fig. 25 are OS transistors, similar to the transistor 611 included in the memory cell 610. The functional layer 650 including the functional circuit 651 can be stacked in the same manner as the memory arrays 620[1] to 620[m].

[0396] The wiring BL_A is connected to the gate of the transistor 652a, and the wiring BL_B is connected to the gate of the transistor 652b. The wiring GBL_A is connected to one of the sources and drains of the transistors 653a and 654a. The wiring GBL_B is connected to one of the sources and drains of the transistors 653b and 654b. The wiring GBL_A and the wiring GBL_B are provided in the vertical direction like the wiring BL_A and the wiring BL_B, and are connected to the transistors included in the driver circuit 621. As shown in FIG. 25, a selection signal MUX, a control signal WE, or a control signal RE is applied to the gates of the transistors 653a, 653b, 654a, 654b, 655a, and 655b, respectively.

[0397] 25, the transistors 681_1 to 681_6 and the transistors 682_1 to 682_4 constituting the sense amplifier 646, the precharge circuit 671A, and the precharge circuit 671B are configured with Si transistors. The switches 683A to 683D constituting the switch circuit 672A and the switch circuit 672B can also be configured with Si transistors. One of the source and the drain of the transistors 653a, 653b, 654a, and 654b is connected to the transistor or switch constituting the precharge circuit 671A, the precharge circuit 671B, the sense amplifier 646, and the switch circuit 672A.

[0398] The precharge circuit 671A includes n-channel transistors 681_1 to 681_3. The precharge circuit 671A is a circuit for precharging the wirings BL_A and BL_B to an intermediate potential VPC that corresponds to a potential VDD / 2 between a high power supply potential (VDD) and a low power supply potential (VSS) in response to a precharge signal applied to a precharge line PCL1.

[0399] The precharge circuit 671B includes n-channel transistors 681_4 to 681_6. The precharge circuit 671B is a circuit for precharging the wirings GBL_A and GBL_B to an intermediate potential VPC that corresponds to a potential VDD / 2 between VDD and VSS in response to a precharge signal provided to a precharge line PCL2.

[0400] The sense amplifier 646 includes p-channel transistors 682_1 and 682_2, and n-channel transistors 682_3 and 682_4, which are connected to the wiring VHH or the wiring VLL. The wiring VHH or the wiring VLL is a wiring having a function of applying VDD or VSS. The transistors 682_1 to 682_4 are transistors that configure an inverter loop. The potentials of the precharged wirings BL_A and BL_B are changed by selecting the memory cell 610A and the memory cell 610B, and the potentials of the wirings GBL_A and GBL_B are set to VDD or VSS in response to the change. The potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 683C and 683D, and the write / read circuit 673. The wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to a bit line pair. The write / read circuit 673 controls writing of a data signal in response to a signal EN_data.

[0401] The switch circuit 672A is a circuit for controlling the conduction state between the sense amplifier 646 and the wiring GBL_A and the wiring GBL_B. The switch circuit 672A is switched on or off under the control of a switching signal CSEL1. When the switches 683A and 683B are n-channel transistors, the switching signal CSEL1 is turned on at a high level and turned off at a low level. The switch circuit 672B is a circuit for controlling the conduction state between the write / read circuit 673 and the bit line pair connected to the sense amplifier 646. The switch circuit 672B is switched on or off under the control of a switching signal CSEL2. The switches 683C and 683D may be similar to the switches 683A and 683B.

[0402] 25, the memory device 600 can be configured such that the memory cell 610, the functional circuit 651, and the sense amplifier 646 are connected via wirings BL and GBL that are provided in the vertical direction, which is the shortest distance. Although the number of functional layers 650 having transistors that configure the functional circuit 651 is increased, the load of the wirings BL is reduced, thereby shortening the write time and making it easier to read data.

[0403] 25, each transistor included in the functional circuit 651A and the functional circuit 651B is controlled in response to control signals WE, RE, and a selection signal MUX. Each transistor can output the potential of the wiring BL to the driver circuit 621 via the wiring GBL in response to the control signal and the selection signal. The functional circuit 651A and the functional circuit 651B can function as a sense amplifier configured with OS transistors. With this configuration, a slight potential difference of the wiring BL can be amplified during reading to drive the sense amplifier 646 using Si transistors.

[0404] <Storage device configuration example 2> An example of the configuration of the storage device 600 will be described with reference to FIG.

[0405] The memory device 600 includes a driver circuit 621 which is a layer including the transistor 310, a functional layer 650 which is a layer including a transistor 652, a transistor 653, a transistor 654, a transistor 655, and the like over the driver circuit 621, and a memory array 620[1] to a memory array 620[m] over the functional layer 650. Note that the transistor 652 corresponds to the transistors 652a and 652b. The transistor 653 corresponds to the transistors 653a and 653b. The transistor 654 corresponds to the transistors 654a and 654b. The transistor 655 corresponds to the transistors 655a and 655b.

[0406] 26 illustrates a transistor 310 included in a driver circuit 621. The transistor 310 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate electrode, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 including a part of the substrate 311, a low-resistance region 314a functioning as one of a source region and a drain region, and a low-resistance region 314b functioning as the other of the source region and the drain region. The transistor 310 may be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single crystal silicon substrate can be used.

[0407] Here, in the transistor 310 shown in FIG. 26, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductive layer 316 is provided so as to cover the side and top surface of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulating layer that is in contact with an upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0408] Note that the transistor 310 illustrated in FIG. 26 is just an example and is not limited to the structure. Any appropriate transistor can be used depending on the circuit configuration or driving method.

[0409] Between each structure, a wiring layer having an interlayer insulating layer, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Here, the conductive layer having the function of a plug or wiring may be collectively given the same reference symbol as a plurality of structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0410] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer insulating layer over the transistor 310. A conductive layer 328 and the like are embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330 and the like are embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0411] In addition, the insulating layer functioning as an interlayer insulating layer may also function as a planarizing film that covers the uneven shape underneath. For example, the upper surface of the insulating layer 322 may be planarized by CMP processing to improve flatness.

[0412] 26 illustrates a transistor 652, a transistor 653, and a transistor 655 included in the functional layer 650. The transistor 652, the transistor 653, and the transistor 655 have a structure similar to that of the transistor 11 described in the above embodiment. The source electrodes and drain electrodes of the transistor 652, the transistor 653, and the transistor 655 are connected in series.

[0413] An insulating layer 208 is provided over the transistor 652, the transistor 653, and the transistor 655, and a conductive layer 207 is provided in an opening formed in the insulating layer 208. Further, an insulating layer 210 is provided over the insulating layer 208, and a conductive layer 209 is provided in an opening formed in the insulating layer 210. Further, an insulating layer 212 is provided over the insulating layer 210. A part of a conductive layer 240 provided in the memory array 620[1] is embedded in the opening formed in the insulating layer 212. Here, the conductive layer 240 is provided to extend in the Z direction and functions as a wiring BL.

[0414] The insulating layer 208 and the insulating layer 210 can be formed using an insulating layer applicable to the insulating layer 101 in the above embodiment. The insulating layer 212 can be formed using an insulating layer applicable to the insulating layer 131 in the above embodiment.

[0415] The bottom surface of the conductive layer 207 is in contact with the top surface of the conductive layer 111 of the transistor 652. The top surface of the conductive layer 207 is in contact with the bottom surface of the conductive layer 209. The top surface of the conductive layer 209 is in contact with the bottom surface of the conductive layer 240 provided in the memory array 620[1]. With this structure, the conductive layer 240 corresponding to the wiring BL and the gate of the transistor 652 can be electrically connected to each other.

[0416] Each of the memory arrays 620[1] to 620[m] includes a plurality of memory cells 610. As described above, the memory cell 610 includes a transistor 611 and a capacitor 612. Figure 26 illustrates an example in which the transistor 611 and the capacitor 612 have the same configurations as the transistor 11 and the capacitor 13 shown in Figure 6C of the above embodiment, respectively.

[0417] As shown in FIG. 26, a conductive layer 240 is provided in contact with the conductive layer 115a of the transistor 611. As described above, the conductive layer 240 is provided extending in the Z direction and functions as a wiring BL. FIG. 26 shows an example in which the upper surface and side end of the conductive layer 115a have a region in contact with the conductive layer 240 extending in the Z direction. Since the conductive layer 240 directly contacts at least a part of the upper surface and side end of the conductive layer 115a, there is no need to provide a separate electrode for connection, and therefore the area occupied by the memory array can be reduced. In addition, the integration degree of the memory cells is improved, and the memory capacity of the memory device can be increased.

[0418] The conductive layer 240 of each memory cell 610 is electrically connected to the conductive layer 240 in the upper layer and the conductive layer 240 in the lower layer. The conductive layer 240 is shared between adjacent memory cells 610. Furthermore, in adjacent memory cells 610, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductive layer 240.

[0419] In the above-described memory array 620, a plurality of memory arrays 620[1] to 620[m] can be stacked. The memory arrays 620[1] to 620[m] of the memory array 620 can be arranged in the vertical direction of the substrate surface on which the driver circuit 621 is provided, thereby improving the memory density of the memory cells 610. The memory array 620 can be manufactured by repeatedly manufacturing the same manufacturing process in the vertical direction. The memory device 600 can reduce the manufacturing cost of the memory array 620.

[0420] <Memory cell configuration example> An example of the configuration of a memory cell having a 2T (transistor) 1C (capacitor) type configuration will be described with reference to FIG.

[0421] 27 includes a transistor 310, a transistor 200 provided above the transistor 310, and a capacitor 400 provided above the transistor 310 and the transistor 200. In the example shown in FIG 27, the transistor 200 and the capacitor 400 have structures similar to those of the transistor 11 and the capacitor 13 shown in FIG 7A of the above embodiment, respectively.

[0422] The transistor 200 is a transistor that uses a metal oxide layer as a semiconductor layer. Since the off-state current of the transistor 200 is small, the use of the transistor 200 in a memory device enables stored data to be retained for a long period of time. In other words, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.

[0423] The memory device shown in FIG. 27 can be arranged in a matrix to form a memory cell array.

[0424] The above description of <Structure Example 2 of Memory Device> can be referred to for the structure of the transistor 310. Note that the transistor 310 illustrated in FIG. 27 is just an example and is not limited to the structure, and an appropriate transistor can be used depending on the circuit configuration or a driving method.

[0425] The capacitor 400 has a conductive layer 410 that functions as one of a pair of electrodes, a conductive layer 420 that functions as the other of the pair of electrodes, and an insulating layer 430 that functions as a dielectric layer.

[0426] The conductive layer 410 can be formed using, for example, the material that can be used for the conductive layer 153c in the above embodiment. The conductive layer 420 can be formed using, for example, the material that can be used for the conductive layer 157 in the above embodiment.

[0427] The conductive layer 412 can be formed, for example, at the same time as the conductive layer 410. Note that the conductive layer 412 functions as a plug or a wiring electrically connected to the capacitor 400, the transistor 200, or the transistor 310.

[0428] 27, the conductive layer 412 and the conductive layer 410 each have a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, between a conductive layer having a barrier property and a conductive layer having high conductivity, a conductive layer having a barrier property and a conductive layer having high adhesion to the conductive layer having high conductivity may be formed.

[0429] The insulating layer 430 can be an insulating layer which can be used as the insulating layer 156 in the above embodiment.

[0430] In the memory cell shown in FIG. 27, a wiring 1001 is electrically connected to a low-resistance region 314a of the transistor 310. A wiring 1002 is electrically connected to a low-resistance region 314b of the transistor 310. A wiring 1003 is electrically connected to a conductive layer 115a of the transistor 200. A wiring 1004 is electrically connected to a conductive layer 111 of the transistor 200. A conductive layer 316 of the transistor 310 and a conductive layer 115b of the transistor 200 are electrically connected to a conductive layer 410 of the capacitor 400. A wiring 1005 is electrically connected to a conductive layer 420 of the capacitor 400.

[0431] Between each of the structures, a wiring layer may be provided that includes an interlayer insulating layer, wiring, plugs, etc. Also, a plurality of wiring layers may be provided according to the design.

[0432] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer insulating layer over the transistor 310. A capacitor 400, or a conductive layer 328 and a conductive layer 330 electrically connected to the transistor 200 are embedded in the insulating layer 320, the insulating layer 322, the insulating layer 324, and the insulating layer 326. For these insulating layers and these conductive layers, the description in the above <Structure Example 2 of Memory Device> can be referred to.

[0433] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in FIG. 27, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0434] 27, an insulating layer 210, an insulating layer 212, and an insulating layer 216 are stacked in this order over the insulating layer 354 and the conductive layer 356. A conductive layer 213 is embedded in the insulating layer 210, the insulating layer 212, and the insulating layer 216. Note that the conductive layer 213 functions as a plug or a wiring electrically connected to the capacitor 400 or the transistor 310.

[0435] A conductive layer 218 is embedded in the insulating layer 216. The conductive layer 218 may be provided so as to be in contact with a part of a side surface and an upper surface of the conductive layer 213. In other words, the conductive layer 218 may be provided so as to be in contact with a portion of the conductive layer 213 that is exposed from the insulating layer 212. An insulating layer 221 is provided over the insulating layer 216 and the conductive layer 218, and the transistor 200 is provided over the insulating layer 221.

[0436] Note that the conductive layer 218 functions as a plug or a wiring electrically connected to the capacitor 400, the transistor 200, or the transistor 310. Over the conductive layer 420 and the insulating layer 430, an insulating layer 450 is provided.

[0437] The insulating layer 137, the insulating layer 135, the insulating layer 133, the insulating layer 131, the insulating layer 105, and the insulating layer 221 are provided with an opening that reaches the conductive layer 218, and the conductive layer 241 is provided so as to have a region located inside the opening. The insulating layer 137, the insulating layer 135, the insulating layer 133, and the insulating layer 131 are provided with an opening that reaches the conductive layer 115a, and the conductive layer 245a is provided so as to have a region located inside the opening. The insulating layer 137, the insulating layer 135, the insulating layer 133, and the insulating layer 131 are provided with an opening that reaches the conductive layer 115b, and the conductive layer 245b is provided so as to have a region located inside the opening. Here, the conductive layer 241, the conductive layer 245a, and the conductive layer 245b can be formed in parallel.

[0438] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0439] (Embodiment 3) In this embodiment, an example of a chip on which a memory device of one embodiment of the present invention is mounted will be described with reference to FIG.

[0440] 28(A) and 28(B) are implemented with multiple circuits (systems). A technology for integrating multiple circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0441] As shown in FIG. 28A, a chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0442] 28(B), the chip 1200 is provided with bumps (not shown) and is connected to a first surface of a package substrate 1201. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201 and are connected to a motherboard 1203.

[0443] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used for the DRAM 1221. This allows the DRAM 1221 to consume less power, operate at a higher speed, and have a larger capacity.

[0444] The CPU 1211 preferably has a plurality of CPU cores. The GPU 1212 preferably has a plurality of GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The memory may be the above-mentioned DOSRAM. The GPU 1212 is suitable for parallel calculation of a large amount of data and may be used for image processing or multiplication and accumulation. By providing the GPU 1212 with an image processing circuit or a multiplication and accumulation circuit using the OS transistor described in the previous embodiment, it becomes possible to execute image processing or multiplication and accumulation with low power consumption.

[0445] In addition, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0446] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0447] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0448] The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark), or the like can be used.

[0449] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0450] The above circuits (systems) can be formed in the same manufacturing process in the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0451] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided, can be called a GPU module 1204.

[0452] Since the GPU module 1204 has the chip 1200 using SoC technology, its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. In addition, since a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), or a deep belief network (DBN), the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0453] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0454] (Embodiment 4) In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as DCs) in which the semiconductor device described in the above embodiment can be used will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0455] [Electronic components] FIG. 29(A) shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted. The electronic component 700 shown in FIG. 29(A) has a semiconductor device 710 in a mold 711. In FIG. 29(A), some parts are omitted in order to show the inside of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0456] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 is configured by stacking a plurality of memory cell arrays. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as TSV (Through Silicon Via) and a bonding technology such as Cu-Cu direct bonding. By forming the drive circuit layer 715 and the memory layer 716 as a monolithic stack, for example, a so-called on-chip memory configuration in which a memory is formed directly on a processor can be formed. By forming the on-chip memory, it is possible to increase the speed of the operation of the interface between the processor and the memory.

[0457] In addition, by configuring an on-chip memory, it is possible to reduce the size of the connection wiring, for example, compared to technologies that use through electrodes such as TSV, and therefore to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).

[0458] In addition, it is preferable that the memory cell arrays in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that in the case of a configuration using Si transistors in the memory layer 716, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that the OS transistor has a superior structure to the Si transistor in the monolithic stacked configuration.

[0459] The semiconductor device 710 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into a dice shape in the manufacturing process of a semiconductor chip. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0460] 29B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0461] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0462] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0463] The interposer 731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or in multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In some cases, a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV may be used as the through electrode.

[0464] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer for mounting HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for mounting HBM.

[0465] In addition, in SiP and MCM using silicon interposers, the reliability is less likely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. In addition, since the surface of the silicon interposer is highly flat, connection failure between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0466] On the other hand, when a silicon interposer, TSV, or the like is used to electrically connect multiple integrated circuits with different terminal pitches, a space is required for the width of the terminal pitch. Therefore, when trying to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacking configuration using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacking memory cell array.

[0467] A heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 730. When providing a heat sink, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0468] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided on the bottom of the package substrate 732. Fig. 29(B) shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. The electrodes 733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

[0469] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0470] [Electronic equipment] Next, a perspective view of an electronic device 6500 is shown in FIG. 30A. The electronic device 6500 shown in FIG. 30A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0471] An electronic device 6600 shown in FIG. 30B is an information terminal that can be used as a notebook computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention for the control device 6509 and the control device 6616 described above is preferable because power consumption can be reduced.

[0472] [Large computer] Next, Fig. 30(C) shows a perspective view of the large scale computer 5600. The large scale computer 5600 shown in Fig. 30(C) has a rack 5610 housing a plurality of rack-mounted computers 5620. The large scale computer 5600 may also be called a supercomputer.

[0473] The computer 5620 can have the configuration shown in the perspective view of Fig. 30(D), for example. In Fig. 30(D), the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.

[0474] A PC card 5621 shown in Fig. 30E is an example of a processing board including a CPU, a GPU, a storage device, and the like. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that although semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are illustrated in Fig. 30E, for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0475] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0476] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621 and inputting signals. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for the respective terminals include HDMI (registered trademark).

[0477] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0478] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected to each other by, for example, soldering the terminals to wiring provided on the board 5622 by a reflow method. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0479] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected to the terminals by, for example, reflow soldering to wiring provided on the board 5622. An example of the semiconductor device 5628 is a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0480] The mainframe 5600 can also function as a parallel computer. By using the mainframe 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference of artificial intelligence, for example.

[0481] [Space equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing data.

[0482] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor has small changes in electrical characteristics due to radiation exposure. In other words, the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident. For example, the OS transistor can be preferably used in outer space.

[0483] Fig. 31 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 31, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may include the thermosphere, mesosphere, and stratosphere.

[0484] 31, a battery management system (also referred to as BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0485] Furthermore, outer space is an environment with radiation levels 100 times higher than on the ground. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, meson rays, etc.

[0486] When sunlight is irradiated onto the solar panel 6802, power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight or where the amount of sunlight irradiated onto the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 is not generated. In order to operate the satellite 6800 even under a situation where the amount of power generated is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0487] The artificial satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver that received the signal can be measured. As described above, the artificial satellite 6800 can constitute a satellite positioning system.

[0488] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the semiconductor device according to one embodiment of the present invention is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0489] The artificial satellite 6800 can also be configured to have a sensor. For example, by configuring the artificial satellite 6800 to have a visible light sensor, the artificial satellite 6800 can have a function of detecting sunlight reflected from an object on the ground. Or, by configuring the artificial satellite 6800 to have a thermal infrared sensor, the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have a function as, for example, an earth observation satellite.

[0490] Note that in this embodiment, an artificial satellite is given as an example of space equipment, but the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0491] As described above, OS transistors have the excellent advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance than Si transistors.

[0492] [Data Center] The semiconductor device according to one embodiment of the present invention can be suitably used in a storage system applied to a data center, for example. The data center is required to perform long-term management of data, such as ensuring the immutability of the data. In order to manage long-term data, it is necessary to increase the size of the building, such as by installing storage and servers for storing a huge amount of data, by securing a stable power source for holding the data, or by securing cooling equipment required for holding the data.

[0493] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores data. Therefore, it is possible to miniaturize the storage system, the power source for storing data, and the cooling equipment. Therefore, it is possible to save space in the data center.

[0494] In addition, the semiconductor device of one embodiment of the present invention consumes less power, and thus heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0495] Fig. 32 shows a storage system applicable to a data center. A storage system 6900 shown in Fig. 32 has a plurality of servers 6901sb as a host 6901 (illustrated as Host Computer). It also has a plurality of storage devices 6903md as a storage 6903 (illustrated as Storage). The host 6901 and storage 6903 are shown connected via a storage area network 6904 (illustrated as SAN: Storage Area Network) and a storage control circuit 6902 (illustrated as Storage Controller).

[0496] The host 6901 corresponds to a computer that accesses data stored in the storage 6903. The hosts 6901 may be connected to each other via a network.

[0497] Although the storage 6903 uses flash memory to reduce the data access speed, that is, the time required to store and output data, this time is significantly longer than the time required by DRAM that can be used as cache memory in the storage. In a storage system, in order to solve the problem of the long access speed of the storage 6903, a cache memory is usually provided in the storage to reduce the time required to store and output data.

[0498] The above-mentioned cache memory is used in the storage control circuit 6902 and the storage 6903. Data exchanged between the host 6901 and the storage 6903 is stored in the cache memory in the storage control circuit 6902 and the storage 6903, and then output to the host 6901 or the storage 6903.

[0499] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing can be reduced and power consumption can be reduced. In addition, by stacking memory cell arrays, the cache memory can be made smaller.

[0500] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframes, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO2). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.

[0501] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0502] (Embodiment 5) In this embodiment, a structural example of a display device to which a transistor of one embodiment of the present invention can be applied will be described.

[0503] [Display module] 33A shows a perspective view of a display module 580. The display module 580 includes a display device 500A and an FPC 590. Note that the display panel included in the display module 580 is not limited to the display device 500A and may be a display device 500B or a display device 500C described later.

[0504] The display module 580 has a substrate 591 and a substrate 592. The display module 580 has a display unit 581. The display unit 581 is a region for displaying an image.

[0505] 33(B) is a perspective view showing a schematic configuration on the substrate 591 side. A circuit portion 582, a pixel circuit portion 583 on the circuit portion 582, and a pixel portion 584 on the pixel circuit portion 583 are stacked on the substrate 591. A terminal portion 585 for connecting to an FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel portion 584. The terminal portion 585 and the circuit portion 582 are electrically connected by a wiring portion 586 formed of a plurality of wirings.

[0506] The pixel section 584 has a plurality of pixels 584a arranged periodically. An enlarged view of one pixel 584a is shown on the right side of Fig. 33(B). The pixel 584a has a light emitting element 190R that emits red light, a light emitting element 190G that emits green light, and a light emitting element 190B that emits blue light.

[0507] The pixel circuit portion 583 has a plurality of pixel circuits 583a arranged periodically. One pixel circuit 583a is a circuit that controls the emission of three light-emitting elements (also called light-emitting devices) included in one pixel 584a. One pixel circuit 583a may be configured to have three circuits that control the emission of one light-emitting element. For example, the pixel circuit 583a may have at least one selection transistor, one current control transistor (drive transistor), and a capacitance element for each light-emitting element. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

[0508] The circuit portion 582 has a circuit for driving each pixel circuit 583a of the pixel circuit portion 583. For example, it is preferable that the circuit portion 582 has one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 582 may have at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 582 may constitute a part of the pixel circuit 583a. That is, the pixel circuit 583a may be constituted by a transistor included in the pixel circuit portion 583 and a transistor included in the circuit portion 582.

[0509] The FPC 590 functions as wiring for supplying a video signal, a power supply potential, and the like from the outside to the circuit portion 582. In addition, an IC may be mounted on the FPC 590.

[0510] The display module 580 can be configured such that one or both of the pixel circuit unit 583 and the circuit unit 582 are provided overlappingly under the pixel unit 584, so that the aperture ratio (effective display area ratio) of the display unit 581 can be extremely high. For example, the aperture ratio of the display unit 581 can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. In addition, the pixels 584a can be arranged at an extremely high density, so that the resolution of the display unit 581 can be extremely high. For example, it is preferable that the pixels 584a are arranged in the display unit 581 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and further preferably 6000 ppi or more, and 20000 ppi or less, or 30000 ppi or less.

[0511] Such a display module 580 is extremely high-definition and can be suitably used in VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration in which the display unit of the display module 580 is viewed through a lens, the display module 580 has an extremely high-definition display unit 581, so that even if the display unit is enlarged with a lens, pixels are not visible, and a highly immersive display can be performed. In addition, the display module 580 is not limited to this, and can be suitably used in electronic devices having a relatively small display unit. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0512] [Display device 500A] The display device 500A shown in FIG. 34 includes a substrate 201, a light emitting element 190R, a light emitting element 190G, a light emitting element 190B, a capacitor 180, and a transistor 520.

[0513] The substrate 201 corresponds to the substrate 591 in FIG.

[0514] The transistor 520 has a structure similar to that of the transistor 11 described in the above embodiment. The transistor 520 includes a conductive layer 111, a semiconductor layer 113, a conductive layer 115a and a conductive layer 115b, an insulating layer 105, and the like.

[0515] An insulating layer 210 is provided over the substrate 201. The insulating layer 210 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 201 to the transistor 520 and prevents oxygen from being released from the semiconductor layer 113 toward the insulating layer 210. As the insulating layer 210, a film in which one or both of hydrogen and oxygen are less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0516] The transistor 520 and the insulating layer 131 are provided over the insulating layer 210, and the insulating layer 133 is provided over the insulating layer 131. An insulating layer 135 is provided over the transistor 520, the insulating layer 131, and the insulating layer 133, and an insulating layer 137 is provided over the insulating layer 135.

[0517] Openings reaching the conductive layer 115b are provided in the insulating layers 137, 135, 133, and 131, and the conductive layer 174 is provided to have a region located inside the opening. The conductive layer 174 functions as a plug or a wiring. FIG. 34 shows an example in which the conductive layer 174 includes a conductive layer 174a covering at least a part of the side surfaces of the openings of the insulating layers 137, 135, 133, and 131 and the top surface of the conductive layer 115b, and a conductive layer 174b in contact with the top surface of the conductive layer 174a. In this case, it is preferable to use a conductive material through which hydrogen and oxygen are unlikely to diffuse as the conductive layer 174a.

[0518] Furthermore, a capacitor 180 is provided on the insulating layer 137. The capacitor 180 has a conductive layer 181, a conductive layer 185, and an insulating layer 183 located therebetween. The conductive layer 181 functions as one electrode of the capacitor 180, the conductive layer 185 functions as the other electrode of the capacitor 180, and the insulating layer 183 functions as a dielectric layer of the capacitor 180.

[0519] The conductive layer 181 is provided over the conductive layer 174 and the insulating layer 137, and is embedded in the insulating layer 154 over the insulating layer 137. The conductive layer 181 is electrically connected to the conductive layer 115b of the transistor 520 by the conductive layer 174. The insulating layer 183 is provided to cover the conductive layer 181. The conductive layer 185 is provided in a region overlapping with the conductive layer 181 with the insulating layer 183 interposed therebetween.

[0520] An insulating layer 155a is provided covering the capacitor 180, an insulating layer 155b is provided on the insulating layer 155a, and an insulating layer 155c is provided on the insulating layer 155b.

[0521] For the insulating layer 155a, the insulating layer 155b, and the insulating layer 155c, an inorganic insulating film can be suitably used. For example, it is preferable to use a silicon oxide film for the insulating layer 155a and the insulating layer 155c, and a silicon nitride film for the insulating layer 155b. This allows the insulating layer 155b to function as an etching protection film. In this embodiment, an example is shown in which a part of the insulating layer 155c is etched to form a recess, but the insulating layer 155c does not necessarily have to have a recess.

[0522] A light emitting element 190R, a light emitting element 190G, and a light emitting element 190B are provided on the insulating layer 155c.

[0523] The light-emitting element 190R has a pixel electrode 191R, an organic layer 192R, a common layer 194, and a common electrode 193. The light-emitting element 190G has a pixel electrode 191G, an organic layer 192G, a common layer 194, and a common electrode 193. The light-emitting element 190B has a pixel electrode 191B, an organic layer 192B, a common layer 194, and a common electrode 193. The common layer 194 and the common electrode 193 are provided in common to the light-emitting element 190R, the light-emitting element 190G, and the light-emitting element 190B.

[0524] The organic layer 192R of the light emitting element 190R has a light emitting organic compound that emits at least red light. The organic layer 192G of the light emitting element 190G has a light emitting organic compound that emits at least green light. The organic layer 192B of the light emitting element 190B has a light emitting organic compound that emits at least blue light. The organic layer 192R, the organic layer 192G, and the organic layer 192B can each be called an EL layer, and have at least a layer (light emitting layer) containing a light emitting organic compound.

[0525] In the display device 500A, since a light-emitting element is produced for each emission color, the change in chromaticity between emission at low luminance and emission at high luminance is small. In addition, since the organic layer 192R, the organic layer 192G, and the organic layer 192B are separated from each other, the occurrence of crosstalk between adjacent subpixels can be suppressed even in a high-definition display panel. Therefore, a display panel that is high in definition and has high display quality can be realized.

[0526] In the regions between adjacent light emitting elements, an insulating layer 195, a resin layer 196, and a layer 198 are provided.

[0527] The pixel electrode 191R, pixel electrode 191G, and pixel electrode 191B of the light-emitting element are electrically connected to the conductive layer 115b of the transistor 520 by the conductive layer 186 embedded in the insulating layers 155a, 155b, and 155c, the conductive layer 181 embedded in the insulating layer 154, and the conductive layer 174. The height of the top surface of the insulating layer 155c and the height of the conductive layer 186 are the same or approximately the same. The conductive layer 186 functions as a plug or wiring. Various conductive materials can be used for the conductive layer 186.

[0528] Further, a protective layer 231 is provided on the light emitting elements 190R, 190G, and 190B. Onto the protective layer 231, a substrate 170 is attached with an adhesive layer 171.

[0529] Between two adjacent pixel electrodes 191, there is no insulating layer covering the upper end of the pixel electrode 191. Therefore, the distance between adjacent light emitting elements can be made extremely narrow. As a result, a high-definition or high-resolution display device can be obtained.

[0530] [Display device 500B] A display device having a configuration partially different from that described above will be described below, but the same configuration as the above will be referred to and the description thereof may be omitted.

[0531] 35 illustrates an example in which a transistor 520A and a transistor 520B are provided over the transistor 520A. The transistor 520A and the transistor 520B have a similar structure to the transistor 520 in the display device 500A.

[0532] An insulating layer 214 is provided over a substrate 201, and a transistor 520A is provided over the insulating layer 214. The insulating layer 214 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 201 to the transistor 520A and prevents oxygen from being released from the semiconductor layer 113 of the transistor 520A toward the insulating layer 214. As the insulating layer 214, for example, a film in which one or both of hydrogen and oxygen are less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0533] [Display device 500C] A display device 500C shown in FIG. 36 has a stacked structure of a transistor 310 in which a channel is formed in a semiconductor substrate and a transistor 520.

[0534] The transistor 310 has a channel formation region in a substrate 311. The substrate 311 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 311, a conductive layer 316, a low-resistance region 314, an insulating layer 315, and an insulating layer 317. The conductive layer 316 functions as a gate electrode. The insulating layer 315 is located between the substrate 311 and the conductive layer 316 and functions as a gate insulating layer. The low-resistance region 314 is a region in which the substrate 311 is doped with an impurity, and functions as one of a source and a drain. The insulating layer 317 is provided to cover a side surface of the conductive layer 316.

[0535] In addition, an element isolation layer 318 is provided between two adjacent transistors 310 so as to be embedded in the substrate 311 .

[0536] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0537] (Embodiment 6) In this embodiment, a configuration example of a display device that can be used for a display device manufactured using a transistor of one embodiment of the present invention will be described. The display device described below can be used for the pixel portion 584 in the above embodiment, for example.

[0538] One embodiment of the present invention is a display device having a light-emitting element. The display device has two or more pixels that emit light of different colors. Each pixel has a light-emitting element. Each light-emitting element has a pair of electrodes and an EL layer therebetween. The light-emitting element is preferably an organic EL element (organic electroluminescence element). The two or more light-emitting elements that emit different light colors each have an EL layer containing a different light-emitting material. For example, a full-color display device can be realized by having three types of light-emitting elements that emit red (R), green (G), or blue (B) light.

[0539] When manufacturing a display device having a plurality of light-emitting elements each having a different light-emitting color, it is necessary to form at least a layer (light-emitting layer) containing a light-emitting material in an island shape. When manufacturing a part or the whole of an EL layer separately, a method of forming an island-shaped organic film by a deposition method using a shadow mask such as a metal mask is known. However, in this method, due to various influences such as the accuracy of the metal mask, the positional deviation between the metal mask and the substrate, the deflection of the metal mask, and the spread of the contour of the formed film due to the scattering of vapor, the shape and position of the island-shaped organic film deviate from the design, making it difficult to achieve high definition and high aperture ratio of the display device. In addition, during deposition, the contour of the layer may become blurred and the thickness of the edge may become thin. In other words, the thickness of the island-shaped light-emitting layer may vary depending on the location. In addition, when manufacturi...

Claims

1. a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, an insulating layer, and a first metal oxide layer; the second conductive layer is provided on the first conductive layer; the third conductive layer has a region in contact with a first side surface of the first conductive layer and a second side surface of the second conductive layer; the fourth conductive layer has a region in contact with a third side surface of the first conductive layer facing the first side surface, and a fourth side surface of the second conductive layer facing the second side surface, the insulating layer has, in a region between the first conductive layer and the second conductive layer, a region in contact with an upper surface of the first conductive layer, a region in contact with a lower surface of the second conductive layer, a region in contact with a side surface of the third conductive layer, and a region in contact with a side surface of the fourth conductive layer; the insulating layer has a region in contact with a fifth side surface of the first conductive layer, a region in contact with a sixth side surface opposite to the fifth side surface, a region in contact with a seventh side surface of the second conductive layer, and a region in contact with an eighth side surface opposite to the seventh side surface, the first metal oxide layer has a first region surrounded by the first to fourth conductive layers with the insulating layer interposed therebetween, a second region facing the seventh side surface with the insulating layer interposed therebetween, and a third region facing the eighth side surface with the insulating layer interposed therebetween; the fifth conductive layer has the second region and a region facing the seventh side surface with the insulating layer interposed therebetween, and is provided so as to be electrically connected to the first metal oxide layer; The sixth conductive layer has the third region and a region facing the eighth side with the insulating layer therebetween, and is provided so as to be electrically connected to the first metal oxide layer.

2. In claim 1, the fifth conductive layer has a shape that conforms to a side surface of the first metal oxide layer that includes the second region, The sixth conductive layer has a shape along a side surface of the first metal oxide layer that includes the third region.

3. In claim 2, A second metal oxide layer and a third metal oxide layer, the second metal oxide layer is provided between the first metal oxide layer and the fifth conductive layer, the third metal oxide layer is provided between the first metal oxide layer and the sixth conductive layer, the second metal oxide layer has a shape that conforms to a side surface of the first metal oxide layer that includes the second region, the third metal oxide layer has a shape that follows a side surface of the first metal oxide layer that includes the third region, the second metal oxide layer has a region in contact with the fifth conductive layer, The third metal oxide layer has a region in contact with the sixth conductive layer.

4. In claim 1, A seventh conductive layer is provided; the seventh conductive layer is provided on the second conductive layer; a ninth side surface of the seventh conductive layer has a region in contact with the third conductive layer; a tenth side surface of the seventh conductive layer opposite to the ninth side surface has a region in contact with the fourth conductive layer; an upper surface of the second conductive layer, a lower surface of the seventh conductive layer, a side surface of the third conductive layer, and a side surface of the fourth conductive layer each have a region in contact with the insulating layer in a region between the second conductive layer and the seventh conductive layer; an eleventh side surface of the seventh conductive layer and a twelfth side surface opposite to the eleventh side surface each have a region in contact with the insulating layer; the first metal oxide layer has a fourth region surrounded by the second to fourth conductive layers and the seventh conductive layer with the insulating layer interposed therebetween, a fifth region facing the eleventh side surface with the insulating layer interposed therebetween, and a sixth region facing the twelfth side surface with the insulating layer interposed therebetween; the fifth conductive layer has the fifth region and a region facing the eleventh side surface with the insulating layer therebetween, The sixth conductive layer has the sixth region and a region facing the twelfth side with the insulating layer interposed therebetween.

5. In claim 4, the fifth conductive layer has a shape along a side surface of the first metal oxide layer that includes the second region and a shape along a side surface of the first metal oxide layer that includes the fifth region, A semiconductor device, wherein the sixth conductive layer has a shape along a side surface of the first metal oxide layer that includes the third region and a shape along a side surface of the first metal oxide layer that includes the sixth region.

6. In claim 5, A second metal oxide layer and a third metal oxide layer, the second metal oxide layer is provided between the first metal oxide layer and the fifth conductive layer, the third metal oxide layer is provided between the first metal oxide layer and the sixth conductive layer, the second metal oxide layer has a shape that conforms to a side surface including the second region and a side surface including the fifth region, of the first metal oxide layer; the third metal oxide layer has a shape conforming to a side surface including the third region and a side surface including the sixth region, of the first metal oxide layer; the second metal oxide layer has a region in contact with the fifth conductive layer, The third metal oxide layer has a region in contact with the sixth conductive layer.

7. In any one of claims 1 to 6, The third conductive layer and the fourth conductive layer each have the same material as the second conductive layer.

8. In any one of claims 1 to 6, A semiconductor device in which the third conductive layer and the fourth conductive layer each have a thickness equal to or greater than the thickness of at least one of the first conductive layer and the second conductive layer.

9. In any one of claims 1 to 6, the third conductive layer includes a first layer having a region in contact with the second side surface, and a second layer provided outside the first layer; the fourth conductive layer includes a third layer having a region in contact with the fourth side surface, and a fourth layer provided outside the third layer, The first layer and the third layer each have the same material as the second conductive layer.

10. In any one of claims 1 to 6, the first metal oxide layer contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

11. In claim 3 or 6, the first metal oxide layer contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony; The semiconductor device, wherein the electrical conductivity of the second metal oxide layer and the third metal oxide layer is equal to or higher than the electrical conductivity of the first metal oxide layer.

12. In claim 11, The semiconductor device, wherein the second metal oxide layer and the third metal oxide layer each contain indium.

13. forming a first conductive layer, a first sacrificial layer on the first conductive layer, and a second conductive layer on the first sacrificial layer; forming a third conductive layer having a region in contact with a first side surface of the first conductive layer, a region in contact with a second side surface of the second conductive layer, a region in contact with a third side surface opposite to the first side surface, and a region in contact with a fourth side surface opposite to the second side surface, and having a region located on the second conductive layer; removing the first sacrificial layer; forming an insulating layer so as to cover the first to third conductive layers; forming a metal oxide layer so as to cover the insulating layer; forming a fourth conductive layer on the metal oxide layer; forming a fifth conductive layer and a sixth conductive layer opposed to the fifth conductive layer with the metal oxide layer interposed therebetween by a planarization process on the fourth conductive layer; A method for manufacturing a semiconductor device, comprising: forming a seventh conductive layer and an eighth conductive layer that faces the seventh conductive layer with the second conductive layer therebetween by planarization treatment of the third conductive layer.

14. In claim 13, forming a second sacrificial layer on the second conductive layer prior to forming the third conductive layer; forming the third conductive layer having an area overlying the second sacrificial layer; A method for manufacturing a semiconductor device, comprising the steps of: performing planarization treatment on the second sacrificial layer in parallel with planarization treatment on the third conductive layer and planarization treatment on the fourth conductive layer.

15. In claim 14, forming the second sacrificial layer having a first layer and a second layer on the first layer, the first layer having a thickness equal to or less than a thickness of the second layer; A method for manufacturing a semiconductor device, wherein a planarization treatment for the second sacrificial layer is performed at least until an upper surface of the first layer is exposed.

16. In claim 15, A method for manufacturing a semiconductor device, wherein the third conductive layer is formed to have a thickness equal to or greater than a thickness of the second conductive layer.

17. In claim 13, forming a second sacrificial layer on the second conductive layer and a ninth conductive layer on the second sacrificial layer before forming the third conductive layer; the third conductive layer is formed to have a region in contact with a fifth side surface of the ninth conductive layer and a region in contact with a sixth side surface opposite to the fifth side surface, and to have a region located on the ninth conductive layer; removing the second sacrificial layer by the same process as removing the first sacrificial layer; The method for manufacturing a semiconductor device, wherein the insulating layer is formed to cover the ninth conductive layer.

18. In claim 17, forming a third sacrificial layer on the ninth conductive layer before forming the third conductive layer; forming the third conductive layer having an area overlying the third sacrificial layer; A method for manufacturing a semiconductor device, comprising the steps of: performing planarization treatment on the third sacrificial layer in parallel with planarization treatment on the third conductive layer and planarization treatment on the fourth conductive layer.

19. In claim 18, forming the third sacrificial layer such that the third sacrificial layer has a first layer and a second layer on the first layer, and the thickness of the first layer is equal to or less than the thickness of the second layer; A method for manufacturing a semiconductor device, wherein a planarization treatment for the third sacrificial layer is performed at least until an upper surface of the first layer is exposed.

20. 20. In claim 19, a third conductive layer formed to have a thickness equal to or greater than a thickness of the ninth conductive layer;

21. In any one of claims 13 to 20, The metal oxide layer is formed by an ALD method.

Images