Method for controlling ion energy distribution using pulse generator having current feedback output stage

Abstract

To provide an electrode biasing method that maintains a nearly constant cathode sheath voltage, thereby producing a monoenergetic ion energy distribution function (IEDF) at the surface of the substrate, thereby precisely controlling the shape and feature profile of the IEDF formed at the surface of the substrate.SOLUTION: A method 400 for processing a substrate using a pulsed voltage bias scheme includes generating a plasma over a surface of a substrate disposed on a substrate support (401) and establishing a pulsed voltage waveform at a bias electrode disposed within the substrate support using a pulsed bias generator (402). The pulsed bias generator is connected to the bias electrode using an external electrical conductor.SELECTED DRAWING: Figure 4

Description

background

[0001] (Field) TECHNICAL FIELD The embodiments described herein relate generally to plasma processing chambers used in semiconductor manufacturing.

[0002] Description of Related Art Reliably producing high aspect ratio features is one of the key technological challenges for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. One method of forming high aspect ratio features uses a plasma-assisted etching process, such as a reactive ion etching (RIE) plasma process, to form high aspect ratio openings in a material layer (e.g., a dielectric layer) of a substrate. In a typical RIE plasma process, a plasma is formed in a RIE processing chamber and ions from the plasma are accelerated toward a surface of the substrate to form openings in a material layer disposed under a mask layer formed on the surface of the substrate.

[0003] A typical reactive ion etching (RIE) plasma processing chamber includes a radio frequency (RF) bias generator to supply a radio frequency voltage to a "power electrode," which is a metal base plate embedded in an "electrostatic chuck" (ESC) assembly. The "power electrode" is more commonly referred to as a "cathode." FIG. 1A illustrates a plot of a typical radio frequency voltage supplied to the power electrode in a typical processing chamber. The power electrode is capacitively coupled to the plasma of the processing system through a layer of dielectric (e.g., ceramic material) and is part of the ESC assembly. Application of a radio frequency voltage to the power electrode forms an electron-repulsive plasma sheath (also called a "cathode sheath") above the processing surface of the substrate. During processing, the substrate is positioned on the substrate support surface of the ESC assembly. The nonlinear, diode-like nature of the plasma sheath provides a rectifying effect to the applied radio frequency field. As a result, a direct current (DC) voltage drop, or "self-bias," appears between the substrate and the plasma, making the substrate potential negative with respect to the plasma potential. This voltage drop determines the average energy of the plasma ions accelerated towards the substrate and therefore the etch anisotropy. More specifically, the ion directionality, feature profile, and etch selectivity towards the mask and stop layers are controlled by the ion energy distribution function (IEDF). In a radio frequency biased plasma, the IEDF typically has two peaks at low and high energies with an ion population between them, as shown in Figure 1B. The presence of an ion population between the two peaks of the IEDF reflects the fact that the voltage drop between the substrate and the plasma oscillates at the radio frequency bias frequency. When using a lower frequency (e.g., 2 MHz) radio frequency bias generator to obtain a higher self-bias voltage, the energy difference between these two peaks can become significant, potentially leading to bowing of the feature walls, since the etch profile with ions of the low energy peak is more isotropic. Compared to high energy ions, low energy ions are less effective at reaching the bottom corners of the etched features (e.g., due to charging effects), but they sputter less mask material.This is important in high aspect ratio etch applications such as hardmask opening or dielectric mold etching.

[0004] Feature sizes continue to shrink and aspect ratios increase while feature profile control requirements become more stringent. As such, it is more desirable to have a well-controlled ion energy distribution function (IEDF) at the substrate surface during processing. A single-peak IEDF can be used to construct any IEDF, including a two-peak IEDF with independently controlled peak height and energy, which is beneficial for precision plasma processing. The authors have found that to create a single-peak IEDF (e.g., single-peak IEDF 520 shown in FIG. 5C), it is necessary that the potential difference between the plasma and the substrate is nearly constant, i.e., the sheath voltage is nearly constant, since the sheath voltage determines the ion energy at the substrate surface during processing. Assuming that the plasma potential (usually within a few tens of volts of ground potential in processing plasmas) is nearly constant, this requires maintaining a nearly constant negative potential at the substrate surface with respect to ground. The authors further found that this cannot be achieved by simply applying a DC voltage to the power electrode. This is because in the presence of an electron-repelling plasma (cathode) sheath, the ionic current from the bulk plasma is not balanced by the electronic current from the bulk plasma, and this imbalance occurs because the sheath field repels electrons to the substrate. As a result, the unbalanced net current (equal to the ionic current) from the bulk plasma constantly builds up charge on the substrate surface, which ultimately results in all of the applied DC voltage being dropped across the substrate and the dielectric layer of the ESC assembly (i.e., the chuck capacitor), and not across the plasma sheath (i.e., the sheath capacitor) as desired.

[0005] Therefore, there is a need in the art for a novel biasing method that allows the sheath voltage to be maintained nearly constant (assuming the plasma potential is near zero, the sheath voltage is equal to the value of the substrate voltage relative to ground). Maintaining the sheath voltage nearly constant creates a monoenergetic IEDF at the surface of the substrate, which results in precise control over the shape and feature profile of the IEDF formed at the surface of the substrate. Overview

[0006] The embodiments of the disclosure provided herein may include a method of processing a substrate that allows for maintaining a nearly constant sheath voltage for up to about 90% of the substrate processing time. The implementation of the method results in a (narrow) single-peaked ion energy distribution function (IEDF), which can be used to create an IEDF of any shape. Herein, the method includes generating a plasma above a surface of a substrate disposed on a substrate support and establishing a pulsed voltage waveform at a bias electrode disposed within the substrate support. The pulsed voltage waveform is established at the bias electrode using a pulsed bias generator connected to the bias electrode by a second electrical conductor. The pulsed bias generator comprises a pulse generator and a current feedback output stage, which are simultaneously connected to the second electrical conductor. The pulse generator maintains a predetermined positive voltage across its output (i.e., to ground) by repeatedly opening and closing its internal switch at a predetermined rate for regularly repeated time intervals of predetermined length. The pulse generator comprises a constant voltage source, a switch, and a snubber. When the switch is closed, it electrically connects the positive output of the substantially constant constant voltage source to the output of the pulse generator, and at the same time, the positive output of the constant voltage source is also connected to the second conductor through the first conductor. A snubber (e.g., a "flyback" diode) across the output of the pulse generator minimizes (i.e., "snubs") voltage spikes that may occur during the rapid release of magnetic energy by the inductive components (e.g., the first and second conductors) following the opening of the switch. Herein, a first end of a current feedback output stage is electrically connected to the positive output of the nanosecond pulse generator through the first conductor, and at the same time, is also electrically connected to the second conductor, and a second end of the current feedback output stage is electrically grounded.

[0007] In some embodiments, the pulsed voltage waveform includes multiple pulsed voltage cycles, each pulsed voltage cycle including a sheath collapse phase, a chuck capacitor recharge phase, a sheath formation phase, and an ionic current phase. During the collapse phase, the switch is closed and the sheath capacitor is discharged by current provided by the pulse generator. During the chuck capacitor recharge phase, the switch is maintained in a closed position and a positive charge is provided to the bias electrode by current from the pulse generator. During the sheath formation phase, the switch is open and current flows from the sheath and stray capacitance through the current feedback output stage to ground. During the ionic current phase, the switch is maintained in an open position and ionic current also flows from the plasma through the current feedback output stage to ground, causing a positive charge to build up on the substrate surface and gradually discharging the sheath capacitor and the chuck capacitor, thus slowly reducing the sheath voltage drop.

[0008] In some embodiments, the sheath collapse phase, the recharging phase, and the sheath formation phase have a total duration of between about 200 ns and about 300 ns. In some embodiments, the positive output voltage of the pulse generator during the time the switch remains closed is between about 0.1 kV and about 10 kV. In some embodiments, the switch remains in the closed position for about 10 ns to about 100 ns of each pulse voltage cycle. In some embodiments, each pulse voltage cycle has a duration of between about 2 μs and about 3 μs. In some embodiments, the sheath collapse phase and the recharging phase together constitute less than about 10% of the pulse voltage cycle. In some embodiments, the bias electrode is spaced from the substrate support surface of the substrate support by a dielectric layer, and the combined series capacitance of the dielectric layer of the substrate support and the substrate disposed thereon is between about 5 nF and about 12 nF. In some embodiments, a chuck power supply is connected to the external conductor at the connection point, and a blocking capacitor having a capacitance between about 40 nF and about 80 nF is disposed in series with the pulsed bias generator between the connection point and the pulsed bias generator, hi some embodiments, a blocking resistor having a resistance greater than about 1 Mohm is disposed between the chuck power supply and the connection point.

[0009] In another embodiment, the process chamber comprises a chamber lid, one or more sidewalls, and a chamber base, which together define a process volume. The process chamber further comprises a substrate support disposed within the process volume, the substrate support comprising a bias electrode separated from a substrate support surface of the substrate support by a dielectric layer, and a pulse bias generator connected to the bias electrode by a second electrical conductor. The pulse bias generator comprises a pulse generator and a current feedback. The pulse generator comprises a voltage source and a switch that, when closed, electrically connects a positive output of the voltage source to an output of the pulse generator, the output of the pulse generator being connected via a first electrical conductor to a second electrical conductor and a snubber between both ends of the output of the pulse generator. The voltage source may be a constant voltage source. Herein, a first end of the current feedback output stage is electrically connected to the second electrical conductor and simultaneously connected to a positive output of the pulse generator via the first electrical conductor. A second end of the current feedback output stage is electrically grounded. In some embodiments, the process chamber comprises an inductively coupled plasma (ICP) or capacitively coupled plasma (CCP) plasma generator.

[0010] The embodiments of the present disclosure further comprise a processing chamber, the processing chamber comprising a substrate support comprising a bias electrode separated from a substrate support surface of the substrate support by a dielectric layer, and a bias generator connected to the bias electrode by an electrical conductor. The bias generator comprises a pulse generator, the pulse generator comprising a voltage source having a positive terminal and a negative terminal, the negative terminal being grounded, a switch that, when closed, electrically connects the positive terminal to one end of the electrical conductor, and a snubber connected between the one end of the electrical conductor and ground. The bias generator also comprises a current feedback output stage, a first end of the current feedback output stage electrically connected to the electrical conductor and a second end of the current feedback output stage electrically grounded. The electrical conductor may further comprise a first electrical conductor and a second electrical conductor connected in series, one end of the first electrical conductor connected to the positive terminal of the voltage source and one end of the second electrical conductor connected to the bias electrode. In some configurations, the first conductor is an "internal" conductor located within the bias generator, and the second conductor is an "external" conductor disposed between the bias generator and the bias electrode.

[0011] Embodiments of the present disclosure further include a method of processing a substrate, the method including generating a plasma over a surface of a substrate disposed on a substrate support, and biasing a bias electrode disposed in the substrate support using a bias generator connected to the bias electrode by an electrical conductor. The bias generator includes a pulse generator, the pulse generator including a voltage source having a positive terminal and a negative terminal, the negative terminal being grounded, a switch that when closed electrically connects the positive terminal to the electrical conductor, and a current feedback output stage, a first end of the current feedback output stage being electrically connected to the electrical conductor and a second end of the current feedback output stage being electrically grounded. The method of biasing the bias electrode includes generating a pulse voltage waveform at the bias electrode by repeatedly closing the switch for a first time period, and then opening the switch a number of times for a second time period, where closing the switch applies a positive voltage relative to ground by the voltage source to the electrical conductor during the first time period, and opening the switch causes current to flow from the bias electrode through the current feedback output stage to ground during at least a portion of the second time period. The method may also include substantially eliminating a sheath voltage drop formed on the surface of the substrate by the generated plasma by the end of the first time period, and flowing current from the bias electrode through a current feedback output stage to ground during a second time period. The method may also include forming a plasma potential. The first time period includes a sheath collapse phase having a first duration, where at the end of the first duration, the potential formed on the surface of the substrate is substantially equal to the plasma potential of the generated plasma, and a chuck capacitive recharge phase having a second duration, where the sheath voltage drop formed on the surface of the substrate by the generated plasma is eliminated after the first and second durations are completed, respectively.The second period may include a sheath formation phase having a third duration, where current flowing from the bias electrode through the current feedback output stage to ground occurs during the third duration, and an ionic current phase having a fourth duration, where the fourth duration is longer than the combined time of the first, second and third durations.

[0012] Embodiments of the present disclosure further include a process chamber, the process chamber comprising a substrate support comprising a bias electrode separated from a substrate support surface of the substrate support by a dielectric layer, and a bias generator connected to the bias electrode by an electrical conductor. The bias generator comprises a pulse generator, the pulse generator comprising a voltage source having a positive terminal and a negative terminal, the negative terminal being connected to ground, and a switch that, when closed, electrically connects the positive terminal to one end of the electrical conductor. The bias generator also comprises a current feedback output stage, a first end of the current feedback output stage electrically connected to the electrical conductor and a second end of the current feedback output stage electrically grounded. The processing chamber also includes a computer readable medium having instructions stored thereon, when executed by a processor, for performing a method of processing a substrate, the method including generating a plasma over a surface of a substrate disposed on a substrate support, and biasing a bias electrode with a bias generator, the biasing electrode generating a pulsed voltage waveform at the bias electrode by repeatedly closing a switch for a first time period and then opening the switch multiple times for a second time period, where closing the switch applies a positive voltage with respect to ground to one end of the conductor during the first time period and opening the switch causes current to flow from the bias electrode through a current feedback output stage to ground during at least a portion of the second time period. The conductor may further include a first conductor and a second conductor connected in series, one end of the first conductor connected to a positive terminal of a voltage source and one end of the second conductor connected to the bias electrode. [Brief description of the drawings]

[0013] In order to allow the above features of the present disclosure to be understood in detail, a more particular description of the present disclosure briefly summarized above will be made with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the present disclosure, and therefore should not be construed as limiting the scope thereof, and the present disclosure may include other equally effective embodiments. [Figure 1A] 1 illustrates a radio frequency voltage waveform supplied to a bias electrode of a plasma processing chamber according to the prior art. [Figure 1B] 1 shows an ion energy distribution function (IEDF) at a surface of a substrate during a plasma process performed in a conventional processing chamber according to the prior art. [Diagram 2] 1 is a schematic cross-sectional view of an exemplary processing chamber configured to perform a method described herein, according to one embodiment. [Diagram 3] FIG. 2 is an approximate circuit diagram functionally equivalent to the pulsed voltage biasing scheme described herein, according to one embodiment. [Figure 4] FIG. 2 is a flow diagram of a method for processing a substrate using a pulsed voltage bias scheme described herein, according to one embodiment. [Figure 5A] ~ [Figure 5C] The method is illustrated in FIG. [Figure 6] FIG. 4 is a simplified circuit diagram of the biasing scheme described in relation to FIGS. 2-3. [Figure 7A] ~ [Figure 7H] 1 shows the results of a numerical simulation of the biasing scheme described herein. [Figure 8] 1 shows an oscilloscope trace of a substrate voltage measurement waveform produced by an actual implementation of the pulsed voltage bias scheme proposed herein.

[0014] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without specific recitation. DETAILED DESCRIPTION

[0015] The embodiments described herein are applicable to all plasma-assisted or plasma-enhanced processing chambers and plasma-assisted or plasma-enhanced methods of processing substrates. More specifically, the embodiments of the present disclosure describe an electrode biasing scheme that maintains a nearly constant sheath voltage, thereby creating a monoenergetic IEDF at the surface of the substrate, and thus allowing precise control of the shape and feature profile of the IEDF formed at the surface of the substrate. The following definitions are used throughout this disclosure: (1) All potentials are referenced to ground unless otherwise specified. (2) The voltage at any physical point (such as the substrate or bias electrode) is similarly defined as the potential of that point relative to ground (a point of zero potential). (3) The cathode sheath is meant to be an electron-repulsive ion acceleration sheath, which corresponds to a negative substrate potential relative to the plasma. (4) The sheath voltage (sometimes referred to as the "sheath voltage drop") V SH is defined as the absolute value of the potential difference between the plasma and an adjacent surface (e.g., the surface of the substrate or the chamber wall). (5) The substrate potential is the potential of the substrate surface facing the plasma.

[0016] A pulsed voltage bias scheme (e.g., the bias scheme described with respect to Figs. 2 and 3) is proposed, in which a pulsed bias generator (e.g., pulsed bias generator 240 of Fig. 2) is used to establish a pulsed voltage waveform (e.g., pulsed voltage waveform 500 shown in Fig. 5A) at a bias electrode (e.g., chucking pole 204) that is separated from the substrate by a thin layer of dielectric material in the ESC assembly (this thin layer is the ESC capacitor C ESC(Forming a sheath voltage biasing scheme). This pulsed voltage bias scheme allows maintaining a nearly constant sheath voltage for up to about 90% of the substrate processing time. This results in a (narrow) single peak IEDF (e.g., IEDF 520 in FIG. 5C), which can be further used to create IEDFs with any shape.

[0017] However, other biasing schemes may be used to establish a pulsed voltage waveform, such as waveform 500 (shown in FIG. 5A ) at a bias electrode (such as a chucking pole) that is separated from the substrate by a thin layer of dielectric in an ESC assembly. It is therefore proposed that, separately (without specifying the biasing scheme), a pulsed voltage waveform such as waveform 500 at said bias electrode allows maintaining a nearly constant sheath voltage for up to about 90% of the substrate plasma processing time, thereby obtaining a (narrow) single peak IEDF and using this IEDF to create an IEDF of any shape.

[0018] One embodiment of the pulsed voltage bias scheme proposed above is shown in the chamber diagram of Figure 2, an equivalent electrical circuit for this bias scheme is shown in Figure 3, and a simplified diagram of this equivalent electrical circuit is shown in Figure 6. The simplified electrical circuit shown in Figure 6 is numerically modeled to produce the results shown in Figures 7A-7H.

[0019] A chamber diagram with the pulsed voltage bias scheme proposed above, according to one embodiment, is shown in Figure 2 (a more detailed explanation of Figure 2 is provided later in the text). The bias scheme described herein essentially consists of the following main components: (1) A nanosecond pulse generator 214 that maintains a substantially constant, predetermined positive voltage across its output (i.e., to ground) by repeatedly opening and closing its internal switch at a predetermined rate for regularly repeating time intervals of predetermined length. A simplified but functionally equivalent schematic diagram of a nanosecond pulse generator is shown in FIG. 2. The nanosecond pulse generator of FIG. 2 is simplified to a minimum set of components, but it is important to understand its role in the context of establishing a desired pulse voltage waveform (such as waveform 500) at a bias electrode (such as chucking pole 204). These components typically include an internal voltage source, a high repetition rate switch, and a flyback diode. It should be understood that an actual nanosecond pulse generator may include any number of internal components and may be based on a more complex electrical circuit than that of FIG. 2. Similarly, the schematic diagram of FIG. 2 depicts only the components of the nanosecond pulse generator and their functional equivalents in electrical circuitry, and only to the extent necessary to explain the basic principles of its operation, its interaction with the plasma in the process volume, and its role in establishing a pulsed voltage waveform (such as waveform 500) at a bias electrode (such as chucking pole 204). As can be inferred from the schematic diagram shown in FIG. 2, when switch S1 moves from an open (off) to a closed (on) position, it connects the output of the nanosecond pulse generator to its internal voltage source, which generates a nearly constant output voltage. In fact, as can be seen from the more detailed (but still simplified) equivalent electrical circuit of one embodiment of a nanosecond pulse generator shown in FIG. 3, the switch actually connects an internal battery to a step-up output transformer. The details of this portion are not important to understanding the basic principles of the operation of the nanosecond pulse generator and its function in establishing a pulsed voltage waveform (such as waveform 500) at a bias electrode (such as chucking pole 204), but they have important practical implications that will be explained later. The purpose of the flyback diode, which could be replaced by another snubber circuit, is to suppress or “snub” voltage spikes that may be caused by the opening of switch S1, following which the magnetic energy stored in the inductive element is rapidly released.These inductive elements include: (A) composite inductance L; transm and (B) an external conductor such as a transmission line 206 having a combined inductance L internal and a pulse bias generator 240 component including an internal conductor having a magnetic field. Magnetic energy accumulates in the inductive element during a time interval while switch S1 remains in a closed position and the nanosecond pulse generator is supplying current to the system. The magnitude V of the output voltage V0 of the nanosecond pulse generator during the time interval is m is when switch S1 is in the closed (on) position and there is a nearly constant positive output voltage (V m ) is maintained, it can be several kilovolts (e.g., 0.1-10 kV). The time interval during which the switch remains in the closed (on) position and a nearly constant positive output voltage is maintained is called the "pulse width" τ p Similarly, the time interval between when a switch goes from an open (off) position to a closed (on) position is called the "rise time" τ rise When the switch transitions from the open to the closed position, the output voltage of the nanosecond pulse generator is V mFinally, the length of time between two successive transitions from the open (off) position to the closed (on) position (or vice versa) is called the "period", T, and is equal to the inverse of the pulse repetition frequency, which can be as high as 400 kHz, for example. Note that: (a) in the pulsed voltage bias scheme proposed here, the nanosecond pulse generator is used primarily as a charge injector (current source) and not as a constant voltage source. Therefore, there is no strict requirement on the stability of the output voltage, which may vary over time even when the switch remains in the closed (on) position. (b) the nanosecond pulse generator is essentially a sourcing power supply, but not a sinking power supply, which allows current to flow in only one direction (i.e., it can charge but not discharge a capacitor, for example). (c) when the switch is in the open (off) position, the voltage V0 across the output of the nanosecond pulse generator is not controlled by an internal voltage source. Instead, it is determined by its internal components and their interaction with other circuit elements. (d) The name "nanosecond pulse generator" comes from the fact that when it is operated into a resistively dominated load with low stray capacitance / inductance, it produces a voltage waveform across its output which can be described as a continuous, ground referenced, positive voltage pulse. (2) A current feedback output stage 215, one end 215B of which is grounded and the other end 215A of which is connected via an internal conductor to the positive output of the nanosecond pulse generator and simultaneously to an external conductor. The combination of the nanosecond pulse generator, the current feedback output stage and the internal conductor is referred to herein as a "pulsed bias generator" 240. It is both a sourcing and sinking power supply, and allows current to flow in both directions. The current feedback output stage may be composed of the following elements: (a) a resistor, (b) a resistor and an inductor connected in series, or (c) a more complex combination of electrical elements including a parallel capacitor, allowing positive current to flow toward ground. (3) An outer conductor that connects the output of the pulsed bias generator 240 to the chucking pole. The output of the pulsed bias generator 240 is at point 215A, where the output of the nanosecond pulse generator 214 is connected to the current feedback output stage 215 via the inner conductor. The outer conductor may include: (a) the coaxial transmission line 206, where the coaxial transmission line 206 may include a flexible coaxial cable having an inductance L_flex connected in series with a rigid coaxial transmission line having an inductance L_rigid; (b) an insulated high voltage corona resistant hook-up wire; (c) a bare wire; (d) a metal rod; (e) an electrical connector; or (f) any combination of the electrical elements (a)-(e). However, the inner conductor may include the same basic elements as the outer conductor. The chucking pole is typically a metal plate embedded in the electrostatic chuck and separated from the plasma by a thin layer of dielectric (e.g., about 0.3 mm thick). The chucking pole may be a bias electrode 204 embedded in the electrostatic chuck portion (i.e., the ESC substrate support 205) of the ESC assembly shown in FIG. 2. The external conductor, such as the transmission line 206, and the bias electrode 204 have some combined stray capacitance to ground C s has.

[0020] FIG. 3 shows a simplified electrical circuit 300 that is functionally equivalent to the pulsed voltage bias scheme proposed herein with the plasma in the process volume. FIG. 6 also shows a further simplified circuit 600 of the circuit 300. These circuits are used only to model the main aspects of the interaction of the pulsed bias generator (e.g., 240) with the process chamber 308, to explain its basic operating principle and role of establishing a pulsed voltage waveform (e.g., 500) at the bias electrode (e.g., 204), to explain the accompanying physical phenomena that occur during various phases of the pulsed voltage waveform (e.g., 500), and to outline the basic principles of operation of the pulsed voltage bias scheme proposed herein. In reality, the interaction of the pulsed voltage bias scheme described herein with the plasma in the process volume may involve complex physical phenomena (e.g., high frequency oscillations caused by the presence of inductive elements such as external and internal conductors), which are hardly considered here. However, it should be understood as follows: That is, the discussion (later in the text) of aspects 501-504 of the pulsed voltage waveforms (e.g., 500) is based primarily on a simplified circuit model 600 without consideration of some more complex physical phenomena that are not important to understanding the basic principles of operation of the pulsed voltage biasing scheme proposed herein. Furthermore, the waveforms in Figures 5A-5B and 7A-7H were generated by numerically simulating the simplified circuit 600 using OrCAD P-Spice Designer software (each set of figures was generated using a different set of circuit parameters), and the main underlying physical phenomena revealed by the modeling (i.e., sheath collapse, ESC recharging, sheath formation, and charging of the substrate surface by ionic currents) are appropriate for a real system. In the equivalent circuits 300 and 600 shown in Figures 3 and 6, respectively, all relevant physical components displayed in the chamber diagram of Figure 2 are represented by individual circuit elements, according to the following description.

[0021] First, the chucking pole is separated from the plasma by a dielectric layer in the electrostatic chuck and a treated substrate placed on its surface (e.g., a 0.8 mm thick doped silicon slab with a capacitance greater than 10 nF). In the circuits of FIGS. 3 and 6, the capacitance C e 3. The ESC is represented by a single chuck capacitor 303 (which is actually two capacitors connected in series) having a capacitance (e.g., about 7-10 nF). In other words, the substrate (usually made of thin layers of semiconductors and / or dielectrics) is considered to be electrically part of the ESC dielectric layer, and the chuck capacitance C e Whenever you refer to e is ESC (i.e. C ESC ) and the substrate (i.e., C wafer ) is the combined series capacitance of the board capacitance C wafer is usually very large (>10 nF) or the board may be conductive (infinite capacitance), so the series capacitance is mainly the actual C ESC is determined by.

[0022] Second, the chucking pole 204, the pulsed bias generator 240, and the external conductors (such as the transmission line 206) connecting them together have: (A) a capacitance C s (B) A stray capacitance to ground represented by a single stray capacitor 302 having a capacitance of about 100 pF (e.g., about 500 pF). (B) An inductor L representing the inner conductors and other components of the pulsed bias generator 240 in the circuit 600. internal (e.g., about 300 nH), as well as an inductor L representing an external conductor such as the transmission line 206. transm (e.g., about 500 nH). The current feedback output stage 215 includes a single resistor R ros (e.g., about 150 ohms).

[0023] Third, a standard electrical plasma model is used to represent the entire plasma in the process volume as three elements in series: I. An electron-repellent cathode sheath 304 adjacent to the substrate (sometimes called the "plasma sheath" or simply the "sheath"). The cathode sheath is represented in Figures 3 and 6 by a conventional three-part circuit element that includes: (a) a diode D SH : When this opens, it represents the collapse of the sheath. (b) Current source I i (e.g., about 0.5 to 5 A): This represents the ionic current flowing through the substrate in the presence of the sheath. (c) Capacitor C SH (eg, about 100-300 pF for high aspect ratio applications): this represents the sheath during the major period (about 90%) of the bias cycle, i.e., the ionic current phase, during which ion acceleration and etching occurs. II. In Figures 3 and 6, a single resistor R pl (e.g., about 5-10 ohms) for the bulk plasma 305. III. An electron-repellent wall sheath 306 formed by the chamber walls. The wall sheath is similarly represented in Figures 3 and 6 by a three-part circuit element, which includes: (a) a diode D w . (b) Current source I iw (e.g., about 5-10 A): This represents the ionic current to the wall. (c) Capacitor C w (e.g., about 5-10 nF): this primarily represents the wall sheath during the ESC recharging phase 502 (discussed later in the text), when the electron-repellent cathode sheath is not present and the wall sheath capacitor is charged by the large current pushed through the ESC by the nanosecond pulse generator. Since the cathode sheath is much thicker than the wall sheath (due to the high voltage) and the total wall area is much larger than the substrate area, C w ≫C SH The inner surface of the grounded metal wall is considered to be covered with a thin layer of dielectric material, and in Figs. 3 and 6, a large capacitor C coat (e.g., approximately 300 to 1000 nF).

[0024] 4 shows a flow diagram of a method 400 for processing a substrate using the pulsed voltage bias scheme described herein, according to one embodiment. In step 401, the method 400 includes generating a plasma over a surface of a substrate disposed on a substrate support. In step 402, the method 400 includes establishing a pulsed voltage waveform at a bias electrode disposed within the substrate support using a pulsed bias generator, the pulsed bias generator being connected to the bias electrode using an external conductor, such as transmission line 206.

[0025] FIG. 5A shows a pulsed voltage waveform 500 established at the bias electrode. The result of the pulsed voltage waveform 500 shown in FIG. 5A is the substrate voltage waveform 510 shown in FIG. 5B, thus allowing the sheath voltage to be kept nearly constant for about 90% of the substrate processing time. The voltage waveforms 500 and 510 shown in FIGS. 5A-5B, as well as the waveforms shown in FIGS. 7A-7H, were generated by numerically simulating a simplified circuit 600 using OrCAD P-Spice Designer software. The circuit parameters used to generate FIGS. 5A-5B were selected to clearly illustrate various aspects of the waveforms 500 and 510 (e.g., the waveform period was set to 1 μs). Conversely, the parameters used to generate FIGS. 7A-7H were selected to demonstrate the feasibility and practical implementation of the pulsed voltage biasing scheme proposed herein (e.g., the waveform period was set to 2.5 μs). However, the waveforms shown in Figures 5A-5B and 7A-7H should be interpreted as simplified schematics of experimentally observable waveforms (examples are shown in Figure 8). The actual waveforms may be very complex and contain many fine features (e.g., high frequency vibrations caused by the presence of inductive elements such as external and internal conductors) that are not shown in Figures 5A-5B and 7A-7H. However, these fine features are not essential to understanding the fundamental physical phenomena that determine the overall shape of the actual pulsed voltage waveforms generated by the pulsed voltage biasing scheme proposed herein. Thus, although the following description is based primarily on the circuit 600 and the simulated waveforms shown in Figures 5A-5B and 7A-7H, the main underlying physical phenomena that occur during phases 501-504 of the pulsed voltage waveform cycle (i.e., sheath collapse, ESC recharging, sheath formation, and charging of the substrate surface by ionic currents) are relevant to the actual system.

[0026] 5A, a pulsed voltage waveform 500 includes a periodic series of short positive pulses repeating with a period T (e.g., 2.5 microseconds) superimposed on a voltage offset. Within each period (repeating cycle) the waveform includes the following: (1) A positive voltage surge that charges the floating capacitors of the system and collapses the cathode sheath, i.e., sheath collapse phase 501. During this time, the sheath capacitor is discharged and the substrate potential is brought to the level of the local plasma potential (as shown in FIG. 5B). The sheath collapse phase 501 allows for rapid recharging of the chuck capacitor by electrons brought from the plasma during the ESC recharge phase 502. While phase 501 lasts, switch S1 (see FIG. 6) is closed and remains in the closed (on) position. As a result, the nanosecond pulse generator (e.g., 214) can maintain a nearly constant positive voltage across its output and supply current to the system. The duration T1 of phase 501 is much shorter than the duration T4 (described below) or overall period T of the ionic current phase 504, typically on the order of tens of nanoseconds (e.g., 20-50 ns). This is in part because the plasma current during phase 501 is carried by electrons. This is because the cloud of electrons moves towards the substrate and gradually overwhelms the ionic space charge, thus eliminating the sheath voltage drop, and secondly, the electron velocity is much faster than the ion velocity, and this velocity difference is due to the very large mass ratio between the two species. (2) Chuck capacitor C during ESC recharging phase 502 e recharging of the substrate surface during ionic current phase 504 (described below) due to the rapid injection of a charge of equal and opposite polarity to the total charge accumulated on the substrate surface during ionic current phase 504 (described below). As during phase 501, the nanosecond pulse generator 214 maintains a nearly constant positive voltage across its output (switch S1 remains in the on position). As with phase 501, the duration T2 of phase 502 is much shorter than the duration T4 (described below) or overall period T of ionic current phase 504, typically on the order of a few tens of nanoseconds (e.g., 30-80 ns). This is because the plasma current during phase 502 is also carried by electrons; that is, in the absence of a cathode sheath, electrons reach the substrate and build up a surface charge, thus charging the capacitor C. e becomes charged. (3) Discharge the stray capacitors in the processing chamber to reform the sheath and reduce the sheath voltage (V SH ) value to adjust the negative voltage change (V OUT 6 is opened at the beginning of the sheath formation phase 503, and the inductive element rapidly (e.g., within about 10 nanoseconds) transfers the stored magnetic energy to the chuck capacitor C e and floating capacitor C s The inductive element has an inductance L internal and an inductance L, which is labeled 309 in the circuit 600. transm During magnetic energy release, the corresponding current flows through a flyback diode or another snubber circuit with a similar function to suppress (i.e., "snub") possible voltage spikes. As can be seen from the time history curve of the nanosecond pulse generator output voltage V0 shown in FIG. 7B, during magnetic energy release, the internal voltage source of the nanosecond pulse generator (e.g., 214) does not maintain a positive output voltage (switch S1 remains in the off position), so it temporarily drops to a few negative volts, allowing the flyback diode to pass current. Note that without a flyback diode (or another component with a similar function to "snub" possible voltage spikes), the magnetic energy would have to be released through a resistive current feedback output stage, which would result in an impractically large negative voltage (e.g., -20 kV, which could damage the internal components of the pulse bias generator 240) across the resistor for a few nanoseconds, and would not drop to near zero. Magnetic energy is released, L transm The current passing through (L internal ) to zero, then reverses direction and flows from the plasma and the floating capacitor through the current feedback output stage to ground (the flyback diode is reverse biased and blocks the current from flowing through itself). In this way, the floating capacitor C s is discharged, and the sheath capacitor CSH becomes charged (i.e., the sheath is reformed). The onset of sheath formation (C SH 5B, the substrate potential begins to drop below the local plasma potential. As with phase 501, the duration T3 of phase 503 is much shorter than the duration T4 (described below) or overall period T of ionic current phase 504, typically on the order of 100-300 ns. This is because the plasma current during phase 503 is also carried by electrons. That is, the cloud of electrons moves away from the substrate, gradually exposing the ionic space charge, thus forming a sheath and resulting in a sheath voltage drop. Note the following: (1) T3 is determined primarily by the stray capacitance and the values ​​of the elements (e.g., resistors) that make up the current feedback output stage. (2) The negative voltage change V OUT and the established sheath voltage V SH V m (the magnitude of the nanosecond pulse generator output voltage during phases 501-502), and the total pulse width τ tot = τ rise +τ p =T1+T2. tot (actual controlled parameter) is V OUT and V SH To illustrate the effect of T2 and the increase in bias electrode voltage ΔV during phase 502, s、2 Both are mainly V m and ionic current I i It should be noted that the equation is determined by V m and I i Given the total pulse width τ tot controls T1, and in turn, T1 controls the increase in substrate voltage ΔV during phase 501. sub、1 and the increase in bias electrode voltage ΔV s、1 ≒ΔV sub、1 Therefore, V OUT = ΔV s、1 +ΔV s、2 , and V SH ≒ΔV sub、1 is required. (4) A long ionic current phase 504 (approximately 85-90% of cycle duration T) having duration T4. During this time, the nanosecond pulse generator 214 similarly does not maintain a positive voltage across its output (switch S1 remains in the OFF position) and ionic current flows from the plasma through the current feedback output stage to ground. The ionic current causes a positive charge to build up on the substrate surface, gradually discharging the sheath and chuck capacitors, thus slowly reducing the sheath voltage drop and causing the substrate potential to approach zero. This causes a voltage droop ΔV in the substrate voltage waveform 510 shown in FIG. 5B. SH In order for this sheath voltage droop to occur, the pulse voltage waveform 500 must transition to the next cycle described above in (1)-(3). During this next cycle, the nanosecond pulse generator 214 removes the charge accumulated during the ionic current phase (or restores the initial ESC charge) and creates the desired sheath voltage V SH Note that surface charge and sheath voltage droop builds up whenever there is an unbalanced net current (equal to the ionic current) from the electron-repelling cathode sheath and the bulk plasma. As mentioned above, this is because the ionic current from the bulk plasma does not balance the electronic current from the bulk plasma, and this imbalance occurs because the sheath field repels electrons to the substrate. Thus, surface charge buildup and voltage droop occur during the sheath formation phase 503 as well, and the sheath voltage drop is not zero from the beginning of this phase.

[0027] As can be seen from (1)-(4) above, the total duration of the "electronic current" phases 501-503 constituting a single voltage pulse in a pulsed voltage waveform (such as pulsed voltage waveform 500) is about 200-400 ns, which corresponds to a relatively short duty ratio of about 10-15%. The short duty ratio characteristic of pulsed voltage waveform 500 is a result of the large ion-to-electron mass ratio that is typical of all plasmas. Thus, in the pulsed voltage bias scheme proposed herein, the pulsed bias generator actively interacts with the plasma only for a short period of each cycle, while the cathode sheath is allowed to develop naturally for the rest of the time. By effectively utilizing fundamental plasma properties, the bias scheme can maintain the sheath voltage nearly constant for up to about 90% of the process time, which results in a single-peak IEDF (e.g., IEDF 520 in FIG. 5C). Conversely, in a conventional bias scheme, the applied RF voltage (having a waveform like that of FIG. 1A) modulates the cathode sheath throughout the RF cycle, thus constantly varying the sheath voltage drop to produce a bi-peak IEDF (e.g., the IEDF shown in FIG. 1B).

[0028] The pulsed voltage bias scheme proposed herein allows for the maintenance of a particular substrate voltage waveform, such as the substrate voltage waveform 510 shown in FIG. 5B. This substrate voltage waveform can be described as a periodic series of short positive pulses 511 superimposed on a negative voltage offset 512. During each pulse (with total duration T5=T1+T2+T3), the substrate potential reaches the local plasma potential and the sheath collapses for a short period of time. However, for about 90% of each cycle (with cycle duration T), the sheath voltage drop remains approximately constant and the absolute value of the most negative substrate potential V SH (FIG. 5B). Its absolute value thus determines the average ion energy at the substrate surface. During the sheath collapse phase 501 of the bias cycle, the current from the nanosecond pulse generator (e.g., 214) flows through the processing plasma and through a floating capacitor C s In any case, almost C SH / C sHowever, this is not a meaningful amount. w is typically very large, so that the voltage drop that builds up across the wall sheath during phase 501 is relatively small. As a result, the near-wall plasma potential V w is the wall sheath voltage drop and the (very large C coat (Fig. 6) and remains nearly zero (Fig. 7F). Therefore, the local (near-substrate) plasma potential V pl is equal to the sum of the near-wall plasma potential and the voltage drop across the bulk plasma (FIG. 6) and is determined primarily by the latter, increasing slightly above zero (FIGS. 5B and 7F). Then, during the ESC recharging phase 502, the electron-repelling cathode sheath is absent and the wall sheath capacitor is charged to a significant voltage (e.g., hundreds of volts) due to the large currents being pushed through the ESC by the nanosecond pulse generator (e.g., 214). Due to the rise in the near-wall plasma potential and the presence of a relatively large voltage drop across the bulk plasma (caused by the same large currents), the local (near-substrate) plasma potential V pl and the substrate potential V sub is the established sheath voltage V SH Finally, during the sheath formation phase 503, the current through the processing plasma again increases by approximately 1 / 3 C SH / C s and is relatively small (and also decays quickly). As a result, the voltage drop across the bulk plasma is also relatively small. Thus, the local (near-substrate) plasma potential remains approximately equal to the near-wall plasma potential, and toward the end of phase 503, they both settle to approximately zero as the wall sheath is discharged primarily by ionic currents to the chamber walls. As a result of the local plasma potential disturbances during phases 501-503, the established sheath voltage V SH is the overall negative jump V' in the substrate voltage waveform 510 at the end of phase 503. SH The negative sudden change V' is only about 75% of the SH Vm and τ tot Given, (C w is close to infinity, and R pl is close to zero), and further determines the maximum sheath voltage, and further determines the sudden negative change V' in the bias electrode voltage waveform 500. SH V' is close to a sudden negative change SH ≒V OUT The latter holds true because during phase 503, the chuck capacitor loses a small fraction of its initial charge (∝C SH / C e ≪1) to the sheath, thus maintaining a nearly constant potential difference between the electrode and the substrate. OUT From V SH To estimate V SH / V OUT A relationship of ≒0.75~0.8 can be used. A. Practical Considerations

[0029] A practical simplified electrical circuit 600 and the results of a numerical simulation of that circuit are shown in Figures 6 and 7A-7H, respectively. Note that in order to simulate a non-ideal switch with a finite termination time, the practical PSPICE model uses a constant voltage source V m Instead of the maximum voltage V m and a trapezoidal voltage pulse with finite rise time (synchronous with the switch control voltage pulse P1) was used. All circuit parameters used for modeling are listed in Table 1. [Table 1]

[0030] FIG. 7A shows a time history (and three waveform cycle history) of a modeled nanosecond pulse generator output voltage, V(t). FIG. 7B shows an expanded view of a portion of FIG. 7A. FIG. 7C shows the voltage V at the bias electrode, modeled as shown in circuit 600 of FIG. 6. s (t), i.e., C s FIG. 7D is an expanded view of a portion of FIG. 7C. FIG. 7E shows the substrate potential Vsub , local (near the substrate) plasma potential V pl , and the near-wall plasma potential V w 7F is an enlarged view of a portion of FIG. 7D. FIG. 7G shows the inductance L transm The modeled current I L FIG. 7H is an enlarged view of a portion of FIG. 7G.

[0031] The calculated results in Figures 7E and 7F clearly demonstrate that the use of a pulsed bias generator 240 (comprising a nanosecond pulse generator 214 and a current feedback output stage 215) produces a nearly constant sheath (and substrate) voltage over a large portion of the waveform period, thus creating a narrow single-peak IEDF (such as the single-peak IEDF 520 shown in Figure 5C). The pulse repetition frequency used to obtain the results in Figures 7A-H is 400 kHz, with a corresponding waveform period of 2.5 microseconds. The substrate potential waveforms in Figures 7E and 7F exhibit a small voltage droop (ΔV in Figure 5B). SH ) which accumulates over the course of the ionic current phase 504 and can be estimated as follows: During the ionic current phase 504, (a) the voltage on the bias electrode (i.e., the chucking pole) decreases with respect to the resistance R ros remains constant at a level determined by V esc =I i *R ros and (b) the sheath voltage droop ΔV over the duration T4 of the ionic current phase 504 (close to the waveform period T) since the plasma potential also remains constant (close to zero). SH It is easy to see that is given by: ΔV SH =I i T / (C e +C SH ) (1), Here, I iis the ionic current flowing through the sheath. This formula means that the ionic current flows through the sheath capacitor C SH and chuck capacitor C e and both must be discharged to change the sheath voltage. The above equations allow the selection of appropriate parameters for effective operation of the pulsed voltage bias scheme proposed herein, as well as the determination of application limits.

[0032] For example, the nearly constant sheath voltage V SH In order to maintain a relatively small voltage droop, i.e., I i T / (C e +C SH )≪V SH The requirements for ionic current (typically 0.5-5A), C e Given and T, the requirement gives a range of sheath voltages for which the pulsed voltage bias scheme proposed herein is most useful. This requirement indicates that the effectiveness of this bias scheme in producing a narrow single-peak IEDF (i.e., IEDF 520 in FIG. 5C) increases with the desired sheath voltage and ion energy. Hence, the pulsed voltage bias scheme is particularly suitable for challenging high aspect ratio applications such as “hard mask opening” and “dielectric mold etching”. More precisely, the relative width of the monoenergetic peak in the “monoenergetic” IEDF produced using the bias scheme described herein is approximately ΔV SH / V SH or in practice C e , I i , and T.

[0033] The above requirements also imply that the pulsed voltage biasing scheme proposed herein works well when the pulsed voltage waveform (e.g., voltage waveform 500 of FIG. 5A) has a higher pulse repetition frequency (PRF) (i.e., when the period T is shorter). Indeed, as can be seen from equation (1), the value of voltage droop, ΔV, SHIn turn, as the voltage droop increases, the relative width ΔV of the single-peak IEDF generated using the pulsed voltage biasing scheme proposed here increases. SH / V SH , which results in a reduced ability to precisely control the shape of any IEDF created using this single-peak IEDF. However, the PRF must be selected in balance with two further considerations: (a) the challenge of generating high voltage nanosecond pulses increases significantly with switching frequency, and (b) the duration T4 of the ionic current phase 504, during which ions are accelerated toward the substrate surface and ion bombardment of the substrate surface occurs (e.g., etching occurs during an etching process), must be much longer than the total duration T1+T2+T3 of the sheath collapse phase 501, the ESC recharge phase 502, and the sheath formation phase 503. This total duration is independent of the pulse repetition frequency and is proportional to the total duration T1+T2+T3 of the circuit elements C. s , R ros , L ros , L internal , L transm (Figure 6), typically about 200-400 ns. In practice, 400 kHz is used for ionic currents of several amperes and C of several nanofarads (e.g., 7-10 nF). e where the pulse repetition frequency is appropriate for the desired sheath voltage V SH But, ΔV SH (For example, with the above parameters, V SH is approximately 3 to 8 kV).

[0034] From the above requirements, it is also clear that: e is beneficial, which is why the pulsed voltage biasing scheme proposed herein works most effectively when the pulsed voltage is applied to the chucking pole, rather than to the support base 207 (FIG. 2) where the RF power is typically applied in conventional plasma reactors. In fact, in order for the proposed biasing scheme to be effective, C e must be on the order of a few nanofarads. SHis around 100-300pF, which is typical for high aspect ratio applications, this also automatically reduces C e ≫C SH This condition means that for a given V OUT Under V' SH This is important to maximize

[0035] It should be noted that in the pulsed voltage bias scheme proposed herein, voltage switching occurs only inside the nanosecond pulse generator and only at the relatively small voltages (e.g., 100-800V) driving the primary side of the output step-up transformer. This provides a significant practical advantage over previously proposed schemes, which typically have a second switch (placed in place of the resistive output stage) that must be switched at the maximum sheath voltage (i.e., several thousand volts). The presence of the second switch in these previously proposed bias schemes significantly reduces the robustness of the system and, in practice, limits their scalability to sufficiently high sheath voltages (e.g., V of about 4000-8000V) required for high aspect ratio applications. SH ) The authors have not been able to identify any commercially available switches capable of switching at high voltages, e.g. 8,000V, simultaneously at high frequencies (e.g. 400kHz). At this point it should be mentioned that the purpose of the blocking diode in Figure 3 is to prevent return current from flowing in the secondary winding of the step-up transformer, not in the current feedback output stage between phases 503 and 504.

[0036] Note that the authors note that the current feedback output stage 215 may include a combination of reactive elements such as inductors and capacitors (e.g., series inductors) without limiting its effectiveness in generating a nearly constant sheath voltage. We also note that the resistance of the current feedback output stage (e.g., resistor R ros ) is calculated based on not only the power balance but also the RC discharge time t stab ≒R ros (Cs +C SH ) must be determined in combination with the requirement to minimize the RC discharge time, which determines the duration T3 of the sheath formation phase 503. The commercial availability of nanosecond pulse generators is another advantage of the pulsed voltage bias scheme proposed here.

[0037] The pulsed voltage bias scheme proposed herein can also be easily integrated with a high voltage module (HVM), which is typically used to chuck, or "electrically clamp," a substrate to the substrate receiving surface of an ESC substrate support, as shown in Figures 2 and 3. Chucking the substrate allows the gap between the substrate receiving surface and the non-device surface of the substrate to be filled with helium gas (He). This is done to provide good thermal contact between the two and to allow substrate temperature control by regulating the temperature of the ESC substrate support. Combining the DC chucking voltage generated by the HVM with the pulsed voltage generated by the pulsed bias generator (e.g., 240) at the bias electrode (e.g., chucking pole 204) produces an additional voltage offset in the pulsed voltage waveform (e.g., 500) equal to the DC chucking voltage. The effect of the HVM on the operation of the pulsed bias generator can be determined by a suitable magnitude of C hvm and R hvm The blocking capacitor C in the circuit 300 can be neglected by selecting hvm The main function of is to protect the pulse bias generator from the DC voltage of the HVM, thus hvm The DC voltage of the HVM across the two ends of C drops and the output of the pulsed bias generator is not disturbed. hvm The value of must be chosen so that it does not load the high frequency output voltage of the pulsed bias generator while blocking only the DC voltage of the HVM. hvm By selecting a capacitance (e.g. 40-80nF), a 400kHz signal can be almost transmitted. hvmis much larger than any other relevant capacitance in the system, and the voltage drop across this element is e , C SH This is because the voltage drop across the blocking resistor R hvm The purpose of this blocking resistor R is to block the high frequency pulsed bias generator voltage and minimize the current it induces in the HVM DC voltage supply. hvm must be large enough to effectively minimize the current flowing through it. For example, R hvm If I is greater than 1 megohm, it is sufficient to make the 400 kHz current from the pulse bias generator to the HVM negligible, and then I hvm ≒V OUT / R hvm is of the order of 5 mA peak, about a factor of 10 averaged over the waveform period. The resulting average induced current, on the order of 0.5 to 1 mA, is certainly much smaller than the typical limit for HVM power supplies, i.e., DC current of about 5 mA. The above estimates are based on V OUT ≈5 kV, where V OUT (see FIG. 5A) is a positive voltage jump at the chucking pole 204 during the sheath collapse phase 501 and ESC recharge phase 502, during which the switch S1 remains in the closed (on) position and the nanosecond pulse generator 214 maintains a nearly constant positive voltage across its output. Also, R hvm When selecting, be sure to leak *R hvm ≪V hvm It is important to remember that this cannot be made too large in order to satisfy the following: leak Considering that is on the order of tens of microamperes, I leak *R hvm ≪V hvm It shouldn't be that difficult to meet.

[0038] FIG. 8 shows an oscilloscope trace of the substrate voltage measurement waveform generated by an actual implementation of the pulsed voltage bias method proposed herein. Measurements were performed using a LeCroy PPE4kV (100:1, 50MΩ / 6pF, 4kVpp, 400MHz) high voltage oscilloscope probe in an oxygen dominated 10mT plasma with an ionic current to the wafer of about 1.35A. The probe was connected via an electrical (vacuum) feedthrough to a direct contact sensor comprising a Kapton™ coated wire wrapped in an alumina bead, which was connected to a low resistivity silicon wafer using a large enough patch of aluminum tape with conductive adhesive (for good capacitive coupling), which was further covered with Kapton™ tape and alumina paste. This diagnosis was performed in bench tests using a test signal from a function generator, and the substrate potential measurement was also independently verified using an aluminum wafer. As can be seen from FIG. 8, the experimentally observed substrate voltage waveform is in good agreement with the model generated waveform shown in FIG. 7E. Good agreement between the model and experiment was also observed for oscilloscope traces (not shown) of the plasma potential measured near the chamber lid. The measurements used a floating Langmuir probe similarly connected to a LeCroy PPE 4 kV probe via an electrical (vacuum) feedthrough. The measured waveform shows that the plasma potential settles to near zero by the onset of the ionic current phase 504. These measurements demonstrate that the pulsed voltage bias scheme proposed herein can indeed be used to generate a nearly constant sheath (substrate) voltage for up to 90% of the substrate processing time, which in turn results in a narrow single-peak IEDF (i.e., IEDF 520 in FIG. 5C) that can be used to create IEDFs with arbitrary shapes. B. Detailed description of FIG. 2: Chamber diagram

[0039] FIG. 2 is a schematic cross-sectional view of a processing chamber configured to implement the biasing scheme proposed herein, according to an embodiment. In this embodiment, the processing chamber is a plasma processing chamber, such as a reactive ion etching (RIE) plasma chamber. In some other embodiments, the processing chamber is a plasma deposition chamber, such as a plasma enhanced chemical vapor deposition (PECVD) chamber, a plasma enhanced physical vapor deposition (PEPVD) chamber, or a plasma enhanced atomic layer deposition (PEALD) chamber. In some other embodiments, the processing chamber is a plasma treatment chamber, or a plasma-based ion implantation chamber, such as a plasma enhanced doping (PLAD) chamber. Herein, the processing chamber comprises an inductively coupled plasma (ICP) source electrically connected to a radio frequency (RF) power source. In other embodiments, the plasma source is a capacitively coupled plasma (CCP) source, such as a source electrode disposed in the processing volume facing the substrate support, where the source electrode is electrically connected to a radio frequency power source.

[0040] The main part of the process chamber 200 is a chamber body 213, which includes a chamber lid 223, one or more sidewalls 222, and a chamber base 224 that define a process volume 226. A gas inlet 228 disposed through the chamber lid 223 is used to supply one or more process gases to the process volume 226 from a process gas source 219 in fluid communication therewith. Here, a plasma generator configured to ignite and sustain a process plasma 201 from the process gases includes one or more induction coils 217 disposed proximate the chamber lid 223 outside the process volume 226. The one or more induction coils 217 are electrically connected to a radio frequency power source 218 via a radio frequency matching circuit 230. The plasma generator is used to ignite and sustain the plasma 201 using the process gases and an electromagnetic field generated by the induction coil 217 and the radio frequency power source 218. The processing volume 226 is fluidly connected via a vacuum outlet 220 to one or more dedicated vacuum pumps, which maintain the processing volume 226 at sub-atmospheric conditions and evacuate processing and / or other gases therefrom. A substrate support assembly 236 disposed within the processing volume 226 is disposed on a support shaft 238 that sealingly extends through the chamber base 224.

[0041] The substrate 203 is loaded into and removed from the process volume 226 through an opening (not shown) in one of the one or more side walls 222. During plasma processing of the substrate 203, this opening is sealed with a door or valve (not shown). The substrate 203 is then transferred to and from the receiving surface of the ESC substrate support 205 using a lift pin system (not shown).

[0042] The substrate support assembly 236 includes a support base 207 and an ESC substrate support 205 thermally coupled to and disposed thereon. Typically, the support base 207 is used to regulate the temperature of the ESC substrate support 205 and the substrate 203 disposed thereon during substrate processing. In some embodiments, the support base 207 includes one or more cooling channels (not shown) disposed therein that are fluidly connected to and in fluid communication with a cooling fluid source (not shown), such as a coolant source or a cooling water source having a relatively high electrical resistance. In some embodiments, the ESC substrate support 205 includes a heater (not shown), such as an electrically resistive heating element embedded in its dielectric. Here, the support base 207 is formed of a corrosion-resistant, thermally conductive material (such as a corrosion-resistant metal, e.g., aluminum, an aluminum alloy, or stainless steel) and is coupled to the substrate support by adhesive or mechanical means. Typically, the ESC substrate support 205 is formed of a dielectric material such as a bulk sintered ceramic material, such as a corrosion resistant metal oxide or metal nitride material (e.g., aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof). In embodiments herein, the ESC substrate support 205 further comprises a bias electrode 204 embedded in the dielectric material. In one configuration, the bias electrode 204 is a chucking pole that is used to secure (chuck) the substrate 203 to the support surface of the ESC substrate support 205 and bias the substrate 203 against the processing plasma 201 using a pulsed voltage bias scheme described herein. Typically, the bias electrode 204 is formed of one or more conductive components, such as a mesh, foil, thin sheet, or combinations thereof, of one or more metals. Here, the bias electrode 204 is electrically connected using a conductor such as a coaxial transmission line 206, e.g., a coaxial cable, to a high voltage module 216 that supplies a chucking voltage thereto (e.g., a static DC voltage between about -5000V and about 5000V).

[0043] The support base 207 is electrically isolated from the chamber base 224 by an insulating plate 211, and a ground plate 212 is disposed between the insulating plate 211 and the chamber base 224. In some embodiments, the process chamber 200 further comprises a quartz tube 210, or a quartz ring, surrounding the substrate support assembly 236 to prevent corrosion of the ESC substrate support 205 and / or contact of the support base 207 with corrosive process gases or plasmas, cleaning gases or plasmas, or by-products thereof. Typically, the quartz tube 210, the insulating plate 211, and the ground plate are surrounded by a liner 208. Herein, a plasma screen 209, which is generally flush with the substrate receiving surface of the ESC substrate support 205, prevents plasma from forming in the volume between the liner 208 and one or more sidewalls 222.

[0044] Herein, the bias electrode 204 is spaced from the substrate receiving surface of the ESC substrate support 205, and thus from the substrate 203, by a dielectric layer of the ESC substrate support 205. Typically, the dielectric layer has a thickness between about 0.1 mm and about 1 mm (such as about 0.1 mm to about 0.5 mm, e.g., about 0.3 mm). Herein, the bias electrode 204 is electrically connected to a pulse bias generator 240 using an external conductor, such as a transmission line 206. The pulse bias generator 240 and its components have been described in detail earlier in the body of this disclosure. As discussed above, the dielectric and layer thicknesses are selected to determine the capacitance C of the dielectric layer. e can be between about 5 nF and about 12 nF (eg, between about 7 and about 10 nF).

[0045] In general, a lower neutral fill pressure in the process volume 226 of the process chamber 200 results in lower thermal conduction between surfaces disposed therein. For example, reduced thermal conduction between the dielectric of the ESC substrate support 205 and the substrate 203 disposed on its substrate receiving surface reduces the effectiveness of the ESC substrate support 205 in heating or cooling the substrate 203. Thus, in some processes, a thermally conductive inert heat transfer gas, typically helium, is introduced into a volume (not shown) disposed between the non-device surface of the substrate 203 and the substrate receiving surface of the ESC substrate support 205 to improve heat transfer therebetween. The heat transfer gas, supplied by a heat transfer gas source (not shown), is disposed through the support base 207 and flows into the backside volume through a gas communication path (not shown) disposed through the ESC substrate support 205.

[0046] The processing chamber 200 further comprises a system controller 232. The system controller 232 herein comprises a central processing unit (CPU) 233, a memory 234, and support circuits 235. The system controller 232 is used to control a processing sequence comprising the substrate biasing method described herein and to process the substrate 203 using the processing sequence. The CPU 233 is a general-purpose computer processor configured for use in an industrial environment for controlling the processing chamber and its associated sub-processors. The memory 234 described herein may comprise random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of local or remote digital storage. The support circuits 235 are conventionally connected to the CPU 233 and comprise caches, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions and data may be coded and stored in the memory 234 for instructions to the processor in the CPU 233. Programs (or computer instructions) readable by the system controller 232 determine which tasks are executable by the components in the processing chamber 200. Preferably, the program readable by the system controller 232 includes code that, when executed by a processor, performs tasks associated with monitoring and executing the electrode biasing schemes described herein. The program includes instructions used to control various hardware and electrical components within the process chamber 200 to perform various process tasks and various process sequences used to implement the electrode biasing schemes described herein.

[0047] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be made without departing from the basic scope thereof, which is defined by the following claims.

Claims

1. 1. A method for processing a substrate, comprising: generating a plasma on a surface of a substrate disposed on a substrate support assembly, the substrate support assembly comprising a bias electrode and a layer of dielectric material disposed between the bias electrode and the substrate; establishing a pulsed voltage waveform at the bias electrode using a bias generator electrically coupled to the bias electrode via a blocking capacitor and one or more electrical conductors; chucking the substrate to the substrate support assembly by supplying a chucking voltage from a high voltage module through one of the one or more electrical conductors to a bias electrode; The blocking capacitor is disposed between the high voltage module and the bias generator.

2. The method of claim 1 , wherein the blocking capacitor has a capacitance of about 40 nF to about 80 nF.

3. The pulsed voltage waveform includes a series of repeating cycles, a waveform in each cycle of the series of repeating cycles having a first portion occurring during a first time interval and a second portion occurring during a second time interval; The method of claim 1 , wherein the positive voltage pulse is only present during the first time interval.

4. the one or more conductors include a first conductor coupled to the bias electrode and a second conductor coupled to the bias generator; The method of claim 3 , wherein a blocking capacitor is coupled between the first conductor and the second conductor.

5. the bias generator comprises a pulse generator electrically coupled to the second conductor and a current feedback output stage; a first end of the current feedback output stage electrically coupled to the second conductor; a second end of the current feedback output stage is electrically grounded; 5. The method of claim 4, wherein current flows from the bias electrode through a current feedback output stage to ground during at least a portion of the second time interval.

6. the high voltage module is electrically coupled between ground and the first conductor; The method of claim 4 , wherein the chucking voltage is applied to the first conductor relative to ground.

7. A processing chamber comprising:

1. A pulsed DC bias system comprising: a substrate support assembly comprising a bias electrode and a substrate support surface; a pulsed DC bias system comprising a bias generator electrically coupled to a bias electrode using one or more electrical conductors and a blocking capacitor; A non-transitory computer readable medium having stored thereon instructions for, when executed by a processor, performing a method for processing a substrate, the method comprising: generating a plasma on a surface of a substrate, the substrate being separated from a bias electrode by a layer of dielectric material of a substrate support assembly; establishing a pulsed voltage waveform on a bias electrode via a blocking capacitor using a bias generator; chucking the substrate to the substrate support assembly by supplying a chucking voltage from a high voltage module through one of the one or more electrical conductors to a bias electrode; A processing chamber comprising a computer-readable medium, wherein the blocking capacitor is disposed between the high voltage module and the bias generator.

8. The pulsed voltage waveform includes a series of repeating cycles, a waveform in each cycle of the series of repeating cycles having a first portion occurring during a first time interval and a second portion occurring during a second time interval; 8. The processing chamber of claim 7, wherein the positive voltage pulse is only present during the first time interval.

9. the one or more conductors include a first conductor coupled to the bias electrode and a second conductor coupled to the bias generator; The processing chamber of claim 8 , wherein the blocking capacitor is coupled between the first conductor and the second conductor.

10. The bias generator is a pulse generator electrically coupled to the second conductor; A current feedback output stage is provided. a first end of the current feedback output stage electrically coupled to the second conductor; a second end of the current feedback output stage electrically coupled to ground; 10. The processing chamber of claim 9, wherein current flows from the bias electrode through a current feedback output stage to ground during at least a portion of the second time interval.

11. 1. A pulsed DC bias system comprising: a substrate support assembly comprising a bias electrode and a substrate support surface, the bias electrode being electrically coupled to the first electrical conductor; a bias generator electrically coupled to the second conductor; a blocking capacitor electrically coupled between the first conductor and the second conductor; a blocking resistor electrically coupled to the first conductor at a connection point disposed between the blocking capacitor and the bias electrode; 1. A non-transitory computer readable medium having stored thereon instructions that, when executed by a processor, perform a method for processing a substrate, the method comprising: generating a plasma on a surface of a substrate disposed on a substrate support surface; establishing a pulsed voltage waveform on a bias electrode via a blocking capacitor using a bias generator; A system including a computer readable medium that includes chucking a substrate to a substrate support assembly by supplying a chucking voltage from a high voltage module through a first conductor to a bias electrode.

12. 12. The pulsed DC bias system of claim 11, wherein the bias electrode is spaced from the substrate support surface by a layer of dielectric material.

13. 12. The pulsed DC bias system of claim 11, wherein the blocking capacitor has a capacitance of about 40 nF to about 80 nF.

14. 12. The pulsed DC bias system of claim 11, wherein the high voltage module is electrically coupled to the first electrical conductor at a connection point disposed between the bias electrode and the blocking capacitor.

15. 15. The pulsed DC bias system of claim 14, wherein the high voltage module is disposed between the blocking resistor and ground.

16. 16. The pulsed DC bias system of claim 15, wherein the blocking resistor has a resistance greater than about 1 Mohm.

17. 20. The pulsed DC bias system of claim 16, wherein the high voltage module is configured to apply a voltage to the first conductor relative to ground.

18. the high voltage module is electrically coupled to the first end of the first electrical conductor; a bias electrode coupled to the second end of the first conductor; a blocking capacitor disposed between the first end of the first conductor and the bias generator; 12. The pulsed DC bias system of claim 11, wherein the blocking resistor is disposed between the first end of the first conductor and the bias generator.

19. The pulsed voltage waveform includes a series of repeating cycles, a waveform in each cycle of the series of repeating cycles having a first portion occurring during a first time interval and a second portion occurring during a second time interval; 12. The pulsed DC bias system of claim 11, wherein the positive voltage pulse is only present during the first time interval.

20. the pulse voltage waveform is substantially constant during at least a portion of the second time interval; 20. The pulsed DC bias system of claim 19, wherein the second time interval is greater than the first time interval.

21. the high voltage module is electrically coupled between ground and the first conductor; 21. The pulsed DC bias system of claim 20, wherein the chucking voltage is applied to the first conductor with respect to ground.

22. 1. A pulsed DC bias system comprising: a substrate support assembly including a bias electrode and a substrate support surface; a bias generator electrically connected to the bias electrode; a blocking capacitor electrically coupled to the bias electrode using a first conductor and electrically coupled between the bias generator and the bias electrode; a blocking resistor electrically coupled to the first conductor at a connection point disposed between the blocking capacitor and the bias electrode; A non-transitory computer readable medium having stored thereon instructions for, when executed by a processor, performing a method for processing a substrate, the method comprising: generating a plasma on a surface of a substrate disposed on a substrate support surface; establishing a pulsed voltage waveform on a bias electrode via a blocking capacitor using a bias generator; A system including a computer readable medium that includes chucking a substrate to a substrate support assembly by supplying a chucking voltage from a high voltage module through a first conductor to a bias electrode.

23. A pulsed voltage waveform consists of a series of repeating cycles, a waveform in each cycle of the series of repeating cycles having a first portion occurring during a first time interval and a second portion occurring during a second time interval; 23. The pulsed DC bias system of claim 22, wherein the positive voltage pulse is only present during the first time interval.

24. a second conductor coupled to the bias generator; 24. The pulsed DC bias system of claim 23, wherein the blocking capacitor is coupled between the first conductor and the second conductor.

25. 25. The pulsed DC bias system of claim 24, wherein the high voltage module is disposed between the blocking resistor and ground.

26. 25. The pulsed DC bias system of claim 24, wherein the substrate is positioned spaced apart from the bias electrode by a layer of dielectric material of the substrate support assembly.

27. 1. A non-transitory computer readable medium having stored thereon instructions that, when executed by a processor, perform a method for processing a substrate, the method comprising: generating a plasma on a surface of a substrate disposed on a substrate support surface of a substrate support assembly comprising a bias electrode and a substrate support surface, the bias electrode being electrically coupled to a first electrical conductor; establishing a pulsed voltage waveform at a bias electrode through a blocking capacitor using a bias generator, the bias generator being electrically coupled to the second conductor; chucking the substrate to the substrate support assembly by supplying a chucking voltage from a high voltage module through a first conductor to a bias electrode, a blocking capacitor coupled between the first conductor and the second conductor; The blocking resistor is electrically coupled to the first conductor at a connection point disposed between the blocking capacitor and the bias electrode.

28. A pulsed voltage waveform consists of a series of repeating cycles, 30. The computer-readable medium of claim 27, wherein the waveform in each cycle of the series of repeating cycles has a first portion occurring during a first time interval and a second portion occurring during a second time interval.

29. 30. The computer-readable medium of claim 28, wherein the positive voltage pulse is only present during the first time interval.

30. 30. The computer readable medium of claim 29, wherein the substrate is spaced from the bias electrode by a layer of dielectric material of the substrate support assembly.

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