Wiring board

Abstract

To make an electron component mounted onto a wiring board to preferably operate and surely perform a power supply from a mother board to which the wiring board is mounted.SOLUTION: A wiring board 1 comprises: a core substrate CB1 including a conductive layer onto first and second surfaces S1 and S2; a first build up part BU1 in which a first insulation layer 11 and a first conductive layer 12 are alternately laminated onto the first surface S1, a conductive layer C1 on the first surface and both of the first conductive layers 12 and 12 on a first surface are connected in a first via conductor 13; and a second build up part BU2 in which a second insulation layer 21 and a second conductive layer 22 are alternately laminated onto a second surface S2, and a conductive layer C2 on a second surface and both of the second conductive layers 22 and 22 are connected in a second via conductor 23. A connection part with a bottom part of the first via conductor 13 in the conductor layer C1 and the first conductive layer 12 includes a first concave part D1, and a connection part with the bottom part of the second via conductor 23 of the conductive layer C2 and the second conductive layer 22 is flattened, or includes a second concave part D2 that is narrower than that of the first concave part D1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board having a plurality of build-up portions. [Background technology]

[0002] Patent Document 1 discloses a wiring board 100 including a core substrate CB100 having a first surface S100 and a second surface S200, a first buildup section BU100 formed on the first surface S100, and a second buildup section BU200 formed on the second surface S200, as shown in Fig. 3. Here, the core substrate CB100 has a conductor layer C100 on the first surface S100 and a conductor layer C200 on the second surface S200, and the conductor layer C100 and the conductor layer C200 are connected via a through-hole conductor C300 that penetrates the core substrate CB100.

[0003] The first buildup section BU100 is configured by alternately stacking first insulating layers 110 and first conductor layers 120, with the conductor layer C100 and the first conductor layer 120 and the first conductor layers 120 being connected to each other via first via conductors 130. The second buildup section BU200 is configured by alternately stacking second insulating layers 210 and second conductor layers 220, with the conductor layer C200 and the second conductor layer 220 and the second conductor layers 220 being connected to each other via second via conductors 230.

[0004] A first recess D100 is formed in a connection portion of the conductor layer C100 and the first conductor layer 120 that will become the via bottom when the first via conductor 130 is formed, in order to increase the connection area with the bottom of the first via conductor 130 compared to when the connection portion is flat, thereby improving connection reliability and reducing electrical resistance. A second recess D200 is also formed in a connection portion of the conductor layer C200 and the second conductor layer 220 that will become the via bottom when the second via conductor 230 is formed, for the same reason. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2006 / 101134 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the conventional wiring board 100, since there are recesses in the connection portions of both the conductor layer C100 and the first conductor layer 120 and the conductor layer C200 and the second conductor layer 220, when the first and second via conductors 130, 230 connected to these recesses are formed by electrolytic plating together with the first and second conductor layers 120, 220, the vias are poorly filled with conductors. Therefore, when the wiring board 100 is subjected to an external force, a thermal shock, or the like, the via conductors may break. [Means for solving the problem]

[0007] The wiring board of the present invention is a core substrate having conductor layers on a first surface and a second surface connected via through-hole conductors; a first build-up section in which first insulating layers and first conductor layers are alternately laminated on a first surface, and the conductor layers on the first surface and the first conductor layers are connected to each other via first via conductors; a second buildup section in which second insulating layers and second conductor layers are alternately laminated on the second surface, and the conductor layers on the second surface and the second conductor layers are connected to each other via second via conductors; A wiring board comprising: a first recess is formed in a connection portion of the conductor layer on the first surface and the first conductor layer with a bottom of the first via conductor; The conductive layer on the second surface and the second conductive layer have a connection portion with the bottom of the second via conductor that is flat or has a second recess that is shallower than the first recess. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a schematic diagram of a wiring board according to an embodiment of the present invention; [Diagram 2]5A and 5B are enlarged cross-sectional views showing connection portions of conductor layers on the front and back sides, respectively, of the wiring board of the embodiment. [Diagram 3] FIG. 11 is a cross-sectional view showing a schematic diagram of a wiring board according to a conventional example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An embodiment of the wiring board of the present invention will be described with reference to the drawings. Fig. 1 is a cross-sectional view showing a schematic diagram of the wiring board of one embodiment of the present invention. In the embodiment shown in Fig. 1, the dimensions of each member, particularly the height direction dimensions, are shown in dimensions different from the actual dimensions in order to allow a better understanding of the features of the present invention.

[0010] The wiring board 1 of the embodiment shown in Fig. 1 includes a core substrate CB1 having a first surface S1 as a front surface and a second surface S2 as a back surface, a first build-up section BU1 formed on the first surface S1, and a second build-up section BU2 formed on the second surface S2, similar to the wiring substrate of the conventional example shown in Fig. 3. Here, the core substrate CB1 has a conductor layer C1 on the first surface S1 and a conductor layer C2 on the second surface S2, and the conductor layer C1 and the conductor layer C2 are connected via a through-hole conductor C3 that penetrates the core substrate CB1.

[0011] The first buildup section BU1 is configured by alternately stacking first insulating layers 11 and first conductor layers 12, with the conductor layers C1 and the first conductor layers 12 and the first conductor layers 12 being connected to each other via first via conductors 13. The second buildup section BU2 is configured by alternately stacking second insulating layers 21 and second conductor layers 22, with the conductor layers C2 and the second conductor layers 22 and the second conductor layers 22 being connected to each other via second via conductors 23.

[0012] A first recess D1 is formed in the connection portion of the conductor layer C1 and the first conductor layer 12, which will become the via bottom when the first via conductor 13 is formed, in order to increase the connection area with the bottom of the first via conductor 13 compared to when it is flat, thereby improving connection reliability and reducing electrical resistance. Meanwhile, a second recess D200 as deep as the first recess D100 as in the conventional example is not formed in the connection portion of the conductor layer C2 and the second conductor layer 22, which will become the via bottom when the second via conductor 23 is formed, but a substantially flat surface PS or a second recess D2 shallower than the first recess D1 is formed.

[0013] Specifically, the depth of the first recess D1 is preferably 3 μm or more and 7 μm or less, and the depth of the second recess D2 is preferably greater than 0 and less than 3 μm. The first and second via conductors 13 and 23 are preferably filled with a metal, and the metal is preferably copper. The first and second via conductors 13 and 23 are preferably filled with electrolytic plating. The bottom of the first via conductor 13 connected to the first recess D1 is preferably anchor-shaped.

[0014] In the wiring board 1 of this embodiment configured as described above, electronic components such as IC chips are preferably mounted on the first surface S1 side of the core substrate CB1. In addition, in the wiring board 1 of this embodiment, the second surface S2 side of the core substrate CB1 is preferably mounted on a motherboard. The first recess D1 increases the reliability of the interlayer connection of the first conductor layer 12 and reduces the electrical resistance, so that the electronic components mounted on the first surface S1 side of the core substrate CB1 can be operated satisfactorily by the wiring board 1.

[0015] The first and second via conductors 13 and 23 preferably include stacked vias, and although not shown in FIG. 1, the maximum number of stacked vias included in the first via conductor 13 is preferably greater than the maximum number of stacked vias included in the second via conductor 23. The stacked vias reduce the interlayer electrical resistance in the first and second conductor layers 12 and 22. In particular, when the second surface S2 side of the core substrate CB1 is mounted on a motherboard, the flat connection surface PS or the second recess D2 shallower than the first recess D1 in the second conductor layer 22 improves the filling of the conductor into the via, making the via conductor less likely to break even if a thermal shock occurs during operation, and the stacked vias of the first via conductor 13, which has a greater maximum stack number than the second via conductor, reduce the interlayer electrical resistance of the first conductor layer 12, so that the electronic components mounted on the first surface S1 side of the core substrate CB1 can be operated well by the wiring substrate 1.

[0016] Figures 2(a) and (b) are enlarged cross-sectional views respectively showing the connection portions of the pads of the first and second conductor layers 12, 22 on the front and back sides of the wiring board 1 of the above embodiment. As shown in these figures, a first recess D1 is formed in the pad of the first conductor layer 12 on the front side as a connection portion with the first via conductor 13, while a second recess D2 shallower than the first recess D1 is formed in the pad of the second conductor layer 22 on the back side as a connection portion with the second via conductor 23, or a substantially flat surface PS is left, although not shown.

[0017] Such a first recess D1 and a shallower second recess D2 or a substantially flat surface PS can be formed, for example, during the manufacturing process of the wiring board 1, by making different processing conditions, such as the processing time of soft etching performed in the via as a pretreatment to provide a seed layer for filling the via conductor by electrolytic plating, between the first build-up section BU1 and the second build-up section BU2. [Explanation of symbols]

[0018] 1,100 Wiring boards 11,110 First insulating layer 12,120 First conductor layer 13,130 First via conductor 21,210 Second insulating layer 22,220 Second conductor layer 23,230 Second via conductor BU1,BU100 First build-up section BU2,BU200 Second build-up section C1, C100 Conductor layer C2, C200 Conductor layer C3, C300 through hole conductor CB1,CB100 core board D1, D100 First recess D2, D200 Second recess PS flat surface S1,S100 1st page S2,S200 2nd side

Claims

1. a core substrate having conductor layers on a first surface and a second surface connected via through-hole conductors; a first build-up section in which first insulating layers and first conductor layers are alternately laminated on the first surface, and the conductor layers on the first surface and the first conductor layers are connected to each other via first via conductors; a second buildup section in which second insulating layers and second conductor layers are alternately laminated on the second surface, and the conductor layers on the second surface and the second conductor layers are connected to each other via second via conductors; A wiring board comprising: a first recess is formed in a connection portion between the conductor layer on the first surface and the bottom of the first via conductor, and The conductive layer on the second surface and the second conductive layer have a connection portion with the bottom of the second via conductor that is flat or has a second recess that is shallower than the first recess.

2. 2. The wiring board according to claim 1, wherein the depth of the first recess is not less than 3 [mu]m and not more than 7 [mu]m.

3. 2. The wiring board according to claim 1, further comprising the second recess, the depth of the second recess being greater than 0 and less than 3 [mu]m.

4. 2. The wiring board according to claim 1, wherein the first via conductor and the second via conductor are filled with a metal.

5. 5. The wiring board according to claim 4, wherein the metal is copper.

6. 2. The wiring board according to claim 1, wherein the first via conductor and the second via conductor are filled with electrolytic plating.

7. 2. The wiring board according to claim 1, wherein a bottom portion of the first via conductor is formed in an anchor shape.

8. 2. The wiring board according to claim 1, wherein an electronic component is mounted on the first surface side of the core substrate.

9. 2. The wiring board according to claim 1, wherein the second surface side of the core substrate is mounted on a motherboard.

10. 2. The wiring board according to claim 1, wherein the first via conductor and the second via conductor include a stacked via.

11. 11. The wiring board according to claim 10, wherein a maximum number of stacked vias included in the first via conductor is greater than a maximum number of stacked vias included in the second via conductor.

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