High pressure annealing process for metal-containing material

Abstract

To provide a method of performing an annealing process on a metal-containing layer in a TFT display application, and a semiconductor or a memory application.SOLUTION: In one example, a method of forming a metal-containing layer on a substrate includes the steps of supplying an oxygen-containing gas mixture to a substrate in a processing chamber, in which the substrate includes a metal-containing layer disposed on an optically transparent substrate, maintaining the oxygen-containing gas mixture at a process pressure of between about 2 bar and about 50 bar within the processing chamber, and thermally annealing the metal-containing layer in the presence of the oxygen-containing gas mixture.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments of the present invention generally relate to methods for forming metal-containing layers of film stacks that can be used in TFT device structures, semiconductor, or memory applications. [Background technology]

[0002] Display devices are widely used in a wide range of electronic applications, such as televisions, monitors, mobile phones, MP3 players, e-book readers, and personal digital assistants (PADs). Display devices are generally designed to generate a desired image by applying an electric field to liquid crystals, which fill the gap between two substrates and have an anisotropic dielectric constant that controls the strength of the dielectric field. By adjusting the amount of light passing through the substrates, the light intensity and image intensity, image quality, and power consumption can be efficiently controlled.

[0003] A wide variety of display devices, such as active matrix liquid crystal displays (AMLCDs) or active matrix organic light emitting diodes (AMOLEDs), can be used as light sources for display devices utilizing touch screen panels. In the fabrication of TFT devices, electronic devices with high electron mobility, low leakage current, and high breakdown voltage allow for larger pixel areas and circuit integration for light to pass through, resulting in displays with brighter displays, higher overall electrical efficiency, faster response times, and higher resolution. Poor film quality of material layers formed within the device, such as metal electrode layers containing impurities, often leads to poor electrical performance of the device and a short service life of the device. Therefore, a stable and reliable method of forming and integrating film layers within TFT devices has become very important to provide device structures with low film leakage and high breakdown voltage for use in fabricating electronic devices with low threshold voltage shift, and improved overall performance of electronic devices is desired. Summary of the Invention [Problem to be solved by the invention]

[0004] Therefore, there is a need for improved materials for fabricating TFT devices that provide improved device electrical performance and device stability. [Means for solving the problem]

[0005] The present disclosure provides a method for performing an annealing process on a metal-containing layer in a TFT display application, a semiconductor, or a resistive random access memory (ReRAM). In one example, a method for forming a metal-containing layer on a substrate includes the steps of: supplying an oxygen-containing gas mixture to a substrate in a process chamber, the substrate including a metal-containing layer disposed on an optically transparent substrate; maintaining the oxygen-containing gas mixture at a process pressure between 2 bar and 50 bar in the process chamber; and thermally annealing the metal-containing layer in the presence of the oxygen-containing gas mixture.

[0006] In another example, a method of densifying a metal-containing layer disposed on a substrate includes heat treating the metal-containing layer disposed on an optically transparent substrate at a pressure greater than 2 bar and maintaining a substrate temperature below 500° C. during heat treating the dielectric layer.

[0007] In yet another example, a method of densifying a metal-containing layer disposed on a substrate includes forming a metal-containing layer on the substrate, implanting a dopant into the metal-containing layer, and heat treating the metal-containing layer on the substrate at a pressure greater than 2 bar while maintaining a substrate temperature less than 500° C.

[0008] So that the manner in which the features of the invention as set forth above can be understood in detail, a more particular description of the invention briefly summarized above will be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that since the invention is capable of other equally effective embodiments, the accompanying drawings only illustrate typical embodiments of the invention and therefore should not be considered as limiting the scope of the invention. [Brief description of the drawings]

[0009] [Figure 1] 1 illustrates a simplified cross-sectional front view of a processing chamber in which a cassette is disposed, according to some embodiments. [Diagram 2] FIG. 2 is a diagram of a cluster system into which the processing chamber of FIG. 1 can be incorporated. [Diagram 3] FIG. 1 is a cross-sectional view of an example of a thin film transistor device structure. [Figure 4] FIG. 2 is a cross-sectional view of another example of a thin film transistor device structure. [Diagram 5] FIG. 2 is a flow diagram of an annealing process performed on a metal-containing material, according to some embodiments. [Figures 6A-6D] 6 depicts one embodiment of a sequence for thermally annealing the metal-containing material of FIG. 5, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] For ease of understanding, the same reference numerals are used to designate the same elements common to each of the figures, such as annealing at atmospheric pressure with similar annealing conditions where possible, etc. Elements and features of one embodiment are contemplated to be beneficially incorporated in other embodiments even if not specifically described otherwise.

[0011] It should be noted, however, that the present invention may admit of other equally effective embodiments, and that the accompanying drawings only illustrate exemplary embodiments of the invention and therefore should not be considered as limiting the scope of the invention.

[0012] The embodiments of the present disclosure generally present a TFT device structure and a method of performing a thermal annealing process on the active layer of the source, drain, interface and contact regions of the TFT device structure to improve the electrical performance of the display device. Other applications, including semiconductor or memory device manufacturing processes, can also utilize the embodiments described herein. The thermal annealing process can densify the active layer film properties of the metal electrodes, source / drain and / or contact regions, and / or film layers on the substrate. In one example, the heat treatment process is performed to provide thermal energy to the metal-containing layer, such as the metal-containing layer (e.g., the active layer) or metal electrode layer (e.g., the metal gate electrode, source-drain and / or contact regions or electrode layer, or other suitable metal structures) formed in the TFT device. The thermal annealing process can densify or minimize the oxygen deficiencies of the active layer film structure to provide good quality, interface management and thermal stability to the device structure. The thermal annealing process can also increase the degree of crystallinity of the metal-containing material to improve the electrical properties of the metal-containing layer. Therefore, the desired film properties of the metal electrodes and active layers in the source / drain and / or contact regions of the display device can effectively improve the electrical performance of the transistor and diode devices.

[0013] FIG. 1 is a simplified cross-sectional front view of a single substrate processing chamber 100 for a high pressure annealing process of a single substrate. The single substrate processing chamber 100 has a body 110 with an exterior surface 112 and an interior surface 113 that surrounds an interior volume 115. In some embodiments, as in FIG. 1, the body 110 has an annular cross section, while in other embodiments, the cross section of the body 110 can be rectangular or any closed shape. The exterior surface 112 of the body 110 can be made from a corrosion resistant steel (CRS), such as, but not limited to, stainless steel. One or more thermal shields 125 that prevent heat loss from the single substrate processing chamber 100 to the outside environment are disposed on the interior surface 113 of the body 110. The interior surface 113 of the body 110 as well as the thermal shields 125 can be made from nickel-based steel alloys that exhibit high corrosion resistance, such as, but not limited to, HASTELLOY®, ICONEL®, and MONEL®.

[0014] A substrate support 130 is disposed within the interior volume 115. The substrate support 130 has a stem 134 and a substrate support member 132 carried by the stem 134. The stem 134 passes through a passage 122 formed through the chamber body 110. A rod 139 connected to an actuator 138 passes through a second passage 123 formed through the chamber body 110. The rod 139 is coupled to a plate 135 having an opening 136 that accommodates the stem 134 of the substrate support 130. A lift pin 137 is connected to the substrate support member 132. The actuator 138 actuates the rod 139 such that the plate 135 moves up or down to connect and disconnect with the lift pin 137. As the lift pin 137 rises or lowers, the substrate support member 132 rises or lowers within the interior volume 115 of the chamber 100. Substrate support member 132 has a resistive heating element 131 embedded in its center. A power supply 133 is configured to power resistive heating element 131. The operation of power supply 133 as well as actuator 138 is controlled by controller 180.

[0015] The single substrate processing chamber 100 has an opening 111 in the body 110 through which one or more substrates 120 can be loaded onto and unloaded from a substrate support 130 disposed in the interior volume 115. The opening 111 forms a tunnel 121 in the body 110. A slit valve 128 is configured to sealably close the tunnel 121 such that the opening 111 and the interior volume 115 are only accessible when the slit valve 128 is open. To seal the interior volume 115 for processing, a high-pressure seal 127 is utilized to seal between the slit valve 128 and the body 110. The high-pressure seal 127 can be made from a polymer, for example, a fluoropolymer such as, but not limited to, perfluoroelastomer and polytetrafluoroethylene (PTFE). The high-pressure seal 127 can further include a spring member that biases the seal to improve sealing performance. A cooling channel 124 is disposed in the tunnel 121 adjacent to the high pressure seal 127 to maintain the high pressure seal 127 below its maximum safe operating temperature during processing. A coolant, such as, but not limited to, an inert, dielectric, and high performance heat transfer fluid from a cooling fluid source 126, may be circulated through the cooling channel 124. The flow of coolant from the cooling fluid source 126 is controlled by the controller 180 through feedback received from a temperature sensor 116 or a flow sensor (not shown). An annular shaped thermal choke 129 is formed around the tunnel 221 to block heat flow from the interior volume 115 through the opening 111 when the slit valve 128 is open.

[0016] The single substrate processing chamber 100 has a port 117 through the body 110 that is in fluid communication with a fluid circuit 190 that connects the gas panel 150, the condenser 160 and the port 117. The fluid circuit 190 has a gas conduit 192, a source conduit 157, an inlet isolation valve 155, an exhaust conduit 163 and an outlet isolation valve 165. Several heaters 196, 158, 152, 154, 164, 166 interface with various portions of the fluid circuit 190. Several temperature sensors 151, 153, 119, 167 and 169 are also located in various portions of the fluid circuit 190 to capture temperature measurements and send the information to the controller 180. The controller 180 uses the temperature measurement information to control the operation of the heaters 152 , 154 , 158 , 196 , 164 , and 166 so that the temperature of the fluid circuit 190 is maintained above the condensation point of the process fluid disposed in the fluid circuit 190 and the interior volume 115 .

[0017] The gas panel 150 is configured to supply pressurized processing fluid to the interior volume 115. The pressure of the processing fluid introduced into the interior volume 115 is monitored by a pressure sensor 114 coupled to the body 110. The condenser 160 is fluidly coupled to a cooling fluid source (not shown) and configured to condense the gas phase processing fluid exiting the interior volume 115 through the gas conduit 192. The condensed processing fluid is then removed by the pump 176. One or more heaters 140 are disposed in the body 110 and configured to heat the interior volume 115 of the single substrate processing chamber 100. The heaters 140, 152, 154, 158, 196, 164, and 166 maintain the processing fluid in the fluid circuit 190 in the gas phase, and an outlet isolation valve 165 to the condenser 160 is open to prevent condensation in the fluid circuit.

[0018] A controller 180 controls the operation of the single substrate processing chamber 100. The controller 180 controls the operation of the gas panel 150, the condenser 160, the pump 170, the inlet isolation valve 155, the outlet isolation valve 165, the power supplies 133 and 145. The controller 180 is also communicatively connected to the temperature sensor 116, the pressure sensor 114, the actuator 138, the cooling fluid supply 126, and the temperature reading devices 156 and 162.

[0019] The processing fluid may include oxygen-containing and / or nitrogen-containing gases, and / or chalcogen or tellurium (S, Se, Te, etc.) gases, or vapors of oxygen, dry steam, water, hydrogen peroxide, ammonia, S vapor, Se vapor, H2S, H2Se, etc. The processing fluid may react with metal materials on the substrate to form metal oxynitrides, metal oxides, metal oxychalcogenides, or metal chalcogenides. As an alternative to or in addition to the oxygen-containing and / or nitrogen-containing gases, the processing fluid may also include silicon-containing gases. Examples of silicon-containing gases include organosilicon, tetraalkyl orthosilicate gases, and disiloxanes. Organosilicon gases include gases of organic compounds having at least one carbon-silicon bond. Tetraalkyl orthosilicate gases include SiO4 4-Gases comprised of four alkyl groups associated with an ion are included. More specifically, the one or more gases may be selected from the group consisting of (dimethylsilyl)(trimethylsilyl)methane ((Me)3SiCH2SiH(Me)2), hexamethyldisilane ((Me)3SiSi(Me)3), trimethylsilane ((Me)3SiH), chlorotrimethylsilane ((Me)3SiCl), tetramethylsilane ((Me)4Si), tetraethoxysilane ((EtO)4Si), tetramethoxysilane ((MeO)4Si), tetrakis-(trimethylsilyl)silane ((Me3Si)4Si), (dimethylamino)dimethyl- Silane ((Me2N)SiHMe2), dimethyldiethoxysilane ((EtO)2Si(Me)2), dimethyl-dimethoxysilane ((MeO)2Si(Me)2), methyltrimethoxysilane ((MeO)3Si(Me)), dimethoxytetramethyl-disiloxane (((Me)2Si(OMe))2O), tris(dimethylamino)silane ((Me2N)3SiH), bis(dimethylamino)methylsilane ((Me2N)2CH3SiH), disiloxane ((SiH3)2O), and combinations thereof.

[0020] During processing of the substrate 120, the environment of the high pressure region 115 is maintained at a temperature and pressure that maintains the processing fluid in a vapor phase within the high pressure region. Such pressure and temperature are selected based on the composition of the processing fluid. In the case of water vapor, the temperature and pressure are maintained at conditions that maintain the water vapor in a dry vapor state. In one example, the high pressure region 115 is pressurized to a pressure greater than atmospheric pressure, for example, greater than about 2 bar. In another example, the high pressure region 115 is pressurized to a pressure between about 10 and about 50 bar, such as between about 20 and about 50 bar. In another example, the high pressure region 115 is pressurized to a pressure up to about 100 bar. During processing, the high pressure region 115 is also maintained at an elevated temperature, for example, a temperature greater than 225° C., such as between about 300° C. and about 500° C. (limited by the thermal budget of the substrates 155 placed in the cassette 150).

[0021] 2 is a schematic top view of an exemplary processing system 200 including one or more processing chambers, such as the processing chamber 100 shown in FIG 1, that are incorporated and integrated into the processing system. In one embodiment, the processing system 200 can be a Centura® or Endura® integrated processing system, commercially available from Applied Materials, Inc., Santa Clara, California. It is contemplated that other processing systems, including those from other manufacturers, can be adapted to benefit from the present disclosure.

[0022] The system 200 includes a vacuum-tight processing platform 204, a factory interface 202, and a system controller 244. The platform 204 includes a plurality of processing chambers 100, 212, 232, 228, 220, such as the one processing chamber 100 depicted in Figure 1, and at least one load lock chamber 222 coupled to a vacuum substrate transfer chamber 236. Two load lock chambers 222 are shown in Figure 2. The factory interface 202 is coupled to the transfer chamber 236 by the load lock chamber 222.

[0023] In one embodiment, the factory interface 202 includes at least one docking station 208 and at least one factory interface robot 214 to facilitate transferring substrates. The docking station 208 is configured to receive one or more Front Opening Unified Pods (FOUPs). Two FOUPs 206A-B are shown in the embodiment of FIG. 2. The factory interface robot 214, with a blade 216 disposed at one end of the robot 214, is configured to transfer substrates from the factory interface 202 to the processing platform 204 for processing via a load lock chamber 222. Optionally, one or more metrology stations 518 may be connected to an end 226 of the factory interface 202 to facilitate measuring substrates from the FOUPs 206A-B.

[0024] Each of the load lock chambers 222 has a first port coupled to the factory interface 202 and a second port coupled to the transfer chamber 236. The load lock chambers 222 are coupled to a pressure control system (not shown) that pumps down and vents the load lock chambers 222 to facilitate passing substrates between the vacuum environment of the transfer chamber 236 and the substantially ambient (e.g., atmospheric) environment of the factory interface 202.

[0025] A vacuum robot 230 is disposed in the transfer chamber 236. The vacuum robot 230 has a blade 234 capable of transferring substrates 224 between the load lock chamber 222, the metrology system 210, and the processing chambers 212, 232, 228, 220.

[0026] In one embodiment of the system 200, the system 200 may include one or more processing chambers 100, 212, 232, 228, 220, which may be annealing chambers (e.g., high pressure annealing chambers, RTP chambers, laser annealing chambers), deposition chambers, etch chambers, cleaning chambers, curing chambers, or other similar types of semiconductor processing chambers. In some embodiments of the system 200, at least one of one or more of the processing chambers 100, 212, 232, 228, 220, the transfer chamber 236, the factory interface 202, and / or the load lock chamber 222.

[0027] A system controller 244 is coupled to the processing system 200. The system controller 244, which may include or be contained within the computing device 201, controls the operation of the processing system 200 with direct control of the processing chambers 100, 212, 232, 228, 220 of the system 200. Alternatively, the system controller 244 may control a computer (or controller) associated with the processing chambers 100, 212, 232, 228, and the system 200. During operation, the system controller 244 also allows for data collection and feedback from the respective chambers to optimize the operation of the system 200.

[0028] The system controller 244, much like the computing device 201 described above, generally includes a central processing unit (CPU) 238, memory 240, and support circuits 242. The CPU 238 may be any form of general-purpose computer processor that can be used in an industrial environment. The support circuits 242 are conventionally coupled to the CPU 238 and may include cache, clock circuits, input / output subsystems, power supplies, etc. Software routines turn the CPU 238 into an application-specific computer (controller) 244. The software routines may be stored and / or executed by a second controller (not shown) located remotely from the system 200.

[0029] FIG. 3 depicts an example of a TFT device 350 including a metal-containing layer that can be subjected to a thermal annealing process in a high pressure annealing chamber, such as the high pressure annealing process 100 depicted in FIG. 1 that can be incorporated into the system 200 depicted in FIG. 2. The thin film transistor device structure 350 is a bottom gate TFT structure disposed on a substrate 301. It should be noted that the substrate 301 can have different combinations of films, structures or layers pre-formed thereon to facilitate the formation of different device structures or different film stacks on the substrate 301. In one example, the substrate 301 can have the device structure 350 formed thereon, as shown in FIG. 3. Alternatively, the substrate 301 can have another device structure 450 disposed thereon, as further shown in FIG. 4, which will be further described below. The substrate 301 can be any one of a glass substrate, a plastic substrate, a polymer substrate, a metal substrate, a single substrate, a roll-to-roll substrate, or other suitable transparent substrate suitable for forming thin film transistors.

[0030] A gate electrode layer 302 is formed and patterned on a substrate 301, followed by a gate insulator layer 304. In one embodiment, the gate electrode layer 302 can be made of any suitable metal material, such as aluminum (Al), tungsten (W), chromium (Cr), tantalum (Ta), molybdenum (Mo), copper (Cu), or combinations thereof. Suitable materials for the gate insulator layer 304 include silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and the like. It is noted that the thin film transistor device structure 350 depicted in FIG. 3 is a bottom-gate device structure, in which the gate electrode layer 302 is formed at the bottom of the device structure 350.

[0031] An active layer 306 is formed on the gate insulator layer 304. The material utilized for the active layer 306 can be selected from transparent metal oxide materials with high electron mobility, suitable low temperature fabrication allowing flexible substrate materials such as plastic materials to be processed at low temperatures without substrate damage. Examples of suitable materials that can be utilized for the active layer 306 include a-IGZO (amorphous indium gallium zinc oxide), InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuBO2, CuAlO2, CuGaO2, SrCuO, LaCuOS, GaN, InGaN, AlGaN, or InGaAlN, among others.

[0032] After the active layer 306 is formed, a barrier layer 308 can be formed on the active layer 306. The barrier layer 308 can be formed from a metal-containing material to provide good interfacial adhesion as well as good barrier properties (e.g., diffusion barrier) to the metal electrode layer 310 (e.g., for source-drain electrodes) that is then formed thereon. The barrier layer 308 can be patterned to form a desired pattern on the active layer 306 to facilitate transfer of the features to a film layer disposed on the substrate 301 in a subsequent etching process. It is noted that while the barrier layer 308 depicted in FIG. 3 is patterned to a desired pattern, the barrier layer 308 can be of any shape, including the entire continuous blank film of the device structure 350, or any different features as needed, so long as the barrier layer 308 can effectively provide blocking / diffusion barrier properties to prevent diffusion of components from the active layer 306 into the metal electrode layer 310 or vice versa. In one embodiment, the barrier layer 308 may be a single layer of a metal-containing dielectric layer, as depicted in Figure 3, fabricated with a metal dielectric layer such as Ta2O5 or TiO2, or with any suitable metal dielectric layer as desired. In another embodiment, the barrier layer 308 may be in the form of a composite film as desired.

[0033] After a metal electrode layer 310, such as a source-drain metal electrode layer, is disposed on the barrier layer 308, an etching process is then performed to form a channel 320 in the metal electrode layer 310. After etching, an insulating material layer 314, such as a passivation layer, is then formed on the metal electrode layer 310 to complete the process of forming the thin film transistor device structure 350.

[0034] In one embodiment, examples of materials that can be used for the metal electrode layer 310 include copper (Cu), gold, silver (Ag), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), alloys thereof, and combinations thereof. Suitable materials that can be used for the insulating material layer 314 include silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), or the like.

[0035] 4 depicts an example of a top-gate low temperature polysilicon (LTPS) TFT device structure 450 formed on a substrate 301 rather than the bottom-gate device structure 350 depicted in FIG. The LTPS TFT device 450 is a MOS device constructed with an active layer 452 including a source region 409a, a channel region 408, and a drain region 409b (also referred to as, for example, metal contact regions or source-drain metal contacts) formed on an optically transparent substrate 301 with or without an optional insulating layer 404 disposed thereon. In one example, the active layer including the source region 409a, the channel region 408, and the drain region 409b can be fabricated from a transparent metal-containing layer, such as a metal oxide material with high electron mobility, which is a suitable low-temperature fabrication that allows flexible substrate materials, such as plastic materials, to be processed at low temperatures without substrate damage. Suitable examples of such materials that can be utilized for the source region 409a, the channel region 408, and the drain region 409b include a-IGZO (amorphous indium gallium zinc oxide), doped IGZO, InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuBO2, CuAlO2, CuGaO2, SrCuO, LaCuOS, GaN, InGaN, AlGaN, or InGaAlN, among others.

[0036] A gate insulating layer 406 is then deposited on top of the deposited polysilicon layer to separate the barrier layer 411 and a metal electrode layer 414, such as a gate electrode, disposed thereon from the channel region 408, the source region 409a, and the drain region 409b. The barrier layer 411 can be formed from a metal-containing material to provide good interfacial adhesion as well as good barrier properties (e.g., diffusion barrier) for the metal electrode layer 414 (e.g., gate electrode) subsequently formed thereon. The barrier layer 411 can be patterned to form a desired pattern on the gate insulating layer 406 to facilitate feature transfer to a film layer disposed on the substrate 102 in a subsequent etching process. The barrier layer 411 can effectively provide blocking / diffusion barrier properties that prevent diffusion of components from the gate insulating layer 406 into the metal electrode layer 414 or vice versa. In one embodiment, the barrier layer 411 can be a single layer of a metal-containing dielectric layer, as depicted in Figure 4, fabricated with a metal dielectric layer such as Ta2O5 or TiO2, or with any suitable metal dielectric layer as desired. In another embodiment, the barrier layer 411 can be in the form of a composite film as desired.

[0037] A gate electrode layer 414 is formed on top of the gate insulating layer 406 with a barrier layer 411 between them. The gate insulating layer 406 is also commonly known as a gate oxide layer since it is typically made of a silicon dioxide (SiO2) layer. Next, an insulating material layer 412, such as an interlayer insulator, and device connections (not shown) are made through the insulating material layer 412 to allow control of the TFT device.

[0038] After the insulating material layer 412 is formed, the source-drain metal electrode layers 410a, 410b are then deposited, formed and patterned on the insulating material layer 412. After the source-drain metal electrode layers 410a, 410b are patterned, a passivation layer 418 is then formed over the source-drain metal electrode layers 410a, 410b.

[0039] FIG. 5 illustrates a flow diagram of one example of a thermal annealing process 500 that may be performed on a metal-containing layer, such as the active layer 306, 452 of FIGS. 3-4, or the metal electrodes 302, 310, 410a, 410b, 414 of FIGS. 3-4, respectively.

[0040] The method 500 begins in operation 502 by providing a substrate, such as the substrate 301 of Figures 3 and 4. The substrate 301 may be an optically transparent substrate. The substrate 301 may include a material layer 601 disposed thereon, as shown in Figure 6A. The material layer 601 may be a single layer or multiple layers that may be utilized to form a TFT device structure. Alternatively, the material layer 601 may be a structure that may include multiple materials that may be utilized to form a TFT device structure.

[0041] The substrate 301 further includes a metal-containing layer 602 formed on the material layer 601, as shown in FIG. 6B. In examples where the material layer 601 is not present, the metal-containing layer 602 can be formed directly on the substrate 301. In some examples, the metal-containing layer 602 can be used as the active layer 306, 452 of FIG. 3 or FIG. 4, or the metal electrodes 302, 310, 410a, 410b, 414 of FIG. 3-4. In one example, the metal-containing layer 602 is a metal oxide layer selected from the group consisting of a-IGZO (amorphous indium gallium zinc oxide), doped IGZO, InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuBO2, CuAlO2, CuGaO2, SrCuO, LaCuOS, GaN, InGaN, AlGaN, or InGaAlN, etc. In one example, the metal-containing layer 602 is an IGZO layer or a doped IGZO layer. Alternatively, the metal-containing layer 602 can be a metal layer, such as copper (Cu), gold, silver (Ag), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or alloys thereof.

[0042] In operation 504, an optional ion doping / implantation process is performed to implant ions into the metal-containing layer 602 to form the doped metal-containing layer 610 shown in FIG. 6C. In an example where the ion implantation process is omitted, a thermal annealing process of operation 506, described in more detail below, may be performed directly on the metal-containing layer 602. The ion doping / implantation process is performed to dope, coat, treat, implant, insert or modify specific film / surface properties at specific locations of the metal-containing layer 602 in which the dopants are formed to form the doped metal-containing layer 610. The ion doping / implantation process utilizes incident ions to modify the film / surface properties of the metal-containing layer 602, forming the doped metal-containing layer 610 with the dopants doped into the metal-containing layer 602. The ion doping / implantation process may be performed in any suitable ion implantation / doping processing tool. Ions containing the desired type of atoms may be doped into the metal-containing layer 602 at the desired concentration. The ions doped into the metal-containing layer 602 can modify the film / surface properties of the metal-containing layer 602 to affect, improve, or change the lattice structure, degree of crystallinity, bonding structure, or film density of the metal-containing layer 602 to form a doped metal-containing layer 610.

[0043] In embodiments in which the metal-containing layer 602 comprises InGaZnO, the ions doped into the metal-containing layer 602 may include indium (In) or molybdenum (Mo), gallium (Ga), zinc (Zn), etc. It is believed that the In or Mo dopants doped into the metal-containing layer 602 (e.g., InGaZnO) alter the electrical properties, such as high mobility, crystallinity (e.g., from an amorphous structure, a c-axis oriented crystal structure (CAAC), a polycrystalline structure, or even a single crystal structure) of the InGaZnO material, thereby resulting in a doped metal-containing layer 610 with desired film properties. For example, the high crystallinity provided by the In or Mo dopants of the InGaZnO material is believed to increase the electron mobility of the film properties, thereby improving the electrical performance of the TFT device structure or semiconductor device when the doped metal-containing layer 610 is utilized.

[0044] In addition, it is believed that the ratio of gallium (Ga) and zinc oxide (ZnO) in the InGaZnO material may also affect the resulting lattice structure of the doped metal-containing layer 610. It is believed that the ratio of Ga component in the InGaZnO material may increase the film transparency as well as the overall film band gap. The ratio of Zn or ZnO component in the InGaZnO material may improve the mobility and ease the thermal annealing temperature requirement for crystallinity improvement. Therefore, the desired crystallinity of the InGaZnO material can be obtained by selecting the appropriate dose of In dopant in the InGaZnO material. In addition, the desired crystallinity of InGaZnO also helps ease the temperature requirement of the thermal annealing process in the subsequent operation 506, which provides a process advantage in the application of TFT devices since the substrate 301 is often an optically transparent material with a relatively low thermal cycle budget.

[0045] In one embodiment, the resulting In dopants in the InGaZnO material are approximately 8.5×10 15 ions / cm 2 Approximately 5 × 10 15 ions / cm 2 From about 9 × 10 15 ions / cm 2 Additionally, the proportion of In or Mo components in the InGaZnO material can be increased from about 10%-13% to about 14%-16% by atomic weight (an increase of between about 15% and about 30%).

[0046] Several process parameters can be controlled during the ion doping / implantation process. The ion doping / implantation process can be performed by supplying an ion doping gas mixture with a desired amount of power energy to an ion doping / implantation tool to dope ions from the ion doping gas mixture into the substrate 301. The ion doping gas mixture can be supplied to the ion doping / implantation tool at a flow rate between about 10 sccm and about 1000 sccm. Suitable components for supplying ion doping used in vapor phase during implantation include indium vapor and molybdenum vapor. RF power, such as capacitive or inductive RF power, DC power, electromagnetic energy, ion beam, or magnetron sputtering can be supplied to the ion doping / implantation process to help dissociate the ion doping gas mixture during processing. Ions generated by the dissociation energy can be accelerated toward the substrate using an electric field created by applying a DC or RF electrical bias to the substrate support, or to a gas inlet above the substrate support, or both. In some embodiments, the gas containing energetic ions can be a plasma. An energy of between about 20 keV and about 80 kev, for example about 45 keV, such as between about 35 kev and about 55 keV, may be used to implant ions into the metal-containing layer 602. The substrate temperature may be controlled to between about 5° C. and about 50° C., such as about 15° C.

[0047] In operation 506, a high pressure annealing process is performed. The annealing process performed at a high process pressure, such as greater than but less than 2 bar, can help densify and repair vacancies in the doped metal-containing layer 610 to form an annealed metal-containing layer 603 with desired film properties, as shown in FIG. 6D. In some examples, the high process pressure can be up to 100 bar. In embodiments where an ion doping / implantation process is not performed in operation 504, a high pressure annealing process can be performed on the metal-containing layer 602 of FIG. 6B to form an annealed metal-containing layer 603, as shown in FIG. 6D. The annealing process can be performed in a processing chamber, such as the processing chamber 100 depicted in FIG. 1, or in other suitable processing chambers, including those that process substrates one at a time.

[0048] In the high pressure annealing process performed in operation 506, the process pressure is maintained in a high pressure region in the vapor phase, e.g., in a dry vapor phase with substantially no liquid droplets present. The process pressure and temperature are controlled to densify the film structure to repair film defects, remove impurities, and increase film density. In one example, the high pressure region 115 is pressurized to a pressure greater than atmospheric pressure, e.g., greater than about 2 bar. In another example, the high pressure region 115 is pressurized to a pressure of about 5 to about 100 bar, such as about 5 to about 50 bar, such as about 35 bar. This high pressure can effectively help densify the film structure, so that a relatively low temperature, such as less than 500° C., reduces the possibility of thermal cycling damage to the substrate 301.

[0049] During processing, the high pressure region 115 is maintained at a relatively low temperature, for example, less than 500° C., such as between about 150° C. and about 350° C., by a heater 122 disposed within the outer chamber 110. Hence, a low thermal budget to the substrate can be obtained by utilizing the high pressure annealing process in conjunction with a low temperature regime.

[0050] It is believed that the high pressure process provides a driving force to remove dangling bonds of the metal-containing layer 602 or the doped metal-containing layer 610, so that the dangling bonds of the metal-containing layer 602 may be repaired, reacted, and saturated during the annealing process. In one example, an oxygen-containing gas, such as O3 gas, O2 gas, air, H2O, H2O2, N2O, NO2, CO2, CO, and dry steam, or chalcogen vapor, including sulfur (S) vapor and selenium (Se) vapor, or tellurium vapor or other suitable gas, may be provided during the annealing process. In one particular example, the oxygen-containing gas includes water vapor, e.g., dry steam, and / or air. During the annealing process, the oxygen component from the oxygen-containing gas may penetrate into the metal-containing layer 602, change the bond structure, and remove atomic vacancies therein, thereby densifying and strengthening the lattice structure and increasing the crystallinity of the metal-containing layer 602. In some examples, an inert or carrier gas, such as Ar, N2, He, Kr, etc., may be supplied along with the oxygen-containing gas. In one embodiment, the oxygen-containing gas supplied to the oxygen-containing gas mixture is dry steam supplied at a pressure greater than 2 bar.

[0051] In one exemplary implementation, the process pressure is adjusted to a pressure greater than 2 bar, such as between about 25 bar and 75 bar, such as between about 35 bar, such as between 5 bar and 100 bar, such as between 20 bar and about 80 bar. The process temperature can be controlled to be greater than 150° C. but less than 500° C., such as between about 180° C. and about 400° C., such as between about 150° C. and about 380° C. In one example, chalcogen vapor, such as sulfur (S) vapor, selenium (Se) vapor, etc., may be provided during the annealing process of metal oxychalcogens, such as InGaZnO, that contain S or Se.

[0052] After the high pressure annealing process, the metal-containing layer 602 or the doped metal-containing layer 610 has a densified film structure, which is relatively robust with an amorphous morphology that realizes high film density, high film mobility, low carrier concentration, and low film resistance, compared to the metal-containing layer 602 or the doped metal-containing layer 610 annealed by a conventional annealing process at a pressure of about 1 atmosphere, both annealing processes being at the same annealing temperature. In one example, compared to the conventional annealing process at 1 atmosphere, the mobility of the high pressure annealed metal-containing layer 603 with indium dopant (formed from the doped metal-containing layer 610) increases between about 5 times and about 20 times, the resistance increases about 10 times, and the carrier concentration decreases about 100 times, but at the same annealing temperature.

[0053] In one example, compared to a conventional annealing process at 1 atmosphere pressure, the mobility of the high pressure annealed metal-containing layer 603 without the indium dopant (formed from the metal-containing layer 602) increases by between about 1.5 times and about 5 times, the resistivity increases by about 20 percent to about 99 percent, and the carrier concentration decreases by about 100 times at the same annealing temperature.

[0054] Thus, a method for thermally annealing a metal-containing layer is provided. The metal-containing layer can be thermally treated / annealed by a high pressure annealing process using a high process pressure, such as more than 2 bar but less than 50 bar. By utilizing such a high pressure annealing process, the process temperature can be kept below 500° C., thereby reducing the thermal budget imposed on the substrate on which the metal-containing layer is formed, and good film quality with desired crystallinity and structure integration control can be achieved.

[0055] While the forgoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, the scope of the invention being determined by the appended claims.

Claims

1. 1. A method of forming a metal-containing layer on a substrate, comprising the steps of: providing an oxygen-containing gas mixture to a substrate in a processing chamber, the substrate including a metal-containing layer disposed on an optically transparent substrate; maintaining the oxygen-containing gas mixture in the processing chamber at a process pressure between 2 bar and 50 bar; and thermally annealing the metal-containing layer in the presence of the oxygen-containing gas mixture.

2. The method of claim 1 , wherein the step of supplying the oxygen-containing gas mixture further comprises maintaining a substrate temperature below 400° C.

3. The oxygen-containing mixed gas is O 3 Gas, O 2 Gas, H 2 O, H 2 O 2 , N 2 O, NO 2 , CO 2 2. The method of claim 1, further comprising at least one oxygen-containing gas selected from the group consisting of CO, air, and dry steam.

4. The method of claim 1 , wherein the oxygen-containing gas mixture comprises dry steam or air.

5. The method of claim 1 , wherein the process pressure is between about 5 bar and 100 bar.

6. The method of claim 1 , wherein the metal-containing layer is a metal oxide layer.

7. The metal oxide layer is selected from a-IGZO (amorphous indium gallium zinc oxide), doped IGZO, InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuBO 2 , CuAlO 2 ,CuGaO 2 , SrCuO, LaCuOS, GaN, InGaN, AlGaN and InGaAlN.

8. The method of claim 1 , further comprising the step of implanting a dopant into the metal-containing layer prior to the step of providing the oxygen-containing gas mixture.

9. The method of claim 8 , wherein the dopant implanted into the metal-containing layer comprises indium or molybdenum.

10. The method of claim 9 , wherein the dopant implanted into the metal-containing layer enhances the crystallinity of the metal-containing layer.

11. The method of claim 1 , wherein the metal-containing layer is an active layer of a TFT device structure.

12. The method of claim 1 , wherein the metal oxide layer is InGaZnON.

13. The method of claim 1 , wherein the metal-containing layer is an electrode of a TFT device structure.

14. The method of claim 1 , wherein the metal-containing layer has high mobility after the thermal annealing step.

15. The method of claim 1 , wherein the metal-containing layer has a higher film density after the thermal annealing step.

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