Imaging device

Abstract

To provide a three-dimensionally integrated imaging device.SOLUTION: A first structure including a transistor having silicon as an active layer or active region and a second structure including a transistor having an oxide semiconductor as an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, a three-dimensionally integrated imaging device is formed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, etc. device, power storage device, storage device, imaging device, operation method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] Oxide semiconductors have been attracting attention as a semiconductor material that can be used in transistors. Transistors are made using zinc oxide or In-Ga-Zn oxide semiconductors as the oxide semiconductor. Techniques for producing such a capacitor have been disclosed (see Patent Documents 1 and 2).

[0005] In addition, an imaging device in which a transistor including an oxide semiconductor is used as part of a pixel circuit is It is disclosed in patent document 3.

[0006] In addition, a transistor including silicon, a transistor including an oxide semiconductor, and a crystal Patent Document 4 discloses an imaging device having a structure in which photodiodes each having a conductive silicon layer are stacked. It is being done. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2011-119711 A [Patent Document 4] JP 2013-243355 A Summary of the Invention [Problem to be solved by the invention]

[0008] In semiconductor integrated circuits, while there is a demand for higher density and capacity, there is also a demand for miniaturization. There is a shift from integration to three-dimensional integration.

[0009] Three-dimensional integration can complicate the fabrication process, but the materials and design rules for each layer are This will increase the degree of freedom required for high-performance semiconductor integration, which is difficult to achieve with two-dimensional integration. A circuit can be created.

[0010] Therefore, an object of one aspect of the present invention is to provide a three-dimensionally integrated imaging device. One of the objects of the present invention is to provide an imaging device capable of driving pixels in a divided manner. One of the objects of the present invention is to provide an imaging device that can be made compact. Another object of the present invention is to provide an imaging device capable of capturing an image without any distortion. One of the objects of the present invention is to provide an imaging device suitable for high speed operation. Another object of the present invention is to provide an imaging device capable of imaging under low illumination. Another object of the present invention is to provide an imaging device that can be used in a wide temperature range. One of the objects of the present invention is to provide an imaging device having a high aperture ratio. Another object of the present invention is to provide an imaging device with high reliability. Another object is to provide a novel imaging device or the like.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention relates to an imaging device having a layered structure.

[0013] One aspect of the present invention is an imaging device having a first layer, a second layer, and a third layer, The second layer is provided between the first layer and the third layer, and the first layer has a photoelectric conversion element. The second layer includes a first transistor having an oxide semiconductor as an active layer, a first insulating layer, and The first metal layer and the third layer are the second transistors having silicon as the active layer or region. a first insulating layer and a second metal layer, the first metal layer and the second metal layer being The first metal layer has a region embedded in the first insulating layer. The second metal layer has a region buried in the second insulating layer, and the first metal layer is a second metal. the first insulating layer has an area bonded to the metal layer, the first insulating layer has an area bonded to the second insulating layer, The first transistor and the second transistor have upper surfaces of the gate electrodes facing each other. The photoelectric conversion element is electrically connected to the first transistor. The first transistor is electrically connected to the first metal layer, and the second transistor is electrically connected to the second metal layer. The imaging device is characterized in that the imaging devices are electrically connected to each other.

[0014] The second layer includes a third n-ch transistor having an oxide semiconductor as an active layer, and and a third metal layer, the third layer being a p-ch type semiconductor having a silicon active layer or region. a fourth transistor having a third metal layer and a fourth metal layer, The third metal layer has a region embedded in the first insulating layer. The fourth metal layer has a region buried in the second insulating layer, and the third metal layer has a fourth metal. a third transistor and a fourth transistor, the third transistor and the fourth transistor being connected to each other; The upper surfaces of the gate electrodes are arranged to face each other, and the third transistor is formed of a third metal layer and the fourth transistor is electrically connected to the fourth metal layer; It can also be done like this.

[0015] Another embodiment of the present invention is an imaging device including a first layer, a second layer, and a third layer. The second layer is provided between the first layer and the third layer, and the first layer is a photoelectric conversion layer. The device has a third insulating layer and a fifth metal layer, and the second layer is an oxide semiconductor as an active layer. a fourth insulating layer, and a sixth metal layer; a second transistor having the first metal layer and the second metal layer as an active layer or region; The first metal layer is mainly composed of the same metal element, and the fifth metal layer is embedded in the third insulating layer. the sixth metal layer has a region embedded in the fourth insulating layer; and the fifth metal layer has a region embedded in the fourth insulating layer. The third insulating layer has an area bonded to the fourth insulating layer. a first transistor having a first metal layer and a second metal layer, the first transistor being electrically connected to the fifth metal layer; The second transistor is electrically connected to the fifth metal layer and is electrically connected to the first transistor. The imaging device is characterized in that it is connected to

[0016] The metal element is preferably Cu, Al, W or Au.

[0017] The oxide semiconductor contains In, Zn, and M (M is Al, Ga, Y, or Sn). is preferred. Effect of the Invention

[0018] By using one embodiment of the present invention, a three-dimensionally integrated imaging device can be provided. It is possible to provide an imaging device capable of driving pixels in a divided manner. Alternatively, it is possible to provide an imaging device capable of capturing an image with less noise. Alternatively, an imaging device suitable for high speed operation can be provided. Alternatively, it is possible to provide an imaging device with high resolution. Alternatively, it is possible to provide an imaging device capable of imaging under low illumination. It is possible to provide an imaging device that can be used in a wide temperature range. Alternatively, it is possible to provide an imaging device having a high aperture ratio. Alternatively, a highly reliable imaging device can be provided. We can provide facilities, etc.

[0019] Note that the effects of one embodiment of the present invention are not limited to these. In some cases or depending on the situation, the above effects may be different. Alternatively, for example, one aspect of the present invention may be, in some cases, or depending on the situation, In some cases, these effects may not be present. [Brief description of the drawings]

[0020] [Figure 1] 1A and 1B are a diagram and a circuit diagram illustrating a pixel of an imaging device. [Diagram 2] 2A and 2B are diagrams illustrating pixels of an imaging device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 4] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Diagram 5] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 6] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 7] FIG. 3 is a cross-sectional view illustrating a connection form of photoelectric conversion elements. [Figure 8] 1A and 1B are cross-sectional views illustrating a configuration of an imaging device and a connection mode of photoelectric conversion elements. [Figure 9] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 10] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 11] 3A to 3C illustrate a manufacturing process of an imaging device. [Figure 12] 3A to 3C illustrate a manufacturing process of an imaging device. [Figure 13] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 14] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 15]1A is a block diagram illustrating an imaging device, a circuit diagram of a CDS circuit, and a block diagram of an A / D conversion circuit. [Figure 16] 1A and 1B are a top view and a perspective view illustrating a configuration of an imaging apparatus. [Figure 17] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 18] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 19] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 20] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 21] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 22] 4 is a timing chart illustrating the operation of the imaging apparatus. [Figure 23] FIG. 2 is a circuit diagram illustrating a pixel. [Figure 24] 1A and 1B are diagrams illustrating a curved imaging device. [Diagram 25] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 26] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 27] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 28] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Figure 29] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Diagram 30] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 31] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 32] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Diagram 33] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Diagram 34] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 35] FIG. 1 is a top view illustrating a transistor. [Diagram 36] 1A and 1B are diagrams illustrating the range of atomic ratios of oxide semiconductors. [Figure 37] A diagram explaining the InMZnO4 crystal. [Figure 38] FIG. 1 is a band diagram of a stacked structure of oxide semiconductors. [Figure 39] 1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Diagram 40] Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Diagram 41] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Diagram 42] Cross-sectional TEM image of a-like OS. [Diagram 43] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Diagram 44] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Diagram 45] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Diagram 46] 1A to 1C are diagrams illustrating electronic devices. [Figure 47] External photograph and X-ray image of the X-ray imaging panel. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0022] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "the first" should not be changed to "the second" or "the third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. and the ordinal numbers used to identify an aspect of the invention may not match.

[0023] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0024] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0025] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0026] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0027] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (D / A conversion circuits, A / D conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (Power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.) voltage sources, current sources, switching circuits, amplifier circuits (which output large signal amplitudes or current amounts, etc.) (common circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal One or more circuits (generator, memory, control circuit, etc.) can be connected between X and Y. For example, even if there is another circuit between X and Y, the output from X is If a signal is transmitted to Y, then X and Y are said to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected, and cases where X and Y are functionally connected. and Y are electrically connected.

[0028] In addition, if it is explicitly stated that X and Y are electrically connected, When X and Y are electrically connected (i.e., there is another element or circuit between X and Y), When X and Y are functionally connected (i.e., when X and Y are (X and Y are connected functionally with another circuit between them) and (X and Y are connected directly (That is, when X and Y are connected without any other element or circuit between them.) ) is considered to be disclosed in the present specification. If it is explicitly stated, it is simply stated as connected. The same contents as those in the above case are deemed to be disclosed in the present specification and the like.

[0029] For example, if the source (or the first terminal, etc.) of the transistor is connected to the ), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y through (or without) Z2, or the transistor The source (or first terminal, etc.) of Z1 is directly connected to a part of Z1 and another part of Z1. is directly connected to X, and the drain (or second terminal, etc.) of the transistor is connected to In the case where a part of Z1 is directly connected to Y and another part of Z2 is directly connected to Y, It can be expressed as follows.

[0030] For example, "X and Y and the source (or first terminal, etc.) and drain (or The second terminal, etc., of the transistor are electrically connected to each other, and X, the source of the transistor (or (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and then Y. "The source of the transistor is electrically connected to the (or the first terminal, etc.) is electrically connected to X, and the drain (or The second terminal, etc.) is electrically connected to Y, and the source (or first terminal) of the transistor, The transistor's drain (or second terminal, etc.), and Y are electrically connected in that order. "X is connected to the source ( or the first terminal, etc.) and the drain (or the second terminal, etc.) X is the source (or first terminal, etc.) of the transistor, and The second terminal (or terminal 2, etc.), Y, is provided in this connection order. Using the same expressions as these examples, the order of connections in a circuit configuration can be regulated. By defining the source (or first terminal, etc.) and drain (or The technical scope can be determined by distinguishing between the first terminal and the second terminal.

[0031] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor" ) is electrically connected to X through at least a first connection path, and the first connection path does not have a second connection path, and the second connection path is a The source (or first terminal, etc.) of the transistor and the drain (or second The first connection path is a path via Z1, and the second connection path is a path between the The drain (or second terminal, etc.) of the transistor is connected to the Y, the third connection path does not have the second connection path, and The third connection path is a path via Z2." or " The source (or first terminal, etc.) of the transistor is connected to the , electrically connected to X via Z1, and the first connection path has a second connection path the second connection path has a connection path passing through a transistor, The drain (or second terminal, etc.) of and the third connection path does not include the second connection path. "The source (or first terminal) of the transistor is etc.) is electrically connected to X through Z1 by at least a first electrical path; The first electrical path does not have a second electrical path, and the second electrical path is The source (or first terminal, etc.) of a transistor is connected to the drain (or third terminal, etc.) of a transistor. 2) and the drain (or second terminal, etc.) of the transistor. ) is electrically connected to Y through Z2 by at least a third electrical path, The third electrical path does not have a fourth electrical path, and the fourth electrical path is a The drain (or second terminal, etc.) of a transistor is connected to the source (or first terminal, etc.) of a transistor. The electrical path to the terminal of the By using the current method, the connection paths in the circuit configuration are defined, and the transistor Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of The technical scope can be determined based on the above.

[0032] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0033] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The function of both components is combined with the function of the electrode. Electrical connection means that one conductive film has the functions of multiple components. cases are also included in this category.

[0034] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0035] Generally, potential (voltage) is relative, and the magnitude is relative to a reference potential. The size is determined by the distance between the ground and the ground. Even if it is stated, it does not necessarily mean that the potential is 0 volts. For example, "ground" or "GND" may be defined based on the lowest potential in the circuit. Or, define "ground" or "GND" based on the midpoint of the circuit potential. In such cases, positive and negative potentials are defined based on that potential. This results in:

[0036] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0037] In one embodiment of the present invention, a first structure and a second structure are fabricated, and then the first The structure and the second structure are bonded together to bond the metal layers of each structure. The present invention relates to a configuration and a manufacturing method for an imaging device that is three-dimensionally integrated by using a plurality of semiconductor devices.

[0038] The first structure includes a transistor having an active layer or active region made of silicon, and a The semiconductor device may include a first metal layer electrically connected to the first insulating layer.

[0039] The second structure includes a photoelectric conversion element, a transistor having an oxide semiconductor as an active layer, and a The second metal layer electrically connected to the transistor and the second insulating layer may be included. Cut.

[0040] Alternatively, the first structure may be a first transistor having an active layer or active region made of silicon. a second transistor having an oxide semiconductor as an active layer; The second structure includes a third metal layer connected to the photoelectric conversion element and a third insulating layer. A fourth metal layer electrically connected to the photoelectric conversion element and a fourth insulating layer are included. Good too.

[0041] In addition, the first structure, the second structure, and the third structure may be bonded together. can.

[0042] In this case, the first structure includes a transistor having an active layer or active region made of silicon and a The semiconductor device includes a first metal layer electrically connected to the transistor and a first insulating layer. The second structure includes a transistor having an oxide semiconductor as an active layer, and a second metal layer electrically connected to the stator, a third metal layer, a second insulating layer, and a third insulating layer. The third structure may include a photoelectric conversion element and a layer. and a fourth insulating layer.

[0043] The off-state current of the transistor having the oxide semiconductor as an active layer is small, and the off-state current of the transistor is small. The memory for holding data can be easily configured.

[0044] FIG. 1A is a schematic cross-sectional view of a pixel 20 included in an imaging device of one embodiment of the present invention. FIG. 1B is a circuit diagram of the pixel 20. Note that in FIGS. An example in which the transistor is an n-ch type will be shown, but one embodiment of the present invention is not limited to this. The transistor may be replaced with a p-ch transistor.

[0045] In the pixel 20, one electrode of the photoelectric conversion element PD is connected to the source of the transistor 41 or The other of the source and drain of the transistor 41 is electrically connected to the other of the source and drain of the transistor 41. is electrically connected to one of the source and drain of the transistor 42. The other of the source and drain of the transistor 41 is electrically connected to the gate of the transistor 43. One of the source and drain of the transistor 43 is connected to the source or drain of the transistor 44. is electrically connected to one of the drains.

[0046] Here, the other of the source or drain of the transistor 41 and the source or drain of the transistor 42 A node FD to which the drain of the transistor 41 or the gate of the transistor 42 is connected is used as a charge detection unit. As shown in FIG. 20A, a capacitance element is connected to the node FD. This is also fine.

[0047] In FIG. 1(A) and (B), the other electrode of the photoelectric conversion element PD is connected to a wiring 71 (VPD). The other of the source and the drain of the transistor 42 is electrically connected to a wiring 72 (V The other of the source and the drain of the transistor 43 is electrically connected to a wiring The other of the source and drain of the transistor 44 is electrically connected to 73 (VPI). is electrically connected to the wiring 91 (OUT1).

[0048] In addition, the elements (transistors, photoelectric conversion elements, etc.) shown in Figure 1 (A) and (B) and the wiring The above connection form is an example. Each element may be electrically connected to a different wiring, or multiple elements may be connected to the same wiring. In some cases, the elements are electrically connected to the same wiring.

[0049] The wiring 71 (VPD), the wiring 72 (VRS), and the wiring 73 (VPI) serve as power supply lines. For example, the wiring 71 (VPD) can function as a low-potential power supply line. The wiring 72 (VRS) and the wiring 73 (VPI) are high-potential power supply lines. It can be made to function.

[0050] The gate of the transistor 41 is electrically connected to the wiring 61 (TX). The gate of the transistor 44 is electrically connected to the wiring 62 (RS). It is electrically connected to the wiring 63 (SE).

[0051] The wiring 61 (TX), the wiring 62 (RS), and the wiring 63 (SE) are connected to each other. It can function as a signal line that controls the conduction of a transistor.

[0052] The transistor 41 is a transistor for transferring the potential of the cathode of the photoelectric conversion element PD to the node FD. The transistor 42 can function as a transistor that can adjust the potential of the node FD The transistor 43 can function as a reset transistor. It can function as a transistor to output corresponding to the potential of node FD. The transistor 44 functions as a transistor for selecting the pixel 20. can be done.

[0053] The above-described configuration of the pixel 20 is merely an example. In some cases, the capacitance element or some of the wirings may not be included. In some cases, the circuit may include a transistor, a capacitor, a wiring, etc. The topology may differ from the above configuration.

[0054] As shown in FIG. 1A, an imaging device according to one embodiment of the present invention includes a layer 1100, a layer 1200, and a It has a layer 1300.

[0055] The layer 1100 may have a photoelectric conversion element PD. For example, a two-terminal photodiode can be used. Examples of these include pn-type photodiodes using single crystal silicon substrates, amorphous silicon thin films, and Crystalline silicon thin film or polycrystalline silicon thin film pin type photodiode, selenium Alternatively, a photodiode using a selenium compound or an organic compound may be used. can.

[0056] Layer 1200 may include transistor 41 and transistor 42. The transistors 41 and 42 are transistors having an oxide semiconductor as an active layer (hereinafter In addition, the layer 1200 is preferably made of a transistor 41. and one of the source or drain of transistor 42. It has a metal layer 401b for electrical connection.

[0057] The OS transistor has an extremely low off-state current. The period during which the charge can be held at the node FD due to the low off-current characteristics of the transistor 42. Therefore, without complicating the circuit configuration or operation method, A global shutter method can be applied in which charge accumulation is performed simultaneously in all pixels. Note that the imaging device of one embodiment of the present invention can also be operated by a rolling shutter method. .

[0058] An OS transistor is a transistor that uses silicon in the active region or active layer (hereafter, S Since the temperature dependence of the electrical characteristics fluctuation is smaller than that of the MOSFET, it can be used in an extremely wide temperature range. Therefore, an imaging device and a semiconductor device having an OS transistor can be used. The device is also suitable for installation in automobiles, aircraft, spacecraft, etc.

[0059] In addition, the OS transistor has a higher drain withstand voltage than a Si transistor. In photoelectric conversion elements that use selenium-based materials as the photoelectric conversion layer, avalanche multiplication is utilized. It is preferable to operate the device by applying a relatively high voltage (for example, 10 V or more). By combining an OS transistor with a photoelectric conversion element that uses a selenium-based material as a photoelectric conversion layer, This makes it possible to provide a highly reliable imaging device.

[0060] Layer 1300 may include transistor 43 and transistor 44. The transistors 43 and 44 are transistors having silicon as an active layer or active region. It is preferable to use a transistor having an active layer or region made of silicon. The on-state current is large, and the potential of the node FD can be efficiently amplified. has a metal layer 401 a electrically connected to the gate of transistor 44 .

[0061] As shown in FIG. 1A, the metal layer 401a and the metal layer 401b are in direct contact with each other. The metal layer 401a and the metal layer 401b are provided at a position where they are electrically connected to each other. The configuration will be as follows.

[0062] The imaging device of one embodiment of the present invention may have a structure shown in FIG.

[0063] In the configuration shown in FIG. 2A, the layer 1100 includes a photoelectric conversion element PD and a part of the photoelectric conversion element PD. A metal layer 402b electrically connected to one electrode of the photoelectric conversion element PD and a metal layer 402c electrically connected to the other electrode of the photoelectric conversion element PD are provided. The metal layer 403b is provided on the layer 1100. It's not necessary.

[0064] Layer 1200 includes transistor 41, transistor 42, and the source of transistor 41. A metal layer 402a electrically connected to one of the drain and the wiring 71. The wiring 71 and the metal layer 403a are provided on the layer 1200. It doesn't have to be.

[0065] Layer 1300 includes transistor 43 and transistor 44 .

[0066] As shown in FIG. 2A, the metal layer 402a and the metal layer 402b are in direct contact with each other. The metal layer 402a and the metal layer 402b have a conductive connection portion 402. The metal layer 403a and the metal layer 403b are in direct contact with each other. The metal layer 403a and the metal layer 403b have a conductive connection 403. The configuration will be as follows.

[0067] The imaging device of one embodiment of the present invention may have a structure shown in FIG.

[0068] In the configuration shown in FIG. 2B, the layer 1100 includes a photoelectric conversion element PD and a part of the photoelectric conversion element PD. A metal layer 402b electrically connected to one electrode of the photoelectric conversion element PD and a metal layer 402c electrically connected to the other electrode of the photoelectric conversion element PD are provided. The metal layer 403b is provided on the layer 1100. It's not necessary.

[0069] Layer 1200 includes transistor 41, transistor 42, and the source of transistor 41. A metal layer 402a electrically connected to one of the drain and the wiring 71. The metal layer 403a and one of the source and drain of the transistor 41 and the transistor The metal layer 401b is electrically connected to either the source or drain of the transistor 42. The wiring 71 and the metal layer 403 a do not necessarily have to be provided on the layer 1200 .

[0070] Layer 1300 includes transistor 43, transistor 44, and the gate of transistor 43. It has a metal layer 401a for electrical connection.

[0071] As shown in FIG. 2B, the metal layer 402a and the metal layer 402b are in direct contact with each other. The metal layer 402a and the metal layer 402b have a conductive connection portion 402. The metal layer 403a and the metal layer 403b are in direct contact with each other. The metal layer 403a and the metal layer 403b have a conductive connection 403. The metal layer 401a and the metal layer 401b are in direct contact with each other. The metal layer 401a and the metal layer 401b have a conductive connection portion 401. The composition is as follows.

[0072] 3A, 3B, and 3C are diagrams for explaining a specific configuration of the pixel 20 corresponding to FIG. 1A. FIG. 3A shows the channel length direction of transistors 41, 42, 43, and 44. 3B is a cross-sectional view taken along dashed line X1-X2 shown in FIG. FIG. 3C shows a cross section of the transistor 41 in the channel width direction. 1 is a cross-sectional view taken along dashed line Y1-Y2, showing a cross section of a transistor 42 in the channel width direction. .

[0073] In the cross-sectional views described in this embodiment, wiring, electrodes, metal layers, and contact plugs ( Although the conductors 82) are shown as separate elements, they may be seen to be electrically connected. In some cases, they may be provided as the same element. The embodiment in which the elements are connected via the conductor 82 is an example, and each element may be connected without the conductor 82. In some cases, it may be directly connected to

[0074] It functions as a protective film, an interlayer insulating film, or a planarizing film on each element such as a transistor. For example, the insulating layers 81a to 81j are made of silicon oxide. An inorganic insulating film such as a silicon film or a silicon oxide nitride film can be used. Alternatively, an organic insulating film such as polyimide resin or polyvinyl chloride resin may be used. The top surface of the wafer may be CMP (Chemical Mechanical Polishing) if necessary. It is preferable to perform a planarization process by a method such as a shingle method.

[0075] In addition, some of the wiring etc. shown in the drawing may not be provided, or wiring or traces not shown in the drawing may not be provided. In some cases, layers not shown in the drawings may be included. Also, some layers shown in the drawings may not be included.

[0076] The area where the OS transistor is formed and the area where the Si device (Si transistor or Si phototransistor) is formed are Insulating layers 80a and 80b are provided between the regions where the photodiodes (transistors) are formed.

[0077] Hydrogen in the insulating layer provided near the active regions of the transistors 43 and 44 is converted into silicon dung. The hydrogen terminates the ring bond. Therefore, the hydrogen improves the reliability of the transistors 43 and 44. On the other hand, in the vicinity of the oxide semiconductor layer which is the active layer of the transistors 41 and 42, Hydrogen in the insulating layer provided next to the oxide semiconductor layer is one of the factors that generate carriers in the oxide semiconductor layer. Therefore, the hydrogen may cause a decrease in reliability of the transistors 41 and 42. Therefore, one layer has a Si transistor and the other layer has an OS transistor. When stacking the other layer, an insulating layer 80 having a function of preventing hydrogen diffusion between them is provided. It is preferable to provide the insulating layer 80b. The insulating layer 80b confines hydrogen to one layer, thereby preventing the The reliability of the transistors 43 and 44 can be improved. By suppressing the diffusion of hydrogen, the reliability of the transistors 41 and 42 can be improved. For the same reason as above, one layer having a Si photodiode and the other layer having an OS transistor are An insulating layer 80a having a function of preventing hydrogen diffusion is provided between the other layer having a transistor. It is preferable to do so.

[0078] The insulating layers 80a and 80b may be made of, for example, aluminum oxide, aluminum oxynitride, or oxide. Gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide Materials such as hafnium oxide nitride and yttria stabilized zirconia (YSZ) can be used. Cut.

[0079] In FIG. 3(A), the photoelectric conversion element PD of the layer 1100 is made of a single crystal silicon substrate. The photoelectric conversion element PD is a pn-type photodiode. + area 620, p - region 630, n-type region 640, p + It may have a region 650.

[0080] The n-type region 640 is electrically connected to the metal layer 405. + Region 650 is metal layer 4 The metal layer 405 and the metal layer 406 are electrically connected to the insulating layer 81g. It will be established.

[0081] The layer 1200 is provided with a transistor 41 and a transistor 42, which are OS transistors. The transistors 41 and 42 each have a back gate. Even if only some of the transistors, for example the transistor 41, have a back gate, The back gate of the transistor provided opposite to the back gate of the transistor shown in FIG. In some cases, the back gate may be electrically connected to the front gate. The input terminal may be configured to be capable of supplying a fixed potential different from that of the input terminal.

[0082] The metal layer 401b is provided so as to have a region buried in the insulating layer 81d, and the conductive layer and The other of the source and drain of the transistor 41 and the transistor The source or drain of the transistor 41 is electrically connected to the One of the source and drain is electrically connected to the metal layer 405 via the conductor 82 and a conductive layer, etc. The wiring 71 is electrically connected to the metal layer 406 via the conductor 82. do.

[0083] The layer 1300 is provided with a transistor 43 and a transistor 44, which are Si transistors. In FIG. 3A, transistors 43 and 44 are illustrated as having a fin-type structure. However, it may be a planar type as shown in FIG. 4(A), or a rectangular type as shown in FIG. As shown in FIG. 1, the active layer 660 may be a thin silicon transistor. The single crystal silicon of polycrystalline silicon and SOI (Silicon on Insulator) It can be a recon.

[0084] The metal layer 401a is provided so as to have a region buried in the insulating layer 81c, and the conductive layer and It is electrically connected to the gate of the transistor 43 via a conductor 82 or the like.

[0085] Here, it is preferable that the main component of the metal layer 401a and the metal layer 401b is the same metal element. It is preferable that the insulating layer 81c and the insulating layer 81d are made of the same component. preferable.

[0086] For example, the metal layer 401a and the metal layer 401b may include Cu, Al, Sn, Zn, W, Ag, , Pt or Au can be used. In view of ease of bonding, Cu, A are preferable. The insulating layer 81c and the insulating layer 81d are made of silicon oxide. Silicon oxide nitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be done.

[0087] The same metal material as described above is used for the metal layer 401a and the metal layer 401b, The insulating layer 81c and the insulating layer 81d are each made of the same insulating material as described above. Then, the bonding step can be performed at the bonding position a shown in FIG. Therefore, electrical connection between the metal layer 401a and the metal layer 401b can be obtained. As a result, a connection having sufficient mechanical strength can be obtained between insulating layers 81c and 81d.

[0088] To bond metal layers together, the oxide film and impurity adsorption layer on the surface are removed by sputtering or other methods. The surface activated bonding method is used to bond cleaned and activated surfaces together by contacting them with each other. Alternatively, a method such as diffusion bonding, which uses a combination of temperature and pressure to bond surfaces together, can be used. In both cases, bonding occurs at the atomic level, so they can be used not only electrically but also mechanically. Mechanically excellent bonding can also be obtained.

[0089] In addition, to bond the insulating layers together, a high degree of flatness is obtained by polishing, etc., and then oxygen plasma, etc. is used. The surfaces are temporarily bonded by contacting each other with hydrophilic treatment, and the final bond is then performed by dehydrating the surfaces with heat treatment. Aqueous bonding methods can be used. Hydrophilic bonding methods also involve bonding at the atomic level, so In this way, a mechanically excellent bond can be obtained.

[0090] When the layer 1300 and the layer 1200 are bonded to each other, an insulating layer and a metal layer are formed on each of the bonding surfaces. For example, the surface activation bonding method and the hydrophilic bonding method may be combined. .

[0091] For example, after polishing, the surface is cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment and then a hydrophilic treatment. Alternatively, the surface of the metal layer may be treated with a hard metal such as Au. Alternatively, the metal may be oxidized and hydrophilic treatment may be performed. This is also fine.

[0092] In the bonding method, each device is bonded after it is completed, so OS transistors The silicon transistor and the silicon capacitor can be fabricated using the processes that are most suitable for each. Therefore, the electrical characteristics and reliability of each transistor can be improved. The top-gate transistors are then bonded together, so the OS The front gate electrode of the transistor and the gate electrode of the Si transistor are on top of each other. are arranged facing each other.

[0093] The pixel 20 may also have a stacked structure as shown in FIG. Only the layer 1100 is different from the pixel 20 shown in FIG. 3(A), and the other configurations are the same.

[0094] In FIG. 5, the photoelectric conversion element PD in the layer 1100 is a fluorine-based ... The photoelectric conversion element PD includes a photoelectric conversion layer 561, a transparent conductive The semiconductor device can have a structure including a layer 562 , an electrode 566 , a partition wall 567 , and a wiring 571 .

[0095] The electrode 566 is electrically connected to the metal layer 405. The light-transmitting conductive layer 562 is connected to the wiring 57. The metal layer 405 and the metal layer 406 are electrically connected to each other through the insulating layer 1. It is provided through edge layer 81g.

[0096] FIG. 5 illustrates an embodiment in which a selenium-based material is used for the photoelectric conversion layer 561. The photoelectric conversion element PD using this has a high external quantum efficiency for visible light. Since the selenium-based material has a high light absorption coefficient, it has an advantage that the photoelectric conversion layer 561 can be easily made thin. In photoelectric conversion elements (PDs) using selenium-based materials, avalanche multiplication leads to high sensitivity. In other words, by using a selenium-based material for the photoelectric conversion layer 561, Therefore, even if the pixel area is reduced, sufficient photocurrent can be obtained. It can be said that the photoelectric conversion element PD using this is also suitable for imaging in low-light environments.

[0097] The selenium-based material may be amorphous or crystalline selenium. Crystalline selenium can be obtained, for example, by forming an amorphous selenium film and then heat treating it. By making the crystal grain size smaller than the pixel pitch, the characteristic variation between pixels can be reduced. Crystalline selenium also has higher spectral sensitivity and light absorption for visible light than amorphous selenium. It has high coefficient characteristics.

[0098] In FIG. 5, the photoelectric conversion layer 561 is illustrated as a single layer. On the surface side, a hole injection blocking layer 568 is formed by using gallium oxide, cerium oxide or In-Ga-Zn Alternatively, as shown in FIG. 6B, an oxide or the like may be provided. The blocking layer 569 may be made of nickel oxide or antimony sulfide. 6(C), a hole injection blocking layer 568 and an electron injection blocking layer 569 are provided. It is also possible to use the following.

[0099] The photoelectric conversion layer 561 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, the layer may include a compound of copper, indium, gallium, and selenium (CIGS). CIS and CIGS utilize avalanche multiplication in the same way as a single layer of selenium. A photoelectric conversion element can be formed.

[0100] The photoelectric conversion element PD using a selenium-based material has an electrode 56 formed of, for example, a metal material. A photoelectric conversion layer 561 may be provided between the insulating layer 6 and the light-transmitting conductive layer 562. In addition, CIS and CIGS are p-type semiconductors and require sulfurization of n-type semiconductors to form a junction. Cadmium, zinc sulfide, or the like may be provided in contact with the metal.

[0101] In FIG. 5, the light-transmitting conductive layer 562 and the wiring 571 are in direct contact with each other. As shown in FIG. 5, the two may be connected via a wiring 588. The layer 561 and the light-transmitting conductive layer 562 are not separated between the pixel circuits. As shown in E), the electrodes 5 may be separated between the pixels. In the region not having 66, a partition wall 567 is provided using an insulator, and the photoelectric conversion layer 561 and the transparent conductive layer 562 are It is preferable to prevent cracks in layer 562, but as shown in FIGS. A configuration may be adopted in which no partition wall 567 is provided.

[0102] In addition, the electrode 566 and the wiring 571 may be multi-layered. For example, as shown in FIG. As shown in FIG. 1, the electrode 566 is made of two layers, a conductive layer 566a and a conductive layer 566b, and the wiring 571 is made of a conductive material. The conductive layer 571a and the conductive layer 571b may be two layers. For example, the conductive layer 566a and the conductive layer 571a are formed by selecting a low-resistance metal or the like. The conductive layer 566b and the conductive layer 571b are made of a metal or the like having good contact characteristics with the photoelectric conversion layer 561. By adopting such a configuration, the electrical characteristics of the photoelectric conversion element PD can be improved. In addition, some metals can be in contact with the light-transmitting conductive layer 562. Even if such a metal is used for the conductive layer 571a, the conductive layer 5 By providing 71b, electrolytic corrosion can be prevented.

[0103] The conductive layer 566b and the conductive layer 571b are formed using, for example, molybdenum or tungsten. The conductive layer 566a and the conductive layer 571a may include, for example, aluminum. Aluminum, titanium, or stacks such as aluminum sandwiched between titanium can be used.

[0104] As shown in FIG. 7D, the transparent conductive layer 562 and the wiring 571 are connected to the conductor 82 and the wiring 588.

[0105] The partition 567 can be formed using an inorganic insulator, an insulating organic resin, or the like. The wall 567 is used for blocking light from transistors and the like and / or for reducing the area of ​​the light receiving portion per pixel. The mark may be colored black or the like to confirm the mark.

[0106] The pixel 20 may also have a laminated structure as shown in FIG. The pixel 20 differs from the pixel 20 shown in FIG. 3(A) only in the layer 1100, and the other configurations are the same. be.

[0107] In FIG. 8A, the photoelectric conversion element PD of the layer 1100 has an amorphous silicon layer. The photodiode shown is a pin-type photodiode using a silicon film or a microcrystalline silicon film. The electric conversion element PD is made up of an n-type semiconductor layer 565, an i-type semiconductor layer 564, and a p-type semiconductor layer 56 3, the structure may include an electrode 566, a wiring 571, and a wiring 588.

[0108] The electrode 566 is electrically connected to the metal layer 405. The p-type semiconductor layer 563 is also connected to the wiring 588 and the wiring 571. The metal layer 406 is provided so as to penetrate the insulating layer 81g.

[0109] It is preferable to use amorphous silicon for the i-type semiconductor layer 564. The layer 563 and the n-type semiconductor layer 565 contain dopants that impart their respective conductivity types. The amorphous silicon or the microcrystalline silicon can be used. The photodiode that is used as the electric conversion layer has high sensitivity in the visible light wavelength range and detects weak visible light. is easy to detect.

[0110] Also, the configuration of a photoelectric conversion element PD having a pin-type thin-film photodiode, and The photoelectric conversion element PD and the wiring connection form are shown in the examples of Figs. 8(B), (C), and (D). The configuration of the photoelectric conversion element PD and the connection between the photoelectric conversion element PD and the wiring may be the same as above. The present invention is not limited to the above and may be in other forms.

[0111] FIG. 8B shows a light-transmitting conductive layer 562 in contact with a p-type semiconductor layer 563 of a photoelectric conversion element PD. The light-transmitting conductive layer 562 acts as an electrode and outputs the output voltage of the photoelectric conversion element PD. The flow can be increased.

[0112] The transparent conductive layer 562 is made of, for example, indium tin oxide or indium stannate containing silicon. zinc oxide, zinc oxide, zinc oxide containing gallium, aluminum oxide, Zinc oxide containing fluorine, tin oxide, tin oxide containing antimony, graphene or In addition, the light-transmitting conductive layer 562 is not limited to a single layer. It may also be a laminate of different films.

[0113] In FIG. 8C, the transparent conductive layer 562 and the wiring 571 are connected via the conductor 82 and the wiring 588. The p-type semiconductor layer 563 of the photoelectric conversion element PD and the wiring 571 are connected to each other. Alternatively, the connection may be made via the conductor 82 and the wiring 588. In the case of C), the light-transmitting conductive layer 562 may not be provided.

[0114] FIG. 8D shows a state in which the p-type semiconductor layer 563 is exposed to the insulating layer 81k covering the photoelectric conversion element PD. An opening is provided, and a light-transmitting conductive layer 562 covering the opening and a wiring 571 are electrically connected. This configuration has the following features.

[0115] The photoelectric conversion element PD formed using the above-mentioned selenium-based material and amorphous silicon is formed by film deposition. It is manufactured using general semiconductor manufacturing processes such as the process of lithography and etching. In addition, the selenium-based material has high resistance, and as shown in FIG. It is also possible to configure the circuit without isolating 61 between the circuits. This allows for high yield and low cost. It can be made with

[0116] The photoelectric conversion element PD of the pixel 20 shown in FIG. 5 and FIG. 8(A) is a laminate of thin films. Therefore, it is preferable to form the insulating layer after the bonding step.

[0117] The pixel 20 may also have a stacked structure as shown in FIG. The layer 1200 is formed on the layer 1300, and the layer 1200 and the layer 1100 formed separately are joined at a joining position b. That is, the joint of the metal layer is layer 13 in the laminated structure of FIG. 9. In the stacked configuration shown in FIG. 9, the layer 1200 is provided between the layer 110 and the layer 1200. It is set between 0 and

[0118] In FIG. 9, the photoelectric conversion element PD of the layer 1100 is a p The photoelectric conversion element PD is a p + area 620, p - territory area 630, n-type area 640, p + It may have a region 650.

[0119] The n-type region 640 is electrically connected to the metal layer 402b.+ Region 650 is a metal layer The metal layer 405 and the metal layer 406 are electrically connected to the insulating layer 81g. It is provided through.

[0120] The layer 1200 is provided with a metal layer 402a and a metal layer 403a. The metal layer 402a is an insulating The conductive layer and the conductor 82 are disposed in the layer 81h so as to have a buried region. The metal layer 4 is electrically connected to either the source or the drain of the transistor 41. 03a is provided so as to have a region buried in the insulating layer 81h, and is arranged via the conductor 82. It is electrically connected to the line 71 .

[0121] Layer 1300 is provided with transistors 43 and 44, which are Si transistors. The gate of the transistor 43 is connected to the transistor 41 via a conductive layer, a conductor 82, etc. The other of the source or drain of transistor 41 and one of the source or drain of transistor 42 The other end is electrically connected to the other end.

[0122] The pixel 20 may also have a stacked structure as shown in FIG. , the layers 1300, 1200, and 1100 are formed separately, and the layers 1300 and 1200 are The layers 1200 and 1100 are bonded together at a bonding position a, and the layers 1200 and 1100 are bonded together at a bonding position b. That is, the metal layer junctions are between layer 1300 and layer 1200 and between layer 1200 and layer 1300. It is set between 100 and 200.

[0123] In FIG. 10, the photoelectric conversion element PD of the layer 1100 is made of a single crystal silicon substrate. The photoelectric conversion element PD is a pn-type photodiode. + area 620, p - region 630, n-type region 640, p + It may have a region 650.

[0124] The n-type region 640 is electrically connected to the metal layer 402b. + Region 650 is a metal layer The metal layer 402a and the metal layer 403b are electrically connected to the insulating layer 81g. The groove is provided so as to penetrate the groove.

[0125] The layer 1200 includes a metal layer 401b, a metal layer 402a, and a metal layer 403a. The layer 401b is provided to have a region buried in the insulating layer 81d, and the conductive layer and the conductive The other of the source or drain of the transistor 41 and the transistor 4 The metal layer 402a is electrically connected to one of the source and drain of the insulating layer 81g. The transistor is connected to the conductive layer and the conductor 82 through the conductive layer and the conductor 82. The metal layer 403a is electrically connected to either the source or the drain of the transistor 41. The insulating layer 81g is provided so as to have a buried region, and is connected to the wiring 71 via the conductor 82. are electrically connected.

[0126] The layer 1300 is provided with a metal layer 401a. The metal layer 401a is embedded in an insulating layer 81c. 82 and the like. The transistor is electrically connected to either the source or the drain of the transistor.

[0127] An example of a method for manufacturing the laminated structure shown in FIG. 3(A) will be described with reference to FIGS. 11(A1) to 11(A3). do.

[0128] First, a layer 1300 having an insulating layer 81c and a metal layer 401a on the top layer is fabricated (FIG. 1 1(A1)). The metal layer 401a is, for example, a gate electrode of the transistor 43 on the insulating layer 81c. Through holes are formed that reach the wiring layer that electrically connects to the electrode, and then the electrode is bonded to the wiring layer by using a CVD method, plating method, etc. A metal layer is provided so as to fill the through hole, and the surface is polished to remove excess metal layer. Alternatively, the metal layer 401a may be formed by a film forming method such as a CVD method or a sputtering method. The insulating layer 81c is formed so as to cover the metal layer 401a, and the surface is polished. The upper surface of the metal layer 401a may be exposed. In either method, the polishing is performed by CMP (chemical mechanical polishing). The entire surface is polished using a method such as chemical mechanical polishing. The surface is flattened to minimize any step between the metal layer 401a and the insulating layer 81c. It is preferable.

[0129] In addition, a photoelectric conversion element PD is fabricated, and an insulating layer 81d and a gold layer are formed on the photoelectric conversion element PD as the uppermost layers. A layer 1200 having a metal layer 401b is produced.

[0130] The photoelectric conversion element PD is formed, for example, by a diffusion method, a doping method, or the like on a single crystal silicon substrate 670. Then, an OS transistor is formed on the photoelectric conversion element PD. The uppermost layer is an insulating layer 81d and a metal layer 40. The metal layer 401b can be formed in the same manner as the metal layer 401a, and can be formed by CMP. The surfaces of the insulating layer 81d and the metal layer 401b are planarized by a method such as flattening.

[0131] Next, the planarized surface of layer 1300 and the planarized surface of layer 1200 are subjected to the above-mentioned After that, the metal layer 401a and the metal layer 401b are brought into contact with each other. Then, after proper processing, the two parts and the insulating layer 8 are 1c and the insulating layer 81d are bonded together (see FIG. 11(A2)).

[0132] After the bonding is completed, unnecessary areas of the single crystal silicon substrate 670 are polished off, and the photoelectric conversion The light receiving surface of the element PD is exposed, and a protective film such as an insulating layer is formed as necessary (Figure 11(A As a result, the laminated structure shown in FIG.

[0133] The single crystal silicon substrate 670 is polished before the bonding process or after the OS transistor In this case, a peelable adhesive or the like may be used to attach the support substrate to the substrate. It is preferable to carry out the process by providing

[0134] An example of a method for manufacturing the laminated structure shown in FIG. 5 and FIG. 8(A) is shown in FIG. 11(B1) to (B4). The method of producing the layer 1300 and the bonding of the layer 1300 and the layer 1200 will be described. For the alignment process, the above-described method for producing the pixel 20 shown in FIG. 3(A) can be referred to.

[0135] First, a layer 1300 having an insulating layer 81c and a metal layer 401a on the top layer is fabricated (FIG. 1 1(B1)).

[0136] A peeling layer 1800 is formed on a flat support substrate 1700 such as a glass substrate or a semiconductor substrate. A layer 120 having an insulating layer 81d and a metal layer 401b on the top layer is provided on the release layer 1800. Create 0.

[0137] The peeling layer 1800 is formed, for example, by laminating a tungsten film and a silicon oxide film. The stack is thermally stable and can be used after the transistor fabrication process is completed. By applying physical force, the tungsten film and the silicon oxide film are peeled off near the interface. Alternatively, a polyimide film may be used as the release layer 1800. In the case of using a film, it is preferable to use a light-transmitting substrate. After that, the polyimide film is weakened by irradiating it with light such as laser light from the transparent substrate side, and then peeled off. Alternatively, a thermally stable peelable adhesive or the like can be used as the release layer 1800. It may be used.

[0138] Next, the layer 1300 and the layer 1200 are bonded together (see FIG. 11(B2)).

[0139] After the bonding is completed, the laminate of the layer 1300 and the layer 1200 from the support substrate 1700 At this time, if a part of the peeling layer remains on the surface of the layer 1200, it is possible to remove the part by cleaning or etching. The surfaces of the metal layers 405 and 406 are exposed by etching or the like. See Figure 11(B3) and Figure 3(A).

[0140] Then, the layer 1100 having the photoelectric conversion element PD is formed on the layer 1200 (FIG. 11(B4) ) As a result of the above, the laminated structure shown in FIG. 5 or FIG. 8(A) is completed.

[0141] An example of a method for manufacturing the stacked structure shown in FIG. 9 will be described with reference to FIGS. The method of manufacturing the metal layer of the joint and the method of bonding are the same as those of the laminated structure shown in FIG. The manufacturing method can be referred to.

[0142] First, a layer 1300 is prepared (see FIG. 12(A1)), and an insulating layer 81 is formed on the layer 1300 as the uppermost layer. h, a layer 1200 having a metal layer 402a and a metal layer 403a is prepared (FIG. 12(A2 At this time, the elements of the layer 1300 and the elements of the layer 1200 are electrically connected to each other as necessary. Make a connection.

[0143] Next, the layer 1200 and the single crystal silicon substrate 670 on which the photoelectric conversion element PD is provided are bonded to each other. The metal layers 402a and 402b, the metal layers 403a and 403b, etc. Additionally, insulating layer 81h and insulating layer 81g are bonded together (see FIG. 12(A3)).

[0144] After the bonding is completed, unnecessary areas of the single crystal silicon substrate 670 are polished off, and the photoelectric conversion The light receiving surface of the element PD is exposed, and a protective film such as an insulating layer is formed as necessary (Figure 12(A 4). In this way, the layer 1100 is formed, and the laminated structure shown in FIG. 9 is completed. do.

[0145] The single crystal silicon substrate 670 may be polished before the bonding process. In this case, it is preferable to use a peelable adhesive or the like and to provide a suitable supporting substrate before carrying out the process.

[0146] An example of a method for manufacturing the laminated structure shown in FIG. 10 will be described with reference to FIGS. 12(B1) to 12(B5). The method of manufacturing the metal layer of the joint and the method of bonding are the same as those of the laminated structure shown in Figure 3(A). You can refer to the preparation method.

[0147] First, a layer 1300 having an insulating layer 81c and a metal layer 401a on the top layer is fabricated (FIG. 1 2(B1)).

[0148] A peeling layer 1800 is formed on a flat support substrate 1700 such as a glass substrate or a semiconductor substrate. On the release layer 1800, an insulating layer 81g, a metal layer 402a and a metal layer 403a are provided as the bottom layers. A layer 1200 having an insulating layer 81d and a metal layer 401b on the top layer is fabricated.

[0149] Next, the layer 1300 and the layer 1200 are bonded together (see FIG. 12(B2)).

[0150] After the bonding is completed, the laminate of the layer 1300 and the layer 1200 from the support substrate 1700 At this time, if a part of the peeling layer remains on the surface of the layer 1200, it is possible to remove the part by cleaning or etching. The surfaces of the metal layers 402a and 403a are exposed by etching or the like. (See FIG. 12(B3)).

[0151] Next, the layer 1200 and the single crystal silicon substrate 670 on which the photoelectric conversion element PD is provided are bonded to each other. The metal layers 402a and 402b, the metal layers 403a and 403b, etc. Additionally, insulating layer 81h and insulating layer 81g are bonded together (see FIG. 12(B4)).

[0152] After the bonding is completed, unnecessary areas of the single crystal silicon substrate 670 are polished off, and the photoelectric conversion The light receiving surface of the element PD is exposed, and a protective film such as an insulating layer is formed as necessary (Figure 12(B) 5). In this way, the layer 1100 can be formed, and the laminated structure shown in FIG. 10 is completed. Complete.

[0153] The single crystal silicon substrate 670 may be polished before the bonding process. In this case, it is preferable to use a peelable adhesive or the like and to provide a suitable supporting substrate before carrying out the process.

[0154] In the imaging device according to one embodiment of the present invention, a pixel circuit is formed using a Si transistor formed in the layer 1300. Circuits other than the above may be provided. Such circuits may include, for example, column drivers and and low drivers, data conversion circuits such as A / D converters, CDS (C Noise reduction circuits such as MOS or related double sampling circuits, and a control circuit for the entire imaging device.

[0155] The transistors 46 and 47 included in either of the above circuits are shown in FIG. The transistors 46 and 47 can be formed in a region overlapping with the photoelectric conversion element PD. In addition, one or both of the transistors 46 and 47 may be connected to one or both of the transistors 41 and 42. In other words, the circuit may be formed in an area overlapping the pixel 20. In FIG. 13, the transistor 46 is a p-ch type, and the transistor 47 is an n- Although an example of a ch-type CMOS inverter is shown, other circuit configurations are also possible. Good too.

[0156] As shown in FIG. 14, transistor 47 is an OS transistor provided in layer 1200. In the configuration shown in FIG. 14, the transistors 46 and 47 are overlapped with each other. This allows the circuit area to be reduced by a bonding process. In addition, when the transistors 44 and 45 of the pixel 20 are formed as p-ch type transistors, single crystal silicon is used. All the transistors provided on the silicon substrate 600 can be p-ch type, or n-ch type This makes it possible to omit the step of forming a Si transistor.

[0157] 13 and 14 show a pixel 20 shown in FIG. 3A with transistors 46 and 47 added thereto. 5, 9, or 10. However, the pixel 20 of FIG. 5, FIG. 9, or FIG. 10 may include a transistor 4. 6 and 47 can also be added.

[0158] FIG. 15A is a block diagram illustrating a circuit configuration of an imaging device according to one embodiment of the present invention. The imaging device includes a pixel array 21 having pixels 20 arranged in a matrix, and a A circuit 22 (row driver) having a function of selecting a row of the pixel 21 and a circuit 23 (row driver) having a function of selecting a row of the pixel 20 A circuit 23 (CDS circuit) for performing CDS operation on the analog input signal, and an analog output signal from the circuit 23. A circuit 24 (such as an A / D conversion circuit) having a function of converting log data into digital data; A circuit 25 (column driver) having a function of selecting and reading the data converted by the circuit 24 ) and the like. Note that a configuration may be adopted in which the circuit 23 is not provided. The destination circuits 25 are collectively referred to as circuit 30.

[0159] FIG. 15B is a circuit diagram of a circuit 23 and a circuit 24 connected to one column of the pixel array 21. The circuit 23 includes a transistor 51, a transistor 52, a capacitance element C3, and a capacitance element C4. The circuit 24 may also include a comparator circuit. The configuration may include a circuit 27 and a counter circuit 29.

[0160] The transistor 53 functions as a current source circuit. A wiring 91 (OUT1) is electrically connected to one of the drains, and the other of the source or drain A power supply line is connected to the other side. The power supply line can be, for example, a low-potential power supply line (VSS). In addition, a bias voltage is constantly applied to the gate of the transistor 53. Let us assume that.

[0161] In the circuit 23, one of the source and drain of the transistor 51 is connected to the transistor 52. The source or drain of the transistor 51 is electrically connected to the One of the drains is electrically connected to one of the electrodes of the capacitance element C3. The other of the source and drain is electrically connected to one electrode of the capacitance element C4. The other of the source and drain of the transistor 52 is electrically connected to the wiring 92 (OUT2). The other of the source and drain of the transistor 51 is connected to a high potential to which a reference potential is supplied, for example. The other electrode of the capacitance element C4 is electrically connected to the potential power supply line (CDSVDD). For example, it is electrically connected to the low potential power supply line (CDSVSS).

[0162] An example of the operation of the circuit 23 when connected to the pixel 20 shown in FIG. 1B will be described. The transistor 51 and the transistor 52 are turned on. Next, the line 91 ( The potential of the image data is output to the wiring 92 (OUT1), and the reference potential (CDSVD Then, the transistor 51 is turned off to disconnect the pixel 20 from the wiring 91 (OU T1) is reset to a potential (here, a potential higher than the potential of the image data, for example, VDD potential). At this time, the wiring 92 (OUT2) outputs the potential of the image data and the reset potential. The absolute value of the difference between the voltages is added to the reference voltage (CDSVDD). A low-noise potential signal is obtained by adding the potential of the net image data to the potential (CDSVDD). It can be supplied to the circuit 24.

[0163] The reset potential is a potential (such as a GND potential) lower than the potential of the image data. In this case, the wiring 92 (OUT2) is connected to the reference potential, which is the absolute value of the difference between the potential of the image data and the reset potential. The potential is subtracted from the CDSVDD potential.

[0164] In the circuit 24, the signal potential input from the circuit 23 to the comparator circuit 27 is compared with the rising or The potential is compared with a reference potential (RAMP) that is swept downward. The counter circuit 29 operates in response to the output of the circuit 27, and a digital A signal is output.

[0165] The imaging device according to one embodiment of the present invention includes a pixel array 21 and a circuit unit 35 having a circuit 30. For example, FIG. 16A is a top view of the pixel array 21, and FIG. When 6(B1) and 6(B2) are top views of the circuit section 35, as shown in the perspective view of FIG. Such a stacked structure of the pixel array 21 and the circuit section 35 can be used. Therefore, it is possible to use transistors suitable for each element and reduce the area of ​​the image pickup device. The layout of the circuit in FIG. 16(B1) and (B2) is the same. The above is an example, and other layouts may be used. However, the control circuit 26 may be provided outside the circuit section 35.

[0166] The circuit 22 and the circuit 30 shown in FIG. 16(B1) are divided into two parts, and the circuit is located near the center instead of the end. The shift register circuits of the circuits 22 and 30 are arranged in a two-phase It can be divided into two regions and operated independently, or it can be operated as a series of shift register circuits. It may be allowed.

[0167] The circuit 22 and the circuit 30 shown in FIG. 16(B2) are divided into two parts similarly to FIG. 16(B1). However, the circuit is arranged diagonally.

[0168] By using the configuration shown in FIG. 16B1 and FIG. 16B2, the circuit 22 and the circuit 30 are provided at the end portions. In addition, the load on each of the wirings connected to the pixel 20 can be reduced by using the same wiring. The wiring load is not uniform, but if the wiring capacitance and resistance are small, the non-uniformity is not a problem. do not have.

[0169] The circuits 22 and 30 are silicon-based in order to achieve both high speed operation and a CMOS circuit configuration. It is preferable to manufacture the semiconductor device using a transistor that uses silicon (hereinafter, referred to as a silicon transistor). For example, the circuit section 35 can be formed on a silicon substrate. It is possible to manufacture the device using a transistor that uses an oxide semiconductor (hereinafter, OS transistor). It is preferable that some of the transistors constituting the circuit 22 and the circuit 30 are OS transistors. It may be formed by a stamper.

[0170] FIG. 17A is a cross-sectional view of an example of an imaging device to which a color filter or the like is added. The cross-sectional view shows a part of an area having pixel circuits for three pixels. On the layer 1100 to be formed, an insulating layer 2500 is formed. The insulating layer 2500 is irradiated with visible light. A highly transparent silicon oxide film can be used for the passivation. The anti-reflection film may be a silicon nitride film. A configuration in which a dielectric film such as fluorine is laminated may also be used.

[0171] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 may include an upper The light shielding layer 2510 has a function of preventing the mixing of colors of light passing through the color filter. A metal layer such as tungsten or aluminum, or a dielectric layer that functions as an anti-reflective coating The film may be laminated.

[0172] An organic resin layer 2520 is provided on the insulating layer 2500 and the light-shielding layer 2510 as a planarizing film. In addition, a color filter 2530 (color filter 25 30a, color filter 2530b, and color filter 2530c) are formed. For example, , color filter 2530a, color filter 2530b, and color filter 2530 c: R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By assigning colors, a color image can be obtained.

[0173] A light-transmitting insulating layer 2560 or the like may be provided on the color filter 2530. do.

[0174] Also, as shown in FIG. 17B, an optical conversion layer 255 is used instead of the color filter 2530. 0 may be used. With this configuration, images in various wavelength regions can be obtained. It is possible to provide an imaging device having such a configuration.

[0175] For example, if a filter that blocks light with wavelengths shorter than visible light is used for the optical conversion layer 2550, infrared The optical conversion layer 2550 can be used as an imaging device. If a filter having such a structure is used, a far-infrared imaging device can be obtained. If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. .

[0176] In addition, if a scintillator is used for the optical conversion layer 2550, it is possible to use a radiation detector such as an X-ray imaging device. It is possible to make an imaging device that can obtain an image that visualizes the strength of lines. When radiation enters the scintillator, it is converted into visible light and ultraviolet light by the photoluminescence phenomenon. The light is converted into light (fluorescence) such as external light. Then, the light is detected by the photoelectric conversion element PD. Image data is acquired by the above. Also, the imaging device having the above configuration is used for a radiation detector, etc. Good too.

[0177] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy and These include substances that emit visible light or ultraviolet light. For example, Gd2O2S:Tb, Gd2O2S:P r, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, C eF3, LiF, LiI, and ZnO dispersed in resin or ceramics can be used. Cut.

[0178] FIG. 47(A) is a photograph of an X-ray imaging panel prototyped using OS transistors. The size of the lens is 100.5mm x 139mm, the number of pixels is 384 x 512, and the pixel size is 120 μm×120μm, resolution is 106ppi, and the photodiode is amorphous silicon The panel also uses a row driver for selecting pixels and a control circuit for controlling output signals. The NI 6110 has a built-in multiplexer that

[0179] Figure 47(B) shows the above X-ray imaging panel with a scintillator (Gd2O2S:Tb) added. The X-ray photograph shows a lead plate, a copper coin, and a resin-coated plate on the panel. The X-ray detector is placed above the detector, and X-rays are irradiated from above to capture the image. The image is black because the insulator does not emit light. The image taken under the coin appears gray. Also, since X-rays can penetrate resin exterior watches, the inside of the watch cannot be seen. The image shows metal parts inside the housing.

[0180] In addition, in photoelectric conversion elements PD that use selenium-based materials, radiation such as X-rays is directly converted into electric charges. Since the light can be converted, a configuration can be made in which a scintillator is not required.

[0181] As shown in FIG. 17C, the color filter 2530a and the color filter 2530 A microlens array 2540 may be provided on color filter 2530b and color filter 2530c. The light passing through each lens of the microlens array 2540 hits the color filter directly below. As shown in FIG. 17(D), the light A microlens array 2540 may be provided on the optical conversion layer 2550. 1100 , the area other than the layer 1100 shown in (A), (B), (C), and (D) is referred to as the layer 1600 .

[0182] FIG. 18 illustrates a pixel 20 according to one embodiment of the present invention and the microlens array 2 shown in FIG. FIG. 18 is a diagram illustrating a specific stacked configuration of the pixel 20 shown in FIG. 19 is an example using the pixel configuration shown in FIG.

[0183] In this manner, the photoelectric conversion element PD and the circuit of the pixel 20 have an overlapping area. Since it is possible to configure the imaging device in this way, it is possible to reduce the size of the imaging device.

[0184] In addition, as shown in FIG. 18 and FIG. 19, a diffraction grating is provided above the microlens array 2540. The image of the subject through the diffraction grating 1500 (diffraction image) may be The input image (image of the subject) is calculated from the captured image at the pixel. In addition, by using a diffraction grating 1500 instead of a lens, the imaging device can be This can reduce the cost of electronic devices that have such devices.

[0185] The diffraction grating 1500 can be made of a material having optical transparency. For example, silicon oxide. An inorganic insulating film such as a silicon oxide nitride film or an acrylic resin film can be used. Alternatively, an organic insulating film such as a resin or a polyimide resin may be used. It may be laminated with an organic insulating film.

[0186] The diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. It can also be formed by using a lithography process and an etching process. It can also be formed by using nanoimprint lithography, laser scribing, or the like. do.

[0187] A distance X may be provided between the diffraction grating 1500 and the microlens array 2540. X can be 1 mm or less, preferably 100 μm or less. Alternatively, a light-transmitting material may be provided as a sealing layer or an adhesive layer. An inert gas such as a rare gas can be sealed in the gap. Alternatively, acrylic resin, Epoxy resin or polyimide resin may be provided in the gap. In addition, when the microlens array 2540 is not provided, In this case, a distance X may be provided between the color filter 2530 and the diffraction grating 1500 .

[0188] The pixel 20 may have a circuit configuration shown in FIG. In this case, the direction in which the photoelectric conversion element PD is connected is different from that of the pixel 20 shown in FIG. The potentials of the wiring 71 (VPD) and the wiring 72 (VRS) are opposite to those in the circuit of FIG. It can be made to work by changing it to

[0189] As shown in FIG. 21A, the transistor used in the pixel 20 is a transistor 41. The transistor 44 may have a back gate. A constant potential is applied to the gate, making it possible to control the threshold voltage.

[0190] The wirings 75 to 78 connected to the back gates are supplied with different potentials. Alternatively, as shown in FIG. 21B, a transistor 41 and a transistor The wiring connected to the back gate of the gate electrode 42 may be electrically connected. The wiring connected to the back gates of the transistors 43 and 44 is a The electrodes may be electrically connected.

[0191] In an n-channel transistor, when a potential lower than the source potential is applied to the back gate, On the other hand, if the back gate is applied with a potential higher than the source potential, the threshold voltage shifts in the positive direction. When a potential is applied, the threshold voltage shifts in the negative direction. When controlling the on / off of each transistor with a gate voltage, the source voltage is applied to the back gate. When a potential lower than the back gate potential is applied, the off-state current can be reduced. When a potential higher than the source potential is applied to the gate, the on-current can be reduced.

[0192] In the circuits shown in FIG. 1, FIG. 20(A), (B), FIG. 21(A), and (B), the potential of the node FD Since a high retention capability is desired, the transistors 41 and 42 are provided with an off-state current as described above. It is preferable to use OS transistors with low current. By applying a potential to the gate that is lower than the source potential, the off-current can be reduced. Therefore, the potential holding capability of the node FD can be improved.

[0193] As described above, the transistors 43 and 44 are Si transistors with high on-state current. It is preferable to use a potential higher than the source potential at the back gates of the transistors 43 and 44. By applying a potential, the on-state current can be increased. The read potential output to (OUT1) can be quickly determined, that is, high It can be operated at a higher frequency.

[0194] As shown in FIG. 21C, the transistor 44 has a back gate with the same potential as the front gate. The transistors 43 and 44 may be Si transistors. The on-current of an OS transistor is comparatively However, by providing a back gate, the on-current can be increased, and It is possible to operate it with

[0195] In addition to the power supply potentials, the image pickup device also includes a signal potential and a potential to be applied to the back gate. When multiple potentials are supplied from the outside of the imaging device, the number of terminals increases. In order to meet the increasing demands for power supplies, the imaging device must have a power supply circuit that generates multiple potentials. is preferred.

[0196] The operation of the pixel circuit shown in FIG. 21(A) will be described with reference to the timing chart shown in FIG. In the timing chart, "V1" is a potential higher than the reference potential, for example, It can be the power supply potential (VDD). “V0” is the reference potential, i.e., the source potential. For example, it can be 0V, a GND potential, or a low power supply potential (VSS).

[0197] First, at time T1, the potential of the wiring 75 (RS) and the wiring 61 (TX) is set to "V1". Then, the transistors 41 and 42 become conductive, and the node FD becomes a reset potential (for example, VDD). At this time, the wiring 75 and the wiring 76 are reset to "V0" (reset operation). By setting the potential to high (>“V0”), the on-current of the transistors 41 and 42 is increased. The reset operation can be performed quickly.

[0198] When the potential of the wiring 75 (RS) is set to “V0” at time T2, the transistor 42 is turned off. At this time, the wiring 76 is connected to "V0" and the accumulation operation is started. By setting the potential to low, the off-state current of the transistor 42 can be reduced, and the leakage current At time T2, the supply of charge to the node FD by the The potential of the line 75 may be "V0."

[0199] When the potential of the wiring 61 (TX) is set to “V0” at time T3, the transistor 41 is turned off. At this time, the potential of the node FD is determined and held (holding operation). By setting the potential lower than "V0", the off-state current of the transistor 41 can be reduced. This makes it possible to prevent charge from flowing out of the node FD due to leakage current.

[0200] At time T4, when the potential of the wiring 63 (SE) is set to "V1", the transistor 44 is turned on. The potential of the wiring 91 (OUT1) changes according to the current flowing through the transistor 43 (read At this time, the wiring 77 and the wiring 78 are set to a potential higher than “V0” (>“V0”). This increases the on-state current of the transistors 43 and 44, and the wiring 91 (OUT1 ) can be determined.

[0201] When the potential of the wiring 63 (SE) is set to "V0" at time T5, the transistor 44 is turned off. The read operation is then completed. Note that the potential of the node FD is The potential of the wiring 75 and 76 is kept lower than “V0” (<“V0”) so that the In the above description, it is preferable that the wiring 76 is connected at the same timing as the wiring 75. The potential may be changed by

[0202] In this manner, a signal according to the potential of the node FD can be read out. The pixel 20 shown in FIG. 20 omits the control of the wirings 75 to 78 in the timing chart shown in FIG. The pixel 20 shown in FIG. 21B is operated in accordance with the timing chart shown in FIG. This can be achieved by omitting the control of the wires 76 and 78.

[0203] In addition, the pixel circuit of one embodiment of the present invention is a transistor having a plurality of pixels as shown in FIGS. The transistors may be shared.

[0204] In the transistor-sharing type pixel shown in FIG. 23(A), pixels 20a to 20d are photoelectric The conversion element PD and the transistor 41 are individually included, and the transistors 42, 43, 44 and The transistors included in the pixels 20a to 20d are the same as the capacitance element C1. The operation of each of the pixels 41 is controlled by wiring 61a to 61d. It can perform reset, accumulation, retention, and readout operations in sequence. This is suitable for imaging using a fast shutter method.

[0205] In the transistor-sharing type pixel shown in FIG. 23B, the pixels 20a to 20d are photoelectric The conversion element PD and the transistors 41 and 45 are individually provided. 4 and the capacitance element C1 are shared. A transistor 45 controlled by the transistor 45 is provided between the photoelectric conversion element PD and the wiring 71 (VPD). This allows the cathode of the photoelectric conversion element PD to be held at a potential. The reset operation, accumulation operation, and retention operation are performed simultaneously on each pixel, and the readout operation is performed for each pixel. This is suitable for imaging using a global shutter method.

[0206] The pixel circuit shown in FIGS. 23A and 23B is arranged in a direction in which the wiring 91 (OUT1) extends (hereinafter, A transistor is formed in a plurality of pixels (pixels 20a, 20b, 20c, and 20d) arranged in a vertical direction. In the figure, the wiring 63 (SE) is shared in the direction in which it extends (hereinafter, the horizontal direction). A transistor may be shared by a plurality of pixels arranged in a row. A transistor may be shared by a plurality of pixels arranged in a line.

[0207] In addition, the number of pixels that share a transistor is not limited to four pixels, but can be two, three, or five pixels. It may be more than that.

[0208] In FIGS. 23A and 23B, the wiring 72 (VRS) and the wiring 73 (VPI) shown in FIG. Although the configuration is shown in which the wiring 72 (VRS) is omitted by integrating the wiring 72 (VRS), The other electrode of the capacitance element C1 may be connected to the wiring 73 (VPI). However, it may be connected to the wiring 71 (VPD).

[0209] The imaging device may also be curved as shown in FIG. 24(A1) and FIG. 24(B1). FIG. 24(A1) shows a state in which the imaging device is bent along the two-dot chain line Y1-Y2 in the figure. FIG. 24(A2) shows the portion indicated by the two-dot chain line X1-X2 in FIG. 24(A1). FIG. 24(A3) is a cross-sectional view of the area indicated by the two-dot chain line Y1-Y2 in FIG. 24(A1). FIG.

[0210] FIG. 24(B1) shows a case where the imaging device is bent along the two-dot chain line X3-X4 in the same figure, and FIG. 24(B2) shows a state where the bent portion is bent along the two-dot chain line Y3-Y4 in the figure. FIG. 24(B3) is a cross-sectional view of a portion indicated by a two-dot chain line X3-X4 in FIG. 24(B1). 25 is a cross-sectional view of a portion indicated by a two-dot chain line Y3-Y4 in FIG. 24(B1).

[0211] By curving the imaging device, it is possible to reduce the field curvature and astigmatism. This makes it easier to design the lenses and other components used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, enabling miniaturization of semiconductor devices using imaging devices. It is possible to easily reduce the size and weight of the camera. In addition, it is possible to improve the quality of the captured image. Cut.

[0212] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. However, the present invention is not limited to this embodiment. In some cases or depending on the situation, one aspect of the present invention may be applied to an imaging device. For example, one embodiment of the present invention may be applied to a semiconductor device having another function. For example, in one embodiment of the present invention, a channel formation region, a source / drain region, etc. of a transistor However, one embodiment of the present invention is not limited thereto. In some cases, or depending on the situation, various transistors in one aspect of the present invention may be used. A transistor channel forming region, a transistor source drain region, etc. may comprise a variety of semiconductors. Various transistors, channel formation regions of transistors, or The source and drain regions of the transistor are made of, for example, silicon, germanium, silicon gel, etc. manium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, The semiconductor may have at least one of gallium nitride and organic semiconductors. For example, in some cases or circumstances, various transistors in one aspect of the present invention may be A transistor channel forming region, a transistor source drain region, etc. For example, in one embodiment of the present invention, a global However, one embodiment of the present invention is not limited to this. Depending on the circumstances, one aspect of the present invention is to use another method, for example, a rolling system. Alternatively, depending on the circumstances, a global shutter system may be used. It is not necessary to use a shutter system.

[0213] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0214] (Embodiment 2) In this embodiment, an OS transistor that can be used in one embodiment of the present invention will be described with reference to drawings. In the drawings in this embodiment, some elements are illustrated for clarity. The drawings may be enlarged, reduced, or omitted.

[0215] 25A and 25B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 25(A) is a top view, and FIG. 25(A) is a cross section taken along the dashed line B1-B2 shown in FIG. corresponds to FIG. 25(B). Also, the cross section in the direction of the dashed line B3-B4 shown in FIG. 25(A) is 27(A). The dashed line B1-B2 direction is the channel length direction, and the dashed line B The 3-B4 direction is called the channel width direction.

[0216] The transistor 101 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; layer 150, the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 1 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. In addition, the insulating layer 180 may have a function as a planarizing film, if necessary. .

[0217] The conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is a gate insulator. The insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0218] In FIG. 25B, a region 231 is a source region, a region 232 is a drain region, and a region 233 is a The region 231 and the region 232 can function as a channel forming region. 40 and conductive layer 150, respectively, as conductive layer 140 and conductive layer 150. By using a conductive material that easily bonds with oxygen, the resistance of the regions 231 and 232 can be reduced. can be done.

[0219] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The n-type of the resistor.

[0220] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. In addition, the term "electrode layer" can be replaced with "wiring." can.

[0221] The conductive layer 170 is illustrated as being formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The same can be applied to transistors.

[0222] Although the conductive layer 140 and the conductive layer 150 are illustrated as being formed as a single layer, they may be formed as a laminate of two or more layers. This structure can be applied to other transistors described in this embodiment. .

[0223] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 25(C) is a top view of the transistor 102, and the dashed line C1-C The cross sections in the two directions correspond to FIG. 25(D). Also, the dashed line C3-C4 shown in FIG. The cross section in the direction corresponds to FIG. 27(B). The direction of the dashed dotted line C3-C4 is referred to as the channel width direction.

[0224] The transistor 102 is formed by connecting the end of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the ends of the conductive layer 170 acting as a gate electrode are not aligned with each other. The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layer 140, the conductive layer 150, and the conductive layer 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is low.

[0225] The transistor 101 and the transistor 102 are formed by a conductive layer 170, a conductive layer 140, and a conductive The top gate structure has a region where the gate insulating layer 150 overlaps the gate insulating layer 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. In this structure, since no offset region is formed in the oxide semiconductor layer 130, the on-current is high. This makes it easier to form small transistors.

[0226] The transistor of one embodiment of the present invention may have the structure shown in FIGS. 25(E) is a top view of the transistor 103, and the dashed line D1-D shown in FIG. The cross sections in the two directions correspond to FIG. 25(F). Also, the dashed line D3-D4 shown in FIG. 25(E) The cross section in the direction corresponds to FIG. 27(A). The direction of the dashed dotted line D1-D2 is the channel rectangular direction. The direction of the dashed dotted line D3-D4 is referred to as the channel width direction.

[0227] The transistor 103 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. An edge layer 175, an insulating layer 180 in contact with the insulating layer 175, and a layer including the insulating layer 175 and the insulating layer 180. A conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. In addition, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer (flattening film) or the like may be provided in contact with 150 .

[0228] The conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is a gate insulator. The insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0229] In FIG. 25(F), a region 231 is a source region, a region 232 is a drain region, and a region 233 is The region 231 and the region 232 can function as a channel forming region. 75. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the region 231 And the resistance of the region 232 can be reduced.

[0230] Specifically, the process up to the formation of the insulating layer 175 generates a thin film in the region 231 and the region 232. The oxygen vacancies caused by the oxygen vacancies interact with hydrogen diffusing from the insulating layer 175 into the regions 231 and 232. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, silicon nitride or aluminum nitride can be used.

[0231] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 26(A) is a top view of the transistor 104, and the dashed line E1-E The cross sections in the two directions correspond to FIG. 26(B). Also, the dashed line E3-E4 shown in FIG. The cross section in the direction corresponds to FIG. 27(A). The direction of the dashed dotted line E3-E4 is referred to as the channel width direction.

[0232] In the transistor 104, the conductive layer 140 and the conductive layer 150 are disposed at the end of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0233] Regions 331 and 334 shown in FIG. 26B are source regions, regions 332 and 3 The region 35 can function as a drain region, and the region 333 can function as a channel forming region.

[0234] Regions 331 and 332 correspond to regions 231 and 23 in transistor 101. As with 2, the resistance can be reduced.

[0235] Regions 334 and 335 correspond to regions 231 and 232 in transistor 103. In addition, the resistance of the region 334 and the region 335 in the channel length direction can be reduced in the same manner as in the region 2. When the length of the region 335 is 100 nm or less, preferably 50 nm or less, the gate electric field The on-current does not decrease significantly due to the contribution of the low In some cases, resistance may not be achieved.

[0236] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. This makes it suitable for high-speed operation.

[0237] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 26(C) is a top view of the transistor 105, and the dashed line F1-F shown in FIG. The cross sections in the two directions correspond to FIG. 26(D). Also, the dashed line F3-F4 shown in FIG. 26(C) The cross section in the direction corresponds to FIG. 27(A). The direction of the dashed line F1-F2 is the channel length. The dashed dotted line F3-F4 direction is referred to as the channel width direction.

[0238] The transistor 105 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151; The conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175 in contact with insulating layer 175; The insulating layer 175 and the insulating layer 180 are electrically conductive through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer may be provided.

[0239] The conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and in contact with the side surfaces of the oxide semiconductor layer 130. This is not a structure that can be used in this way.

[0240] The transistor 105 includes a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening provided in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. and conductive layer 142) can act as a source electrode layer, and conductive layer 150 (conductive Layer 151 and conductive layer 152) can act as a drain electrode layer.

[0241] The transistor of one embodiment of the present invention may have the structure shown in FIGS. 26(E) is a top view of the transistor 106, and the dashed line G1-G The cross sections in the two directions correspond to FIG. 26(F). Also, the dashed line G3-G4 shown in FIG. 26(E) The cross section in the direction corresponds to FIG. 27(A). The direction of the dashed line G1-G2 is the channel length. The direction of the dashed dotted line G3-G4 is referred to as the channel width direction.

[0242] The transistor 106 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; a conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer 162 in contact with the insulating layer 160; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. The conductive layer 141 and the conductive layer 142 are formed through the openings provided in the insulating layer 175 and the insulating layer 180. The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, an insulating layer 180, an insulating layer (planarizing film) in contact with the conductive layer 142 and the conductive layer 152, ) and the like.

[0243] The conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and in contact with the side surfaces of the oxide semiconductor layer 130. This is not a structure that can be used in this way.

[0244] The transistor 106 has the same structure as the transistor 106 except that it has a conductive layer 141 and a conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has a structure similar to that of the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 15 2) can act as a drain electrode layer.

[0245] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 Since the insulating layer 120 is not in contact with the conductive layer 140, the oxygen in the insulating layer 120 is The oxide semiconductor layer 130 is less likely to be deprived of oxygen by the conductive layer 150. This makes it easier to supply the raw material.

[0246] Regions 231 and 232 in transistor 103, transistors 104 and In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed to increase the electrical conductivity. As the impurity that forms oxygen vacancies in the oxide semiconductor layer, Examples of these elements include phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, and helix. Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more selected from zinc and carbon can be used. The methods of adding the metal oxide include plasma treatment, ion implantation, ion doping, plasma ion implantation, etc. A deposition ion implantation method or the like can be used.

[0247] When the above-mentioned element is added to the oxide semiconductor layer as an impurity element, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes an oxide The conductivity of the semiconductor layer can be increased.

[0248] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of an impurity element, the oxygen vacancies Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide conductor Here, an oxide semiconductor that has been made into a conductor is referred to as an oxide conductor. Note that an oxide conductor has a light-transmitting property like an oxide semiconductor.

[0249] An oxide conductor is a degenerate semiconductor, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a gate electrode is an ohmic contact. In addition, the contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer can be reduced.

[0250] The transistor of one embodiment of the present invention is shown in FIG. 27(C) and (D) are cross-sectional views in the channel length direction and the channel width direction, respectively. As shown in the cross-sectional view of the upper side, a conductive layer 173 is provided between the oxide semiconductor layer 130 and the substrate 115. By using the conductive layer as a second gate electrode layer (back gate), It is possible to increase the on-state current and control the threshold voltage. In the cross-sectional views shown in (C), (D), (E), and (F), the width of the conductive layer 173 is set to 0.1 mm. The conductive layer 173 may be shorter than the conductive layer 130. may also be shortened.

[0251] In order to increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and a double In order to control the threshold voltage, the MOSFET is driven as a gate transistor. A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 73 may be electrically connected via a contact hole.

[0252] In the transistors 101 to 106 in FIG. 25 and FIG. 26, an oxide semiconductor Although an example in which the conductor layer 130 is a single layer is illustrated, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 is 29(D) or 29(E) can be replaced with the oxide semiconductor layer 130 shown in FIG. Cut.

[0253] FIG. 29A is a top view of the oxide semiconductor layer 130, and FIGS. 29B and 29C are top views of the oxide semiconductor layer 130 having a two-layer structure. 29(D) and (E) are cross-sectional views of an oxide semiconductor layer 130 having a three-layer structure. 1 is a cross-sectional view of an oxide semiconductor layer 130 having a structure.

[0254] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers having different compositions can be used.

[0255] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 30(A) is a top view of the transistor 107, and the dashed line H1-H The cross sections in the two directions correspond to FIG. 30(B). Also, the dashed line H3-H4 shown in FIG. 32(A). The dashed line H1-H2 direction corresponds to the channel length direction. The direction of the dashed dotted line H3-H4 is referred to as the channel width direction.

[0256] The transistor 107 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 140 and the conductive layer 150 connected to each other, 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170; and an insulating layer 180 that functions as a flattening film, if necessary. A function may be added.

[0257] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 140 and the conductive layer 150 are the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 101 .

[0258] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 30(C) is a top view of the transistor 108, and the dashed line I1-I The cross sections in the two directions correspond to FIG. 30(D). Also, the dashed line I3-I4 shown in FIG. 32(B). The direction of the dashed dotted line I1-I2 corresponds to the channel length direction. The direction of the dashed dotted line I3-I4 is referred to as the channel width direction.

[0259] In the transistor 108, the insulating layer 160 and the end of the oxide semiconductor layer 130c are connected to the conductive layer 17. It differs from transistor 107 in that it does not coincide with the end of 0.

[0260] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 30(E) is a top view of the transistor 109, and the dashed line J1-J shown in FIG. The cross sections in the two directions correspond to FIG. 30(F). Also, the dashed line J3-J4 shown in FIG. 32(A) corresponds to the cross section in the direction of the dashed dotted line J1-J2. The direction of the dashed dotted line J3-J4 is referred to as the channel width direction.

[0261] The transistor 109 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. A stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. a second insulating layer 160 in contact with the oxide semiconductor layer 130c; 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covers the conductive layer 170, an insulating layer 180 contacts the insulating layer 175, and the insulating layer 175 is and a conductive layer 14 electrically connected to the stack through an opening in the insulating layer 180. 0 and conductive layer 150. Also, as required, insulating layer 180, conductive layer 140 and An insulating layer (planarizing film) in contact with the conductive layer 150 may be provided.

[0262] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 has a second insulating layer 130c.

[0263] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 31(A) is a top view of the transistor 110, and the dashed line K1-K The cross sections in the two directions correspond to FIG. 31(B). Also, the dashed line K3-K4 shown in FIG. 32(A) corresponds to the cross section in the direction. Also, the direction of the dashed dotted line K1-K2 corresponds to the channel length direction. The direction of the dashed dotted line K3-K4 is referred to as the channel width direction.

[0264] The transistor 110 has two oxide semiconductor layers 130 in the regions 331 and 332. In the region 333, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 104 has a similar structure to the transistor 104, except that the transistor 104 has a second insulating layer 130c.

[0265] The transistor of one embodiment of the present invention may have a structure as shown in FIGS. 31(C) is a top view of the transistor 111, and the dashed line L1-L The cross sections in the two directions correspond to FIG. 31(D). Also, the dashed line L3-L4 shown in FIG. 32(A). The direction of the dashed dotted line L1-L2 corresponds to the channel length direction. The direction of the dashed dotted line L3-L4 is referred to as the channel width direction.

[0266] The transistor 111 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 141 and the conductive layer 151 connected to each other, and the laminate, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the laminate, the conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 in contact with the insulating layer 175 and the openings provided in the insulating layer 175 and the insulating layer 180 are Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 may also include an insulating layer 180, a conductive layer 142, and a conductive layer 153. An insulating layer (flattening film) or the like may be provided in contact with 52 .

[0267] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 141 and the conductive layer 151 are the insulating layer 16. 0, except that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between The transistor has a similar structure to that of the transistor 105 .

[0268] The transistor of one embodiment of the present invention may have the structure shown in FIGS. 31(E) is a top view of the transistor 112, and the dashed line M1-M The cross sections in the two directions correspond to FIG. 31(F). Also, the dashed line M3-M4 shown in FIG. 32(A) corresponds to the cross section in the direction of the dashed dotted line M1-M2. The direction of the dashed dotted line M3-M4 is referred to as the channel width direction.

[0269] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (the oxide semiconductor layer 130a, the oxide 130a and 130b, and an oxide semiconductor layer 130c). They have a similar configuration.

[0270] The transistor according to one embodiment of the present invention is shown in FIG. 32(C) and (D) are cross-sectional views in the channel length direction and the channel width direction, respectively. As shown in the cross-sectional view of the upper side, a conductive layer 173 is provided between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). It is possible to increase the on-current and control the threshold voltage. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive semiconductor layer 130. It may be shorter than the width.

[0271] The transistor of one embodiment of the present invention has the structure shown in FIG. 34(A) and FIG. 34(B). FIG. 34(A) is a top view, and FIG. 34(B) is a one-dot chain view of the structure shown in FIG. 34(A) is a cross-sectional view corresponding to the line N1-N2 and the dashed line N3-N4. In the top view of FIG. 1, some elements are omitted for clarity.

[0272] The transistor 113 shown in FIG. 34(A) and FIG. 34(B) is a transistor including a substrate 115 and a substrate 11 5, and the oxide semiconductor layer 130 on the insulating layer 120 (the oxide semiconductor layer 130 a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) and a The conductive layer 140 and the conductive layer 150 are spaced apart from each other, and the oxide semiconductor layer 130 is c, and a conductive layer 170 in contact with the insulating layer 160. The semiconductor layer 130, the insulating layer 160 and the conductive layer 170 are formed by the insulating layer 1 on the transistor 113. 90, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the insulating layer 120 The opening is provided so as to reach the

[0273] The configuration of the transistor 113 is different from the configurations of the other transistors described above in that the source Or, since the overlapping area between the drain conductor and the gate conductor is small, parasitic Therefore, the transistor 113 is required to operate at high speed. The top surface of the transistor 113 is shown in FIG. Chemical Mechanical Polishing (CMP) method is used. It is preferable to flatten the surface of the substrate by the flattening process, but it is also possible to adopt a structure in which the flattening process is not performed.

[0274] The conductive layer 140 (source electrode layer) and the conductive layer 15 in the transistor according to one embodiment of the present invention 35(A) and 35(B) (the oxide semiconductor layer 130, As shown in FIG. 1, only the conductive layer 140 and the conductive layer 150 are shown. O S ) of the conductive layer 140 and the conductive layer 150. SD ) may be formed long However, it may be formed short. OS ≧W SD (W SD W OS (below) The gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electrical characteristics of the transistor are improved. Also, as shown in FIG. 35(C), the conductive layer 140 and the conductive layer The insulating film 150 may be formed only in the region overlapping with the oxide semiconductor layer 130 .

[0275] In the transistors of one embodiment of the present invention (transistors 101 to 113), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel transistor. This is called the (s-channel) structure.

[0276] A transistor having an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, and The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are included. In the transistor, the material of the two-layer or three-layer that constitutes the oxide semiconductor layer 130 is appropriately By appropriately selecting the oxide semiconductor layer 130b, a current can be passed through the oxide semiconductor layer 130b. By passing current through 130b, the effect of interface scattering is reduced and a high on-current can be obtained. Therefore, the on-current can be improved by thickening the oxide semiconductor layer 130b. There is a match.

[0277] With the above structure, the electrical characteristics of the transistor can be improved.

[0278] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0279] (Embodiment 3) In this embodiment, components of the transistor shown in Embodiment 2 will be described in detail. do.

[0280] The substrate 115 may be a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or a substrate with an insulating surface. A metal substrate with a surface treatment can be used. Alternatively, a transistor or a photodiode can be used. A silicon substrate on which a metal oxide film is formed, and an insulating layer, wiring, contact plug, etc. are formed on the silicon substrate. A conductive material having a function as a guide may be used. When forming a p-ch type transistor on the substrate, n - Silicon substrate having a conductivity type It is preferable to use a plate. - SOI substrate with type or i-type silicon layer In addition, when the transistor provided on the silicon substrate is a p-ch type, The surface orientation of the surface on which the transistor is formed is a (110) silicon substrate. It is preferable to form a p-ch transistor on the (110) surface to increase the mobility. It is possible.

[0281] The insulating layer 120 serves to prevent the diffusion of impurities from the elements contained in the substrate 115. In addition, it can also play a role in supplying oxygen to the oxide semiconductor layer 130. The edge layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. The insulating layer 120 is preferably an insulating film containing a fluorine atom equivalent measured by a TDS method. The calculated amount of oxygen released is 1.0 x 10 19 atoms / cm 3 More preferably, it is equal to or greater than this. The surface temperature of the film during the TDS analysis was 100°C to 700°C or 10 The temperature range is from 0° C. to 500° C. In addition, the substrate 115 is a substrate on which other devices are formed. In this case, the insulating layer 120 also functions as an interlayer insulating film. It is preferable to perform planarization treatment by CMP or the like so that the surface becomes flat.

[0282] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or other oxide insulating films. , silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. A laminate of the above materials can be used. This is also possible.

[0283] The oxide semiconductor layer 130 includes an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. The organic semiconductor layer 130c can be stacked in order from the insulating layer 120 side to form a three-layer structure.

[0284] Note that in the case where the oxide semiconductor layer 130 is a single layer, Simply use the layer corresponding to 0b.

[0285] When the oxide semiconductor layer 130 has two layers, the layer corresponding to the oxide semiconductor layer 130a and the oxide A lamination structure in which layers corresponding to the organic semiconductor layer 130b are stacked in order from the insulating layer 120 side may be used. In this configuration, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b can be interchanged. It is also possible.

[0286] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide layer 130c has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band). A compound semiconductor is used.

[0287] In such a structure, when an electric field is applied to the conductive layer 170, That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. Therefore, it can be said that the oxide semiconductor layer 130b has a region that functions as a semiconductor. However, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are insulators or semi-insulators. It can also be said that the nucleus has a region that functions in a specific manner.

[0288] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are The oxide semiconductor that can be used preferably contains at least In or Zn. Alternatively, it is preferable that both In and Zn are contained. In order to reduce the variation in the electrical characteristics of the transistors, Al, Ga, Y, or It is preferable to include a stabilizer such as Sn.

[0289] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, the transistor It is possible to give stable electrical properties to the crystals. In addition, the crystals oriented along the c-axis are resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0290] A conductive layer 140 acts as a source electrode layer and a conductive layer 141 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and a single layer or a laminate of a material selected from the group consisting of an alloy of said metallic material and a conductive nitride. In addition, a laminate of low-resistance Cu or Cu-Mn alloy and the above materials can be used. The transistor 105, the transistor 106, the transistor 111, and the transistor In the transistor 112, for example, the conductive layer 141 and the conductive layer 151 are made of W, and the conductive layer 14 2 and the conductive layer 152 may be a laminated film of Ti and Al, for example.

[0291] The above material has a property of extracting oxygen from the oxide semiconductor film. In some regions of the oxide semiconductor film, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The oxygen vacancies are combined with the small amount of hydrogen contained in the film, and the area is significantly Therefore, the n-type region becomes the source or drain of the transistor. It can be made to act as such.

[0292] When W is used for the conductive layer 140 and the conductive layer 150, they may be doped with nitrogen. By doping with nitrogen, the oxygen-pulling property can be weakened to an appropriate degree, resulting in an n-type structure. In addition, the conductive layer 140 and the conductive layer 141 can be prevented from expanding into the channel region. The conductive layer 150 is laminated with an n-type semiconductor layer, and the n-type semiconductor layer is in contact with the oxide semiconductor layer. This also makes it possible to prevent the n-type region from expanding into the channel region. For the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, and indium oxide were used. Indium, tin oxide, indium tin oxide, etc. can be used.

[0293] The insulating layer 160 acting as a gate insulating film may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. etc. may be contained as impurities.

[0294] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0295] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 can be reduced. Since the gate insulating film can be made large, the leakage current due to the tunnel current can be reduced. In addition, it is possible to realize a transistor with a small leakage current. Hafnium has a higher dielectric constant than hafnium oxide, which has an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, hafnium oxide having a crystalline structure is used. Examples of the crystal structure include monoclinic and cubic crystals. However, one aspect of the present invention is not limited to these.

[0296] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When the conductor comes into contact with the insulating layer 120, the density of states caused by nitrogen oxides may increase. The insulating layer 160 is made of, for example, a silicon oxynitride film or An oxide insulating layer such as an aluminum oxynitride film can be used.

[0297] The silicon oxynitride film, which emits a small amount of nitrogen oxide, is This is a membrane that releases more ammonia than it outputs, typically releasing 1×10 18 cm -3 5×10 or more 19 cm -3 The amount of ammonia released is as follows: The surface temperature is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. The amount of release is the amount of

[0298] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0299] The conductive layer 170 acting as a gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni. Conductive films of Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W In addition, alloys of the above materials and conductive nitrides of the above materials may be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are Typically, the material may be a laminate of tungsten or tungsten and titanium nitride. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a fluorine atom.

[0300] The conductive layer 170 may be made of In-Ga-Zn oxide, zinc oxide, indium oxide, or tin oxide. Alternatively, a conductive oxide layer such as indium tin oxide may be used.

[0301] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor In transistor 106, transistor 109, transistor 110, and transistor 112, By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer is made n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0302] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In the transistors 107, 108, and 111, the insulating layer 175 is formed of an oxide layer. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Aluminum oxide has a high barrier effect of preventing the permeation of both water and oxygen. The aluminum film is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. Prevents oxygen from being mixed into the oxide semiconductor layer 130, prevents oxygen from being released from the oxide semiconductor layer, and prevents the insulating layer 1 It is suitable for use as a protective film having the effect of preventing unnecessary release of oxygen from 20. .

[0303] An insulating layer 180 is preferably formed on the insulating layer 175. The insulating layer 180 may include an oxide. magnesium oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide The insulating film contains one or more of neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0304] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than the stoichiometric composition. It is preferable that oxygen released from the insulating layer 180 is transported through the insulating layer 160 to the oxide semiconductor Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, resulting in a stable transistor. The electrical properties can be obtained.

[0305] In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. The electrical characteristics of transistors tend to deteriorate as the channel width decreases. If the on-state current is increased, the on-state current decreases.

[0306] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and the on-state voltage of the transistor is The flow can be increased.

[0307] In the transistor of one embodiment of the present invention, the channel width of the oxide semiconductor layer 130 is Since the gate electrode layer (conductive layer 170) is formed so as to electrically surround the In addition to the gate electric field from the direction perpendicular to the top surface of the compound semiconductor layer 130, the gate electric field from the direction perpendicular to the side surface is also applied to the compound semiconductor layer 130. In other words, the gate electric field is applied from the entire direction to the channel forming layer. Since a large electric field is applied, the effective channel width is enlarged, and the on-current is further increased. can be.

[0308] The various films such as the metal film, the semiconductor film, and the inorganic insulating film described in this embodiment are typically The thin film can be formed by a deposition method or a plasma CVD method, but other methods, such as thermal CVD, are also possible. An example of the thermal CVD method is MOCVD (Metal Organic Chemical Vapor Deposition). Chemical Vapor Deposition (ALD) and Atom These include the ic Layer Deposition method.

[0309] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0310] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the inside of the chamber is By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0311] In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is introduced into the chamber. The film is formed by repeatedly introducing and reacting the raw material gas into the inert gas ( For example, two or more kinds of gases (argon, nitrogen, etc.) may be introduced as a carrier gas. The source gases may be supplied to the chamber in sequence. In this case, multiple source gases are not mixed. In this manner, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is exhausted by evacuation, and then the second source gas is introduced. The first source gas may be introduced into the substrate so as to adsorb and react with the surface of the substrate to form a first layer. The second source gas is introduced later and adsorbed and reacted with the second layer, which is then formed on the first layer. The gas introduction sequence is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is injected. This is suitable for fabricating miniaturized FETs.

[0312] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a -Zn-O film, trimethylindium (In(CH3)3), trime Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and triethyl gallium may be used instead of trimethyl gallium. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0313] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide hafnium Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide The raw material gas is made by vaporizing hafnium (such as hafnium amide) and ozone ( Two types of gases are used:

[0314] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas made by vaporizing ethanol, etc., and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, and aluminium. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0315] For example, when forming a silicon oxide film using a deposition system that uses ALD, The silane is adsorbed on the surface to be coated and the radicals of oxidizing gases (O2, nitrous oxide) are provided. is fed to react with the adsorbate.

[0316] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by sequentially introducing WF6 gas and H The tungsten film is formed by sequentially introducing the two gases. Note that SiH4 gas is used instead of B2H6 gas. A gas may also be used.

[0317] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are introduced in sequence to form a GaO layer, and Then, Zn(CH3)2 gas and O3 gas are introduced in sequence to form a ZnO layer. The order of these layers is not limited to this example. It is also possible to form a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer. Alternatively, H2O gas obtained by bubbling an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not contain O2.

[0318] A facing target sputtering device can also be used to form the oxide semiconductor layer. The film formation method using a facing target sputtering device is called VDSP (vapor deposition sputtering). It can also be called the "Synopsis of the Transformation SP."

[0319] By forming an oxide semiconductor layer using a facing target sputtering apparatus, This reduces plasma damage during the deposition of the semiconductor layer. In addition, by using a facing target sputtering device, low pressure Since it is possible to form the oxide semiconductor layer at low temperature, the impurity concentration (e.g., hydrogen, dilute Gases (such as argon), water, etc.) can be reduced.

[0320] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0321] (Embodiment 4) In this embodiment, a material of an oxide semiconductor that can be used in one embodiment of the present invention will be described. Reveal.

[0322] The oxide semiconductor preferably contains at least indium or zinc. In addition, the element M preferably contains aluminum and zinc. It is preferable that the element M contains gallium, yttrium, tin, or the like. These include boron, silicon, titanium, iron, nickel, germanium, zirconium, and molybdenum. Lithium, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, may contain one or more selected from the group consisting of magnesium, etc.

[0323] Here, a case will be considered in which the oxide semiconductor contains indium, the element M, and zinc.

[0324] First, with reference to Figs. 36(A), 36(B), and 36(C), the oxide according to the present invention A preferred range of the atomic ratio of indium, element M, and zinc contained in the semiconductor will be explained. The atomic ratio of oxygen is not described. The terms for the atomic ratio of element m, element M, and zinc are [In], [M], and [Zn], respectively. Let us assume that.

[0325] In Figures 36(A), 36(B), and 36(C), the dashed lines indicate [In]:[M] :[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):2, [I n]:[M]:[Zn]=(1+α):(1-α):3, ]:[M]:[Zn]=(1+α):(1-α):4 atomic ratio line, and [ This line represents the atomic ratio of In:M:Zn=(1+α):(1-α):5. .

[0326] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β is :[M]:[Zn]=1:3:β atomic ratio line, [In]:[M]:[Zn] = 1:4:β atomic ratio line, [In]:[M]:[Zn]=2:1:β atoms The line with the atomic ratio of [In]:[M]:[Zn]=5:1:β Represents in.

[0327] In addition, the atomic ratio of [In]:[M]:[Zn]=0:2:1 or close to it, as shown in FIG. The oxide semiconductors in question tend to have a spinel type crystal structure.

[0328] In FIG. 36A and FIG. 36B, indium oxide semiconductor included in an oxide semiconductor of one embodiment of the present invention is 1 shows an example of a preferred range of the atomic ratio of element M, element M, and zinc.

[0329] As an example, FIG. 37 shows InMZnO, where [In]:[M]:[Zn]=1:1:1. 4. Also, Fig. 37 shows the crystal structure of InMZn The crystal structure of the layer having M, Zn, and oxygen shown in FIG. The metal element in layer n) represents element M or zinc. In this case, element M and zinc The ratio of elements M and zinc is equal. The elements M and zinc can be substituted, and the arrangement is random. .

[0330] InMZnO4 has a layered crystal structure (also called a layered structure), as shown in Figure 37. The layer containing indium and oxygen (hereinafter referred to as the In layer) is 1, while the element M, zinc, and The (M,Zn) layer containing oxygen is called 2.

[0331] Indium and the element M can be substituted for each other. Therefore, the element M in the (M, Zn) layer M can be replaced with indium and expressed as an (In,M,Zn) layer. In that case, the In layer It has a layered structure with one layer and two (In,M,Zn) layers.

[0332] In an oxide semiconductor with an atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer is For [In] and [M], the (M,Zn) layer is three. When [Zn] is large, when the oxide semiconductor crystallizes, the (M,Zn ) layer increases.

[0333] However, in the oxide semiconductor, the number of (M, Zn) layers for one In layer is a non-integer. In this case, multiple types of layered structures are used, each with an In layer and an integer number of (M, Zn) layers. For example, when [In]:[M]:[Zn]=1:1:1.5, A layered structure with 1 In layer and 2 (M,Zn) layers, and a layered structure with 3 (M,Zn) layers. In some cases, the resulting structure may be a layered structure in which a crystalline structure and a crystalline structure are mixed.

[0334] For example, when an oxide semiconductor is deposited by a sputtering device, the ratio of the atoms in the target may deviate from the ratio of the atoms in the target. In particular, depending on the substrate temperature during film formation, the [Zn ] may result in the film's [Zn] being smaller than that of the

[0335] In addition, multiple phases may coexist in an oxide semiconductor (e.g., two-phase coexistence, three-phase coexistence, etc.). For example, in the atomic ratio [In]:[M]:[Zn]=0:2:1, which is close to the atomic ratio In this case, two phases, a spinel type crystal structure and a layered crystal structure, tend to coexist. At the atomic ratio near the atomic ratio of [M]:[Zn]=1:0:0, In oxide semiconductors, two phases, a cubic crystal structure and a layered crystal structure, tend to coexist. When they coexist, grain boundaries form between the different crystal structures. It may be formed.

[0336] In addition, by increasing the indium content, the carrier mobility (electron mobility) of the oxide semiconductor is improved. This is because the oxide semiconductor having indium, element M and zinc can be In conductors, the s-orbitals of heavy metals mainly contribute to carrier conduction, and the indium content By increasing the indium content, the area where the s orbitals overlap becomes larger. Oxide semiconductors with a high indium content have a higher carrier mobility than oxide semiconductors with a low indium content. This is because

[0337] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0, and In the atomic ratios of 0.1 to 0.5 and their neighboring values ​​(for example, region C shown in FIG. 36(C)), the insulating properties are high. do.

[0338] Therefore, the oxide semiconductor of one embodiment of the present invention has high carrier mobility and few grain boundaries. It is preferable that the atomic ratio is as shown in region A in FIG. 36(A), which tends to form a layer structure having no atomic number. I wish.

[0339] Also, in region B shown in FIG. 36(B), [In]:[M]:[Zn]=4:2:3 to 4. 1 and its neighboring values. For example, the atomic ratio [In]:[M] :[Zn]=5:3:4. The oxide semiconductor having the atomic ratio shown in region B is In particular, it is an excellent oxide semiconductor having high crystallinity and high carrier mobility.

[0340] The condition for an oxide semiconductor to form a layered structure is not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. However, depending on the formation conditions, a layered structure may or may not be formed. Therefore, the illustrated region is a region showing an atomic ratio in which the oxide semiconductor has a layered structure, The boundaries between areas A and C are not strict.

[0341] Next, the case where the oxide semiconductor is used for a transistor will be described.

[0342] By using the oxide semiconductor in a transistor, carrier scattering at grain boundaries can be prevented. This allows the realization of transistors with high field effect mobility. In addition, a highly reliable transistor can be realized.

[0343] In addition, it is preferable to use an oxide semiconductor with low carrier density for the transistor. For example, oxide semiconductors have a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That should be enough.

[0344] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a small carrier generation source. Since the carrier density can be reduced, the high purity intrinsic or substantially high purity Since the density of defect states in an intrinsic oxide semiconductor is low, the density of trap states may also be low. There is a match.

[0345] In addition, it takes a long time for the charges trapped in the trap states of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel region is formed in an oxide semiconductor may have unstable electrical characteristics. There is.

[0346] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0347] Here, the influence of each impurity in an oxide semiconductor will be described.

[0348] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, it becomes an oxide. Defect levels are formed in the semiconductor. The concentration of silicon and carbon near the interface with the layer to be treated was measured by secondary ion mass spectrometry (SIM S: Secondary Ion Mass Spectrometry The concentration of 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The control is performed so as to have a region where:

[0349] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals may form a carrier. Transistors using oxide semiconductors containing metals tend to be normally-on. Therefore, it is possible to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor is preferably The concentration (obtained by SIMS analysis) is 1×10 18 atoms / cm 3 The following are the preferred Or 2×10 16 atoms / cm 3 The control is performed so as to have a region where:

[0350] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The density increases and it becomes easier to make the oxide semiconductor n-type. The transistor using this oxide semiconductor is likely to be normally on. In the oxide semiconductor, it is preferable that the nitrogen content is reduced as much as possible. The nitrogen concentration (obtained by SIMS analysis) is 5×10 19 atoms / cm 3 Not yet Less than 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 at oms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The area where The control is performed so that the

[0351] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom to form a carbide. Therefore, the hydrogen-containing oxide semiconductor The transistor using this type of transistor is likely to be normally on. Specifically, the hydrogen concentration in the oxide semiconductor is preferably as low as possible. (Concentration obtained by SIMS analysis) is 1×10 20 atoms / cm 3 Less than, preferred 1×10 19 atoms / cm 3 less than 5×10 18 atoms / c m 3 less than 1×10 18 atoms / cm 3 It has an area that is less than Control it as follows.

[0352] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor As described above, the highly purified oxide can provide stable electrical properties. The off-state current of a transistor using a semiconductor as a channel formation region is extremely small. For example, When the voltage between the source and drain is set to about 0.1V, 5V, or 10V, The off-current per channel width of the transistor is reduced to several yA / μm to several zA / μm. It becomes possible to do so.

[0353] Next, the case where the oxide semiconductor has a two-layer structure or a three-layer structure will be described. A barrier layer made of an insulator is in contact with the stacked structure of the semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S3. The band diagram of the insulator in contact with the stacked structure of the oxide semiconductor S2 and the oxide semiconductor S3. The oxide semiconductor S1 is an oxide semiconductor layer 1. 30a, the oxide semiconductor S2 is the oxide semiconductor layer 130b, and the oxide semiconductor S3 is the oxide semiconductor This corresponds to layer 130c.

[0354] FIG. 38A shows an insulator I1, an oxide semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S3. FIG. 38 is an example of a band diagram in the thickness direction of a laminated structure having an insulator I1 and an insulator I2. (B) is a semiconductor having an insulator I1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. 1 is an example of a band diagram in the thickness direction of a laminated structure. Therefore, the insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator The energy level (Ec) at the bottom of the conduction band of I2 is shown.

[0355] The oxide semiconductors S1 and S3 have a lower energy of the conduction band than the oxide semiconductor S2. The energy level is close to the vacuum level, typically the energy level at the bottom of the conduction band of the oxide semiconductor S2. The difference between the energy level at the bottom of the conduction band of the oxide semiconductor S1 and the oxide semiconductor S3 is 0. 15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or less In other words, the oxide semiconductor S1 has a higher electron affinity than the oxide semiconductor S3. The electron affinity of the semiconductor S2 is large, and the electron affinity of the oxide semiconductor S1 and the oxide semiconductor S3 are , the difference between the electron affinity of the oxide semiconductor S2 is 0.15 eV or more, or 0.5 eV or more, It is also preferable that the electron transport potential is 2 eV or less, or 1 eV or less.

[0356] As shown in FIG. 38(A) and FIG. 38(B), an oxide semiconductor S1, an oxide semiconductor S2 In the oxide semiconductor S3, the energy level at the bottom of the conduction band changes gradually. Then, it can be said that the band changes continuously or that the junction is continuous. In order to have such a property, the interface between the oxide semiconductor S1 and the oxide semiconductor S2 or the oxide semiconductor S The defect level density of the mixed layer formed at the interface between the oxide semiconductor S2 and the oxide semiconductor S3 is reduced. stomach.

[0357] Specifically, the oxide semiconductor S1 and the oxide semiconductor S2, the oxide semiconductor S2 and the oxide semiconductor S 3) A mixture with a low defect level density due to the common element (main component) other than oxygen. For example, the oxide semiconductor S2 may be an In-Ga-Zn oxide semiconductor. In this case, the oxide semiconductor S1 and the oxide semiconductor S3 are In-Ga-Zn oxide semiconductors, It is preferable to use a Ga-Zn oxide semiconductor, gallium oxide, or the like.

[0358] At this time, the main carrier path is the oxide semiconductor S2. Defects at the interface with the semiconductor S2 and at the interface between the oxide semiconductor S2 and the oxide semiconductor S3 Since the level density can be reduced, the effect of interface scattering on carrier conduction is small. A high on-current can be obtained.

[0359] When an electron is captured in a trap level, the captured electron behaves like a fixed charge. Therefore, the threshold voltage of the transistor is shifted in the positive direction. By providing the oxide semiconductor S3, the trap level can be moved away from the oxide semiconductor S2. By adopting this configuration, the threshold voltage of the transistor is shifted in the positive direction. This can prevent the above from happening.

[0360] The oxide semiconductors S1 and S3 have sufficiently high electrical conductivity compared to the oxide semiconductor S2. In this case, the oxide semiconductor S2 and the oxide semiconductor S1 are used. The interface between the oxide semiconductor S1 and the oxide semiconductor S2 and the interface between the oxide semiconductor S3 and the channel region are mainly For example, the oxide semiconductor S1 and the oxide semiconductor S3 have the following structure: Therefore, an oxide semiconductor having an atomic ratio shown in region C where the insulating property is high may be used.

[0361] In particular, when an oxide semiconductor having an atomic ratio shown in region A is used for the oxide semiconductor S2, In the compound semiconductor S1 and the oxide semiconductor S3, [M] / [In] is 1 or more, preferably 2 or more. It is preferable to use an oxide semiconductor having the above atomic ratio. Therefore, the ratio [M] / ([Zn]+[In]) is 1 or more, which is sufficient to obtain high insulation. It is preferable to use an oxide semiconductor having such an atomic ratio.

[0362] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0363] (Embodiment 5) A structure of an oxide semiconductor that can be used in one embodiment of the present invention will be described below.

[0364] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0365] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0366] <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0367] Oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, c-axis-aligned (CAAC-OS) crystalline oxide semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l ike oxide semiconductor and amorphous oxide semiconductor. do.

[0368] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- Examples of such materials include OS, polycrystalline oxide semiconductors, and nc-OS.

[0369] Amorphous structures are generally isotropic, have no inhomogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and the short-range order is not fixed. It is said that...

[0370] From the other perspective, a stable oxide semiconductor can be considered as completely amorphous. In addition, it is not isotropic (for example, in a small area) and cannot be called an oxide semiconductor. An oxide semiconductor having a periodic structure in a crystal structure cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic but has voids (also called voids) and is unstable. In terms of instability, a-like OS is physically an amorphous oxide. Close to semiconductors.

[0371] <caac-os> First, let me explain about CAAC-OS.

[0372] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0373] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals is analyzed by the out-of-plane method. As shown in FIG. 39(A), a peak appears at a diffraction angle (2θ) of about 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so The crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be seen that the crystal is oriented in a direction perpendicular to the upper surface. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the center are due to the crystal structure classified into the space group Fd-3m. It is preferable that -OS does not show such a peak.

[0374] On the other hand, in-pla, X-rays are incident on the CAAC-OS in a direction parallel to the surface on which the film is to be formed. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I The lattice constant is the (110) plane of the nGaZnO4 crystal. The 2θ is fixed at around 56°. The analysis (φ scan) is performed while rotating the sample around the axis (φ axis) of the normal vector of the sample surface. Even if the measurement is performed, no clear peak appears, as shown in FIG. When φ is scanned with 2θ fixed at around 56° for nO4, as shown in Figure 39(C). As shown in Fig. 1, six peaks are observed that are attributable to crystal planes equivalent to the (110) plane. From the structural analysis using RD, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0375] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the CAAC-OS surface. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern (control pattern) as shown in FIG. This is also called the limited-area electron diffraction pattern.) may appear. This diffraction pattern includes In The spots are due to the (009) plane of the GaZnO4 crystal. In some cases, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the material is formed. On the other hand, for the same sample, the direction of the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident vertically is shown in Figure 39(E). As shown in Figure 39(E), a ring-shaped diffraction pattern is observed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed that the pellets in the CAAC-OS It can be seen that the a-axis and b-axis of the slit have no orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. It is considered that the second ring in Figure 39(E) is due to the (110) plane, etc. It is possible.

[0376] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and the diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. In some cases, it may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0377] Figure 40(A) shows a high-resolution T The TEM image is shown. For high-resolution TEM imaging, spherical aberration correction is used. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, the atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed that.

[0378] From Figure 40(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. It has been found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used with CANC (C-Axis Aligned nan The pellets are also called oxide semiconductors with CAAC -OS surface or top surface unevenness, and CAAC-OS surface or top surface unevenness is parallel to the surface.

[0379] In addition, Fig. 40(B) and Fig. 40(C) show CAAC images observed from a direction approximately perpendicular to the sample surface. 40(D) ​​and 40(E) show Cs-corrected high-resolution TEM images of the -OS plane. These are images obtained by processing the images of Figures 40(B) and 40(C), respectively. First, the method of performing the fast Fourier transform (FFT) on FIG. Then, the FFT image is obtained by Fourier Transform (FFT) processing. In the FFT image, the origin is used as the reference point, and the distance is 2.8 nm. -1 From 5.0 nm -1 Remaining range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT: Inverse Fast Fourier Transform (IFFT) processing is used to The image thus obtained is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. The sequence is shown.

[0380] In FIG. 40(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area surrounded by the dashed line is The area indicated by the dashed line is the connection between the pellets. The broken line indicates a hexagonal shape, so it can be seen that the pellets are hexagonal. The shape of the dot is not limited to a regular hexagon, and is often a non-regular hexagon.

[0381] In FIG. 40(E), a dotted line separates an area with a uniform lattice arrangement from an area with a different uniform lattice arrangement. Even in the vicinity of the dotted line, no clear grain boundaries can be confirmed. When you connect the neighboring lattice points, you can get a distorted hexagon, pentagon, or / and heptagon. In other words, by distorting the lattice arrangement, the formation of grain boundaries can be suppressed. This is because the bond distance between atoms in the CAAC-OS is The reason is that the bond distance between atoms changes due to the substitution of metal elements. Therefore, it is believed that distortion can be tolerated.

[0382] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an ane-anchored crystal. do.

[0383] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is improved by the incorporation of impurities. In other words, the CAAC-OS can be regarded as an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0384] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor and rearrange the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0385] <nc-os> Next, we will explain nc-OS.

[0386] The following describes the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of the nc-OS do not have any orientation.

[0387] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed in the region shown in FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. In addition, the diffraction pattern (nm) when an electron beam with a probe diameter of 1 nm was incident on the same sample was The electron diffraction pattern (B) is shown in FIG. 41(B). From FIG. 41(B), a ring-shaped region Therefore, nc-OS has a probe diameter of 50 nm. Although no order was observed by irradiating the electron beam, the order was observed by irradiating the electron beam with a probe diameter of 1 nm. By projecting the images, order is confirmed.

[0388] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 41(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS is ordered. It can be seen that the crystals have highly crystalline regions. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0389] FIG. 41(D) shows the Cs-corrected high resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. As shown in Fig. 1, there are areas where crystals can be confirmed, and areas where no clear crystals can be confirmed. The crystal part in the nc-OS has a size of 1 nm to 10 nm. In particular, the size of the crystal part is often between 1 nm and 3 nm. An oxide semiconductor having a diameter of more than 0 nm and less than 100 nm is called a microcrystalline oxide semiconductor. It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, below, the crystalline part of the nc-OS may be called a pellet.

[0390] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. There is no regularity in the crystal orientation between different pellets. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0391] In addition, since the crystal orientation between pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor can be called an oxide semiconductor.

[0392] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0393] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0394] Figure 42 shows a high-resolution cross-sectional TEM image of the a-like OS. This is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. ) is 4.3 × 10 8 e - / nm 2 Electrons (e - ) High a-like OS after irradiation 42(A) and 42(B) show that the a-like OS It can be seen that from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. It can be seen that the shape of the bright regions changes after electron irradiation. It is estimated to be in the degree range.

[0395] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0396] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample in is also an In-Ga-Zn oxide.

[0397] First, high-resolution cross-sectional TEM images of each sample are obtained. Each of the above has a crystalline portion.

[0398] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn- It is known that the structure has a total of nine layers, including six O layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is the same as the lattice spacing (also called the d value) of the (009) plane. The value is about 0.29 nm, which is determined by crystal structure analysis. In the figure below, the areas where the lattice spacing is between 0.28 nm and 0.30 nm are InGaZn The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0399] Figure 43 shows an example of the average size of the crystal parts (22 to 30 places) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. The crystal part of the OS grows larger according to the cumulative dose of electrons used in obtaining the TEM image. From Figure 42, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that was a nucleus (also called the initial nucleus) is filled with electrons (e - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 1.9 nm in the nc The cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals in the range from The size of the crystalline parts of the nc-OS and CAAC-OS was The results show that the thicknesses are approximately 1.3 nm and 1.8 nm, respectively. A Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. Electron beam irradiation conditions The acceleration voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0400] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. That is, compared with the nc-OS and CAAC-OS, the a-like OS It is clear that this is an unstable structure.

[0401] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of the nc-OS is 78.6% or more and less than 92.3% of that of the oxide semiconductor. The density of the CAAC-OS is 92.3% or more that of single-crystal oxide semiconductors with the same composition. The density of an oxide semiconductor having a density of less than 78% of that of a single crystal oxide semiconductor is less than 0.00%. It is difficult to do so.

[0402] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0403] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions. The density can be estimated by using a weighted average. It is preferable to estimate them together.

[0404] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds.

[0405] <Carrier density in oxide semiconductors> Next, the carrier density of an oxide semiconductor will be described below.

[0406] Factors that affect the carrier density in oxide semiconductors include oxygen vacancies in the oxide semiconductor ( Vo), or impurities in the oxide semiconductor.

[0407] When the number of oxygen vacancies in an oxide semiconductor increases, hydrogen bonds to the oxygen vacancies (this state is called VoH). When the oxide semiconductor is heated, the density of defect states increases. When the impurities are added, the density of defect states increases. By controlling the potential density, the carrier density of the oxide semiconductor can be controlled.

[0408] Here, a transistor in which an oxide semiconductor is used for a channel region will be considered.

[0409] Suppression of negative shift of the threshold voltage of a transistor or suppression of the off-state current of a transistor In order to reduce the carrier density, it is preferable to reduce the carrier density of the oxide semiconductor. In order to reduce the carrier density of an oxide semiconductor, the impurity concentration in the oxide semiconductor is In this specification and the like, the impurity concentration is low and the defect level density is low. A low density of recessed states is called high purity intrinsic or substantially high purity intrinsic. The carrier density of semiconductors is 8×10 15 cm -3 Less than 1 x 10 11 cm -3 less than 1×10 10 cm -3 Less than 1 x 10 -9 cm - 3 That should be enough.

[0410] On the other hand, the improvement of the on-state current of a transistor or the field effect mobility of a transistor In this case, it is preferable to increase the carrier density of the oxide semiconductor. In order to increase the carrier density of an oxide semiconductor, the impurity concentration of the oxide semiconductor is slightly Alternatively, the defect state density of the oxide semiconductor may be increased slightly. It is better to make the band gap of the semiconductor smaller. For example, the Id-Vg In the range where the on / off ratio of the characteristic can be obtained, the impurity concentration is slightly high or the defect level Oxide semiconductors with slightly higher density can be considered essentially intrinsic. As a result, the band gap becomes smaller, and the thermally excited electrons (capacitors) The oxide semiconductor with an increased density of valence oxides can be considered to be essentially intrinsic. When an oxide semiconductor with high resistance is used, the threshold voltage of a transistor is lowered. .

[0411] The oxide semiconductor with the increased carrier density is slightly n-type. An oxide semiconductor with an increased carrier density may be called a "slightly-n" oxide semiconductor. stomach.

[0412] The carrier density of a substantially intrinsic oxide semiconductor is 1×10 5 cm -3 More than 1×10 18 c m -3 Less than 1×10 is preferable. 7 cm -3 More than 1×10 17 cm -3 The following is preferred: 1×10 9 cm -3 5×10 or more 16 cm -3 More preferably, 1×10 10 cm -3 More than 1×10 16 cm -3 More preferably, 1×10 11 cm -3 1 more ×10 15 cm -3 The following is even more preferred:

[0413] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0414] (Embodiment 6) In this embodiment, a package containing an image sensor chip and a camera module An example will be described. The image sensor chip has a structure of an imaging device according to one embodiment of the present invention. The composition can be used.

[0415] FIG. 44(A) is a perspective view showing the appearance of the upper surface side of a package containing an image sensor chip. The package includes a package substrate 810 for fixing an image sensor chip 850, a cover It has a bar glass 820 and an adhesive 830 for bonding the two together.

[0416] FIG. 44(B) is a perspective view of the bottom surface of the package. The structure of BGA (Ball grid array) with solder balls as bumps 840 is used. In addition to BGA, LGA (Land grid array) and PGA (P in Grid Array) etc.

[0417] FIG. 44(C) shows a package in which the cover glass 820 and part of the adhesive 830 are omitted. FIG. 44(D) is a cross-sectional view of the package. Package Substrate An electrode pad 860 is formed on the substrate 810, and the electrode pad 860 and the bump 840 are The electrode pad 860 is electrically connected to the electrode pad 860 via a hole 880 and a land 885. is electrically connected to the electrodes of the image sensor chip 850 by wires 870. is.

[0418] FIG. 45(A) shows a camera in which an image sensor chip is housed in a lens-integrated package. FIG. 1 is a perspective view of the appearance of the upper surface side of a camera module. A package substrate 811 that fixes the cap 851, a lens cover 821, and a lens 835 In addition, between the package substrate 811 and the image sensor chip 851, An IC chip 890 having functions such as a driving circuit for the image device and a signal conversion circuit is also provided. It has a SiP (System in package) configuration.

[0419] FIG. 45B is a perspective view showing the appearance of the lower surface side of the camera module. The bottom surface and four side surfaces of the package 11 are provided with lands 841 for mounting. The structure is a lat no-lead package. Note that this structure is just an example. It can be QFP (Quad flat package) or the BGA mentioned above. stomach.

[0420] FIG. 45(C) shows a module with the lens cover 821 and a portion of the lens 835 omitted. FIG. 45(D) is a cross-sectional view of the camera module. A part of the electrode pad 861 is used as the image sensor chip. The electrodes of the chip 851 and the IC chip 890 are electrically connected by wires 871. is.

[0421] By housing the image sensor chip in a package of the above type, mounting becomes easy. Therefore, the semiconductor device and the electronic device can be incorporated in various semiconductor devices and electronic devices.

[0422] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0423] (Embodiment 7) The imaging device, the display device, and the semiconductor device including both of the imaging device and the display device according to one embodiment of the present invention can be used. Examples of electronic devices that can be used include display devices, personal computers, and image storage devices equipped with recording media. image reproduction devices, mobile phones, portable game consoles, portable data terminals, e-book terminals Cameras such as video cameras and digital still cameras, goggle-type displays (head Mounted displays), navigation systems, audio playback devices (car audio, digital digital audio players, copiers, fax machines, printers, printer-combined machines, These include automated teller machines (ATMs) and vending machines. An example is shown in Figure 46.

[0424] FIG. 46(A) shows a surveillance camera having a housing 951, a lens 952, a support portion 953, etc. As one of the components for acquiring images in the surveillance camera, an imaging device according to one aspect of the present invention is used. The term "surveillance camera" is a common name and does not limit its use. For example, a device that has the function of a surveillance camera is a camera or a video camera. Also called La.

[0425] FIG. 46B shows a video camera, which includes a first housing 971, a second housing 972, a display unit 973, The operation key 974, the lens 975, the connection part 976, etc. 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. As one of the components for acquiring an image in the video camera, one aspect of the present invention is The imaging device may include:

[0426] FIG. 46C shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone 9 63, a light emitting unit 967, a lens 965, etc. Acquire an image with the digital camera The imaging device according to one embodiment of the present invention can be provided as one of the components for performing the imaging.

[0427] FIG. 46D shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, and a wristband 9 The display unit 932 has a time signal, ... A part for acquiring an image in the information terminal. The imaging device according to one embodiment of the present invention can be provided as an imaging device.

[0428] FIG. 46E shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 909, etc. The portable game machine shown in FIG. and a display unit 904, the number of display units that the portable game machine has is not limited to this. The present invention is not limited to the above. The imaging device may include an imaging device according to the present invention.

[0429] FIG. 46(F) shows a portable data terminal, which includes a housing 911, a display unit 912, a camera 919, etc. The display portion 912 has a touch panel function through which data can be input and output. As one of the components for acquiring images in the portable data terminal, the imaging device according to one aspect of the present invention is The imaging device may be provided.

[0430] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0431] 20 pixels 20a pixels 20b pixels 20c pixels 20d pixels 21 Pixel Array 22 Circuit 23 Circuit 24 circuits 25 Circuit 26 Control circuit 27 Comparator Circuit 29 Counter Circuit 30 Circuit 35 Circuit section 41 Transistor 42 Transistor 43 Transistor 44 Transistor 45 Transistor 46 Transistor 47 Transistor 51 Transistor 52 Transistor 53 Transistor 61 Wiring 61a Wiring 61d Wiring 62 Wiring 63 Wiring 65 Wiring 71 Wiring 72 Wiring 73 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 80a Insulation layer 80b Insulating layer 81a Insulating layer 81c Insulating layer 81d Insulating layer 81g Insulation layer 81h Insulation layer 81j Insulation layer 81k Insulation layer 82 Conductors 91 Wiring 92 Wiring 93 Wiring 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 113 Transistor 115 Substrate 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide semiconductor layer 130c Oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive Layer 150 Conductive layer 151 Conductive layer 152 Conductive layer 160 Insulating layer 170 Conductive Layer 171 Conductive Layer 172 Conductive Layer 173 Conductive Layer 175 Insulating Layer 180 Insulating layer 190 Insulating Layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 401 Connection 401a metal layer 401b Metal layer 402 Connection 402a metal layer 402b metal layer 403 Connection 403a metal layer 403b metal layer 405 Metal layer 406 Metal layer 561 Photoelectric conversion layer 562 Transparent conductive layer 563 Semiconductor Layer 564 Semiconductor Layer 565 Semiconductor Layer 566 Electrode 566a conductive layer 566b Conductive layer 567 Bulkhead 568 Hole injection blocking layer 569 Electron injection blocking layer 571 Wiring 571a Conductive layer 571b Conductive layer 588 Wiring 600 Single crystal silicon substrate 620p + region 630p - region 640 n-type region 650 p + region 660 Active layer 670 Single crystal silicon substrate 810 Package Substrate 811 Package Substrate 820 Cover Glass 821 Lens cover 830 Adhesive 835 Lens 840 Bump 841 rand 850 Image Sensor Chip 851 Image sensor chip 860 Electrode Pads 861 Electrode Pads 870 Wire 871 Wire 880 through hole 885 rand 890 IC chips 901 Case 902 Case 903 Display section 904 Display section 905 Mike 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 Case 912 Display section 919 Camera 931 Case 932 Display section 933 Wristband 935 Button 936 Crown 939 Camera 951 Case 952 Lens 953 Support part 961 Case 962 Shutter button 963 Mike 965 Lens 967 Light emitting part 971 Case 972 Case 973 Display section 974 Operation Key 975 Lens 976 Connection 1100 layers 1200 layers 1300 layers 1500 Diffraction Grating 1600 layers 1700 Support Board 1800 peeling layer 2500 Insulation Layer 2510 Light blocking layer 2520 Organic resin layer 2530 Color Filter 2530a Color Filter 2530b Color Filter 2530c Color Filter 2540 Microlens Array 2550 Optical conversion layer 2560 Insulation layer

Claims

[Claim 1] An imaging device having a first layer, a second layer, and a third layer, the second layer being provided between the first layer and the third layer, the first layer having a photoelectric conversion element, the second layer having a first transistor having an active layer made of an oxide semiconductor, a first insulating layer, and a first metal layer, the third layer having a second transistor having an active layer or active region made of silicon, a second insulating layer, and a second metal layer, the first metal layer and the second metal layer being mainly composed of the same metal element, and the first metal layer being a region embedded in the first insulating layer. an upper surface of a gate electrode of the first transistor and an upper surface of a gate electrode of the second transistor facing each other, the upper surface of the gate electrode of the first transistor facing each other, the upper surface of the gate electrode of the first transistor facing each other, the upper surface of the gate electrode of the first transistor facing each other, the upper surface of the gate electrode of the second ... second transistor facing each other, the upper surface of the gate electrode of the first transistor facing each other, the upper surface of the gate electrode of the first transistor facing each other, the upper surface of the gate electrode of the second transistor facing each other, the upper surface of the gate electrode of the first transistor facing each other, the upper surface of the gate electrode of the second transistor facing each other, the upper surface of the gate electrode of the first transistor facing each other, the upper surface of the gate electrode of the first transistor facing each other, the upper surface of the gate electrode of the second transistor facing each other, the upper surface of the gate electrode of the first transistor facing each other, the upper surface of the gate electrode of the second transistor facing each other, the upper surface of the gate electrode of the first transistor facing each other, the upper surface of

Images