Processing device, processing system and processing method

Abstract

To provide a processing device, etc. which can reduce design costs and facilitate timing design.SOLUTION: A processing device comprises: toggle signal reception means which receives a toggle signal in which the value changes between two values, at timing of pulses of a frequency-divided clock signal in which a periodic pattern signal in which predetermined pulses of a mask pulse number smaller than a periodic pulse number are masked is repeated, among continuous pulses of the periodic pulse number of an input clock signal; and communication means which communicates with the other processing device operated by the frequency-divided clock signal, at the timing of the pulses of the frequency-divided clock signal, identified by using the toggle signal, among the pulses of the input clock signal.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] The present disclosure relates to a processing device, a processing system, and a processing method, and more particularly to a processing device, a processing system, and a processing method for communicating with a communication partner to which a divided clock signal generated by rational frequency division is supplied. [Background technology]

[0002] In a digital signal processing circuit including multiple circuit blocks, the optimal operating frequency in terms of circuit size and power consumption is determined according to the content of signal processing that each of the multiple circuit blocks processes. Therefore, the optimal operating frequency of the multiple circuit blocks is not necessarily the same.

[0003] As a method for flexibly providing a clock signal with an optimum frequency for each circuit block, there is a method for generating a clock signal with a lower frequency from a clock signal with a certain frequency by performing frequency division.

[0004] There exists a clock signal divider circuit that divides a clock signal of a certain frequency to generate a clock signal of a lower frequency, and the division ratio, i.e., the ratio of the frequency of the clock signal before division to the frequency of the clock signal after division, is 1 / M (M is an integer). Such a divider circuit is called an integer divider circuit. An integer divider circuit can be easily realized using a counter circuit.

[0005] Among clock divider circuits, a divider circuit with a division ratio of N / M (N and M are integers) is called a rational divider circuit. An example of a rational divider circuit is disclosed in, for example, Patent Document 1. Hereinafter, a division circuit with a division ratio of N / M is also referred to as an N / M division circuit.

[0006] Patent Document 1 describes a clock signal divider circuit that generates a divided clock signal by dividing an input clock signal by N / M. The clock signal divider circuit described in Patent Document 1 masks MN clock pulses out of M consecutive clock pulses of an input clock signal based on a division ratio defined as N / M (N is a positive integer, M is a positive integer greater than N). As a result, the clock signal divider circuit described in Patent Document 1 generates a divided clock signal by dividing the input clock signal by N / M. Specifically, the clock signal divider circuit of Patent Document 1 includes a mask circuit and a mask control circuit. The mask circuit generates and outputs a divided clock signal by masking clock pulses of the input clock signal according to the input mask signal. The mask control circuit generates and outputs a mask signal to the mask circuit based on communication timing information. The communication timing information is information indicating the communication timing of data communication performed in a target circuit using the divided clock signal. The mask signal is a signal in which mask timings are assigned to mask MN clock pulses from among M successive clock pulses of the input clock signal, with the exception of the communication timing.

[0007] In this way, the clock signal divider circuit described in Patent Document 1 outputs the clock pulse of the input clock signal as a divided clock signal without masking it at the communication timing of the target circuit. Therefore, the clock signal divider circuit described in Patent Document 1 can generate a divided clock signal that allows data communication without degrading communication performance, even with a partner circuit that operates on a clock signal different from the input clock signal. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] International Publication No. 2009 / 116398 Summary of the Invention [Problem to be solved by the invention]

[0009] In the following description, a circuit that uses the divided clock signal output by the clock signal divider circuit is referred to as a target circuit, and a circuit that communicates with the target circuit is referred to as a partner circuit.

[0010] The clock signal divider circuit described in Patent Document 1 outputs the clock pulse of the input clock signal as a divided clock signal without masking it at the communication timing of the target circuit. Therefore, the target circuit using the divided clock signal output by the clock signal divider circuit described in Patent Document 1 can perform data communication without degrading communication performance even with a partner circuit that operates with a clock signal different from the input clock signal. However, in order to perform data communication without degrading communication performance, the target circuit needs to recognize the communication timing. Therefore, it is necessary to propagate communication timing information from the clock signal divider circuit to the target circuit. However, it is necessary to match the timing of the distribution of the clock signal and the distribution of the communication timing information. Timing design for this purpose is not easy. Therefore, the design cost increases.

[0011] An object of the present disclosure is to provide a processing device, a processing system, and a processing method that can reduce design costs and facilitate timing design. [Means for solving the problem]

[0012] A processing device according to one aspect of the present disclosure includes a toggle signal receiving means for receiving a toggle signal whose value transitions between two values ​​at the timing of a pulse of a divided clock signal in which a periodic pattern signal is repeated in which a predetermined pulse having a mask pulse number smaller than the periodic pulse number is masked among successive pulses of a periodic pulse number of an input clock signal, and a communication means for communicating with another processing device operated by the divided clock signal at the timing of the pulse of the divided clock signal identified using the toggle signal among the pulses of the input clock signal.

[0013] A processing method according to one aspect of the present disclosure includes receiving a toggle signal whose value transitions between two values ​​at the timing of a pulse of a divided clock signal in which a periodic pattern signal is repeated in which a predetermined pulse having a mask pulse number smaller than the periodic pulse number is masked among successive pulses of a periodic pulse number of an input clock signal, and communicating with another processing device operated by the divided clock signal at the timing of the pulse of the divided clock signal identified using the toggle signal among the pulses of the input clock signal. Effect of the Invention

[0014] The present disclosure has the effect of reducing design costs and facilitating timing design. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram illustrating an example of a circuit using a clock signal divider circuit according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram illustrating an example of a clock B generated by rational division using a clock signal divider circuit according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is a diagram illustrating a configuration of the clock signal divider circuit 10 according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating an example of the configuration of the non-marker portion masking signal generating unit 53 according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram illustrating an example of the transition of signals and values ​​related to the clock signal divider circuit 10 according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram illustrating an example of communication timing between circuit A and circuit B according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating an example of communication timing between circuit A and circuit B according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram illustrating an example of communication timing between circuit A and circuit B according to an embodiment of the present disclosure. [Figure 9]FIG. 9 is a diagram illustrating an example of communication timing between circuit A and circuit B according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating an example of a semiconductor integrated circuit using a clock signal divider circuit according to a first comparative example. [Figure 11] FIG. 11 is a diagram illustrating an example of a clock signal in a semiconductor integrated circuit according to a first comparative example. [Figure 12] FIG. 12 is a diagram illustrating an example of a semiconductor integrated circuit using a clock signal divider circuit according to a second comparative example. [Figure 13] FIG. 13 is a diagram illustrating an example of a clock signal in a semiconductor integrated circuit according to a second comparative example. [Figure 14] FIG. 14 is a block diagram illustrating an example of the configuration of a processing device according to an embodiment of the present disclosure. [Figure 15] FIG. 15 is a flowchart illustrating an example of the operation of the processing device according to an embodiment of the present disclosure. [Figure 16] FIG. 16 is a diagram illustrating an example of the configuration of a processing system according to an embodiment of the present disclosure. [Figure 17] FIG. 17 is a block diagram illustrating an example of the configuration of a clock signal divider device according to the seventh embodiment of the present disclosure. [Figure 18] FIG. 18 is a diagram illustrating an example of a configuration of an output signal generating unit according to an embodiment of the present disclosure. [Figure 19] FIG. 19 is a diagram illustrating an example of the configuration of a mask control unit according to a schematic example of an embodiment of the present disclosure. [Figure 20] FIG. 20 is a block diagram illustrating an example of the configuration of a processing device according to an embodiment of the present disclosure. [Figure 21] FIG. 21 is a block diagram illustrating an example of the configuration of a processing device according to an embodiment of the present disclosure. [Figure 22] FIG. 22 is a flowchart illustrating an example of the operation of the clock signal divider device according to an embodiment of the present disclosure. [Figure 23] FIG. 23 is a flowchart illustrating an example of the operation of the processing device according to an embodiment of the present disclosure. [Figure 24]FIG. 24 is a flowchart illustrating an example of the operation of the processing device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] In the following, a comparative example of the present disclosure will be described first, followed by a detailed description of an embodiment of the present disclosure with reference to the drawings.

[0017] <First Comparative Example> First, as a first comparative example, a clock signal divider circuit according to the techniques described in References 1 and 2 below will be described.

[0018] (Reference 1) JP 2005-45507 A

[0019] (Reference 2) JP 2006-148807 A References 1 and 2 disclose examples of rational frequency divider circuits, among clock frequency divider circuits, whose frequency division ratio is N / M (N and M are integers).

[0020] The clock signal divider circuits (hereinafter also simply referred to as divider circuits) in References 1 and 2 cumulatively add a value that sets the numerator of the division ratio (the value of N in the division ratio N / M), i.e., a value set as the numerator of the division ratio, for each cycle of the input clock signal. When the addition result (i.e., the cumulatively added value) becomes greater than the value that sets the denominator (the value of M in the division ratio N / M), i.e., a value set as the denominator of the division ratio, the divider circuits in References 1 and 2 subtract a value M from the addition result. The divider circuits in References 1 and 2 use the addition result to mask (i.e., thin out) clock pulses of the input clock signal so that the number of unmasked clock pulses out of M clock pulses becomes N. As described above, the divider circuits in References 1 and 2 realize rational division.

[0021] The clock signal divider circuit described in Reference 1 and the clock signal divider circuit described in Reference 2 generate a divided clock signal by selectively masking and dividing the clock pulse of an input clock signal. However, these clock signal divider circuits do not take into consideration the communication timing between a target circuit that uses the divided clock signal output by these clock signal divider circuits and a counterpart circuit that performs data communication. For this reason, when the target circuit performs data communication with a counterpart circuit that operates on a clock signal with a different frequency from the input clock signal, a special clock transfer circuit or a special timing design is required. As a result, communication performance is degraded. Furthermore, power consumption and circuit size are increased. Furthermore, design costs are increased.

[0022] The clock signal divider circuit according to the first comparative example will be described below with reference to FIGS.

[0023] FIG. 10 is a diagram illustrating an example of a semiconductor integrated circuit using a clock signal divider circuit according to a first comparative example.

[0024] FIG. 11 is a diagram illustrating an example of a clock signal in a semiconductor integrated circuit according to a first comparative example.

[0025] In the example shown in FIG. 10, a clock S is supplied to a clock signal divider circuit 100. The clock signal divider circuit 100 generates a clock B by rationally dividing the clock S according to an input division ratio setting. The clock B is a clock signal generated by the clock signal divider circuit 100. The clock B is supplied to a circuit B. A clock A, which is different from the clock S and the clock B, is supplied to the circuit A. The clock A is a clock signal supplied to the circuit A. The circuits A and B communicate with each other through a signal Aout and a signal Bout. The signal Aout is a signal that the circuit A outputs at the timing of the clock A and that the circuit B receives as an input at the timing of the clock B. The signal Bout is a signal that the circuit B outputs at the timing of the clock B and that the circuit A receives as an input at the timing of the clock A.

[0026] As described above, a circuit that uses the divided clock signal output by the clock signal divider circuit is referred to as a target circuit. A circuit that communicates with the target circuit is referred to as a partner circuit. In the example of Figure 10, circuit B is the target circuit, and circuit A is the partner circuit.

[0027] 11 shows clock B generated by clock signal divider circuit 100 by dividing clock S with division ratios of 11 / 12 to 4 / 12. Clock B can be generated by appropriately masking the clock pulses (hereinafter also simply referred to as pulses) of input clock S. For example, clock B with a division ratio of 9 / 12 is generated by masking three clock pulses at timings T3, T8, and T11 out of the 12 clock pulses at timings T0 to T11 of clock S.

[0028] In the example shown in FIG. 11, the frequency of clock A is 1 / 3 of clock S. That is, the division ratio of clock A to clock S is 1 / 3 (=4 / 12). At this time, the phase relationship between clock A and clock B shown in FIG. 11 completes one cycle in 12 cycles of clock S. The timing of the 12 cycles in which this phase relationship completes one cycle is indicated by T0 to T11. Also, it is assumed that circuit A and circuit B communicate at timings T0, T3, T6, and T9, which are all rising timings of clock A. That is, circuit A outputs signal Aout and receives signal Bout as input at timings T0, T3, T6, and T9, which are rising timings of clock A and communication timings.

[0029] However, the clock signal divider circuit 100 illustrated in Fig. 10 does not take into consideration communication with clocks of different frequencies. Therefore, the clock signal divider circuit 100 may generate a clock B in which the clock pulse of the clock S is masked at least at any one of timings T0, T3, T6, and T9, which are the timings of communication with the circuit A. The clock B illustrated in Fig. 11 includes a clock B in which the clock pulse of the clock S is masked at least at any one of timings T3, T6, and T9 among the timings of communication.

[0030] Specifically, at timing T3, the clock pulses of clock B when the division ratio is 9 / 12, clock B when the division ratio is 6 / 12, and clock B when the division ratio is 5 / 12 are masked. The waveform of clock B when the division ratio is 9 / 12 at timing T3 is waveform 110a. The waveform of clock B when the division ratio is 6 / 12 at timing T3 is waveform 110b. The waveform of clock B when the division ratio is 5 / 12 at timing T3 is waveform 110c.

[0031] Similarly, at timing T6, the clock pulse of clock B when the division ratio is 5 / 12 is masked. The waveform of clock B at timing T6 when the division ratio is 5 / 12 is waveform 110d.

[0032] Similarly, at timing T9, the clock pulses of clock B when the division ratio is 7 / 12, 6 / 12, and 5 / 12 are masked. The waveform of clock B when the division ratio is 7 / 12 at timing T9 is waveform 110e. The waveform of clock B when the division ratio is 6 / 12 at timing T9 is waveform 110f. The waveform of clock B when the division ratio is 7 / 12 at timing T9 is waveform 110g.

[0033] As in these cases, when clock B is generated with the clock pulse of clock S masked at the timing of communication when circuit A can communicate, circuit B cannot communicate with circuit A. Specifically, circuit B, which operates on clock B, cannot receive signal Aout, which circuit A, which operates on clock A, outputs to the signal line of signal Aout, as input at the expected timing (i.e., the timing when circuit B can receive signal Bout). Similarly, circuit B, which operates on clock B, cannot output signal Bout to the signal line of signal Bout at the timing expected by circuit A, which operates on clock A (i.e., the timing when circuit B can receive signal Bout as input).

[0034] 10, expected correct communication operation is not realized in communication between circuit B, which operates according to clock B from clock signal divider circuit 100, and circuit A, which operates according to clock A, which has a frequency different from that of clock B. This expected correct communication operation means that one of these circuits receives a signal output by the other circuit at the timing when it can receive a signal, and the above-mentioned one circuit receives a signal output by the other circuit at the timing when it can receive a signal.

[0035] In order to realize the expected correct communication operation in communication between a circuit that operates on a clock from the clock signal divider circuit according to this comparative example and a circuit that operates on a clock with a different frequency, a special clock transfer circuit and a special timing design are required. As a result, communication performance is degraded. Furthermore, power consumption and circuit size are increased. Furthermore, design costs are increased.

[0036] <Second Comparative Example> Next, a clock signal divider circuit according to the technique disclosed in Patent Document 1 will be described with reference to FIGS.

[0037] FIG. 12 is a diagram illustrating an example of a semiconductor integrated circuit using a clock signal divider circuit according to a second comparative example.

[0038] FIG. 13 is a diagram illustrating an example of a clock signal in a semiconductor integrated circuit according to a second comparative example.

[0039] In the example shown in FIG. 12, the semiconductor integrated circuit includes a circuit A, a circuit B, and a clock signal divider circuit 120. A clock A is supplied to the circuit A. The circuit A operates according to the clock A. A clock B is supplied to the circuit B. The circuit B operates according to the clock B. A division ratio setting, communication timing information indicating the timing of communication between a circuit operating according to the clock A and a circuit operating according to the clock B, and a clock S are input to the clock signal divider circuit 120. The clock signal divider circuit 120 generates the clock B by rationally dividing the clock S using the division ratio setting and the communication timing information. The clock signal divider circuit 120 supplies the clock B to the circuit B. The circuit A and the circuit B communicate with each other through the signal Aout and the signal Bout at the communication timing indicated by the communication timing information. The signal Aout is a signal that the circuit A outputs at the timing of the clock A and that the circuit B receives as an input at the timing of the clock B. Signal Bout is a signal that circuit B outputs at the timing of clock B and circuit A receives as input at the timing of clock A.

[0040] FIG. 13 illustrates examples of waveforms of clock S, clock A, communication timing information, and clock B. Clock B is an example of clock division by the clock signal divider circuit 120 according to this comparative example. FIG. 13 illustrates clock B generated by dividing clock S with a division ratio of 11 / 12 to 4 / 12. The clock signal divider circuit 120 generates clock B by appropriately masking clock pulses of the input clock S. For example, the clock signal divider circuit 120 generates clock B with a division ratio of 9 / 12 by masking three clock pulses at timings T2, T5, and T8 among the 12 clock pulses at timings T0 to T11 of the clock S.

[0041] In the example shown in FIG. 13, the frequency of clock A is 1 / 3 of the frequency of clock S. That is, the division ratio of clock A to clock S is 1 / 3 (=4 / 12). In this case, the phase relationship between clock A and clock B completes one cycle in 12 cycles of clock S. The timing of the 12 cycles in which this phase relationship completes one cycle is shown as timings T0 to T11. Assume that circuit A and circuit B communicate at timings T0, T3, T6, and T9, which are all rising timings of clock A. That is, circuit A outputs signal Aout and receives signal Bout as input at timings T0, T3, T6, and T9, which are rising timings of clock A and communication timings.

[0042] The clock signal division circuit 120 receives as an input communication timing information 124 indicating the timing of the above communication, and performs rational division taking into consideration the timing of the communication based on the communication timing information 124. Specifically, the clock signal division circuit 120 realizes rational division by always not masking clock pulses that occur at communication timings, and by masking clock pulses that do not occur at other communication timings.

[0043] In the example shown in FIG. 13, in the clock B generated by dividing the clock, the clock pulse is not masked at any of the timings T0, T3, T6, and T9, which are the timings of communication. And the clock pulse at any of the timings T1, T2, T4, T5, T7, T8, T10, and T11, which are not the timings of communication, is masked. The clock signal divider circuit 120 generates the clock B by masking the clock pulse at the timing other than the communication timing indicated by the communication timing information 124. That is, the clock B generated by the clock signal divider circuit 120 always has a clock pulse at the communication timing indicated by the communication timing information 124. Therefore, the circuit B operating by the clock B can always receive the signal Aout output by the circuit A operating by the clock A to the signal line of the signal Aout as an input at the expected timing. Similarly, the circuit B operating by the clock B can always output the signal Bout to the signal line of the signal Bout at the expected timing by the circuit A operating by the clock A.

[0044] Incidentally, clock B has clock pulses other than the communication timing. Therefore, in order for circuit B to communicate only at the communication timing expected by circuit A, circuit B needs to recognize the communication timing. For this reason, clock signal divider circuit 120 outputs communication timing information 125 indicating the above communication timing to circuit B.

[0045] Here, the communication timing information 125 needs to be a signal synchronized with clock B. Therefore, it is necessary to match the distribution timing of clock B with the propagation timing of the communication timing information 125. Since a clock signal is distributed to a large number of flip-flops, the distribution delay is usually very large. In order to match the distribution timing of clock B with the propagation timing of the communication timing information 125, it is necessary to adjust the propagation delay of the communication timing information 125 so that it becomes equivalent to the distribution delay of clock B. However, due to variations in semiconductor processes, temperature, voltage, etc., the respective delay times also vary. As a result, timing design becomes difficult.

[0046] <First embodiment> Next, a first embodiment of the present disclosure will be described in detail with reference to the drawings.

[0047] <Overall composition> FIG. 1 is a diagram illustrating an example of a circuit using a clock signal divider circuit according to an embodiment of the present disclosure.

[0048] A semiconductor integrated circuit in which a clock signal divider circuit according to a first embodiment of the present disclosure is used will be described with reference to FIG.

[0049] In the example shown in FIG. 1, the semiconductor integrated circuit includes a circuit A, a circuit B, and a clock signal divider circuit 10. A clock S is supplied to the circuit A and the clock signal divider circuit 10. A division ratio setting 30 is input to the clock signal divider circuit 10. The division ratio setting 30 is a signal that sets the division ratio of the clock B. The clock signal divider circuit 10 generates the clock B by performing rational division on the clock S with the division ratio indicated by the division ratio setting 30. The clock signal divider circuit 10 outputs the clock B. The clock B is supplied to the circuit B. The clock S and the clock B are clock signals.

[0050] Circuit A and circuit B communicate with each other through signals Aout and Bout. Signal Aout is a signal that circuit A outputs at the timing of clock A and circuit B receives as an input at the timing of clock B. Signal Bout is a signal that circuit B outputs at the timing of clock B and circuit A receives as an input at the timing of clock A.

[0051] FIG. 2 is a diagram illustrating an example of a clock B generated by rational division using a clock signal divider circuit according to an embodiment of the present disclosure.

[0052] The rational division by the clock signal divider circuit 10 of this embodiment will be described in detail with reference to Fig. 2. Fig. 2 shows clock B generated by dividing clock S by each of division ratios 11 / 12 to 1 / 12.

[0053] In these examples, the denominator of the division ratio of clock B to clock S is 12. Therefore, the phase relationship between clock S and clock B completes one cycle in 12 cycles of clock S. In FIG. 2, the timing of the 12 cycles in which this phase relationship completes one cycle is shown as timings T0 to T11. Circuit A and circuit B communicate at a timing when both the clock supplied to circuit A and the clock supplied to circuit B have a clock pulse. For example, when the division ratio of clock B is 7 / 12, the timings when both the clock supplied to circuit A and the clock supplied to circuit B have a clock pulse are timings T0, T3, T4, T6, T7, T9, and T10. In this case, circuit A and circuit B communicate at timings T0, T3, T4, T6, T7, T9, and T10.

[0054] The clock signal divider circuit 10 places a marker section at the beginning of a cycle in which the clock phase relationship makes one revolution, in order to identify the beginning of the cycle. The marker section is a clock pulse pattern of a predetermined number of cycles. In other words, the clock signal divider circuit 10 generates clock B such that the clock pulse pattern of a predetermined number of cycles from the beginning of a cycle in which the clock phase relationship of clock B makes one revolution is the clock pulse pattern of the marker section. The marker section is set so that it does not appear anywhere other than the marker section in clock B that includes the marker section. When the division ratios are different, the marker sections do not have to be the same.

[0055] In the example of clock B shown in FIG. 2, the first three cycles of a cycle of 12 cycles in which the phase relationship makes one revolution are any of markers 11 to 14.

[0056] Specifically, the marker portion of clock B when the division ratio is 11 / 12 is marker 11, which is three consecutive cycles of a clock pulse with, with, and without a clock pulse.

[0057] The marker portion of clock B when the division ratio is 10 / 12 to 6 / 12 is marker 12, which is three consecutive cycles of a clock pulse with, without, and without.

[0058] The marker portion of clock B when the division ratio is 5 / 12 to 2 / 12 is a marker 13 of three consecutive cycles of a clock pulse with, with, and without a clock pulse.

[0059] The marker portion of clock B when the division ratio is 1 / 12 is a marker 14 consisting of three consecutive cycles of a clock pulse with, without, and without.

[0060] When the division ratio is 11 / 12, cycles without clock pulses exist only in the portion of the marker 11. The cycle two cycles before the cycle without a clock pulse is the start of the marker 11. In other words, when the division ratio is 11 / 12, the cycle two cycles before the cycle without a clock pulse is the start cycle of the 12-cycle period in which the phase relationship makes one cycle.

[0061] When the division ratio is 10 / 12 to 6 / 12, cycles without two consecutive clock pulses are present only in the portion of the marker 12. The cycle immediately before the cycle without two consecutive clock pulses is the start of the marker 12. In other words, when the division ratio is 10 / 12 to 6 / 12, the cycle immediately before the cycle without two consecutive clock pulses is the start cycle of a 12-cycle period in which the phase relationship completes one cycle.

[0062] When the division ratio is 5 / 12 to 2 / 12, a cycle with two consecutive clock pulses exists only at the portion of the marker 13. The beginning of a cycle with two consecutive clock pulses is the beginning of the marker 13. In other words, when the division ratio is 5 / 12 to 2 / 12, the beginning of a cycle with two consecutive clock pulses is the beginning cycle of a 12-cycle period in which the phase relationship completes one cycle.

[0063] When the division ratio is 1 / 12, the clock pulse is present only at the marker 14. The cycle in which the clock pulse is present is the beginning of the marker 14. In other words, when the division ratio is 1 / 12, the cycle in which the clock pulse is present is the beginning cycle of a 12-cycle period in which the phase relationship makes one revolution.

[0064] More generally, when the division ratio is N / M (N and M are integers greater than N), the marker portion is as follows:

[0065] When M and N satisfy N=M-1, the marker portion is a marker 11 having three consecutive cycles of a clock pulse with, with, and without a clock pulse.

[0066] When M and N satisfy M / 2 ≤ N and N < M - 1, the marker part is the marker 12 of three consecutive cycles with a clock pulse, no clock pulse, and no clock pulse.

[0067] When M and N satisfy 2 ≤ N and N < M / 2, the marker part is the marker 13 of three consecutive cycles with a clock pulse, a clock pulse, and no clock pulse.

[0068] When N satisfies N = 1, the marker part is the marker 14 of three consecutive cycles with a clock pulse, no clock pulse, and no clock pulse.

[0069] And when M and N satisfy N = M - 1, the cycle without a clock pulse exists only in the part of marker 11.

[0070] When M and N satisfy M / 2 ≤ N and N < M - 1, the cycles without clock pulses for two consecutive cycles exist only in the part of marker 12.

[0071] When M and N satisfy 2 ≤ N and N < M / 2, the cycles with clock pulses for two consecutive cycles exist only in the part of marker 13.

[0072] When N satisfies N = 1, the cycles with a clock pulse exist only in the part of marker 14.

[0073] As described above, the marker part is defined such that the pattern of the clock pulses in the marker part exists only in the leading part of the period in which the phase relationship makes a full cycle.

[0074] From the above, for each division ratio, the clock pulse pattern of any one of the markers 11 to 14 appears only at the beginning of a cycle in which the phase relationship completes one cycle. Therefore, the circuit A and the circuit B can identify the beginning of a cycle in which the phase relationship completes one cycle by detecting any one of the markers 11 to 14 according to the division ratio of the clock B that drives the circuit B. In other words, the circuit A and the circuit B can identify the beginning of a cycle in which the phase relationship completes one cycle by detecting the marker part of the markers 11 to 14 according to the division ratio of the clock B that drives the circuit B. As a result, the circuit A and the circuit B can recognize whether or not a clock pulse is present in the clock B in any cycle from the division ratio of the clock B and the timing of the beginning of the cycle in which the phase relationship completes one cycle.

[0075] 1, circuit B operates on clock B, which is generated by dividing clock S and has a lower frequency than clock S. A toggle signal generation circuit 22 included in circuit B generates a toggle signal 23 whose signal value toggles with clock B. Then, toggle signal generation circuit 22 outputs the generated toggle signal 23.

[0076] Circuit A operates on clock S, which has a higher frequency than clock B. A communication control circuit 20 included in this circuit A generates a communication control signal 21 and outputs the generated communication control signal 21 in the following steps.

[0077] (1) The communication control circuit 20 detects the timing of the marker portion of clock B from the input division ratio setting 30, which is setting information for the division ratio of clock B, and the toggle signal 23, thereby identifying the timing of the beginning of a period in which the phase relationship between clock S and clock B completes one cycle.

[0078] (2) The communication control circuit 20 recognizes the timing at which a clock pulse exists in both clock S and clock B from the timing of the beginning of the identified period and the input division ratio setting 30, which is setting information for the division ratio of clock B.

[0079] (3) The communication control circuit 20 outputs to the signal line of the communication control signal 21 a signal indicating the timing when a clock pulse is present in both clock S and clock B, the timing being the timing when circuit A communicates with circuit B.

[0080] Circuit A refers to the communication control signal 21, and outputs signal Aout and receives signal Bout as input at the communication timing indicated by the communication control signal 21 (i.e., the timing at which circuit A communicates with circuit B). Circuit B outputs signal Bout and receives signal Aout as input in every cycle of clock B. Through the above operations, efficient inter-block data communication is realized between circuit A and circuit B.

[0081] FIG. 3 is a diagram illustrating a configuration of the clock signal divider circuit 10 according to an embodiment of the present disclosure.

[0082] In the following, the clock signal divider circuit 10 according to the first embodiment of the present disclosure will be described in detail with reference to FIG. 3. In the example shown in FIG. 3, the clock signal divider circuit 10 includes a mask circuit 61 and a mask control circuit 51. The clock signal divider circuit 10 receives a supplied clock S as an input. The clock signal divider circuit 10 receives a clock division ratio setting, which is a signal representing a division ratio, as an input. The clock signal divider circuit 10 divides the clock S received as an input, i.e., the input clock S, by a division ratio N / M (M and N are integers). Then, the clock signal divider circuit 10 outputs a signal (i.e., a divided clock) obtained by dividing the clock S as clock A or clock B.

[0083] The mask control circuit 51 operates at the timing of the clock S. The mask control circuit 51 generates a mask signal 55 for each cycle of the clock S by referring to the input clock division ratio setting. The clock division ratio setting includes a division ratio denominator M indicating the value of the denominator of the division ratio, and a division ratio numerator N indicating the value of the numerator of the division ratio. Specifically, a signal indicating the clock division ratio setting is input to the mask control circuit 51 as a signal indicating the division ratio denominator M indicating the value of the denominator of the division ratio, and a signal indicating the division ratio numerator N indicating the value of the numerator of the division ratio. The mask signal 55 is a signal indicating a cycle for masking the clock pulse of the clock S to generate a divided clock (e.g., clock B, etc.). Specifically, the mask signal 55 indicates a cycle for masking the clock pulse of the clock S so that the divided clock includes the above-mentioned marker portion at the beginning of a cycle in which the phase relationship between the clock S and the divided clock makes one cycle, and becomes a clock signal with a division ratio of N / M for the clock S. In the following description, when a mask signal indicates that a clock pulse in a certain cycle of the clock S is to be masked, the mask signal is said to mask the clock pulse in that cycle. In other words, when a mask signal indicates that a clock pulse in a certain cycle of the clock S is to be masked, the mask signal is said to mask the clock pulse in that cycle.

[0084] The mask control circuit 51 includes a marker portion mask signal generating section 52 , a non-marker portion mask signal generating section 53 , a selection circuit 54 , and a counter circuit 56 .

[0085] The counter circuit 56 operates at the timing of the clock S. The counter circuit 56 counts the number of clock pulses of the input clock S with reference to the division ratio denominator M. When the number of counted clock pulses reaches M, the counter circuit 56 resets the counted number to 0. The division ratio denominator M represents the number of cycles in a period in which the clock pulse pattern of the divided clock generated by the clock signal divider circuit 10 goes around. The counter circuit 56 then repeatedly counts the number of clock pulses of the input clock S. The counter circuit 56 outputs a signal representing the number of counted clock pulses (in other words, the counted value) as a counter value 57. The counted value indicates the current cycle in a period in which the clock pulse pattern of the divided clock generated by the clock signal divider circuit 10 goes around (for example, cycle 0 to cycle M-1).

[0086] In other words, the counter circuit 56 outputs, as the counter value 57, a value indicating the current cycle in a cycle (for example, cycle 0 to cycle M−1) in which the clock pulse pattern of the divided clock generated by the clock signal divider circuit 10 makes one revolution.

[0087] The marker section mask signal generation unit 52 receives, as inputs, the clock division ratio setting and the counter value 57. The marker section mask signal generation unit 52 refers to the received clock division ratio setting and the counter value 57, and generates a mask signal for the marker section corresponding to the division ratio indicated by the clock division ratio setting among the markers 11 to 14 shown in FIG. 2. The mask signal for the marker section is a mask signal indicating the cycle of the clock pulse masked in the marker section. In other words, the marker section mask signal generation unit 52 uses the received clock division ratio setting and the counter value 57 to generate a mask signal indicating the cycle of the clock pulse masked in the marker section when the division ratio is the division ratio indicated by the clock division ratio setting. When the counter value 57 indicates the cycle of a part of the marker section, the marker section mask signal generation unit 52 outputs, as the mask signal, a signal indicating whether or not the clock pulse of the cycle indicated by the counter value 57 is masked.

[0088] Specifically, when the division ratio is represented by a division ratio denominator M and a division ratio numerator N, the marker section mask signal generation unit 52 generates the following mask signal.

[0089] When M and N satisfy N = M - 1, the marker section mask signal generation unit 52 generates a mask signal indicating the cycle of the clock pulse masked in marker 11.

[0090] When M and N satisfy M / 2 ≤ N and N < M - 1, the marker section mask signal generation unit 52 generates a mask signal indicating the cycle of the clock pulse masked in marker 12.

[0091] When M and N satisfy 2 ≤ N and N < M / 2, the marker section mask signal generation unit 52 generates a mask signal indicating the cycle of the clock pulse masked in marker 13.

[0092] When N satisfies N=1, the marker portion mask signal generating section 52 generates a mask signal indicating the cycle of the clock pulse that is masked in the marker 14.

[0093] The non-marker section mask signal generating unit 53 receives a clock division ratio setting and a counter value 57 as input. The non-marker section mask signal generating unit 53 references the received clock division ratio setting and counter value 57 to generate a mask signal for the non-marker section, which is a portion other than the marker section in a period in which the phase relationship of the divided clock makes one revolution. The non-marker section is a portion other than the marker section (markers 11 to 14 in the example shown in FIG. 2) in the divided clock. The non-marker section mask signal is a mask signal that indicates the cycle of the masked clock pulse in the non-marker section. When the counter value 57 indicates a cycle of the non-marker section, the non-marker section mask signal generating unit 53 outputs a signal that indicates whether or not the clock pulse of the cycle indicated by the counter value 57 is masked as a mask signal.

[0094] Specifically, when the frequency division ratio is represented by a frequency division ratio denominator M and a frequency division ratio numerator N, the non-marker portion mask signal generating unit 53 generates the following mask signal.

[0095] When M and N satisfy N=M-1, the marker section is the marker 11. The size of the marker 11 is three cycles. The marker 11 includes two clock pulses. Therefore, the division ratio of the non-marker section, which is the portion other than the marker 11 in the period in which the phase relationship of the divided clock makes one revolution, is (N-2) / (M-3)=(M-3) / (M-3). In other words, no division is performed in the non-marker section. That is, no masking of the clock pulse is performed in the non-marker section. Therefore, the non-marker section mask signal generating unit 53 generates a mask signal indicating that no division is performed, that is, a mask signal indicating that no masking process is performed, as a mask signal of the non-marker section when M and N satisfy N=M-1. In other words, the non-marker section mask signal generating unit 53 generates a mask signal indicating that no masking of the clock pulse is performed in all cycles of the non-marker section as a mask signal of the non-marker section when M and N satisfy N=M-1.

[0096] When M and N satisfy M / 2 ≤ N and N < M - 1, the marker part is marker 12. The size of marker 12 is 3 cycles. Marker 12 contains one clock pulse. Therefore, the division ratio of the non-marker part, which is the part other than marker 12 in the cycle in which the phase relationship of the divided clock makes one full turn, is (N - 1) / (M - 3). As described above, marker 12 includes cycles in which the clock pulses are masked for two consecutive cycles. The non-marker part mask signal generation unit 53 generates, as the mask signal for the non-marker part when M and N satisfy M / 2 ≤ N and N < M - 1, a mask signal that realizes a division by (N - 1) / (M - 3) in the non-marker part and does not mask the clock pulses continuously for two or more cycles. A mask signal that does not mask the clock pulses continuously for two or more cycles is, in other words, a mask signal indicating the cycles in which the clock pulses are masked (hereinafter also referred to as mask cycles), and the cycles in which the clock pulses are masked are not consecutive. In the following description, the cycles in which the clock pulses are not masked are also referred to as non-mask cycles. In the mask signal for the non-marker part when M and N satisfy M / 2 ≤ N and N < M - 1, the non-mask cycles may or may not be consecutive.

[0097] When M and N satisfy 2 ≤ N and N < M / 2, the marker part is marker 13. The size of marker 13 is 3 cycles. Marker 13 includes two clock pulses. Therefore, when M and N satisfy 2 ≤ N and N < M / 2, the division ratio of the non-marker part, which is the part other than marker 12 in the period in which the phase relationship of the divided clock makes one round, is (N - 2) / (M - 3). In marker 13, the two clock pulses are consecutive. The non-marker part mask signal generation unit 53 realizes a division by (N - 2) / (M - 3) as the mask signal of the non-marker part when M and N satisfy 2 ≤ N and N < M / 2, and generates a mask signal in which there is no cycle in which clock pulses are not masked for two or more consecutive cycles. A mask signal in which there is no cycle in which clock pulses are not masked for two or more consecutive cycles, in other words, is a mask signal in which the cycles in which clock pulses are not masked (i.e., non-mask cycles) are always two or more consecutive. In the mask signal of the non-marker part when M and N satisfy 2 ≤ N and N < M / 2, at least one of the cycle before the non-mask cycle and the cycle after the non-mask cycle is a non-mask cycle. In the mask signal of the non-marker part when M and N satisfy M / 2 ≤ N and N < M - 1, the cycles in which clock pulses are not masked (i.e., non-mask cycles) are not consecutive. The cycle before the non-mask cycle and the cycle after the non-mask cycle are mask cycles.

[0098] When N satisfies N = 1, the marker part is marker 14. The size of marker 14 is 3 cycles. Marker 14 includes one clock pulse. Therefore, when N satisfies N = 1, the division ratio of the non-marker part, which is the part other than marker 12 in the period in which the phase relationship of the divided clock makes one round, is (N - 1) / (M - 3) = 0. That is, in the non-marker part, all clock pulses are masked. The non-marker part mask signal generation unit 53 generates a mask signal that masks all clock pulses in the non-marker part as the mask signal of the non-marker part when N satisfies N = 1.

[0099] The selection circuit 54 refers to the counter value 57. The counter value 57 indicates the current cycle in the period in which the pattern of the clock pulse of the divided clock makes one revolution (in the example shown in FIG. 2, cycle T0 to cycle T11). The selection circuit 54 selects the mask signal to be output as the mask signal 55 from the mask signal 58 generated by the marker portion mask signal generating unit 52 and the mask signal 59 generated by the non-marker portion mask signal generating unit 53 according to the cycle indicated by the counter value 57. The selection circuit 54 outputs the selected mask signal as the mask signal 55.

[0100] Specifically, when counter value 57 indicates any of cycles TO to T2 included in the marker section, selection circuit 54 selects mask signal 58 generated by marker section mask signal generation unit 52. Then, selection circuit 54 outputs selected mask signal 58 as mask signal 55 to the signal line of mask signal 55. When counter value 57 indicates any of cycles T3 to T11 included in the non-marker section, selection circuit 54 selects mask signal 59 generated by non-marker section mask signal generation unit 53. Then, selection circuit 54 outputs selected mask signal 59 as mask signal 55 to the signal line of mask signal 55.

[0101] A mask signal 55 is input to the mask circuit 61. The mask circuit 61 receives the mask signal 55 as an input. The mask circuit 61 selects whether to mask the clock pulse of the clock S or to output the clock pulse of the clock S without masking it by referring to the mask signal 55. When the mask signal 55 indicates that the clock pulse is to be masked, that is, when the value of the mask signal 55 is a value (for example, 0) indicating that the clock pulse is to be masked, the mask circuit 61 masks the clock pulse of the clock S. Then, the mask circuit 61 outputs the clock S whose clock pulse is masked as the clock B. When the mask signal 55 indicates that the clock pulse is not to be masked, that is, when the value of the mask signal 55 is a value (for example, 1) indicating that the clock pulse is not to be masked, the mask circuit 61 does not mask the clock pulse of the clock S. Then, the mask circuit 61 outputs the clock S whose clock pulse is not masked as the clock B.

[0102] The mask circuit 61 includes a latch circuit 62 and an AND circuit 63. The AND circuit 63 has a function of masking the clock S based on the mask signal 55. When the value of the mask signal 55 is 0, the AND circuit 63 masks the clock S. When the value of the mask signal 55 is 1, the AND circuit 63 does not mask the clock S.

[0103] The latch circuit 62 latches the mask signal 55 at the falling edge of the clock S, thereby limiting the transition of the mask signal 55 input to the AND circuit 63 to the timing when the value of the clock S is 0. As a result, the latch circuit 62 suppresses the occurrence of glitches in the clock B. By using the latch circuit 62 in this way, there is an effect that the timing design is made easier. However, when the occurrence of glitches is avoided by performing the timing design strictly, the latch circuit 62 may be omitted. In the example shown in FIG. 3, an AND circuit is used as a circuit for masking the clock S. However, the circuit used in the mask circuit 61 is not limited to an AND circuit. An OR circuit may be used in the mask circuit 61. Other circuits having equivalent functions may be used in the mask circuit 61.

[0104] FIG. 4 is a diagram illustrating an example of the configuration of the non-marker portion masking signal generating unit 53 according to an embodiment of the present disclosure.

[0105] The non-marker portion mask signal generating unit 53 of this embodiment will be described in detail below with reference to FIG.

[0106] In the example shown in Fig. 4, the non-marker portion mask signal generating unit 53 includes a division ratio setting conversion unit 71, a selector circuit 72, an adder 73, memory circuits 74 and 75, a magnitude comparator 76, and an initialization circuit 81. The non-marker portion mask signal generating unit 53 operates at the timing of the rising edge of the input clock signal. Note that the line indicating the input clock signal of the non-marker portion mask signal generating unit 53 is not drawn in Fig. 4 to simplify the drawing.

[0107] The frequency division ratio setting conversion unit 71 receives as input the frequency division ratio denominator M and the frequency division ratio numerator N which are the frequency division ratio settings. The frequency division ratio setting conversion unit 71 receives the input frequency division ratio setting (that is, the frequency division ratio denominator M and the frequency division ratio numerator N) as input. The frequency division ratio setting conversion unit 71 converts the received frequency division ratio setting (that is, the frequency division ratio denominator M and the frequency division ratio numerator N) into the frequency division ratio denominator M' and the frequency division ratio numerator N' which are the frequency division ratios of the non-marker part. The frequency division ratio setting conversion unit 71 outputs signals indicating the obtained frequency division ratio denominator M' and frequency division ratio numerator N' representing the frequency division ratio of the non-marker part. Specifically, the frequency division ratio setting conversion unit 71 outputs a signal M'-N' representing the value of M'-N, a signal -N' representing the value of -N, and a signal M' representing the value of M'.

[0108] As described above, since the size of the marker part is 3 cycles, the value of the frequency division ratio denominator M' is M' = M - 3. The value of the frequency division ratio numerator N' is as follows.

[0109] When M and N satisfy N = M - 1, the value of the frequency division ratio numerator N' is N' = (N - 2).

[0110] When M and N satisfy M / 2 ≤ N and N < M - 1, the value of the frequency division ratio numerator N' is N' = (N - 1).

[0111] When M and N satisfy 2 ≤ N and N < M / 2, the value of the frequency division ratio numerator N' is N' = (N - 2).

[0112] When N satisfies N = 1, the value of the frequency division ratio numerator N' is N' = (N - 1).

[0113] The initialization circuit 81 generates an initialization signal 82 that initializes the memory circuits 74 and 75 in order to periodically generate a mask signal for the non-marker portion starting from cycle T3 in a period of M cycles in which the phase relationship of the divided clocks completes as illustrated in FIG. 2. The cycles in which the initialization circuit 81 generates the initialization signal 82 in a period of M cycles in which the phase relationship of the divided clocks completes will be described later. The initialization circuit 81 outputs the generated initialization signal 82. The initialization signal output by the initialization circuit 81 is input to the memory circuits 74 and 75.

[0114] The non-marker portion masking signal generating unit 53 cumulatively adds the value of M'-N' for each cycle of the input clock signal, for the division ratio denominator M' and division ratio numerator N', which are the division ratios of the non-marker portion, while the cumulatively added value of M'-N' is smaller than the value of M'. "Cumulatively adding" refers to repeated addition. The cumulatively added value of M'-N' is the value obtained by repeatedly adding the value of M'-N'. The non-marker portion masking signal generating unit 53 performs the cumulative addition of the value of M'-N' using an adder 73 and a memory circuit 74.

[0115] The non-marker portion mask signal generating unit 53 stores in the storage circuit 74 an addition result 77 obtained by cumulatively adding the value of M'-N' for each cycle of the input clock signal while the cumulatively added value of the values ​​of M'-N' is smaller than the value of M'. Specifically, when the addition result stored in the storage circuit 74 is smaller than the value of M', the selector circuit 72 outputs a signal M'-N' representing the value of M'-N'. The signal M'-N' representing the value of M'-N' is input to the adder 73. In addition, the addition result stored in the storage circuit 74 is input to the adder 73. The adder 73 outputs the addition result, which is the value obtained by adding the addition result stored in the storage circuit 74 and the value of M'-N', as the addition result 77. The addition result 77 output by the adder 73 is input to the storage circuit 74. The storage circuit 74 stores the value of the input addition result 77.

[0116] The selector circuit 72, the adder 73 and the storage circuit 74 will be described in more detail below.

[0117] As described above, the memory circuit 74 is initialized by the initialization circuit 81. Specifically, the memory circuit 74 receives the initialization signal 82 generated by the initialization circuit 81 as an input. When the memory circuit 74 receives the initialization signal 82 generated by the initialization circuit 81 as an input, the memory circuit 74 initializes the stored value. In this example, initializing the stored value means setting the stored value to a value of 0. In the initialized state, the memory circuit 74 stores the value 0.

[0118] Furthermore, the storage circuit 74 receives as an input the addition result 77 output by the adder 73. When the storage circuit 74 receives the addition result 77 as an input, it stores the value of the received addition result 77.

[0119] The selector circuit 72 refers to the comparison result 88 representing the value stored in the memory circuit 75 and selects the signal to be output from the signal -N' and the signal M'-N' output by the frequency division ratio setting conversion unit 71 as follows. If the comparison result 88 indicates that the value of M'-N' is equal to or greater than the value of M', the selector circuit 72 selects the signal -N' output by the frequency division ratio setting conversion unit 71. The selector circuit 72 outputs the selected signal -N' to the adder 73 as the addition value 83. This causes the adder 73 to subtract the value of N' from the addition result 87 stored in the memory circuit 74. If the comparison result 88 indicates that the value of M'-N' is smaller than the value of M', the selector circuit 72 selects the signal M'-N' output by the frequency division ratio setting conversion unit 71. The selector circuit 72 outputs the selected signal M'-N' to the adder 73 as the addition value 83. As a result, the adder 73 adds the value M′−N′ to the addition result 87 stored in the memory circuit 74 .

[0120] The adder 73 receives the addition value 83 output from the selector circuit 72 and the addition result 87 output from the memory circuit 74. The addition result 87 is a value stored in the memory circuit 74. The adder 73 adds the value of the addition value 83 and the value of the addition result 87. The adder 73 outputs the addition result obtained by adding the value of the addition value 83 and the value of the addition result 87 as the addition result 77. The addition result 77 output by the adder 73 is input to the magnitude comparator 76. The addition result 77 output by the adder 73 is further input to the memory circuit 74. The memory circuit 74 stores the value of the input addition result 77.

[0121] As will be described in detail later, the magnitude comparator 76 compares the value of the addition result 77 output from the adder 73 with the value of M'. The result of the comparison by the magnitude comparator 76 between the value of the addition result 77 output from the adder 73 and the value of M' in the previous cycle is input to the selector circuit 72 as a comparison result 88.

[0122] Immediately after memory circuit 74 is initialized, the value stored in memory circuit 74 is the value 0. In this case, the value of the comparison result stored in memory circuit 75 is also initialized. Through initialization, the value of the comparison result stored in memory circuit 75 becomes the value 0, which indicates that the value of addition result 77 is smaller than the value of M'. In this case, adder 73 adds the value 0 stored in memory circuit 74 to the value of M'-N'. Adder 73 outputs addition result 77 which indicates the value of M'-N'. Memory circuit 74 stores the value of M'-N'.

[0123] Since the value of M'-N' is smaller than the value of M', in the next cycle, selector circuit 72 selects the value of M'-N'. Adder 73 adds the value of M'-N' stored in memory circuit 74 and the value of M'-N' output by selector circuit 72. Adder 73 outputs addition result 77 indicating the value obtained by adding the value stored in memory circuit 74 and the value of M'-N'. If the value of addition result 77 is smaller than the value of M', in the next cycle, adder 73 adds the value of M'-N' to addition result 77.

[0124] In this way, after the memory circuit 74 is initialized, while the value of the addition result 77 is smaller than the value of M', the adder 73 repeatedly adds the addition result 87, which is the value of the addition result stored in the memory circuit 74, and the value of M'-N' for each cycle. The addition result 77, which is the result of the addition, is stored in the memory circuit 74. Therefore, after the memory circuit 74 is initialized, while the value of the addition result 77 is smaller than the value of M', the addition result 77 representing the value obtained by repeatedly adding the value of M'-N' for each cycle is input to the memory circuit 74. In other words, while the value obtained by repeatedly adding the value of M'-N' for each cycle is smaller than the value of M', the memory circuit 74 stores the value obtained by repeatedly adding the value of M'-N' for each cycle (i.e., the value obtained by cumulatively adding the value of M'-N' described above).

[0125] When the value of addition result 77 becomes equal to or greater than the value of M', adder 73 adds the value of -N' to addition result 87, which is the value of the addition result stored in memory circuit 74. In other words, when the value of addition result 77 becomes equal to or greater than the value of M', adder 73 subtracts the value of N' from addition result 87, which is the value of the addition result stored in memory circuit 74.

[0126] As described above, the non-marker portion masking signal generating unit 53 compares the addition result 77 with the value of M' using the magnitude comparator 76. The non-marker portion masking signal generating unit 53 stores the comparison result 78 output by the magnitude comparator 76, i.e., the comparison result 78 representing the result of comparing the addition result 77 with the value of M', in the memory circuit 75. The magnitude comparator 76 and the memory circuit 75 will be described in further detail below.

[0127] The magnitude comparator 76 receives the addition result 77 and the signal M'. The magnitude comparator 76 compares the value of the addition result 77 with the value of the signal M' (i.e., the value of the division ratio denominator M' in the non-marker section). The magnitude comparator 76 outputs a value representing the result of the comparison as the comparison result 78. Specifically, the magnitude comparator 76 outputs a value representing the result of the comparison as the value of the comparison result 78. When the value of the addition result 77 is equal to or greater than the value of the signal M', the magnitude comparator 76 outputs a value indicating that the value of the addition result 77 is equal to or greater than the value of the signal M' (e.g., value 1) as the value representing the result of the comparison, i.e., the value of the comparison result 78. When the value of the addition result 77 is smaller than the value of the signal M', the magnitude comparator 76 outputs a value indicating that the value of the addition result 77 is smaller than the value of the signal M' (e.g., value 0) as the value representing the result of the comparison, i.e., the value of the comparison result 78. The comparison result 78 is input to the storage circuit 75. The memory circuit 75 stores the value of the input comparison result 78. The comparison result 78, which indicates the result of the comparison by the magnitude comparator 76, is also output as the mask signal 59. In other words, the value of the comparison result 78 is also output as the value of the mask signal 59.

[0128] The comparison result 78 output by the magnitude comparator 76 is input to the memory circuit 75. The memory circuit 75 receives the comparison result 78 as an input. The memory circuit 75 stores the value of the received comparison result 78. The memory circuit 75 outputs the stored value as a comparison result 88.

[0129] The memory circuit 75 further receives the initialization signal 82 output by the initialization circuit 81 as input. The memory circuit 75 receives the initialization signal 82 as an input. When the memory circuit 75 receives the initialization signal 82, it initializes the stored value. In this example, the value 0 as the value of the comparison result (comparison result 78 and comparison result 88) indicates that the value of the addition result 77 is smaller than the value of M'. In this case, when the memory circuit 75 receives the initialization signal 82, it sets the stored value to the value 0.

[0130] As described above, the comparison result 78 representing the result of comparison by the magnitude comparator 76 is also output as the mask signal 59. In other words, the value of the comparison result 78 is also output as the value of the mask signal 59.

[0131] Accordingly, the non-marker part mask signal generation unit 53 outputs a mask signal 59 having a value corresponding to the comparison result 78 by the magnitude comparator 76. Specifically, when the comparison result 78 indicates that the value of the addition result 77 is greater than or equal to the value of M', the non-marker part mask signal generation unit 53 outputs, as the value of the mask signal 59, a value 1 which is a value indicating that the mask circuit 61 performs a masking operation. When the comparison result 78 indicates that the value of the addition result 77 is less than the value of M', the non-marker part mask signal generation unit 53 outputs, as the value of the mask signal 59, a value 0 which is a value indicating that the mask circuit 61 does not perform a masking operation.

[0132] The non-marker part of the divided clock signal output by the non-marker part mask signal generation unit 53 that performs the operations described above has the following characteristics. In the following description as well, as described above, M and N are the denominator M and numerator N of the division ratio in the input division ratio setting.

[0133] When M and N satisfy N = M - 1, in the non-marker part, the clock pulse is not masked. Therefore, in the target circuit operating with the generated divided clock, it is possible to easily detect a marker part including a cycle in which the clock pulse is masked.

[0134] Also, when M and N satisfy M / 2 ≤ N and N < M - 1, in the non-marker part, the clock pulse is not masked for two consecutive cycles. Therefore, in the target circuit, it is possible to easily detect a marker part including a cycle in which the clock pulse is masked for two consecutive cycles.

[0135] Also, when M and N satisfy 2 ≤ N and N < M / 2, in the non-marker part, clock pulses are not masked continuously for two cycles. Therefore, in the target circuit, a marker part including cycles in which clock pulses are not masked continuously for two cycles can be easily detected.

[0136] Also, when N satisfies N = 1, in the non-marker part, clock pulses are not unmasked. That is, all clock pulses in the non-marker part are masked. Therefore, in the target circuit, a marker part including cycles in which clock pulses are not masked can be easily detected.

[0137] FIG. 5 is a diagram showing an example of transitions of signals and values related to the clock signal frequency divider circuit 10 according to an embodiment of the present disclosure.

[0138] Next, an example of the operation of the clock signal frequency divider circuit 10 according to the first embodiment of the present disclosure will be described with reference to FIG. 5. FIG. 5 shows an example of transitions of signals and values related to the clock signal frequency divider circuit 10 when the clock signal frequency divider circuit 10 divides the input clock S with a division ratio N / M = 6 / 12.

[0139] The pattern of clock pulses of the divided clock generated by the clock signal frequency divider circuit 10 makes one round in M cycles (in the example shown in FIG. 5, M = 12 cycles). In FIG. 5, the 12 cycles of one round are indicated by cycles T0 to T11.

[0140] The three cycles of cycles T0 to T2 are the marker part. The marker part mask signal generation unit 52 generates a mask signal for the marker part in the three cycles of cycles T0 to T2. The marker part mask signal generation unit 52 outputs the generated mask signal for the marker part as the mask signal 58.

[0141] Specifically, when the frequency division ratio N / M is 6 / 12 as in the example shown in FIG. 5, M and N satisfy M / 2 ≤ N and N < M - 1. When M and N satisfy M / 2 ≤ N and N < M - 1, the marker part is marker 12. The marker part mask signal generation unit 52 outputs the following signals in the cycles from cycle T0 to cycle T2 as the mask signal used for generating the clock pattern of marker 12. The marker part mask signal generation unit 52 outputs, as the value of the mask signal 58, a value 0 which is a value indicating not to mask the clock pulse in cycle T0. The marker part mask signal generation unit 52 outputs, as the value of the mask signal 58, a value 1 which is a value indicating to mask the clock pulse in cycles T1 and T2.

[0142] The nine cycles from cycle T3 to T11 are non-marker parts. The non-marker part mask signal generation unit 53 generates the mask signals for the non-marker parts in the nine cycles from cycle T3 to T11. Then, the non-marker part mask signal generation unit 53 outputs the generated mask signals as the mask signal 59.

[0143] When the division ratio N / M is 6 / 12 as in the example shown in FIG. 5, M and N satisfy M / 2 ≤ N and N < M - 1. Since M and N satisfy M / 2 ≤ N and N < M - 1, the non - marker part mask signal generation unit 53 converts the division ratio N / M indicated by the input division ratio setting into the division ratio N' / M' of the non - marker part when M and N satisfy M / 2 ≤ N and N < M - 1. Specifically, in the example shown in FIG. 5, since the division ratio N / M is 6 / 12, the non - marker part mask signal generation unit 53 converts the division ratio N / M = 6 / 12 into the division ratio N' / M'=(N - 1) / (M - 3)=5 / 9 of the non - marker part. The non - marker part mask signal generation unit 53 generates a mask signal for the non - marker part so that the division ratio of the non - marker part of the output clock pulse becomes the obtained division ratio N' / M' of the non - marker part. In the example shown in FIG. 5, the non - marker part mask signal generation unit 53 generates a mask signal for the non - marker part so that the division ratio of the non - marker part of the output clock pulse becomes the obtained division ratio N' / M' = 5 / 9 of the non - marker part. Hereinafter, the non - marker part mask signal generation unit 53 will be described in more detail.

[0144] The initialization circuit 81 included in the non-marker portion mask signal generating unit 53 initializes the memory circuit 74 and the memory circuit 75 in cycles T0 to T2 which are the marker portion and in T3 which is the first cycle of the non-marker portion. Specifically, the initialization circuit 81 outputs a signal indicating a value (for example, value 1) representing initialization as the initialization signal 82 in each of cycles T0 to T2 which are the marker portion and in cycles T11 to T2 which are the cycles immediately before T3 which is the first cycle of the non-marker portion. As a result, the memory circuit 74 and the memory circuit 75 are initialized in cycles T0 to T3. As a result, the addition result 87 which is the output of the memory circuit 74 and the comparison result 88 which is the output of the memory circuit 75 are initialized in cycles T0 to T3. Specifically, the value of the addition result 87 which is the output of the memory circuit 74 and the value of the comparison result 88 which is the output of the memory circuit 75 are initialized to a value in the initialized state (for example, value 0). The initial value of the value of the addition result 87 is value 0. The initialized state value of the comparison result 88 (eg, the value 0) is the value that indicates that the value of M'-N' is smaller than the value of M', as described above.

[0145] The cycles after cycle T3 will be described below. In cycles T3 to T10, the value of the initialization signal 82 input to the memory circuits 74 and 75 is the value 0 indicating no initialization (in other words, the value 0 indicating no initialization). As described above, in cycle T11, the value of the initialization signal 82 input to the memory circuits 74 and 75 is the value 1 indicating initialization (in other words, the value 1 indicating initialization).

[0146] In cycle T3, the value stored in memory circuit 75 is 0. The comparison result 88 is input to selector circuit 72 as the value of comparison result 88, which is the value stored in memory circuit 75. The value of comparison result 88 is an initialized value (value 0 in this example). This value indicates that the value of M'-N' is smaller than the value of M'. Therefore, selector circuit 72 selects signal M'-N'. Then, selector circuit 72 outputs the selected signal M'-N' as a signal representing the sum 83. Specifically, in the example shown in FIG. 5, the division ratio N' / M' of the non-marker part is 5 / 9. Selector circuit 72 outputs M'-N'=4, which is the value of the selected signal M'-N', as the value of sum 83.

[0147] The adder 73 adds the value of the addend value 83 and the value of the addition result 87. The adder 73 outputs the value resulting from the addition of the value of the addend value 83 and the value of the addition result 87 as the value of the addition result 77. Specifically, in the above example, the adder 73 obtains the value 4, which is the addition result, by adding the value 4 of the addend value 83 and the value 0 of the addition result 87. The adder 73 outputs the value 4, which is the addition result of the value 4 of the addend value 83 and the value 0 of the addition result 87, as the value of the addition result 77.

[0148] The magnitude comparator 76 compares the value of the addition result 77 with the value of the signal M'. The magnitude comparator 76 outputs a value representing the result of the comparison as the value of the comparison result 78. When the value of the addition result 77 is greater than or equal to the value of M', the magnitude comparator 76 outputs a value (value 1 in this example) indicating that the value of the addition result 77 is greater than or equal to the value of M' as the value representing the result of the comparison, that is, the value of the comparison result 78. When the value of the addition result 77 is less than the value of M', the magnitude comparator 76 outputs a value (value 0 in this example) indicating that the value of the addition result 77 is less than the value of M' as the value representing the result of the comparison, that is, the value of the comparison result 78. The comparison result 78 representing the result of the comparison by the magnitude comparator 76 is also output as the mask signal 59. In the above example, the magnitude comparator 76 compares the value 4 of the addition result 77 with M' = 9 which is the value of the signal M'. Since the value of the addition result 77 < M', the value of the comparison result is a value (value 0 in this example) indicating that the value of the addition result 77 is less than the value of M'. The magnitude comparator 76 outputs the value 0 which is the comparison result of the value 4 of the addition result 77 and M' = 9 which is the value of the signal M' as the value of the comparison result 78. Note that the magnitude comparator 76 is configured such that the value indicating that the value of M' is greater than the value of the addition result 77 is 0. As described above, the magnitude comparator 76 also outputs the comparison result 78 as the mask signal 59. As a result, the value 0 is output as the value of the mask signal 59.

[0149] Also, the addition result 77 is input to the memory circuit 74. The memory circuit 74 stores the value of the addition result 77. The comparison result 78 is input to the memory circuit 75. The memory circuit 75 stores the value of the comparison result 78. In this example, the memory circuit 74 stores the value 4 which is the value of the addition result 77. The memory circuit 75 stores the value 0 which is the value of the comparison result 78.

[0150] In the next cycle T4, the value stored in the memory circuit 75 is the value 0. The value stored in the memory circuit 75 is input to the selector circuit 72 as the value of the comparison result 88. The value 0 input to the selector circuit as the value of the comparison result 88 represents that the value of the addition result 77 is smaller than the value of M'. Therefore, the selector circuit 72 selects the signal M' - N'. Then, the selector circuit 72 outputs the selected signal M' - N' as the signal representing the addition value 83. As described above, in the example shown in FIG. 5, the division ratio N' / M' of the non-marker part is 5 / 9. The selector circuit 72 outputs M' - N' = 4, which is the value of the selected signal M' - N', as the value of the addition value 83.

[0151] As described above, the value of the addition value 83, which is the output of the selector circuit 72, is input to the adder 73. The value stored in the memory circuit 74 is input to the adder 73 as the value of the addition result 87. The adder 73 adds the value of the addition value 83 and the value of the addition result 87. The adder 73 outputs the value that is the result of the addition of the value of the addition value 83 and the value of the addition result 87 as the value of the addition result 77. In the above example, the memory circuit 74 stores the value 4. The adder 73 adds the value 4 of the addition value 83 and the value 4 of the addition result 87. The adder 73 obtains the value 8 as the addition result of the value 4 of the addition value 83 and the value 4 of the addition result 87. The adder 73 outputs the value 8, which is the addition result of the value 4 of the addition value 83 and the value 4 of the addition result 87, as the value of the addition result 77.

[0152] As described above, the magnitude comparator 76 compares the value of the addition result 77 with the value of the signal M'. The magnitude comparator 76 outputs the value representing the result of the comparison as the value of the comparison result 78. The comparison result 78 representing the result of the comparison by the magnitude comparator 76 is also output as the mask signal 59. In the above example, the magnitude comparator 76 compares the value 8 of the addition result 77 with M' = 9, which is the value of the signal M'. Since the value of the addition result 77 < M', the magnitude comparator 76 outputs the value 0, which is the comparison result of the value 4 of the addition result 77 and the value M' = 9 of the signal M', as the value of the comparison result 78. The value indicating that the value of M' is greater than the value of the addition result 77 is 0. As described above, the magnitude comparator 76 also outputs the comparison result 78 as the mask signal 59. As a result, the value 0 is output as the value of the mask signal 59.

[0153] Moreover, the memory circuit 74 stores the value of the addition result 77. The memory circuit 75 stores the value of the comparison result 78. In this example, the memory circuit 74 stores the value of the addition result 77, which is 8. The memory circuit 75 stores the value of the comparison result 78, which is 0.

[0154] In cycle T5, the value stored in memory circuit 75 is the value 0. The value stored in memory circuit 75 is input to selector circuit 72 as comparison result 88. In this example, the value 0 is input to selector circuit 72 as comparison result 88. As described above, the value 0 indicates that the value of addition result 77 is smaller than the value of M'. If the value of addition result 77 is smaller than the value of M', selector circuit 72 selects signal M'-N'. Then, selector circuit 72 outputs the selected value as addition value 83. Therefore, selector circuit 72 selects M'-N'=4. Then, selector circuit 72 outputs the value 4 as addition value 83.

[0155] The adder 73 receives the addend 83 output from the selector circuit 72 and the addition result 87 output from the memory circuit 74. The addition result 87 is a value stored in the memory circuit 74. The adder 73 adds the value of the addend 83 and the value of the addition result 87. The adder 73 outputs the result of adding the value of the addend 83 and the value of the addition result 87 as the addition result 77. In this example, the adder 73 outputs the value 12, which is the result of adding the value 4 of the addend 83 to the value 8 of the addition result 87, as the value of the addition result 77.

[0156] As described above, the magnitude comparator 76 compares the value of the addition result 77 with the value of M'. Then, the magnitude comparator 76 outputs a value representing the result of the comparison between the value of the addition result 77 and the value of M' as the comparison result 78. In cycle T5, the value of the addition result 77 is 12. Also, the value of M' is 9 (that is, the value of M' is represented by M'=9). The magnitude comparator 76 compares the value of the addition result 77, 12, with M'=9. In this case, the value of the addition result 77≧M' holds. Therefore, the magnitude comparator 76 outputs a value representing that the value of the addition result 77 is equal to or greater than M' as the value of the comparison result representing the result of the comparison between the value of the addition result 77 and the value of M'. In this example, the value representing that the value of the addition result 77 is equal to or greater than M' is the value 1. Therefore, in this case, the magnitude comparator 76 outputs the value 1, which is the comparison result representing the result of the comparison between the value of the addition result 77 and the value of M', as the value of the comparison result 78. The value of the comparison result 78 output by the magnitude comparator 76 is also output as the mask signal 59. As a result, the value 1 is output as the value of the mask signal 59.

[0157] Also, as described above, the addition result 77 is input to the memory circuit 74. The memory circuit 74 stores the value of the input addition result. The comparison result 78 is input to the memory circuit 75. The memory circuit 75 stores the value of the input comparison result 78. In cycle T5, the value of the addition result 77 is value 12. The value of the comparison result 78 is value 1. The memory circuit 74 stores the value 12 of the addition result 77. The memory circuit 75 stores the value 1 of the comparison result 78.

[0158] In cycle T6, the memory circuit 74 stores a value (value 1 in this example) indicating that the value of the addition result 77 is equal to or greater than M'. Therefore, the value of the comparison result 88 output by the memory circuit 74 is a value (value 1 in this example) indicating that the value of the addition result 77 is equal to or greater than M'. Because the comparison result 88 is value 1, that is, because the value of the addition result 77 is equal to or greater than M', the selector circuit 72 selects the signal -N'. The selector circuit 72 outputs the selected signal -N' as the addition value 83. In this example, the selector circuit 72 outputs the addition value 83 whose value is -N'=-5.

[0159] The value of the addition result stored in the memory circuit 74 is 12. An addition value 83 with a value of -5 and an addition result 87 with a value of 12 are input to the adder 73. The adder 73 receives the addition value 83 with a value of -5 and the addition result 87 with a value of 12 as inputs. The adder 73 adds the value -5 which is the value of the addition value 83 and the value 12 which is the value of the addition result 87. By adding the value -5 which is the value of the addition value 83 and the value 12 which is the value of the addition result 87, the adder 73 obtains a value 7 as the addition result. The adder 73 outputs an addition result 77 indicating the obtained addition result value 7.

[0160] An addition result 77 with a value of 7 and a signal M' with a value of 9 are input to the magnitude comparator 76. The magnitude comparator 76 receives the addition result 77 with a value of 7 and the signal M' with a value of 9 as inputs. The magnitude comparator 76 compares the value 7 which is the value of the addition result 77 and M' = 9 which is the value of the signal M'. Since the value of the addition result 77 < the value of M' holds, the magnitude comparator 76 outputs a comparison result 78 indicating a value (in this example, the value 0) indicating that the value of the addition result is smaller than the value of M'. Since the comparison result 78 is also output as the mask signal 59, as a result, a mask signal 59 with a value of 0 is output as the mask signal 59.

[0161] Also, an addition result 77 with a value of 7 is input to the memory circuit 74. The memory circuit 74 receives the addition result 77 with a value of 7. The memory circuit 74 stores the value 7 of the addition result 77. A comparison result 78 with a value of 0 is input to the memory circuit 75. The memory circuit 75 receives the comparison result 78 with a value of 0. The memory circuit 75 stores the value 0 of the comparison result 78.

[0162] In cycle T7, the storage circuit 74 stores a value (value 0 in this example) indicating that the value of the addition result 77 is smaller than M'. Therefore, the value of the comparison result 88 output by the storage circuit 74 is a value (value 0 in this example) indicating that the value of the addition result 77 is smaller than M'. Since the comparison result 88 is value 0, that is, since the value of the addition result 77 is smaller than M', the selector circuit 72 selects the signal M'-N'. The selector circuit 72 outputs the selected signal M'-N' as the addition value 83. In this example, the selector circuit 72 outputs the addition value 83 whose value is M'-N'=4.

[0163] The value of the addition result stored in memory circuit 74 is the value 7. Adder 73 is input with addend value 83, which has a value of 4, and addition result 87, which has a value of 7. Adder 73 receives addend value 83, which has a value of 4, and addition result 87, which has a value of 7, as input. Adder 73 adds together value 4, which is the value of addend value 83, and value 7, which is the value of addition result 87. Adder 73 adds together value 4, which is the value of addend value 83, and value 7, which is the value of addition result 87, to obtain value 11 as the addition result. Adder 73 outputs addition result 77, which indicates the obtained addition result, value 11.

[0164] The magnitude comparator 76 receives the addition result 77, whose value is 11, and the signal M', whose value is 9. The magnitude comparator 76 receives the addition result 77, whose value is 11, and the signal M', whose value is 9, as inputs. The magnitude comparator 76 compares the value 11 of the addition result 77 with the value M', whose value is M'=9. Since the value of the addition result 77 is equal to or greater than M', the magnitude comparator 76 outputs a comparison result 78, which indicates a value (in this example, a value of 1) indicating that the value of the addition result is equal to or greater than M'. The comparison result 78 is also output as the mask signal 59, and as a result, the mask signal 59, whose value is 1, is output as the mask signal 59.

[0165] Furthermore, addition result 77, whose value is 11, is input to memory circuit 74. Memory circuit 74 receives addition result 77, whose value is 11. Memory circuit 74 stores the value 11 of addition result 77. Comparison result 78, whose value is 1, is input to memory circuit 75. Comparison result 78, whose value is 1, is received. Memory circuit 75 stores the value 1 of comparison result 78.

[0166] In cycle T8, the memory circuit 74 stores a value (value 1 in this example) indicating that the value of the addition result 77 is equal to or greater than M'. Therefore, the value of the comparison result 88 output by the memory circuit 74 is a value (value 1 in this example) indicating that the value of the addition result 77 is equal to or greater than M'. Because the comparison result 88 is value 1, that is, because the value of the addition result 77 is equal to or greater than M', the selector circuit 72 selects the signal -N'. The selector circuit 72 outputs the selected signal -N' as the addition value 83. In this example, the selector circuit 72 outputs the addition value 83 whose value is -N'=-5.

[0167] The value of the addition result stored in memory circuit 74 is the value 11. Adder 73 is input with addend value 83, which has a value of -5, and addition result 87, which has a value of 11. Adder 73 receives addend value 83, which has a value of -5, and addition result 87, which has a value of 11, as input. Adder 73 adds together the value -5 of addend value 83 and the value 11 of addition result 87. Adder 73 adds together the value -5 of addend value 83 and the value 11 of addition result 87, thereby obtaining the value 6 as the addition result. Adder 73 outputs addition result 77 indicating the obtained addition result, value 6.

[0168] The magnitude comparator 76 receives as input the addition result 77 with a value of 6 and the signal M' with a value of 9. The magnitude comparator 76 takes as input the addition result 77 with a value of 6 and the signal M' with a value of 9. The magnitude comparator 76 compares the value 6 which is the value of the addition result 77 with the value M' = 9 which is the value of the signal M'. Since the value of the addition result 77 < the value of M' holds, the magnitude comparator 76 outputs a comparison result 78 indicating a value (in this example, the value 0) that the value of the addition result is smaller than the value of M'. Since the comparison result 78 is also output as the mask signal 59, as a result, a mask signal 59 with a value of 0 is output as the mask signal 59.

[0169] Also, the addition result 77 with a value of 6 is input to the memory circuit 74. The memory circuit 74 receives the addition result 77 with a value of 6. The memory circuit 74 stores the value 6 of the addition result 77. The comparison result 78 with a value of 0 is input to the memory circuit 75. The memory circuit 75 receives the comparison result 78 with a value of 0. The memory circuit 75 stores the value 0 of the comparison result 78.

[0170] In cycle T9, the memory circuit 74 stores a value (in this example, the value 0) indicating that the value of the addition result 77 is smaller than M'. Therefore, the value of the comparison result 88 output by the memory circuit 74 is a value (in this example, the value 0) indicating that the value of the addition result 77 is smaller than M'. Since the comparison result 88 is 0, that is, since the value of the addition result 77 is smaller than M', the selector circuit 72 selects the signal M' - N'. The selector circuit 72 outputs the selected signal M' - N' as the addition value 83. In this example, the selector circuit 72 outputs an addition value 83 with a value of M' - N' = 4.

[0171] The value of the addition result stored in memory circuit 74 is the value 6. Adder 73 is input with addend value 83, which has a value of 4, and addition result 87, which has a value of 6. Adder 73 receives addend value 83, which has a value of 4, and addition result 87, which has a value of 6, as input. Adder 73 adds together value 4, which is the value of addend value 83, and value 6, which is the value of addition result 87. Adder 73 adds together value 4, which is the value of addend value 83, and value 6, which is the value of addition result 87, to obtain value 10 as the addition result. Adder 73 outputs addition result 77, which indicates the obtained addition result, value 10.

[0172] The magnitude comparator 76 receives the addition result 77, whose value is 10, and the signal M', whose value is 9. The magnitude comparator 76 receives the addition result 77, whose value is 10, and the signal M', whose value is 9, as inputs. The magnitude comparator 76 compares the value 10 of the addition result 77 with the value of the signal M', M'=9. Since the value of the addition result 77 is equal to or greater than M', the magnitude comparator 76 outputs a comparison result 78, which indicates a value (value 1 in this example) indicating that the value of the addition result is equal to or greater than M'. The comparison result 78 is also output as the mask signal 59, and as a result, the mask signal 59, whose value is 1, is output as the mask signal 59.

[0173] Furthermore, addition result 77, whose value is 10, is input to memory circuit 74. Memory circuit 74 receives addition result 77, whose value is 10. Memory circuit 74 stores the value 10 of addition result 77. Comparison result 78, whose value is 1, is input to memory circuit 75. Comparison result 78, whose value is 1, is received. Memory circuit 75 stores the value 1 of comparison result 78.

[0174] In cycle T10, the memory circuit 74 stores a value (value 1 in this example) indicating that the value of the addition result 77 is equal to or greater than M'. Therefore, the value of the comparison result 88 output by the memory circuit 74 is a value (value 1 in this example) indicating that the value of the addition result 77 is equal to or greater than M'. Since the comparison result 88 is value 1, that is, since the value of the addition result 77 is equal to or greater than M', the selector circuit 72 selects the signal -N'. The selector circuit 72 outputs the selected signal -N' as the addition value 83. In this example, the selector circuit 72 outputs an addition value 83 with a value of -N' = -5.

[0175] The value of the addition result stored in the memory circuit 74 is value 10. The adder 73 receives an addition value 83 with a value of -5 and an addition result 87 with a value of 10. The adder 73 receives the addition value 83 with a value of -5 and the addition result 87 with a value of 10 as inputs. The adder 73 adds the value -5, which is the value of the addition value 83, and the value 10, which is the value of the addition result 87. By adding the value -5, which is the value of the addition value 83, and the value 10, which is the value of the addition result 87, the adder 73 obtains a value 5 as the addition result. The adder 73 outputs an addition result 77 indicating the obtained addition result value 5.

[0176] The magnitude comparator 76 receives an addition result 77 with a value of 5 and a signal M' with a value of 9. The magnitude comparator 76 receives the addition result 77 with a value of 5 and the signal M' with a value of 9 as inputs. The magnitude comparator 76 compares the value 5, which is the value of the addition result 77, with M' = 9, which is the value of the signal M'. Since the value of the addition result 77 < the value of M' holds, the magnitude comparator 76 outputs a comparison result 78 indicating a value (value 0 in this example) indicating that the value of the addition result is smaller than the value of M'. Since the comparison result 78 is also output as the mask signal 59, as a result, a mask signal 59 with a value of 0 is output as the mask signal 59.

[0177] Furthermore, addition result 77, whose value is 5, is input to memory circuit 74. Memory circuit 74 receives addition result 77, whose value is 5. Memory circuit 74 stores the value 5 of addition result 77. Comparison result 78, whose value is 0, is input to memory circuit 75. Comparison result 78, whose value is 0, is received. Memory circuit 75 stores comparison result 78, whose value is 0.

[0178] In cycle T11, the storage circuit 74 stores a value (value 0 in this example) indicating that the value of the addition result 77 is smaller than M'. Therefore, the value of the comparison result 88 output by the storage circuit 74 is a value (value 0 in this example) indicating that the value of the addition result 77 is smaller than M'. Since the comparison result 88 is value 0, that is, since the value of the addition result 77 is smaller than M', the selector circuit 72 selects the signal M'-N'. The selector circuit 72 outputs the selected signal M'-N' as the addition value 83. In this example, the selector circuit 72 outputs the addition value 83 whose value is M'-N'=4.

[0179] The value of the addition result stored in memory circuit 74 is the value 5. Adder 73 is input with addend value 83, which has a value of 4, and addition result 87, which has a value of 5. Adder 73 receives addend value 83, which has a value of 4, and addition result 87, which has a value of 5, as input. Adder 73 adds value 4, which is the value of addend value 83, to value 5, which is the value of addition result 87. Adder 73 adds value 4, which is the value of addend value 83, to value 5, which is the value of addition result 87, to obtain value 9 as the addition result. Adder 73 outputs addition result 77, which indicates value 9, the obtained addition result.

[0180] The magnitude comparator 76 receives the addition result 77, whose value is 9, and the signal M', whose value is 9. The magnitude comparator 76 receives the addition result 77, whose value is 9, and the signal M', whose value is 9, as inputs. The magnitude comparator 76 compares the value 9 of the addition result 77 with the value M', whose value is M'=9. Since the value of the addition result 77 is equal to or greater than M', the magnitude comparator 76 outputs a comparison result 78, which indicates a value (in this example, a value of 1) indicating that the value of the addition result is equal to or greater than M'. The comparison result 78 is also output as the mask signal 59, and as a result, the mask signal 59, whose value is 1, is output as the mask signal 59.

[0181] As described above, in cycle T11, the value of the initialization signal 82 output by the initialization circuit 81 is the value 1, which is a value instructing initialization. Therefore, the memory circuits 74 and 75, to which the initialization signal 82 is respectively input, initialize the stored value upon receiving the initialization signal 82. In other words, upon receiving the initialization signal 82, the memory circuits 74 and 75 set the stored value to the value 0. Then, the memory circuits 74 and 75 store the value 0.

[0182] Through the above operations, non-marker portion mask signal generating unit 53 outputs a value of 1, which instructs masking of the clock pulse, as the value of mask signal 59 in cycles T5, T7, T9, and T11 among cycles T3 to T11 which are non-marker portions. Then, non-marker portion mask signal generating unit 53 outputs a value of 0, which instructs not to mask the clock pulse, as the value of mask signal 59 in the other cycles T3, T4, T6, T8, and T10 among cycles T3 to T11 which are non-marker portions.

[0183] The selection circuit 54 included in the clock signal division circuit 10 selects the mask signal 58 output by the marker section mask signal generation unit 52 in cycles TO to T2 which are the marker section. The selection circuit 54 outputs the selected mask signal as the mask signal 55. In cycles TO to T2 which are the marker section, the selection circuit 54 outputs the mask signal 58 output by the marker section mask signal generation unit 52 as the mask signal 55. In cycles T3 to T11 which are the non-marker section, the selection circuit 54 selects the mask signal 59 output by the non-marker section mask signal generation unit 53. In cycles T3 to T11 which are the non-marker section, the selection circuit 54 outputs the mask signal 59 output by the non-marker section mask signal generation unit 53 as the mask signal 55. Therefore, in cycles T1, T2, T5, T7, T9, and T11, the value 1 which instructs masking of the clock pulse is output as the value of the mask signal 55. In other cycles (that is, cycles other than cycles T1, T2, T5, T7, T9 and T11), the value of the mask signal 55 is set to 0, which indicates that the clock pulse is not masked.

[0184] The mask circuit 61 refers to the mask signal 55 to determine which clock pulses of the input clock S are to be masked. In other words, the mask circuit 61 masks the clock pulses of the input clock S in the cycles for which the value of the mask signal 55 indicates that the clock pulses are to be masked. In this example, the mask circuit 61 masks the clock pulses in cycles T1, T2, T5, T7, T9, and T11 of the input clock S. The mask circuit 61 does not mask the clock pulses in other cycles (i.e., cycles other than cycles T1, T2, T5, T7, T9, and T11) of the input clock S. As a result, a divided clock in which the clock pulses are masked in 6 cycles out of 12 cycles in which the division pattern goes around is output, that is, a divided clock with a division ratio of N / M=6 / 12.

[0185] Next, an example of the timing of communication between circuit A and circuit B in this embodiment will be described with reference to FIG.

[0186] FIG. 6 is a diagram illustrating an example of communication timing between circuit A and circuit B according to an embodiment of the present disclosure.

[0187] 6 illustrates signals such as clocks and communication timing when communication is performed between circuit A operating on clock S and circuit B operating on clock B. In the example illustrated in FIG. 6, clock B is a clock signal generated by dividing clock S by a division ratio N / M=11 / 12 using clock signal divider circuit 10. In this example, the clock pulse pattern of clock B generated by clock signal divider circuit 10 completes one cycle in M=12 cycles. In FIG. 6, the 12 cycles are indicated by cycles T0 to T11.

[0188] The three cycles T0 to T2 are the marker section. The division ratio N / M is N / M=1 / 12. That is, M and N indicating the division ratio satisfy N=M-1. As described above, the marker section in this case is the marker 11.

[0189] The toggle signal generation circuit 22 receives the clock B as an input. Then, the toggle signal generation circuit 22 generates a toggle signal 23 whose value is inverted for each clock pulse of the clock B. The toggle signal generation circuit 22 outputs the generated toggle signal 23.

[0190] In other words, the toggle signal generating circuit 22 outputs a toggle signal having one of two values ​​(for example, 0 and 1). The toggle signal generating circuit 22 maintains the same value of the toggle signal it generates while not receiving a clock pulse. Then, when the toggle signal generating circuit 22 receives a clock pulse, it changes (i.e., transitions) the value of the toggle signal from the value before receiving the clock pulse to the other value. When the toggle signal generating circuit 22 receives a clock pulse if the value of the toggle signal is, for example, 1, it transitions the value of the toggle signal from 1 to 0. Also, when the toggle signal generating circuit 22 receives a clock pulse if the value of the toggle signal is, for example, 0, it transitions the value of the toggle signal from 0 to 1. If the initial values ​​of the toggle signals are the same and the clock pulses received by the toggle signal generating circuit 22 are the same, the toggle signals generated by the toggle signal generating circuit 22 are the same. However, if the clock pulses received by the toggle signal generation circuit 22 are different, the toggle signal generated by the toggle signal generation circuit 22 will be different even if the clock pulses received by the toggle signal generation circuit 22 are the same. That is, there are two cases of signal transition (i.e., value transition) of the toggle signal 23 depending on the initial value of the toggle signal 23. In other words, there can be two toggle signals as the toggle signal 23 that differ depending on the initial value, that is, a toggle signal when the initial value is 1 and a toggle signal when the initial value is 0.

[0191] In FIG. 6, two toggle signals with different initial values ​​are illustrated as toggle signal 23a and toggle signal 23b. The toggle signal generating circuit 22 may generate either toggle signal 23a or toggle signal 23b as the toggle signal to be output as the toggle signal 23. In this description, when the toggle signal 23a and the toggle signal 23b are not distinguished from each other, the toggle signal 23a and the toggle signal 23b are collectively referred to as toggle signal 23. In the example shown in FIG. 6, the cycle in which both the toggle signal 23a and the toggle signal 23b do not toggle is only the part of cycle T2. In the example shown in FIG. 6, the marker portion is the marker 11. The part of cycle T2 of the toggle signal 23 (i.e., the part of the cycle in which the toggle signal 23 does not toggle) is the toggle signal marker 41, which is the toggle signal marker of the marker 11 (hereinafter, also referred to as the toggle signal marker). A toggle signal marker (ie, a toggle signal marker) is a signal pattern that is present in a toggle signal only at the toggle signal marker portion.

[0192] In this case, the toggle signal marker (in other words, the signal pattern of the toggle signal marker) may be represented by information representing a transition of the presence or absence of a value transition in one or more cycles. The information representing a transition of the presence or absence of a value transition in one or more cycles is information representing the presence or absence of a value transition in one cycle, or information representing the transition of the presence or absence of a value transition in multiple consecutive cycles. The information representing a transition of the presence or absence of a value transition in one or more cycles is, for example, information indicating that there is no value transition (hereinafter, referred to as "no transition") and information indicating that there is a value transition (hereinafter, referred to as "transition"). The information representing a transition of the presence or absence of a value transition in two consecutive cycles is, for example, information representing "no transition, no transition" and information representing "transition, transition". Then, when a transition of the presence or absence of a value transition represented by the toggle signal marker occurs in the toggle signal, the communication control circuit 20 detects the part of the toggle signal where the transition of the presence or absence of the value transition occurs as the toggle signal marker.

[0193] Therefore, the communication control circuit 20 included in the circuit A can know the timing of the marker portion by identifying the toggle signal marker 41 with reference to the toggle signal 23. Specifically, the communication control circuit 20 detects the toggle signal marker in the toggle signal 23. When the toggle signal marker 41 is detected, the communication control circuit 20 identifies the cycle in which the toggle signal marker 41 was detected in the toggle signal 23. Note that when M and N indicating the frequency division ratio satisfy N=M-1 and the marker portion is the marker 11, the toggle signal marker is the toggle signal marker 41.

[0194] The relationship between the timing of the head of the marker section and the timing of the cycle in which the toggle signal marker exists may be provided in advance to the communication control circuit for each type of toggle signal marker. The cycle in which the toggle signal marker exists is, for example, the timing of the head cycle of the toggle signal marker. The timing of the cycle in which the toggle signal marker exists is also referred to as the timing of the toggle signal marker. The types of toggle signal markers are, for example, a toggle signal marker 41 and toggle signal markers 42 to 44 described later. In addition, when the circuit with which the circuit A communicates is only one circuit B, the toggle signal marker of the toggle signal generated from the divided clock signal having the division ratio of the divided clock signal supplied to the circuit B may be provided to the communication control circuit 20. In the case where the circuits with which the circuit A communicates are multiple circuits B to which divided clock signals having the same division ratio are supplied, the toggle signal marker of the toggle signal generated from the divided clock signal having the division ratio of the divided clock signal supplied to the circuit B may be provided to the communication control circuit 20. The relationship between the timing of the start of the marker section and the timing of the cycle in which the toggle signal marker exists is the magnitude of the difference between the timing of the start of the marker section and the timing of the cycle in which the toggle signal marker exists. The magnitude of this difference may be expressed, for example, by the number of cycles. The start of the marker section is the start of a periodic pattern signal that is a signal having a length in which the phase relationship between the clock S and the clock B completes one cycle. In other words, the communication control circuit 20 specifies the start timing of the periodic pattern signal from, for example, the timing of the cycle of the detected toggle signal marker and the relationship between the timing of the start of the marker section and the timing of the toggle signal marker 41. As a result, the communication control circuit 20 can identify the start timing of the cycle in which the phase relationship between the clock S and the clock B completes one cycle.

[0195] Furthermore, the communication control circuit 20 can recognize (in other words, specify) the timing when a clock pulse exists in both the clock S and the clock B by referring to the division ratio setting 30, which is the setting information of the division ratio of the clock B. As described above, the clock B is generated by masking a part of the clock pulse of the clock S. Therefore, in a cycle (in other words, the timing) when a clock pulse exists in the clock B having the division ratio specified by the division ratio setting 30, a clock pulse exists in both the clock S and the clock B. The communication control circuit 20 generates a signal indicating the recognized timing when a clock pulse exists in both the clock S and the clock B as the communication control signal 21 indicating the timing when the circuit A communicates with the circuit B. The communication control circuit 20 outputs the generated signal indicating the recognized timing when a clock pulse exists in both the clock S and the clock B as the communication control signal 21 indicating the timing when the circuit A communicates with the circuit B.

[0196] 6, the communication control circuit 20 generates, as the communication control signal 21, a signal that has a value of 1 at the timings of T0, T1, T3, T4, T5, T6, T7, T8, T9, T10, and T11. In this example, as described above, the timings at which the value of the communication control signal 21 is 1 are timings at which clock pulses are present in both clock S and clock B. Then, the communication control circuit 20 outputs, as the communication control signal 21, the generated signal that has a value of 1 at the timings of T0, T1, T3, T4, T5, T6, T7, T8, T9, T10, and T11.

[0197] With reference to the communication control signal 21, the circuit A communicates with the circuit B at a timing indicated by the communication control signal 21, when both the clock S and the clock B have clock pulses. That is, the circuit A outputs a signal Aout indicating data to be transmitted to the circuit B in the communication with the circuit B at a timing indicated by the communication control signal 21, when both the clock S and the clock B have clock pulses. The circuit A receives as an input a signal Bout indicating data to be output from the circuit B in the communication with the circuit B at a timing indicated by the communication control signal 21, when both the clock S and the clock B have clock pulses. Specifically, in the example shown in FIG. 6, the circuit A outputs a signal Aout indicating data to be transmitted to the circuit B in the communication with the circuit B at the timings T0, T1, T3, T4, T5, T6, T7, T8, T9, T10, and T11, which are the timings indicated by the communication control signal 21. In addition, circuit A, by referring to the communication control signal 21, receives as input a signal Bout indicating the data output from circuit B in communication with circuit B at timings T0, T1, T3, T4, T5, T6, T7, T8, T9, T10, and T11, which are timings indicated by the communication control signal 21.

[0198] On the other hand, the circuit B communicates with the circuit A at the timing when the clock B has a clock pulse. That is, the circuit B outputs a signal Bout indicating data to be transmitted to the circuit A in the communication with the circuit A at the timing when the clock B has a clock pulse. The circuit B receives as an input a signal Aout indicating data to be output from the circuit A in the communication with the circuit A at the timing when the clock B has a clock pulse. In the example shown in FIG. 6, the timings when the clock B has a clock pulse are T0, T1, T3, T4, T5, T6, T7, T8, T9, T10, and T11. The circuit B outputs a signal Bout indicating data to be transmitted to the circuit A in the communication with the circuit A at the timings T0, T1, T3, T4, T5, T6, T7, T8, T9, T10, and T11. Circuit B receives as input signal Aout, which is communication data output by circuit A, at timings T0, T1, T3, T4, T5, T6, T7, T8, T9, T10, and T11.

[0199] Through the above operations, there are clock pulses in clock B, and circuit A and circuit B can perform communication operations at all timings when circuit B operates.

[0200] Next, another example of the communication timing between circuit A and circuit B in this embodiment will be described with reference to FIG. 7.

[0201] FIG. 7 is a diagram showing an example of communication timing between circuit A and circuit B according to an embodiment of the present disclosure.

[0202] FIG. 7 illustrates signals such as clocks and communication timing when communicating between circuit A operating with clock S and circuit B operating with clock B. In the example shown in FIG. 7, clock B is a clock signal generated by dividing clock S by a division ratio N / M = 7 / 12 by clock signal division circuit 10. In this example, the pattern of the clock pulses of clock B generated by clock signal division circuit 10 repeats every M = 12 cycles. In FIG. 7, the 12 cycles of this repetition are indicated by cycles T0 to T11.

[0203] In the example of FIG. 7, the 3 cycles from cycle T0 to T2 are the marker part. The division ratio is the division ratio N / M = 7 / 12. Therefore, M and N indicating the division ratio satisfy M / 2 ≤ N and N < M - 1. Therefore, the marker part in this case is marker 12.

[0204] Toggle signal generation circuit 22 receives clock B as an input. Then, toggle signal generation circuit 22 generates and outputs a toggle signal 23 whose value toggles for each clock pulse of clock B. As described above, there are two cases for the signal transition (i.e., value transition) of toggle signal 23 depending on the initial value of toggle signal 23. In other words, as toggle signal 23, there can be two different toggle signals depending on the initial value, that is, a toggle signal when the initial value is 1 and a toggle signal when the initial value is 0.

[0205] In Fig. 7, two toggle signals with different initial values ​​are illustrated as toggle signal 23a and toggle signal 23b. In the example shown in Fig. 7, the only cycles in which both toggle signal 23a and toggle signal 23b do not toggle for two consecutive cycles are cycles T1 and T2. In the example shown in Fig. 7, the marker portion is marker 12. The cycles T1 and T2 of toggle signal 23 (i.e., the portion of two consecutive cycles in which the toggle signal does not toggle for two consecutive cycles) is designated as toggle signal marker 42 of marker 12.

[0206] Therefore, the communication control circuit 20 included in the circuit A identifies the timing of the marker section by identifying the toggle signal marker 42 with reference to the toggle signal 23. Specifically, the communication control circuit 20 detects the toggle signal marker in the toggle signal 23. When the toggle signal marker 42 is detected, the communication control circuit 20 identifies the cycle in which the toggle signal marker 42 is detected in the toggle signal 23. The communication control circuit 20 identifies the timing of the beginning of the marker section (the marker 12 in this case) from the relationship between the timing of the beginning of the marker 12 and the timing of the cycle in which the toggle signal marker 42 exists. As described above, the relationship between the timing of the beginning of the marker section and the timing of the toggle signal marker of the toggle signal generated from the marker section is provided to the communication control circuit 20 in advance. The beginning of the marker section is the beginning of a cycle in which the phase relationship between the clock S and the clock B goes full circle. As a result, the communication control circuit 20 can identify the timing of the beginning of a cycle in which the phase relationship between the clock S and the clock B goes full circle.

[0207] Furthermore, the communication control circuit 20 can recognize the timing when a clock pulse exists in both the clock S and the clock B by referring to the division ratio setting 30, which is the setting information of the division ratio of the clock B. As described above, the clock B is generated by masking a part of the clock pulse of the clock S. Therefore, in a cycle (in other words, a timing) when a clock pulse exists in the clock B having the division ratio specified by the division ratio setting 30, a clock pulse exists in both the clock S and the clock B. The communication control circuit 20 generates a signal indicating the recognized timing when a clock pulse exists in both the clock S and the clock B as the communication control signal 21 indicating the timing when the circuit A communicates with the circuit B. The communication control circuit 20 outputs the generated signal indicating the recognized timing when a clock pulse exists in both the clock S and the clock B as the communication control signal 21 indicating the timing when the circuit A communicates with the circuit B.

[0208] 7, the communication control circuit 20 generates, as the communication control signal 21, a signal whose value is 1 at the timings T0, T3, T4, T6, T7, T9, and T10. In this example, as described above, the timings in which the value is 1 in the communication control signal 21 are timings in which there are clock pulses in both clock S and clock B. Then, the communication control circuit 20 outputs, as the communication control signal 21, the generated signal whose value is 1 at the timings T0, T3, T4, T6, T7, T9, and T10.

[0209] As described above, the circuit A refers to the communication control signal 21 and communicates with the circuit B at a timing indicated by the communication control signal 21 when both the clock S and the clock B have clock pulses. That is, the circuit A outputs a signal Aout indicating data to be transmitted to the circuit B in communication with the circuit B at a timing indicated by the communication control signal 21 when both the clock S and the clock B have clock pulses. The circuit A receives as an input a signal Bout indicating data to be output from the circuit B in communication with the circuit B at a timing indicated by the communication control signal 21 when both the clock S and the clock B have clock pulses. Specifically, in the example shown in FIG. 7, the circuit A outputs a signal Aout indicating data to be transmitted to the circuit B in communication with the circuit B at timings T0, T3, T4, T6, T7, T9, and T10 indicated by the communication control signal 21. In addition, circuit A, by referring to the communication control signal 21, receives as input a signal Bout indicating the data output from circuit B in communication with circuit B at timings T0, T3, T4, T6, T7, T9, and T10, which are the timings indicated by the communication control signal 21.

[0210] As described above, the circuit B communicates with the circuit A at the timing when the clock B has a clock pulse. That is, the circuit B outputs a signal Bout indicating data to be transmitted to the circuit A in the communication with the circuit A at the timing when the clock B has a clock pulse. The circuit B receives, as an input, a signal Aout indicating data output from the circuit A in the communication with the circuit A at the timing when the clock B has a clock pulse. In the example shown in FIG. 7, the timings when the clock B has a clock pulse are T0, T3, T4, T6, T7, T9, and T10. The circuit B outputs a signal Bout indicating data to be transmitted to the circuit A in the communication with the circuit A at the timings T0, T3, T4, T6, T7, T9, and T10. The circuit B receives, as an input, a signal Aout which is communication data output by the circuit A at the timings T0, T3, T4, T6, T7, T9, and T10.

[0211] With the above operations, when there are clock pulses in clock B and at all timings when circuit B operates, circuits A and B can perform communication operations.

[0212] In the example shown in FIG. 7, the division ratio is division ratio N / M = 7 / 12. However, even when the division ratio is other division ratios where M and N satisfy M / 2 ≤ N and N < M - 1, communication control circuit 20 detects toggle signal marker 42 as a toggle signal marker from the toggle signal. Then, communication control circuit 20 identifies the start of the marker section, that is, the start of the period in which the phase relationship between clock S and clock B makes one round, in the same way as when the division ratio is division ratio N / M = 7 / 12. Then, communication control circuit 20 identifies the timings at which clock pulses exist in both clock S and clock B according to the division ratio. Note that the timings at which clock pulses exist in both clock S and clock B differ depending on the division ratio.

[0213] Next, another example of the communication timing between circuit A and circuit B in the present embodiment will be described with reference to FIG. 8.

[0214] FIG. 8 is a diagram showing an example of communication timing between circuit A and circuit B according to an embodiment of the present disclosure.

[0215] FIG. 8 illustrates signals such as clocks and communication timing when communicating between circuit A operating with clock S and circuit B operating with clock B. In the example shown in FIG. 8, clock B is a clock signal generated by dividing clock S by a division ratio N / M = 5 / 12 by clock signal division circuit 10. In this example, the pattern of the clock pulses of clock B generated by clock signal division circuit 10 makes one round in M = 12 cycles. In FIG. 8, the 12 cycles of one round are indicated by cycles T0 to T11.

[0216] In the example of FIG. 8, the three cycles of cycles T0 to T2 are the marker part. The division ratio is division ratio N / M = 5 / 12. Therefore, M and N indicating the division ratio satisfy 2 ≤ N and N < M / 2. Therefore, the marker part in this case is marker 13.

[0217] The toggle signal generation circuit 22 receives clock B as an input. Then, the toggle signal generation circuit 22 generates and outputs a toggle signal 23 whose value toggles for each clock pulse of clock B. As described above, there are two cases for the signal transition (i.e., value transition) of the toggle signal 23 depending on the initial value of the toggle signal 23. In other words, as the toggle signal 23, there can be two different toggle signals depending on the initial value, that is, a toggle signal when the initial value is 1 and a toggle signal when the initial value is 0.

[0218] In FIG. 8, two toggle signals with different initial values are illustrated as toggle signal 23a and toggle signal 23b. In the example shown in FIG. 8, the cycles in which both the toggle signal 23a and the toggle signal 23b toggle continuously for two cycles are only the parts of cycles T1 and T2. In the example shown in FIG. 8, the marker part is marker 13. The parts of cycles T0 and T1 of the toggle signal 23 (i.e., the consecutive two cycles in which the toggle signal toggles continuously for two cycles) are set as the toggle signal marker 43 of marker 13.

[0219] Therefore, the communication control circuit 20 included in circuit A can know the timing of the marker part by identifying the toggle signal marker 43 with reference to the toggle signal 23. Specifically, the communication control circuit 20 detects the toggle signal marker in the toggle signal 23. When the toggle signal marker 43 is detected, the communication control circuit 20 specifies the cycle in which the toggle signal marker 43 is detected in the toggle signal 23. The communication control circuit 20 identifies the timing of the start of the marker section (in this case, marker 13) from the relationship between the timing of the start of marker 13 and the timing of the cycle in which toggle signal marker 43 exists. As described above, the relationship between the timing of the start of the marker section and the timing of the toggle signal marker of the toggle signal generated from that marker section is provided to the communication control circuit 20 in advance. The start of the marker section is the start of a cycle in which the phase relationship between clocks S and B completes one cycle. As a result, the communication control circuit 20 can identify (in other words, specify) the timing of the start of a cycle in which the phase relationship between clocks S and B completes one cycle.

[0220] Furthermore, the communication control circuit 20 can recognize the timing when a clock pulse exists in both the clock S and the clock B by referring to the division ratio setting 30, which is the setting information of the division ratio of the clock B. As described above, the clock B is generated by masking a part of the clock pulse of the clock S. Therefore, in a cycle (in other words, a timing) when a clock pulse exists in the clock B having the division ratio specified by the division ratio setting 30, a clock pulse exists in both the clock S and the clock B. The communication control circuit 20 generates a signal indicating the recognized timing when a clock pulse exists in both the clock S and the clock B as the communication control signal 21 indicating the timing when the circuit A communicates with the circuit B. The communication control circuit 20 outputs the generated signal indicating the recognized timing when a clock pulse exists in both the clock S and the clock B as the communication control signal 21 indicating the timing when the circuit A communicates with the circuit B.

[0221] 8, the communication control circuit 20 generates, as the communication control signal 21, a signal whose value is 1 at timings T0, T1, T3, T6, and T9. In this example, as described above, the timings in which the communication control signal 21 has a value of 1 are timings in which there are clock pulses in both clock S and clock B. Then, the communication control circuit 20 outputs, as the communication control signal 21, the generated signal whose value is 1 at timings T0, T1, T3, T6, and T9.

[0222] As described above, the circuit A communicates with the circuit B with reference to the communication control signal 21 at a timing indicated by the communication control signal 21 when both the clock S and the clock B have clock pulses. That is, the circuit A outputs a signal Aout indicating data to be transmitted to the circuit B in communication with the circuit B with a timing indicated by the communication control signal 21 when both the clock S and the clock B have clock pulses. The circuit A receives as an input a signal Bout indicating data output from the circuit B in communication with the circuit B with a timing indicated by the communication control signal 21 when both the clock S and the clock B have clock pulses. Specifically, in the example shown in FIG. 8, the circuit A outputs a signal Aout indicating data to be transmitted to the circuit B in communication with the circuit B with timings T0, T1, T3, T6, and T9 indicated by the communication control signal 21. The circuit A also receives as an input a signal Bout indicating data to be output from the circuit B in communication with the circuit B with timings T0, T1, T3, T6, and T9 indicated by the communication control signal 21 with reference to the communication control signal 21.

[0223] As described above, Circuit B communicates with Circuit A at the timing when a clock pulse exists in Clock B. That is, Circuit B outputs Signal Bout indicating the data transmitted to Circuit A in the communication with Circuit A at the timing when a clock pulse exists in Clock B. Then, Circuit B receives Signal Aout indicating the data output from Circuit A in the communication with Circuit A as an input at the timing when a clock pulse exists in Clock B. In the example shown in FIG. 8, the timings when a clock pulse exists in Clock B are the timings of T0, T1, T3, T6, and T9. Circuit B outputs Signal Bout indicating the data transmitted to Circuit A in the communication with Circuit A at the timings of T0, T1, T3, T6, and T9. Circuit B receives Signal Aout, which is the communication data output by Circuit A, as an input at the timings of T0, T1, T3, T6, and T9.

[0224] By the above operations, Circuit A and Circuit B can perform communication operations at all timings when a clock pulse exists in Clock B and Circuit B operates.

[0225] In the example shown in FIG. 8, the division ratio is division ratio N / M = 5 / 12. However, even when the division ratio is other division ratios where M and N satisfy 2 ≤ N and N < M / 2, Communication Control Circuit 20 detects Toggle Signal Marker 43 as a toggle signal marker from the toggle signal. Then, Communication Control Circuit 20 identifies the start of the marker section, that is, the start of the period in which the phase relationship between Clock S and Clock B makes a full cycle, in the same way as when the division ratio is division ratio N / M = 5 / 12. Then, Communication Control Circuit 20 identifies the timings when clock pulses exist in both Clock S and Clock B according to the division ratio. Note that the timings when clock pulses exist in both Clock S and Clock B differ depending on the division ratio.

[0226] Next, another example of the communication timing between Circuit A and Circuit B in the present embodiment will be described using FIG. 9.

[0227] FIG. 9 is a diagram illustrating an example of communication timing between circuit A and circuit B according to an embodiment of the present disclosure.

[0228] 9 illustrates signals such as clocks and communication timing when communication is performed between circuit A operating on clock S and circuit B operating on clock B. In the example illustrated in FIG. 9, clock B is a clock signal generated by dividing clock S by a division ratio N / M=1 / 12 using clock signal divider circuit 10. In this example, the clock pulse pattern of clock B generated by clock signal divider circuit 10 completes one cycle in M=12 cycles. In FIG. 9, the 12 cycles are indicated by cycles T0 to T11.

[0229] 9, three cycles T0 to T2 are the marker section. The division ratio is N / M=1 / 12. Therefore, the division ratio N satisfies N=1. Therefore, the marker section in this case is the marker 14.

[0230] The toggle signal generation circuit 22 receives the clock B as an input. Then, the toggle signal generation circuit 22 generates and outputs the toggle signal 23 whose value is inverted for each clock pulse of the clock B. As described above, there are two cases of signal transition (i.e., value transition) of the toggle signal 23 depending on the initial value of the toggle signal 23. In other words, as the toggle signal 23, there can be two different toggle signals depending on the initial value, that is, a toggle signal when the initial value is 1 and a toggle signal when the initial value is 0.

[0231] In Fig. 9, two toggle signals with different initial values ​​are illustrated as toggle signal 23a and toggle signal 23b. In the example shown in Fig. 9, the cycle in which both toggle signal 23a and toggle signal 23b toggle is only the portion of cycle T0. In the example shown in Fig. 8, the marker portion is marker 14. The portion of cycle T0 of toggle signal 23 (i.e., the portion of the cycle in which the toggle signal toggles) is set as toggle signal marker 44 of marker 14. Note that when the division ratio N satisfies N=1 and the marker portion is marker 14, the toggle signal marker is marker 14.

[0232] Therefore, the communication control circuit 20 included in the circuit A can know the timing of the marker section by identifying the toggle signal marker 44 with reference to the toggle signal 23. Specifically, the communication control circuit 20 detects the toggle signal marker in the toggle signal 23. When the toggle signal marker 44 is detected, the communication control circuit 20 specifies the cycle in the toggle signal 23 in which the toggle signal marker 44 is detected. The communication control circuit 20 specifies the timing of the beginning of the marker section (the marker 14 in this case) from the relationship between the timing of the beginning of the marker 14 and the timing of the cycle in which the toggle signal marker 44 exists. As described above, the relationship between the timing of the beginning of the marker section and the timing of the toggle signal marker of the toggle signal generated from the marker section is provided to the communication control circuit 20 in advance. The beginning of the marker section is the beginning of a cycle in which the phase relationship between the clock S and the clock B goes full circle. As a result, the communication control circuit 20 can identify (in other words, specify) the timing of the beginning of a cycle in which the phase relationship between the clock S and the clock B goes full circle.

[0233] Furthermore, the communication control circuit 20 can recognize the timing when a clock pulse exists in both the clock S and the clock B by referring to the division ratio setting 30, which is the setting information of the division ratio of the clock B. As described above, the clock B is generated by masking a part of the clock pulse of the clock S. Therefore, in a cycle (in other words, a timing) when a clock pulse exists in the clock B having the division ratio specified by the division ratio setting 30, a clock pulse exists in both the clock S and the clock B. The communication control circuit 20 generates a signal indicating the recognized timing when a clock pulse exists in both the clock S and the clock B as the communication control signal 21 indicating the timing when the circuit A communicates with the circuit B. The communication control circuit 20 outputs the generated signal indicating the recognized timing when a clock pulse exists in both the clock S and the clock B as the communication control signal 21 indicating the timing when the circuit A communicates with the circuit B.

[0234] 9, the communication control circuit 20 generates, as the communication control signal 21, a signal whose value is 1 at timing T0. In this example, as described above, the timing at which the value of the communication control signal 21 is 1 is the timing at which a clock pulse is present in both clock S and clock B. Then, the communication control circuit 20 outputs, as the communication control signal 21, the generated signal whose value is 1 at timing T0.

[0235] As described above, the circuit A communicates with the circuit B with reference to the communication control signal 21 at a timing indicated by the communication control signal 21 when both the clock S and the clock B have clock pulses. That is, the circuit A outputs a signal Aout indicating data to be transmitted to the circuit B in communication with the circuit B with a timing indicated by the communication control signal 21 when both the clock S and the clock B have clock pulses. The circuit A receives as an input a signal Bout indicating data output from the circuit B in communication with the circuit B with a timing indicated by the communication control signal 21 when both the clock S and the clock B have clock pulses. Specifically, in the example shown in FIG. 9, the circuit A outputs a signal Aout indicating data to be transmitted to the circuit B in communication with the circuit B with a timing of T0 indicated by the communication control signal 21. The circuit A also receives as an input a signal Bout indicating data to be output from the circuit B in communication with the circuit B with a timing of T0 indicated by the communication control signal 21 with reference to the communication control signal 21.

[0236] As described above, circuit B communicates with circuit A at the timing when a clock pulse is present in clock B. That is, circuit B outputs signal Bout indicating data to be transmitted to circuit A in communication with circuit A at the timing when a clock pulse is present in clock B. Circuit B receives signal Aout indicating data output from circuit A in communication with circuit A as input at the timing when a clock pulse is present in clock B. In the example shown in FIG. 9, the timing when a clock pulse is present in clock B is timing T0. Circuit B outputs signal Bout indicating data to be transmitted to circuit A in communication with circuit A at timing T0. Circuit B receives signal Aout, which is communication data output by circuit A, as input at timing T0.

[0237] With the above operations, circuits A and B can communicate with each other whenever a clock pulse is present in clock B and circuit B is operating.

[0238] <Effects>As described above, the clock signal divider circuit 10 of this embodiment generates a divided clock signal by masking the clock pulses of the input clock signal in consideration of the timing of communication. Specifically, the clock signal divider circuit 10 generates a divided clock signal that is a repetition of a periodic pattern signal in which the clock pulses are masked according to a division ratio. The clock signal divider circuit 10 generates a periodic pattern signal such that the leading portion of this periodic pattern signal becomes a marker portion, which is a clock pulse signal of a pattern that appears only at the leading portion of the periodic pattern signal in the divided clock signal. The marker portion mask signal generating unit 52 generates a marker portion mask signal for masking the clock pulses of the input clock signal such that the leading portion of the periodic pattern signal becomes this marker portion. The non-marker portion mask signal generating unit 53 generates a non-marker portion mask signal for masking the clock pulses of the non-marker portion such that the ratio of the number of masked clock pulses of the periodic pattern signal to the length of the periodic pattern signal (i.e., the number of cycles) becomes the division ratio. The non-marker portion is a portion other than the marker portion of the divided clock signal. Specifically, the non-marker portion masking signal generating unit 53 uses a division ratio of the non-marker portion that is a ratio of the denominator of the division ratio of the divided clock signal minus the number of clock pulses of the marker portion to the length of the non-marker portion (i.e., the number of cycles). The division ratio of the non-marker portion (hereinafter, referred to as the non-marker portion ratio) represents the ratio of clock pulses that are not masked in the non-marker portion to the length of the non-marker portion (i.e., the number of cycles). The non-marker portion masking signal generating unit 53 generates the non-marker portion masking signal using an existing method for generating a masking signal that generates a divided clock signal in which the division ratio is the non-marker portion ratio and a periodic pattern signal having the same length as the length of the non-marker portion is repeated. The non-marker portion masking signal generating unit 53 generates the non-marker portion masking signal so that the pattern of the clock pulses in the non-marker portion is the same as the pattern of the clock pulses of the periodic pattern signal having the same length as the non-marker portion, which was generated using the above-mentioned existing method. Then, the mask circuit 61 generates the divided clock signal by masking the clock pulses of the input clock signal according to the masking signal.This mask signal includes, as a signal portion that masks the clock pulse of the marker section, a marker section mask signal generated by marker section mask signal generating section 52. This mask signal further includes, as a signal portion that masks the clock pulse of the non-marker section, a non-marker section mask signal generated by non-marker section mask signal generating section 53.

[0239] As a result, the marker portion can identify the beginning of a periodic pattern signal that is repeated in the divided clock signal. By identifying the beginning of the periodic pattern signal, the timing at which a clock pulse exists in the divided clock signal can be identified. Therefore, no special timing design or special clock transfer circuit is required for communication with clock signals of different frequencies. Thus, efficient communication can be performed between different clocks. Therefore, the clock signal divider circuit 10 of this embodiment can realize rational division of a clock signal with low power, a small area, and low design cost.

[0240] Furthermore, in each circuit block that operates with the divided clock from the clock signal divider circuit, the beginning of the period in which the phase relationship of the divided clock makes one revolution can be easily identified. Therefore, the timing of communication can be recognized in each circuit block. Therefore, there is no need to separately propagate information indicating the timing of communication from the clock signal divider circuit. As a result, there are effects that timing design becomes easier, the circuit development period can be shortened, and the circuit size and power consumption can be reduced.

[0241] <Second embodiment> <Configuration> FIG. 14 is a block diagram illustrating an example of the configuration of a processing device according to an embodiment of the present disclosure.

[0242] A processing device according to a second embodiment of the present disclosure will be described below with reference to Fig. 14. A processing device 1000 according to the second embodiment corresponds to a part of the circuit A of the first embodiment.

[0243] In the example shown in FIG. 14, the processing device 1000 includes a toggle signal receiving unit 2002 and a communication unit 2005.

[0244] The toggle signal receiving unit 2002 receives a toggle signal whose value transitions between two values ​​at the timing of the pulses of the divided clock signal. The divided clock signal is a signal in which a periodic pattern signal is repeated in which, among successive pulses of the number of periodic pulses of the input clock signal, pulses having a mask pulse number smaller than the number of periodic pulses are masked.

[0245] In this embodiment, the division ratio of the divided clock signal is determined in advance, and the pulses that are not masked (i.e., the pulses that are present) in the period pattern signal of the divided clock signal are known.

[0246] The communication unit 2005 communicates with another processing device that operates according to the divided clock signal at the timing of the pulse of the divided clock signal, which is specified using the toggle signal, among the pulses of the input clock signal.

[0247] The communication unit 2005 may, for example, identify the timing of the start of the periodic pattern signal by using a portion of the toggle signal whose relationship with the timing of the start of the periodic pattern signal is known. The communication unit 2005 may, for example, identify the timing of an unmasked pulse in the periodic pattern signal by using the timing of the start of the periodic pattern signal.

[0248] The toggle signal receiving unit 2002 corresponds to the portion of the communication control circuit 20 of the circuit A in the first embodiment to which the toggle signal 23 is input. The communication unit 2005 corresponds to the communication control circuit 20 of the circuit A in the first embodiment. The other processing devices correspond to the circuit B in the first embodiment.

[0249] <Operation> FIG. 15 is a flowchart illustrating an example of the operation of the processing device according to an embodiment of the present disclosure.

[0250] An example of the operation of the processing device 1000 according to the second embodiment of the present disclosure will be described below with reference to FIG. 15. In the example shown in FIG. 15, first, the toggle signal receiving unit 2002 receives a toggle signal whose value transitions between two values ​​at the timing of a pulse of the divided clock signal (step S11). As described above, the divided clock signal is a signal in which a periodic pattern signal in which a number of mask pulses smaller than the number of periodic pulses among successive pulses of the number of periodic pulses of the input clock signal are masked is repeated. Next, the communication unit 2005 communicates with another processing device that operates by the divided clock signal at the timing of the pulse of the divided clock signal identified by using the toggle signal among the pulses of the input clock signal (step S12).

[0251] <Effects> This embodiment has the effect of reducing design costs and facilitating timing design, because the communication unit 2005 communicates with other processing devices that operate according to the divided clock signal at the timing of the pulse of the divided clock signal, which is specified using the toggle signal among the pulses of the input clock signal.

[0252] <Third embodiment> FIG. 16 is a diagram illustrating an example of the configuration of a processing system according to an embodiment of the present disclosure.

[0253] A processing system according to the third embodiment of the present disclosure will be described below with reference to FIG. 16. This embodiment is a schematic representation of the first embodiment. In the example shown in FIG. 16, a processing system 1001 includes a clock signal divider device 1010, a processing device 2000, and a processing device 3000. The clock signal divider device 1010 corresponds to the clock signal divider circuit 10 of the first embodiment. The processing device 2000 corresponds to the circuit A of the first embodiment. The processing device 3000 corresponds to the circuit B of the first embodiment.

[0254] Clock S is an input clock signal. Clock S is input to clock signal divider device 1010 and processing device 2000. The division ratio setting represents the division ratio of clock B to clock S. The division ratio is represented by a division ratio denominator M and a division ratio numerator N. The division ratio setting represents a division ratio denominator M and a division ratio numerator N.

[0255] The clock signal divider device 1010, like the clock signal divider circuit 10 of the first embodiment, generates a clock B by performing rational division on the clock S according to the division ratio setting. The clock B is a divided clock signal having a division ratio indicated by the division ratio setting. The clock B is supplied to the processing device 3000.

[0256] The processing device 3000 operates according to a clock B. Moreover, like the circuit B of the first embodiment, the processing device 3000 generates a toggle signal from the clock B. The processing device 3000 outputs the generated toggle signal.

[0257] The processing device 2000 operates according to a clock S. The processing device 2000 receives a toggle signal. The processing device 2000, like the circuit A in the first embodiment, uses the received toggle signal to identify the timing at which a clock pulse of the clock B is present.

[0258] The processing device 2000 communicates with the processing device 3000 at the identified timing when there is a clock pulse of the clock B. The processing device 3000 communicates with the processing device 2000 at the timing when there is a clock pulse of the clock B.

[0259] <Clock signal divider 1010> FIG. 17 is a block diagram illustrating an example of the configuration of a clock signal divider device according to the seventh embodiment of the present disclosure.

[0260] A clock signal divider device 1010 according to a third embodiment of the present disclosure will be described in detail below with reference to FIG. 17. In the example shown in FIG. 17, the clock signal divider device 1010 includes a clock signal receiving unit 1011, a setting information receiving unit 1012, an output signal generating unit 1013, and an output unit 1014. As described above, the clock signal divider device 1010 corresponds to the clock signal divider circuit 10 of the first embodiment. The clock signal divider device 1010 operates in the same manner as the clock signal divider circuit 10 of the first embodiment.

[0261] <Clock signal receiving unit 1011> The clock signal receiving unit 1011 receives an input clock signal (that is, the clock S). The clock signal receiving unit 1011 corresponds to the signal line to which the clock S is input in the clock signal divider circuit 10 of the first embodiment.

[0262] <Setting Information Receiving Unit 1012> The setting information receiving unit 1012 receives the division ratio setting. The setting information receiving unit 1012 corresponds to a signal line to which the division ratio setting (i.e., the division ratio denominator M and the division ratio numerator N) of the clock signal divider circuit 10 of the first embodiment is input. The length of the period in which the phase relationship between clock A and clock B goes full circle, that is, the number of cycles, is set as the value of the division ratio denominator M. The value of the division ratio numerator N is set so that N / M becomes the division ratio when the value of the division ratio denominator M is the length of the period in which the phase relationship with clock B goes full circle.

[0263] <Output section 1014> The output unit 1014 outputs the divided clock signal (i.e., clock B). The output unit 1014 corresponds to the signal line from which the divided clock signal (i.e., clock B) is output in the clock signal divider circuit 10 of the first embodiment.

[0264] <Output signal generating unit 1013> The output signal generating unit 1013 operates in the same manner as the clock signal dividing circuit 10 of the second embodiment. As described above, the output signal generating unit 1013 generates a divided clock signal in which a periodic pattern signal is repeated from the pulses of the received input clock signal. The periodic pattern signal is a signal in which, among successive pulses of the periodic pulse number, pulses having a mask pulse number smaller than the periodic pulse number are masked. The periodic pattern signal includes a marker section including at least one unmasked pulse at the beginning of the periodic pattern signal. The mask pulse number is a value obtained by subtracting the division ratio numerator N from the division ratio denominator M.

[0265] The marker portion is the same as the marker portion in the second embodiment. The periodic pattern signal is a signal of a portion of the frequency-divided clock signal having a length from the beginning of a period in which the phase relationship between clock S and clock B makes one cycle to the period in which the phase relationship between clock S and clock B makes one cycle.

[0266] The non-marker portion is a portion of the periodic pattern signal other than the marker portion, and is the same as the non-marker portion in the first embodiment.

[0267] The output signal generating unit 1013 corresponds to the parts of the clock signal divider circuit 10 of the first embodiment excluding the signal line to which the clock S is input, the signal line to which the division ratio setting is input, and the signal line to which the divided clock signal is output.

[0268] <Details of the output signal generating unit 1013> FIG. 18 is a diagram illustrating an example of a configuration of an output signal generating unit according to an embodiment of the present disclosure.

[0269] The output signal generating unit 1013 according to this embodiment will be described in detail below with reference to FIG. 18. In the example shown in FIG. 18, the output signal generating unit 1013 includes a mask control unit 1051 and a mask unit 1061. The mask control unit 1051 corresponds to the mask control circuit 51 and the counter circuit 56 of the first embodiment. The mask control unit 1051 operates in the same manner as the mask control circuit 51 of the first embodiment. The mask unit 1061 corresponds to the mask circuit 61 of the first embodiment. The mask unit 1061 operates in the same manner as the mask circuit 61 of the first embodiment.

[0270] <Mask control unit 1051> An input clock signal (that is, clock S), a frequency division ratio setting, and communication timing information are input to the mask control unit 1051. The mask control unit 1051 operates according to the clock S.

[0271] The mask control unit 1051 determines whether or not to mask each of the pulses of the input clock signal based on the number of periodic pulses and the number of non-masked pulses, which is the number of pulses that are not masked, and generates a mask signal indicating the result of the determination. The number of periodic pulses is the denominator M of the frequency division ratio described above. The number of non-masked pulses is the numerator N of the frequency division ratio described above. The mask control unit 1051 outputs the mask signal.

[0272] <Mask section 1061> The mask unit 1061 receives an input clock signal (that is, clock S) and a mask signal.

[0273] Masking section 1061 masks pulses that are determined to be masked in accordance with the mask signal, and outputs pulses that are not determined to be masked as is.

[0274] <Details of the mask control unit 1051> FIG. 19 is a diagram illustrating an example of the configuration of a mask control unit according to a schematic example of an embodiment of the present disclosure.

[0275] In the following, the mask control unit 1051 of this embodiment will be described in detail with reference to FIG. 19. In the example shown in FIG. 19, the mask control unit 1051 includes a marker portion mask signal generation unit 1052, a non-marker portion mask signal generation unit 1053, and a selection unit 1054. FIG. 19 shows a portion of the mask control unit 1051 that corresponds to the marker portion mask signal generation unit 52, the non-marker portion mask signal generation unit 53, and the selection circuit 54 of the mask control circuit 51 of the first embodiment. The marker portion mask signal generation unit 1052, the non-marker portion mask signal generation unit 1053, and the selection unit 1054 operate according to the input clock S. However, in order to prevent the diagram from becoming complicated, the signal line of the clock S is not drawn in FIG. 19.

[0276] The marker portion mask signal generating unit 1052 and the non-marker portion mask signal generating unit 1053 receive a division ratio setting.

[0277] The marker section mask signal generating unit 1052 generates a marker section mask signal that is a mask signal of the marker section determined by the number of periodic pulses and the number of non-masked pulses. The method by which the marker section mask signal generating unit 1052 generates the marker section mask signal is the same as the method by which the marker section mask signal generating unit 52 of the first embodiment generates the marker section mask signal.

[0278] The non-marker portion mask signal generating unit 1053 generates a non-marker portion mask signal, which is a mask signal of the non-marker portion, so that the pattern of unmasked pulses of the non-marker portion, which is a portion other than the marker portion of the periodic pattern signal, is the same as the second frequency division pattern. The second frequency division pattern is a pattern of unmasked pulses of the periodic clock signal when rational frequency division is performed with a frequency division ratio determined from the second periodic pulse number and the second unmasked pulse number. The rational frequency division in this case is a rational frequency division according to any of the existing rational frequency division algorithms. The second periodic pulse number is the number of pulses obtained by subtracting the number of pulses of the marker portion from the periodic pulse number. The second unmasked pulse number is the number of pulses obtained by subtracting the number of unmasked pulses included in the marker portion from the unmasked pulse number. The method by which the non-marker portion mask signal generating unit 1053 generates the non-marker portion mask signal is the same as the method by which the non-marker portion mask signal generating unit 53 of the first embodiment generates the non-marker portion mask signal.

[0279] The selection unit 1054 outputs the marker portion mask signal as a mask signal while outputting the marker portion of the periodic pattern signal, and outputs the non-marker portion mask signal as a mask signal while outputting the non-marker portion of the periodic pattern signal. In other words, the selection unit 1054 selects the marker portion mask signal as a mask signal while outputting the marker portion of the periodic pattern signal, and selects the non-marker portion mask signal as a mask signal while outputting the non-marker portion of the periodic pattern signal. The selection unit 1054 outputs the signal selected as the mask signal as a mask signal. The method of selecting the marker portion mask signal and the non-marker portion mask signal to be output as the mask signal by the selection unit 1054 is the same as the method of selecting the signal to be output as the mask signal from the marker portion mask signal and the non-marker portion mask signal by the selection circuit 54.

[0280] When the number of output pulses obtained by subtracting the number of mask pulses from the number of cycle pulses is a value obtained by subtracting 1 from the number of cycle pulses, it is expressed as N = M - 1. Also, when the number of output pulses is 2 or more and the number of output pulses is smaller than the value obtained by dividing the number of cycle pulses by 2, it is expressed as 2 ≤ N and N < M / 2. In these cases, the marker portion includes non-masked pulses at two consecutive output clock timings, which are the timings at which pulses are output as the divided clock signal when the pulses are not masked. And the non-marker portion does not include the non-masked pulses at two consecutive output clock timings.

[0281] When the number of output pulses is greater than or equal to the value obtained by dividing the number of cycle pulses by 2 and the number of output pulses is smaller than the value obtained by subtracting 1 from the number of cycle pulses, it is expressed as M / 2 ≤ N and N < M - 1. Also, when the number of output pulses is 1, it is expressed as N = 1. In these cases, in the marker portion, pulses at at least two consecutive output clock timings are masked, and in the non-marker portion, pulses at two consecutive output clock timings are not masked.

[0282] <Processing device 3000> FIG. 20 is a block diagram showing an example of the configuration of a processing device according to an embodiment of the present disclosure.

[0283] Hereinafter, the processing device 3000 according to the third embodiment of the present disclosure will be described in detail with reference to FIG. 20. In the example shown in FIG. 20, the processing device 3000 includes a clock signal receiving unit 3001, a toggle signal generating unit 3002, and a communication unit 3003. As described above, the processing device 3000 corresponds to circuit B of the first embodiment. The processing device 3000 operates in the same manner as circuit B of the first embodiment.

[0284] <Clock signal receiving unit 3001> The clock signal receiving unit 3001 receives the above-mentioned clock B (i.e., the divided clock signal) output from the clock signal dividing device 1010. The clock signal receiving unit 3001 corresponds to the signal line to which the clock B is supplied in the circuit B of the first embodiment.

[0285] <Toggle signal generating unit 3002> The toggle signal generation unit 3002 generates a toggle signal from the clock B. The toggle signal generation unit 3002 corresponds to the toggle signal generation circuit 22 of the first embodiment. The toggle signal generation unit 3002 operates in the same manner as the toggle signal generation circuit 22 of the first embodiment.

[0286] <Communication Department 3003> The communication unit 3003 communicates with the circuit A at the timing of the clock pulse of the clock B. The communication unit 3003 corresponds to a circuit (for example, a combination of circuits) of the circuit B of the first embodiment that outputs the signal Bout and receives the signal Aout as an input. The communication unit 3003 operates in the same manner as the circuit of the circuit B of the first embodiment that outputs the signal Bout and receives the signal Aout as an input. Note that the information output as the signal Bout may be generated by the processing device 3000 (i.e., the circuit B). The information output as the signal Bout may be generated by another circuit or device connected to the processing device 3000 (i.e., the circuit B). The information input as the signal Aout may be processed by the processing device 3000 (i.e., the circuit B). The information input as the signal Aout may be processed by another circuit or device connected to the processing device 3000 (i.e., the circuit B).

[0287] <Processing device 2000> FIG. 21 is a block diagram illustrating an example of the configuration of a processing device according to an embodiment of the present disclosure.

[0288] A processing device 2000 according to the third embodiment of the present disclosure will be described in detail below with reference to Fig. 21. In the example shown in Fig. 21, the processing device 2000 includes a clock signal receiving unit 2001, a toggle signal receiving unit 2002, a detecting unit 2003, a specifying unit 2004, and a communicating unit 2005. As described above, the processing device 2000 corresponds to the circuit A of the first embodiment.

[0289] <Clock signal receiving unit 2001> The clock signal receiving unit 2001 receives the clock S (ie, the input clock signal described above).

[0290] <Toggle signal receiving unit 2002> The toggle signal receiving unit 2002 receives the toggle signal output by the processing device 3000. As described above, the toggle signal is a signal whose value transitions between two values ​​at the timing of the pulses of the frequency-divided clock signal. The frequency-divided clock signal is a signal in which a periodic pattern signal is repeated in which a predetermined number of mask pulses, which is smaller than the number of periodic pulses, is masked out of the successive pulses of the number of periodic pulses of the input clock signal.

[0291] <Detection Unit 2003> The detector 2003 receives the division ratio setting, which is the same as the division ratio setting in the first embodiment.

[0292] The detection unit 2003 detects a toggle signal marker in the toggle signal at the division ratio indicated by the division ratio setting. The detection unit 2003 corresponds to the function of the communication control circuit 20 of the circuit A in the first embodiment to detect a toggle signal marker from a toggle signal. The detection unit 2003 performs the same operation as the operation of the communication control circuit 20 of the circuit A in the first embodiment when detecting a toggle signal marker from a toggle signal.

[0293] <Specific section 2004> The identifying unit 2004 identifies the timing of the pulse of the frequency-divided clock signal from the timing of the detected toggle signal marker. Specifically, the identifying unit 2004 identifies the timing of the head of the periodic pattern signal from the timing of the detected toggle signal marker and the relationship between the timing of the toggle signal marker and the head timing of the periodic pattern signal at the division ratio indicated by the division ratio setting. The identifying unit 2004 then identifies the timing of the unmasked pulse of the frequency-divided clock signal from the identified head timing of the periodic pattern signal and information on the unmasked pulse in the periodic pattern signal of the frequency-divided clock signal at the division ratio indicated by the division ratio setting. The identifying unit 2004 holds information on the unmasked pulse in the periodic pattern signal of the frequency-divided clock signal for each division ratio in advance. The identifying unit 2004 corresponds to a function of identifying the timing of the unmasked pulse of the frequency-divided clock signal of the communication control circuit 20 of the circuit A in the first embodiment. The identifying unit 2004 performs an operation similar to that performed by the communication control circuit 20 of the circuit A in the first embodiment when identifying the timing of an unmasked pulse of the frequency-divided clock signal.

[0294] <Communications Department 2005> The communication unit 2005 communicates with the processing device 3000 that operates according to the divided clock signal at the timing of the pulse of the divided clock signal identified using the toggle signal among the pulses of the input clock signal. The pulse of the divided clock signal identified using the toggle signal is an unmasked pulse of the divided clock signal identified by the identification unit 2004. As described above, the divided clock signal is generated by masking a portion of the pulses of the input clock signal that is determined according to the division ratio. Therefore, the timing of the pulse of the divided clock signal coincides with one of the pulses of the input clock signal.

[0295] The communication unit 3003 corresponds to a circuit (e.g., a combination of circuits) of the circuit B of the first embodiment that outputs the signal Aout and receives the signal Bout as an input. The communication unit 3003 operates in the same manner as the circuit of the circuit B of the first embodiment that outputs the signal Aout and receives the signal Bout as an input. Note that the information output as the signal Aout may be generated by the processing device 2000 (i.e., the circuit A). The information output as the signal Aout may be generated by another circuit or device connected to the processing device 2000 (i.e., the circuit A). The information input as the signal Bout may be processed by the processing device 2000 (i.e., the circuit A). The information input as the signal Bout may be processed by another circuit or device connected to the processing device 2000 (i.e., the circuit A).

[0296] <Modification> The toggle signal generating unit 3002 may be included in a device other than the processing device 2000 to which the divided clock signal (i.e., clock B) is supplied. In that case, the toggle signal may be output from the device including the toggle signal generating unit 3002. And, the processing device 3000 may not include the toggle signal generating unit 3002.

[0297] <Operation> Next, the operation of the processing system 1001 according to this embodiment will be described in detail with reference to the drawings. In the following, the operation of the clock signal divider device 1010, the operation of the processing device 3000, and the operation of the processing device 2000 will be described.

[0298] FIG. 22 is a flowchart illustrating an example of the operation of the clock signal divider device according to an embodiment of the present disclosure.

[0299] First, the operation of the clock signal divider device 1010 according to this embodiment will be described in detail below with reference to FIG.

[0300] At the start of the operation shown in Fig. 22, an input clock signal (i.e., clock S) is supplied to the clock signal divider device 1010. The clock signal receiver 1011 receives the input clock signal (step S101). The clock signal divider device 1010 is driven by the input clock signal.

[0301] 22, the setting information receiving unit 1012 then receives a division ratio setting (step S102). The mask control unit 1051 starts generating a mask signal for generating a divided clock signal having a division ratio indicated by the received division ratio setting from the next step onward. The mask control unit 1051 may start generating a mask signal after the division ratio setting is received so that a divided clock signal is generated from the beginning of the periodic pattern signal.

[0302] If the current timing is the timing to output the marker section (YES in step S103), the marker section mask signal generating unit 1052 of the mask control unit 1051 generates a marker section mask signal (step S104). Then, the selecting unit 1054 of the mask control unit 1051 selects the marker section mask signal as the mask signal (step S105).

[0303] If the current timing is not the timing to output the marker portion (NO in step S103), the non-marker portion mask signal generating unit 1053 of the mask control unit 1051 generates a non-marker portion mask signal (step S106). Then, the selecting unit 1054 of the mask control unit 1051 selects the non-marker portion mask signal as the mask signal (step S107).

[0304] Then, the mask unit 1061 generates a frequency-divided clock signal by masking the pulses of the input signal in accordance with the mask signal (step S108), and the output unit 1014 outputs the frequency-divided clock signal (step S109).

[0305] The clock signal divider device 1010 may, for example, repeat the operations from step S103 to step S109 while the input clock signal is being supplied.

[0306] FIG. 23 is a flowchart illustrating an example of the operation of the processing device according to an embodiment of the present disclosure.

[0307] The operation of the processing device 3000 of this embodiment will be described below with reference to FIG.

[0308] 23, the clock signal receiving unit 3001 receives a divided clock signal (step S301). The toggle signal generating unit 3002 generates a toggle signal from the divided clock signal (step S302). The toggle signal generating unit 3002 outputs the generated toggle signal (step S303).

[0309] The communication unit 3003 communicates with a communication partner at the timing of the pulse of the frequency-divided clock signal (step S304). The communication partner is, for example, the processing device 2000.

[0310] The processing device 3000 may perform the operation of step S301 from the start of the supply of the frequency-divided clock signal to the end of the supply of the frequency-divided clock signal. The processing device 3000 performs the operations of steps S302 to S304 at the timing of the pulses of the frequency-divided clock signal.

[0311] FIG. 24 is a flowchart illustrating an example of the operation of the processing device according to an embodiment of the present disclosure.

[0312] The operation of the processing device 2000 of this embodiment will be described below with reference to FIG.

[0313] 24, the clock signal receiving unit 2001 receives an input clock signal (step S201), and the toggle signal receiving unit 2002 receives a toggle signal (step S202).

[0314] The detection unit 2003 detects a toggle signal marker from the toggle signal (step S203). The identification unit 2004 identifies the timing of the pulse of the frequency-divided clock signal from the timing of the detected toggle signal marker (step S204). The communication unit 2005 communicates with a communication partner at the timing of the pulse of the frequency-divided clock signal (step S205). The communication partner of the processing device 2000 is, for example, the processing device 3000.

[0315] The processing device 2000 may perform the operation of step S201 while the input clock is being supplied, and may perform the operations of steps S202 to S205 while the toggle signal is being input.

[0316] <Effects> The present embodiment described above has the same effect as the second embodiment. The reason why the effect of the second embodiment is produced is the same as that why the effect of the second embodiment is produced. The present embodiment has the same effect as the first embodiment. The reason why the effect of the first embodiment is produced is the same as that why the effect of the first embodiment is produced.

[0317] <Other embodiments> A part or all of the above-described embodiments can be described as, but is not limited to, the following supplementary notes.

[0318] (Appendix 1) a toggle signal receiving means for receiving a toggle signal whose value transitions between two values ​​at the timing of a pulse of a divided clock signal in which a periodic pattern signal is repeated in which a predetermined number of mask pulses smaller than the number of periodic pulses of an input clock signal are masked; a communication means for communicating with another processing device that operates according to the divided clock signal at the timing of the pulse of the divided clock signal, the timing being specified using the toggle signal among the pulses of the input clock signal; A processing device comprising:

[0319] (Appendix 2) the toggle signal includes a toggle signal marker that is a signal pattern; The signal pattern of the toggle signal marker is present only in the toggle signal at the portion of the toggle signal marker. 2. The processing device of claim 1.

[0320] (Appendix 3) the toggle signal marker is a signal pattern generated in the toggle signal by a part of a marker portion, which is a leading portion of the periodic pattern signal, The processing device includes: detection means for detecting the toggle signal marker from the toggle signal; a determination means for determining a timing of the pulse of the frequency-divided clock signal from the detected timing of the toggle signal marker; Further equipped 3. The processing device according to claim 2.

[0321] (Appendix 4) the divided clock signal includes a marker portion including at least one unmasked pulse at the beginning of the periodic pattern signal, The pulse pattern of the marker portion appears only in the marker portion of the divided clock signal. 4. The processing device according to claim 3.

[0322] (Appendix 5) when the number of output pulses obtained by subtracting the number of mask pulses from the number of periodic pulses is a value obtained by subtracting 1 from the number of periodic pulses, the toggle signal marker is a signal in a cycle in which the value of the toggle signal does not transition, when the number of output pulses is 2 or more and is smaller than the value obtained by dividing the number of periodic pulses by 2, the toggle signal marker is a two-cycle signal in which the value of the toggle signal does not transition for two consecutive cycles; when the number of output pulses is equal to or greater than the value obtained by dividing the number of periodic pulses by 2 and the number of output pulses is smaller than the value obtained by subtracting 1 from the number of periodic pulses, the toggle signal marker is a two-cycle signal in which the value of the toggle signal transitions for two consecutive cycles; When the number of output pulses is 1, the toggle signal marker is a signal of a cycle in which the value of the toggle signal transitions. 4. The processing device according to claim 2 or 3.

[0323] (Appendix 6) when the number of output pulses obtained by subtracting the number of mask pulses from the number of periodic pulses is a value obtained by subtracting 1 from the number of periodic pulses, and when the number of output pulses is 2 or more and is smaller than a value obtained by dividing the number of periodic pulses by 2, the marker portion includes the pulse that is not masked in two consecutive output clock timings that are timings at which the pulse is output as the divided clock signal when the pulse is not masked, and a non-marker portion that is a portion of the periodic pattern signal other than the marker portion does not include the pulse that is not masked in two consecutive output clock timings, When the number of output pulses is equal to or greater than the value obtained by dividing the number of periodic pulses by 2 and is smaller than the value obtained by subtracting 1 from the number of periodic pulses, and when the number of output pulses is 1, the pulses at at least two consecutive output clock timings are masked in the marker portion, and the pulses at two consecutive output clock timings are not masked in the non-marker portion. 5. The processing device according to claim 3 or 4.

[0324] (Appendix 7) A processing device according to claim 1 or 2; a frequency-divided clock generating device for generating the frequency-divided clock signal from the input clock signal; a toggle signal generator that receives the divided clock signal and generates the toggle signal using the divided clock signal; 13. A processing system comprising:

[0325] (Appendix 8) The frequency-divided clock generating device comprises: determining whether or not to mask each of the pulses of the input clock signal based on the number of periodic pulses and a non-masked pulse number, which is the number of pulses that are not masked, and generating a mask signal indicative of the result of the determination; masking the pulses that have been determined to be masked in accordance with the mask signal, and outputting the pulses that have not been determined to be masked as they are; 8. The processing system of claim 7.

[0326] (Appendix 9) The frequency-divided clock generating device comprises: generating a marker portion mask signal, the marker portion being a leading portion of the periodic pattern signal, the marker portion being a mask signal determined by the number of periodic pulses and the number of unmasked pulses; generating a non-marker portion mask signal, which is the mask signal of the non-marker portion, such that an unmasked pulse pattern of a non-marker portion, which is a portion of the periodic pattern signal other than the marker portion, is identical to an unmasked pulse pattern of a periodic clock signal when rational frequency division is performed according to a predetermined rational frequency division algorithm at a frequency division ratio determined by a second periodic pulse number obtained by subtracting the number of pulses of the marker portion from the periodic pulse number and a second unmasked pulse number obtained by subtracting the number of unmasked pulses included in the marker portion from the non-masked pulse number; outputting the marker portion mask signal as the mask signal while the marker portion of the periodic pattern signal is being output, and outputting the non-marker portion mask signal as the mask signal while the non-marker portion of the periodic pattern signal is being output. 9. The processing system of claim 8.

[0327] (Appendix 10) receiving a toggle signal whose value transitions between two values ​​at the timing of a pulse of a divided clock signal in which a periodic pattern signal is repeated in which a predetermined number of mask pulses smaller than the number of periodic pulses of an input clock signal are masked; communicating with another processing device that is operated by the divided clock signal at the timing of the pulse of the divided clock signal, which is specified using the toggle signal, among the pulses of the input clock signal; Processing methods.

[0328] (Appendix 11) the toggle signal includes a toggle signal marker that is a signal pattern; The signal pattern of the toggle signal marker is present only in the toggle signal at the portion of the toggle signal marker. 10. The method of claim 10.

[0329] (Appendix 12) the toggle signal marker is a signal pattern generated in the toggle signal by a part of a marker portion, which is a leading portion of the periodic pattern signal, Detecting the toggle signal marker from the toggle signal; The timing of the pulse of the divided clock signal is determined from the timing of the detected toggle signal marker. 12. The processing method according to claim 11.

[0330] (Appendix 13) the divided clock signal includes a marker portion including at least one unmasked pulse at the beginning of the periodic pattern signal, The pulse pattern of the marker portion appears only in the marker portion of the divided clock signal. 13. The processing method according to claim 12.

[0331] (Appendix 14) when the number of output pulses obtained by subtracting the number of mask pulses from the number of periodic pulses is a value obtained by subtracting 1 from the number of periodic pulses, the toggle signal marker is a signal of a cycle in which the value of the toggle signal does not transition, when the number of output pulses is 2 or more and is smaller than the value obtained by dividing the number of periodic pulses by 2, the toggle signal marker is a two-cycle signal in which the value of the toggle signal does not transition for two consecutive cycles; when the number of output pulses is equal to or greater than the value obtained by dividing the number of periodic pulses by 2 and the number of output pulses is smaller than the value obtained by subtracting 1 from the number of periodic pulses, the toggle signal marker is a two-cycle signal in which the value of the toggle signal transitions for two consecutive cycles; When the number of output pulses is 1, the toggle signal marker is a signal of a cycle in which the value of the toggle signal transitions. 13. The processing method according to claim 11 or 12.

[0332] (Appendix 15) when the number of output pulses obtained by subtracting the number of mask pulses from the number of periodic pulses is a value obtained by subtracting 1 from the number of periodic pulses, and when the number of output pulses is 2 or more and is smaller than a value obtained by dividing the number of periodic pulses by 2, the marker portion includes the pulse that is not masked in two consecutive output clock timings that are timings at which the pulse is output as the divided clock signal when the pulse is not masked, and a non-marker portion that is a portion of the periodic pattern signal other than the marker portion does not include the pulse that is not masked in two consecutive output clock timings, When the number of output pulses is equal to or greater than the value obtained by dividing the number of periodic pulses by 2 and is smaller than the value obtained by subtracting 1 from the number of periodic pulses, and when the number of output pulses is 1, the pulses at at least two consecutive output clock timings are masked in the marker portion, and the pulses at two consecutive output clock timings are not masked in the non-marker portion. 14. The processing method according to claim 12 or 13.

[0333] (Appendix 16) generating the divided clock signal from the input clock signal; receiving the divided clock signal and generating the toggle signal using the divided clock signal; 12. The processing method according to claim 10 or 11.

[0334] (Appendix 17) determining whether or not to mask each of the pulses of the input clock signal based on the number of periodic pulses and a non-masked pulse number, which is the number of pulses that are not masked, and generating a mask signal indicative of the result of the determination; masking the pulses that have been determined to be masked in accordance with the mask signal, and outputting the pulses that have not been determined to be masked as they are; 16. The method of claim 16.

[0335] (Appendix 18) generating a marker portion mask signal, the marker portion being a leading portion of the periodic pattern signal, the marker portion being a mask signal determined by the number of periodic pulses and the number of unmasked pulses; generating a non-marker portion mask signal, which is the mask signal of the non-marker portion, such that an unmasked pulse pattern of a non-marker portion, which is a portion of the periodic pattern signal other than the marker portion, is identical to an unmasked pulse pattern of a periodic clock signal when rational frequency division is performed according to a predetermined rational frequency division algorithm at a frequency division ratio determined by a second periodic pulse number obtained by subtracting the number of pulses of the marker portion from the periodic pulse number and a second unmasked pulse number obtained by subtracting the number of unmasked pulses included in the marker portion from the non-masked pulse number; outputting the marker portion mask signal as the mask signal while the marker portion of the periodic pattern signal is being output, and outputting the non-marker portion mask signal as the mask signal while the non-marker portion of the periodic pattern signal is being output. 17. The processing method described in Appendix 17.

[0336] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above embodiments. Various modifications that can be understood by a person skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. [Explanation of symbols]

[0337] 10 Clock signal divider circuit 11 Marker 12 Markers 13 Marker 14 Marker 20 Communication control circuit 21 Communication control signal 22 Toggle signal generation circuit 23 Toggle Signal 23a Toggle signal 23b Toggle signal 30 Division ratio setting 41 Toggle Signal Marker 42 Toggle Signal Marker 43 Toggle Signal Marker 44 Toggle Signal Marker 51 Mask control circuit 52 Marker mask signal generator 53 Non-marker mask signal generator 54 Selection circuit 55 Mask signal 56 Counter Circuit 57 Counter Value 58 Mask Signal 59 Mask Signal 61 Mask Circuit 62 Latch Circuit 63 AND Circuit 71 Division ratio setting conversion section 72 Selector circuit 73 Adder 74 Memory circuit 75 Memory circuit 76 Size comparator 77 Addition result 78 Comparison results 81 Initialization circuit 82 Initialization signal 83 Addition 87 Addition result 88 Comparison results 100 Clock signal divider circuit 110a waveform 110b waveform 110c waveform 110d waveform 110e waveform 110f waveform 110g waveform 120 Clock signal divider circuit 124 Communication Timing Information 125 Communication Timing Information 1000 Processing Equipment 1001 Processing System 1010 Clock Signal Divider 1011 Clock signal receiver 1012 Setting information receiving unit 1013 Output signal generator 1014 Output section 1051 Mask control section 1052 Marker section mask signal generating section 1053 Non-marker mask signal generating unit 1054 Selection section 1061 Mask section 2000 Processing Unit 2001 Clock signal receiving section 2002 Toggle signal receiver 2003 Detection section 2004 Specific section 2005 Communications Department 3000 Processing Units 3001 Clock signal receiving section 3002 Toggle signal generator 3003 Communications Department

Claims

1. a toggle signal receiving means for receiving a toggle signal whose value transitions between two values ​​at the timing of a pulse of a frequency-divided clock signal in which a periodic pattern signal is repeated in which a predetermined number of mask pulses smaller than the number of periodic pulses of an input clock signal are masked out of successive pulses of the number of periodic pulses; a communication means for communicating with another processing device that operates according to the divided clock signal at the timing of the pulse of the divided clock signal, the timing being specified using the toggle signal among the pulses of the input clock signal; A processing device comprising:

2. the toggle signal includes a toggle signal marker that is a signal pattern; The signal pattern of the toggle signal marker is present only in the toggle signal at the portion of the toggle signal marker. The processing device of claim 1 .

3. the toggle signal marker is a signal pattern generated in the toggle signal by a part of a marker portion, which is a leading portion of the periodic pattern signal, The processing device includes: detection means for detecting the toggle signal marker from the toggle signal; a determination means for determining a timing of the pulse of the frequency-divided clock signal from the detected timing of the toggle signal marker; Further equipped The processing device according to claim 2 .

4. the divided clock signal includes a marker portion including at least one unmasked pulse at the beginning of the periodic pattern signal, The pulse pattern of the marker portion appears only in the marker portion of the divided clock signal. The processing device according to claim 3 .

5. when the number of output pulses obtained by subtracting the number of mask pulses from the number of periodic pulses is a value obtained by subtracting 1 from the number of periodic pulses, the toggle signal marker is a signal in a cycle in which the value of the toggle signal does not transition, when the number of output pulses is 2 or more and is smaller than the value obtained by dividing the number of periodic pulses by 2, the toggle signal marker is a two-cycle signal in which the value of the toggle signal does not transition for two consecutive cycles; when the number of output pulses is equal to or greater than the value obtained by dividing the number of periodic pulses by 2 and is smaller than the value obtained by subtracting 1 from the number of periodic pulses, the toggle signal marker is a two-cycle signal in which the value of the toggle signal transitions for two consecutive cycles; When the number of output pulses is 1, the toggle signal marker is a signal of a cycle in which the value of the toggle signal transitions. The processing device according to claim 2 or 3.

6. when the number of output pulses obtained by subtracting the number of mask pulses from the number of periodic pulses is a value obtained by subtracting 1 from the number of periodic pulses, and when the number of output pulses is 2 or more and is smaller than a value obtained by dividing the number of periodic pulses by 2, the marker portion includes the pulse that is not masked at two consecutive output clock timings that are timings at which the pulse is output as the divided clock signal when the pulse is not masked, and a non-marker portion that is a portion of the periodic pattern signal other than the marker portion does not include the pulse that is not masked at two consecutive output clock timings, When the number of output pulses is equal to or greater than the value obtained by dividing the number of periodic pulses by 2 and is smaller than the value obtained by subtracting 1 from the number of periodic pulses, and when the number of output pulses is 1, the pulses at at least two consecutive output clock timings are masked in the marker portion, and the pulses at two consecutive output clock timings are not masked in the non-marker portion. The processing device according to claim 3 or 4.

7. A processing device according to claim 1 or 2; a frequency-divided clock generating device for generating the frequency-divided clock signal from the input clock signal; a toggle signal generator that receives the divided clock signal and generates the toggle signal using the divided clock signal; 13. A processing system comprising:

8. The frequency-divided clock generating device comprises: determining whether or not to mask each of the pulses of the input clock signal based on the number of periodic pulses and a non-masked pulse number, which is the number of pulses that are not masked, and generating a mask signal indicative of the result of the determination; masking the pulses that have been determined to be masked in accordance with the mask signal, and outputting the pulses that have not been determined to be masked as they are; The processing system of claim 7 .

9. The frequency-divided clock generating device comprises: generating a marker portion mask signal, the marker portion being a leading portion of the periodic pattern signal, the marker portion being a mask signal determined by the number of periodic pulses and the number of unmasked pulses; generating a non-marker portion mask signal, which is the mask signal of the non-marker portion, such that an unmasked pulse pattern of a non-marker portion, which is a portion of the periodic pattern signal other than the marker portion, is identical to an unmasked pulse pattern of a periodic clock signal when rational frequency division is performed according to a predetermined rational frequency division algorithm with a frequency division ratio determined by a second periodic pulse number obtained by subtracting the number of pulses of the marker portion from the periodic pulse number and a second unmasked pulse number obtained by subtracting the number of unmasked pulses included in the marker portion from the non-masked pulse number; outputting the marker portion mask signal as the mask signal while the marker portion of the periodic pattern signal is being output, and outputting the non-marker portion mask signal as the mask signal while the non-marker portion of the periodic pattern signal is being output. The processing system of claim 8 .

10. receiving a toggle signal whose value transitions between two values ​​at the timing of a pulse of a divided clock signal in which a periodic pattern signal is repeated in which a predetermined number of mask pulses smaller than the number of periodic pulses of an input clock signal are masked; communicating with another processing device that is operated by the divided clock signal at the timing of the pulse of the divided clock signal, which is specified using the toggle signal, among the pulses of the input clock signal; Processing methods.

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