Wiring board, manufacturing method thereof, and semiconductor device

Abstract

To provide a wiring board in which unevenness on a conductor surface is reduced, and a manufacturing method thereof.SOLUTION: A wiring board 1 includes a ceramic substrate 10 and a metal layer 20 containing silver and copper arranged in contact with the ceramic substrate 10, and when viewed in cross section, the metal layer 20 has a lamellar structure of a silver-rich phase and a copper-rich phase.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present disclosure relates to a wiring board, a manufacturing method thereof, and a semiconductor device. [Background technology]

[0002] Conductors in some types of wiring boards are formed by firing a metal paste (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-129238 A Summary of the Invention [Problem to be solved by the invention]

[0004] When the conductors of the wiring board are formed by firing a metal paste, unevenness may occur on the surface of the conductor after firing, which may reduce the polishing efficiency and yield in the next process. Therefore, an object of an embodiment of the present disclosure is to provide a wiring board in which unevenness on a conductor surface is reduced, and a manufacturing method thereof. [Means for solving the problem]

[0005] The wiring board according to the first aspect of the present disclosure has a ceramic substrate and a metal layer containing silver and copper arranged in contact with the ceramic substrate, and in a cross-sectional view of the metal layer, the metal layer has a lamellar structure of a silver-rich phase and a copper-rich phase.

[0006] A wiring board according to a second aspect of the present disclosure comprises a ceramic substrate and a metal layer containing silver and copper arranged in contact with the ceramic substrate, the metal layer having a surface roughness (Ra) of 60 μm or less, and the surface of the metal layer being unpolished.

[0007] A semiconductor device according to a third aspect of the present disclosure includes a wiring board having a ceramic substrate and a metal layer containing silver and copper arranged in contact with the ceramic substrate, the metal layer having a lamellar structure of a silver-rich phase and a copper-rich phase in a cross-sectional view, and a semiconductor element arranged on the metal layer.

[0008] A method for manufacturing a wiring board according to a fourth aspect of the present disclosure includes preparing a ceramic substrate, arranging a conductive paste layer containing silver and copper so as to contact the ceramic substrate, heating the ceramic substrate on which the conductive paste layer is arranged, and cooling the heated ceramic substrate, wherein in heating the ceramic substrate, a maximum temperature is 700°C or higher and 900°C or lower, and in cooling the ceramic substrate, a cooling rate to 400°C is 3.0°C / min or higher. Effect of the Invention

[0009] According to one aspect of the present disclosure, it is possible to provide a wiring board having reduced unevenness on the surface of a metal layer, and a method for manufacturing the same. [Brief description of the drawings]

[0010] [Figure 1A] 1 is a schematic plan view showing a wiring board according to an embodiment; [Figure 1B] FIG. 1B is a schematic cross-sectional view showing a cross section taken along line IB-IB in FIG. 1A. [Diagram 2] 2 is a schematic cross-sectional view showing a cross section of a metal layer of a wiring board according to an embodiment. [Figure 3A] 3 is a schematic cross-sectional view showing a prepared ceramic substrate in the method for manufacturing a wiring substrate according to the embodiment; FIG. [Figure 3B] 3 is a schematic cross-sectional view showing a state in which a conductive paste layer is disposed in the method for manufacturing a wiring board according to the embodiment. FIG. [Figure 3C] 4 is a schematic cross-sectional view showing a state in which a metal layer has been formed in the method for manufacturing a wiring board according to the embodiment. FIG. [Figure 4A] 1 is a schematic plan view showing a light emitting device according to an embodiment. [Figure 4B] 4B is a schematic cross-sectional view showing a cross section taken along line IVB-IVB in FIG. 4A. [Diagram 5] 4 is a cross-sectional image of a metal layer of the wiring board of Example 1. [Figure 6] 1 is a planar image of a metal layer of a wiring board according to a first embodiment. [Figure 7] 1 is a cross-sectional image of a metal layer of a wiring board in Comparative Example 1. [Figure 8] 1 is a planar image of a metal layer of a wiring board in Comparative Example 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment according to the present disclosure will be described. However, the embodiment described below is for embodying the technical idea according to the present disclosure, and the invention is not limited to the following unless otherwise specified. The contents described in one embodiment are applicable to other embodiments and modified examples. In addition, the drawings are schematic diagrams of the embodiments, and in order to clarify the description, the scale, interval, positional relationship, etc. of each member may be exaggerated, or some of the members may be omitted, or an end view showing only the cut surface may be used as a cross-sectional view. The directions shown in each figure indicate the relative positions between the components, and are not intended to indicate absolute positions. In addition, the same names and symbols indicate, in principle, the same or homogeneous members, and detailed descriptions are omitted as appropriate.

[0012] (wiring board) A wiring board according to an embodiment and a manufacturing method thereof will be described with reference to Figs. 1A, 1B, 2, and 3A to 3C. Fig. 1A is a schematic plan view showing a wiring board 1 according to an embodiment. Fig. 1B is a schematic cross-sectional view showing a cross section along line IB-IB in Fig. 1A. Fig. 2 is a schematic cross-sectional view showing a cross section of a metal layer 20 of a wiring board according to an embodiment. Figs. 3A to 3C are schematic cross-sectional views for explaining a manufacturing method of the wiring board 1 shown in Figs. 1A and 1B.

[0013] A wiring board 1 according to an embodiment of the present disclosure has a ceramic substrate 10 and a metal layer 20 containing silver and copper arranged in contact with the ceramic substrate 10, and in a cross-sectional view of the metal layer 20, it has a lamellar structure of a silver-rich phase 21 and a copper-rich phase 22.

[0014] A manufacturing method of a wiring board 1 according to an embodiment of the present disclosure includes: (a) preparing a ceramic substrate 10; (b) arranging a conductive paste layer 31 containing silver and copper so as to contact the ceramic substrate 10; (c) heating the ceramic substrate 10 on which the conductive paste layer 31 is arranged; and (d) cooling the heated ceramic substrate 10, wherein in heating the ceramic substrate 10, the maximum temperature is 700°C or more and 900°C or less, and in cooling the ceramic substrate 10, the cooling rate to 400°C is 3.0°C / min or more. Each step will be described in detail below.

[0015] (a) Preparing a ceramic substrate A ceramic substrate 10 is prepared (FIG. 3A).

[0016] The ceramic substrate 10 is an insulating member that serves as a base on which the metal layer 20 will be disposed later. The ceramic substrate 10 has a first surface 11 and a second surface 12 that is the opposite side to the first surface 11. The first surface 11 has a first planar portion 13 and a first arrangement portion 14 that is recessed from the first planar portion 13. The first planar portion 13 is a flat surface and constitutes a part of the outer surface of the wiring substrate 1. Note that, although the ceramic substrate 10 having two first arrangement portions 14 corresponding to one wiring substrate 1 is illustrated, a ceramic substrate 10 having a plurality of first arrangement portions 14 corresponding to a plurality of wiring substrates 1 can be used.

[0017] From the viewpoint of heat dissipation, the material of the ceramic substrate 10 is preferably a ceramic with high thermal conductivity. For example, the material of the ceramic substrate 10 is preferably a nitride-based ceramic such as silicon nitride, aluminum nitride, or boron nitride, but an oxide-based ceramic such as aluminum oxide, silicon oxide, calcium oxide, or magnesium oxide may also be used. The material of the ceramic substrate 10 is particularly preferably aluminum nitride or silicon nitride.

[0018] The thickness of the ceramic substrate 10 is preferably, for example, not less than 0.08 mm and not more than 2 mm.

[0019] The first arrangement portion 14 is rectangular in plan view and has a long side and a short side. The two first arrangement portions 14 are arranged so that their long sides face each other. The first arrangement portion 14 may have rounded corners in plan view, or the entire end portion in the long side may be curved. The inner surface in the plate thickness direction of the first arrangement portion 14 may be a curved surface. In a cross-sectional view of the ceramic substrate 10 in the plate thickness direction, the first arrangement portion 14 is curved except for a partial flat surface of the bottom surface. The first arrangement portion 14 may have a curved bottom surface that is continuous with the inner surface. For example, the first arrangement portion 14 may be curved in a cross-sectional view of the ceramic substrate 10 in the thickness direction.

[0020] The inner surface defining the first arrangement portion 14 is preferably roughened. By roughening the surface, peeling of the metal layer 20 disposed in the first arrangement portion 14 can be reduced. The arithmetic mean roughness Ra of the inner surface defining the first arrangement portion 14 can be, for example, 200 nm or more and 2 μm or less, and preferably 300 nm or more and 800 nm or less. In this specification, the arithmetic mean roughness Ra may be measured in accordance with JIS B 0601. For example, it may be measured using a stylus-type surface roughness meter (for example, SE3500 manufactured by Kosaka Laboratory Co., Ltd.) equipped with a diamond stylus with a tip curvature radius r of 2 μm.

[0021] The ceramic substrate 10 is a sintered substrate. When a conductor paste, which will be described later, is arranged using a green sheet before sintering, the ceramic substrate warps or shrinks significantly before and after sintering the green sheet, making it difficult to arrange the first arrangement portion with high accuracy. In contrast, in this embodiment, a sintered ceramic substrate is used and the conductor paste is arranged, so that warping and shrinkage of the ceramic substrate are significantly reduced, and the first arrangement portion can be arranged with high accuracy. The ceramic substrate 10 may be formed by sintering ceramic, or a sintered substrate such as a commercially available product may be used. The first arrangement portion 14 in the ceramic substrate 10 may be present in advance, or may be formed after purchasing a sintered substrate such as a commercially available product. In addition, a substrate on which the first arrangement portion 14 is formed may be purchased as the ceramic substrate 10.

[0022] The first arrangement portion 14 can be formed by, for example, etching, blasting, or laser processing. This allows the inner surface that defines the first arrangement portion 14 to have a curved shape. Note that only one of the etching, blasting, and laser processing may be performed, or two or more of them may be combined. Also, the bottom surface that defines the recess of the first arrangement portion 14 in a cross-sectional view may have a flat portion.

[0023] The etching can be performed by wet etching or dry etching, and wet etching is preferred. Wet etching can form the curved first arrangement portion 14 by etching using an acidic or alkaline agent such as HF, NHF, KOH, NaOH, or CsOH.

[0024] (b) disposing a layer of conductive paste; A conductive paste layer 31 containing silver and copper is disposed so as to be in contact with the ceramic substrate 10. That is, the conductive paste layer 31 containing silver and copper is disposed on the first placement portion 14 of the ceramic substrate 10 (FIG. 3B).

[0025] A conductive paste layer 31 is disposed within the first arrangement portion 14 of the ceramic substrate 10. The conductive paste layer 31 becomes the metal layer 20 by firing. The conductive paste layer 31 is a member having fluidity, and the conductive paste can be applied and disposed on the surface of the first arrangement portion 14 so as to be in close contact with the surface.

[0026] The conductive paste layer 31 contains silver and copper, and is preferably a metal powder. Silver and copper may be present as a mixture of silver or a silver compound and copper or a copper compound, or may be present as a silver-copper alloy. The silver-copper alloy may be a eutectic with a melting point of 780°C to 850°C, preferably a eutectic with a melting point of about 780°C. In addition, the conductive paste layer 31 may contain silver or a silver compound and copper or a copper compound together with the silver-copper alloy. This is because firing can be performed at a temperature lower than the melting points of silver and copper, and a metal layer having a thermal conductivity close to that of 100% silver or copper can be formed. However, when a powder of a metal having a melting point higher than the firing temperature (about 800°C), such as silver (962°C) or copper (1082°C), is mixed with the silver-copper alloy, the silver and copper powders may be dispersed in the metal layer after firing.

[0027] The median diameter of the metal powder is preferably 1 μm or more and 50 μm or less, more preferably 2 μm or more and 40 μm or less, and particularly preferably 5 μm or more and 30 μm or less. By making the median diameter of the metal powder 5 μm or more, it is possible to suppress aggregation and increase thermal conductivity. On the other hand, by making the median diameter of the metal powder 10 μm or less, it is possible to increase the packing property. In addition, the shape of the metal powder is preferably spherical or elliptical from the viewpoint of fluidity, but it may be flat or acicular. By making the shape flat or acicular, it is possible to increase contact between particles, increase thermal conductivity, and reduce electrical resistance.

[0028] The mixture ratio of silver and copper in the conductive paste layer 31 may be preferably 1:99 to 99:1, more preferably 1:99 to 99:1, even more preferably 30:70 to 90:10, even more preferably 50:50 to 85:15, and particularly preferably 60:40 to 80:20. In the case of a silver-copper alloy, it is preferable that the silver content is about 72% and the copper content is about 28%.

[0029] The conductive paste layer 31 may contain at least an active metal powder. The active metal powder may be at least one selected from TiH2, CeH2, ZrH2, and MgH2. Among these, TiH2 is preferable. By containing TiH2, it reacts with the nitrogen contained in the ceramic substrate 10 and forms a metal compound layer that becomes a reaction layer such as TiN at the interface with the ceramic substrate 10. This improves the adhesion between the metal layer 20, which is formed by hardening the conductive paste layer 31, and the ceramic substrate 10.

[0030] The conductive paste layer 31 may further contain an organic solvent. Examples of the organic solvent include those used in general conductive pastes. For example, glycol-based solvents, carbitol-based solvents, and terpineol-based solvents are included.

[0031] The conductor paste layer 31 may further contain an organic resin binder. The viscosity of the conductor paste layer 31 can be adjusted by the type and amount of the organic resin binder. The organic resin binder may be, for example, a solvent generally used in conductor pastes, or a resin material such as acrylic, epoxy, urethane, ethyl cellulose, silicone, phenol, polyimide, polyurethane, melamine, or urea. The organic binder is decomposed and evaporated and removed by firing, which will be described later.

[0032] The conductive paste layer 31 may contain a plurality of inorganic fillers other than metal. By containing the inorganic filler, it is possible to reduce the volumetric shrinkage during sintering of the conductive paste layer 31. As the inorganic filler, for example, AlN, Si3N4, etc. can be used.

[0033] The conductive paste layer 31 preferably contains, by weight percentage, 50% to 98.4% silver and copper, 0.5% to 20% metal active powder, 1% to 20% inorganic filler, and 0.1% to 10% organic binder.

[0034] As an example, the conductive paste layer 31 preferably contains, by weight percentage, 50% to 98.4% silver-copper alloy with a silver to copper mixing ratio of 72:28, 0.5% to 20% TiH2 as a metal active powder, 1% to 20% AlN as an inorganic filler, and 0.1% to 10% organic binder.

[0035] (c) Heating the ceramic substrate The ceramic substrate 10 on which the conductive paste layer 31 is disposed is heated. In this process, the conductive paste layer 31 is heated.

[0036] The maximum temperature at which the ceramic substrate 10 is heated may be 700° C. or higher and 900° C. or lower, preferably 750° C. or higher and 880° C. or lower, and more preferably 800° C. or higher and 860° C. or lower.

[0037] The rate at which the ceramic substrate 10 is heated to the maximum temperature may be, for example, 5.0° C. / min to 30° C. / min, and preferably 10° C. / min to 20° C. / min.

[0038] The heating time at the maximum temperature when heating the ceramic substrate 10 (in other words, the holding time at the maximum temperature) may be preferably 10 minutes or more and 60 minutes or less, and more preferably 15 minutes or more and 45 minutes or less.

[0039] The atmosphere in which the ceramic substrate 10 is heated is preferably 10 -2 Pa or more and 300 Pa or less, more preferably 10 -2 Pa or more and 100 Pa or less, more preferably 10 -2The atmosphere during heating of the ceramic substrate 10 may be a vacuum atmosphere of 10 Pa or more and 10 Pa or less. Alternatively, the atmosphere during heating of the ceramic substrate 10 may be an inert atmosphere of 99.9% or more, preferably an Ar atmosphere.

[0040] (d) Cooling the ceramic substrate The ceramic substrate 10 heated in (c) above is cooled. In this step, the conductive paste layer 31 is cooled. The ceramic substrate 10 on which the conductive paste layer 31 is disposed is heated (step (c)) and then cooled (step (d)), thereby turning the conductive paste layer 31 into the metal layer 20 (FIG. 3C).

[0041] When the ceramic substrate is cooled, the cooling rate to 400° C. may be 3.0° C. / min or more, preferably 5.0° C. / min or more, and more preferably 7.0° C. / min or more.

[0042] When the ceramic substrate is cooled, the cooling rate to 400° C. may be preferably 10° C. / min or less, more preferably 9.0° C. / min or less, and further preferably 8.0° C. / min or less.

[0043] The cooling rate for cooling the ceramic substrate in the temperature range below 400° C. may be the same as the cooling rate up to 400° C. For example, the cooling rate from 400° C. to 200° C. may be the same as the cooling rate up to 400° C.

[0044] The ceramic substrate is cooled preferably to 100°C or less, more preferably to 50°C or less, and further preferably to room temperature, for example, 25°C.

[0045] The atmosphere during cooling of the ceramic substrate 10 is preferably 10 -2 Pa or more and 300 Pa or less, more preferably 10 -2 Pa or more and 100 Pa or less, more preferably 10 -2 The atmosphere during cooling of the ceramic substrate 10 may be a vacuum atmosphere of not less than 10 Pa and not more than 10 Pa. Alternatively, the atmosphere during cooling of the ceramic substrate 10 may be an inert atmosphere of not less than 99.9%, for example, an Ar atmosphere.

[0046] The atmosphere during heating and cooling of the ceramic substrate 10 is preferably the same. -2 Pa or more and 300 Pa or less, more preferably 10 -2 Pa or more and 100 Pa or less, more preferably 10 -2 It is preferable to perform heating and cooling under a pressure of from 10 Pa to 10 Pa. Alternatively, the atmosphere during heating and cooling of the ceramic substrate 10 may be an inert atmosphere of 99.9% or more, preferably an Ar atmosphere.

[0047] In the method for manufacturing a wiring board of the present disclosure, the maximum temperature when heating the ceramic substrate 10 is set to 700° C. or more and 900° C. or less, and the cooling rate to 400° C. when cooling the ceramic substrate 10 is set to 3.0° C. / min or more, thereby reducing unevenness on the surface of the obtained metal layer 20. Since the wiring substrate 1 has less unevenness on the surface of the metal layer 20, the polishing efficiency and yield of the metal layer surface are improved when mounting electronic components such as semiconductor elements.

[0048] The surface roughness (arithmetic mean roughness Ra) of the metal layer 20 may be preferably 60 μm or less, more preferably 40 μm or less, even more preferably 20 μm or less, and even more preferably 10 μm or less.

[0049] The wiring board 1 can have the above-mentioned surface roughness with few irregularities on the surface of the metal layer 20 at the time of forming the metal layer 20, i.e., before polishing. That is, the wiring board 1 of the present disclosure has a ceramic substrate 10 and a metal layer 20 containing silver and copper that is arranged so as to be in contact with the ceramic substrate 10, and the surface roughness (Ra) of the metal layer 20 is 60 μm or less before the surface of the metal layer 20 is polished.

[0050] Wiring board 1 manufactured by the wiring board manufacturing method of the present disclosure has a lamellar structure of silver-rich phase 21 and copper-rich phase 22 in a cross-sectional view of metal layer 20.

[0051] In this specification, the lamellar structure refers to a lamellar crystal structure, and means a layered structure in which a silver-rich phase and a copper-rich phase are layered in a cross-sectional view.

[0052] The layers of the silver-rich phase 21 and the copper-rich phase 22 are not limited to being linear in cross section, but may be curved, that is, bent.

[0053] In this specification, silver-rich phase means a phase having a silver content of more than 50% by weight.

[0054] In this specification, copper-rich phase means a phase having a copper content of more than 50% by weight.

[0055] The silver content relative to the total of silver and copper in the silver-rich phase 21 may be preferably 91.2% by weight or more and 94.0% by weight or less, and more preferably 91.2% by weight or more and 93.0% by weight or less.

[0056] The content of copper in the silver-rich phase 21 relative to the total of silver and copper may be preferably 6.0% by weight or more and 8.8% by weight or less, and more preferably 7.0% by weight or more and 8.8% by weight or less.

[0057] The content of silver in the copper-rich phase 22 relative to the total of silver and copper may be preferably 7.4% by weight or more and 8.0% by weight or less, and more preferably 7.6% by weight or more and 8.0% by weight or less.

[0058] The copper content relative to the total of silver and copper in the copper-rich phase 22 may be preferably 92.0% by weight or more and 92.6% by weight or less, and more preferably 92.0% by weight or more and 92.4% by weight or less.

[0059] The components constituting the metal layer 20 may be measured by observing a cross section of the metal layer 20 using SEM-EDX. For example, the measurement may be performed using a scanning electron microscope SU8230 manufactured by Hitachi and an energy dispersive X-ray analyzer SDD detector manufactured by Horiba, Ltd.

[0060] In a cross-sectional view of the metal layer 20, the width of the silver-rich phase 21 is preferably 0.1 μm or more and 5.0 μm or less, more preferably 0.2 μm or more and 4.0 μm or less, and further preferably 0.3 μm or more and 3.0 μm or less.

[0061] In a cross-sectional view of the metal layer 20, the width of the copper-rich phase 22 is preferably 0.1 μm or more and 5.0 μm or less, more preferably 0.2 μm or more and 4.0 μm or less, and further preferably 0.3 μm or more and 3.0 μm or less.

[0062] In a cross-sectional view of the metal layer 20, the width of the silver-rich phase 21 and the copper-rich phase 22 is preferably 0.1 μm or more and 5.0 μm or less, more preferably 0.2 μm or more and 4.0 μm or less, and further preferably 0.3 μm or more and 3.0 μm or less. Here, the width of the silver-rich phase 21 and the copper-rich phase 22 refers to the maximum length among the lengths in a direction perpendicular to the longitudinal direction in a cross-sectional view.

[0063] In a cross-sectional view of the metal layer 20, the aspect ratio of the silver-rich phase 21 may be preferably 1:1 to 1:50, more preferably 1:5 to 1:40, and further preferably 1:10 to 1:30.

[0064] In a cross-sectional view of the metal layer 20, the aspect ratio of the copper-rich phase 22 may be preferably 1:1 to 1:50, more preferably 1:5 to 1:40, and further preferably 1:10 to 1:30.

[0065] The aspect ratio of the silver-rich phase 21 and the copper-rich phase 22 refers to the value obtained by dividing the length of each phase by the width.

[0066] The widths and aspect ratios of the silver-rich phase 21 and the copper-rich phase 22 in a cross-sectional view of the metal layer 20 may be measured by observing the cross-section of the metal layer 20 using an SEM. For example, the measurements may be performed using a scanning electron microscope SU8230 manufactured by Hitachi, Ltd.

[0067] In a cross-sectional view of the metal layer 20, the areas of the silver-rich phase 21 and the copper-rich phase 22 may be preferably 50% or more, more preferably 70% or more, even more preferably 80% or more, and even more preferably 85% or more of the area of ​​the cross section. Also, the areas of the silver-rich phase 21 and the copper-rich phase 22 may be preferably 99% or less, more preferably 95% or less, and even more preferably 90% or less of the area of ​​the cross section.

[0068] In a cross-sectional view of the metal layer 20, the area of ​​the silver-rich phase 21 is preferably larger than the area of ​​the copper-rich phase 22. The area of ​​the silver-rich phase 21 may be preferably 1.1 times or more, more preferably 1.3 times or more, and even more preferably 1.5 times or more, for example, 2.0 times or more or 2.5 times or more, of the area of ​​the copper-rich phase 22. The area of ​​the silver-rich phase 21 may be preferably 5.0 times or less, more preferably 3.0 times or less, and even more preferably 2.0 times or less, of the area of ​​the copper-rich phase 22.

[0069] The metal layer 20 may contain at least one selected from an active metal and an inorganic filler. The active metal and the inorganic filler are as described above with respect to the conductive paste.

[0070] In a cross-sectional view of the metal layer 20, the metal layer 20 may have other phases besides the silver-rich phase 21 and the copper-rich phase 22. Examples of the other phases include a phase 23 derived from an inorganic filler contained in the conductive paste layer and a phase 24 derived from an active metal. The phase 23 derived from the inorganic filler and the phase 24 derived from the active metal may be the phases of the inorganic filler and the active metal themselves, respectively, or may be phases obtained as a result of reaction with other components. For example, when the inorganic filler is AlN and the active metal is TiH2, the phase derived from the inorganic filler may be AiN, and the phase 24 derived from the active metal may be TiN.

[0071] The total area of ​​the phases other than the silver-rich phase 21 and the copper-rich phase 22 may be preferably 1% or more, more preferably 5% or more, and even more preferably 10% or more of the cross-sectional area. The total area of ​​the phases other than the silver-rich phase 21 and the copper-rich phase 22 may be preferably 50% or less, more preferably 30% or less, even more preferably 20% or less, and even more preferably 15% or less of the cross-sectional area.

[0072] (Semiconductor Device) The semiconductor device according to the present disclosure includes a ceramic substrate, a metal layer containing silver and copper arranged in contact with the ceramic substrate, the metal layer having a lamellar structure of a silver-rich phase and a copper-rich phase in a cross-sectional view, and a semiconductor element arranged on the metal layer. That is, the semiconductor device according to the present disclosure includes the wiring substrate according to the present disclosure and the semiconductor element arranged thereon.

[0073] Examples of the semiconductor element include an LSI, an IC, an LED (light emitting device), an LD (semiconductor laser), etc. Examples of the semiconductor device include a light emitting device.

[0074] Hereinafter, a light emitting device 100 according to an embodiment of the present disclosure will be described with reference to Fig. 4A and Fig. 4B. Fig. 4A is a schematic plan view showing the light emitting device 100. Fig. 4B is a schematic cross-sectional view showing a cross section taken along line IVB-IVB in Fig. 4A.

[0075] The light emitting device 100 includes the wiring board 1 of the present disclosure, and a light emitting element 40 having an element electrode 41 arranged on the wiring board 1, with the element electrode 41 and the metal layer 20 being electrically connected. The light emitting element 40 is arranged on the metal layer 20. Here, the light emitting device 100 further includes a light transmissive member 42 arranged on the upper surface of the light emitting element 40, and a covering member 43 that exposes the upper surface of the light transmissive member 42 and covers the light emitting element 40 and the light transmissive member 42. The light emitting device 100 has one light emitting element 40 as an example. Each configuration of the light emitting device 100 will be described below.

[0076] (Light emitting element) The light emitting element 40 is a member that emits light when supplied with power. The shape of the light emitting element 40 in a plan view is, for example, rectangular. The light emitting element 40 includes a semiconductor laminate, in which a light-transmitting substrate such as sapphire or gallium nitride is disposed on the upper surface side of the semiconductor laminate, and a pair of element electrodes 41 is disposed on the lower surface side. The semiconductor laminate can have any composition depending on the desired emission wavelength. For example, a nitride semiconductor (In x Al y Ga 1-x-y N, 0≦X, 0≦Y, X+Y≦1), GaP, or GaAlAs or AlInGaP capable of emitting red light can be used. The size and shape of the light emitting element 40 can be appropriately selected depending on the purpose of use.

[0077] The pair of element electrodes 41 have, for example, a rectangular shape in a plan view, and are exposed on the lower surface 40B of the light emitting element 40. The element electrodes 41 can be made of, for example, a single layer film or a laminate film of a metal such as gold, platinum, palladium, rhodium, nickel, tungsten, molybdenum, chromium, titanium, or an alloy thereof.

[0078] Here, the element electrode 41 is connected to the metal layer 20 via a conductive member 44. The conductive member 44 can be, for example, a bump of gold or solder, or the element electrode 41 and the metal layer 20 may be connected without providing a bump by, for example, printing and arranging solder on the entire electrode surface.

[0079] (Translucent member) The light-transmitting member 42 is a member that protects the upper surface 40A of the light-emitting element 40 and is located on the light extraction surface of the light-emitting device 100. Here, the light-transmitting member 42 is rectangular, as an example, and has the same size and shape as the light-emitting element 40 in a planar view. The light-transmitting member 42 may have a shape and size that encompasses the light-emitting element 40 in a planar view.

[0080] The light-transmitting member 42 is made of, for example, a light-transmitting resin material, and may be, for example, an epoxy resin, a silicone resin, or a resin obtained by mixing these. The light-transmitting member 42 may contain a phosphor, and for example, by containing a phosphor that absorbs blue light from the light-emitting element 40 and emits yellow light, the light-emitting device 100 can emit white light. The light-transmitting member 42 may also contain multiple types of phosphors, and for example, by containing a phosphor that absorbs blue light from the light-emitting element 40 and emits green light and a phosphor that emits red light, the light-emitting device 100 can emit white light.

[0081] The light-transmitting member 42 may further include a light-emitting material such as a phosphor or quantum dots. Examples of such phosphors include yttrium aluminum (gallium-doped) garnet activated with cerium, nitrogen-containing calcium aluminosilicate (strontium) activated with europium, potassium fluorosilicate activated with manganese, and β-sialon phosphors. Specific examples of phosphors include yttrium aluminum garnet phosphors (e.g., (Y,Gd)3(Al,Ga)5O 12 :Ce), lutetium aluminum garnet phosphors (e.g., Lu3(Al,Ga)5O 12 :Ce), terbium aluminum garnet phosphors (e.g., Tb3(Al,Ga)5O 12 :Ce), CCA phosphors (e.g., Ca 10 (PO4)6Cl2:Eu), SAE phosphors (e.g., Sr4Al 14 O 25 :Eu), chlorosilicate phosphors (e.g., Ca8MgSi4O 16 Cl2:Eu), silicate phosphors (e.g., (Ba,Sr,Ca,Mg)2SiO4:Eu), β-sialon phosphors (e.g., (Si,Al)3(O,N)4:Eu) or α-sialon phosphors (e.g., Ca(Si,Al) 12 (O,N) 16 :Eu) and other oxynitride phosphors, LSN phosphors (e.g., (La,Y)3Si6N 11:Ce), BSESN-based phosphors (e.g., (Ba,Sr)2Si5N8:Eu), SLA-based phosphors (e.g., SrLiAl3N4:Eu), CASN-based phosphors (e.g., CaAlSiN3:Eu), or SCASN-based phosphors (e.g., (Sr,Ca)AlSiN3:Eu), etc., nitride-based phosphors, KSF-based phosphors (e.g., K2SiF6:Mn), KSAF-based phosphors (e.g., K2(Si 1-x Al x )F 6-x :Mn, where 0 < x < 1. ) or fluoride-based phosphors such as MGF-based phosphors (e.g., 3.5MgO·0.5MgF2·GeO2:Mn), etc. Examples of quantum dots include quantum dots having a perovskite structure (e.g., (Cs,FA,MA)(Pb,Sn)(F,Cl,Br,I)3, where FA represents formamidinium and MA represents methylammonium), II-VI group quantum dots (e.g., CdSe), III-V group quantum dots (e.g., InP), quantum dots having a chalcopyrite structure (e.g., (Ag,Cu)(In,Ga)(S,Se)2), etc.

[0082] (Coating member) The coating member 43 is disposed on the upper surface of the wiring substrate 1 and covers and protects the side surfaces of the light-emitting element 40 and the light-transmitting member 42. The coating member 43 is disposed with the upper surface of the light-transmitting member 42 exposed. Further, the coating member 43 enters between the light-emitting element 40 and the wiring substrate 1 to also cover the side surfaces of the element electrode 41 and the conductive member 44.

[0083] The covering member 43 can be formed of a resin having light reflectivity, light transmission, light blocking properties, etc., or a resin containing a light reflecting substance in such a resin. The covering member 43 preferably has at least one of light reflectivity and light blocking properties. Examples of the resin include a resin containing one or more of silicone resin, modified silicone resin, epoxy resin, modified epoxy resin, and acrylic resin, or a hybrid resin. Examples of the light reflecting substance include titanium oxide, silicon oxide, zirconium oxide, potassium titanate, aluminum oxide, aluminum nitride, boron nitride, and mullite. The covering member 43 may contain a phosphor, a diffusing material, a colorant, etc.

[0084] (Method of manufacturing a light emitting device) Next, a method for manufacturing the light emitting device 100 will be described.

[0085] The manufacturing method of the light emitting device 100 includes preparing the wiring board 1 and arranging the light emitting element 40 having the element electrode 41 on the metal layer 20, and in arranging the light emitting element 40, the metal layer 20 and the light emitting element 40 are directly or indirectly electrically connected. Here, the manufacturing method further includes arranging a conductive member 44, exposing the upper surface of the light transmissive member 42 arranged on the upper surface of the light emitting element 40 to form a covering member 43 covering the light emitting element 40 and the light transmissive member 42, and singulating. Each component of the manufacturing method of the light emitting device will be described below.

[0086] (Prepare the wiring board) Prepare the wiring board 1. The wiring board 1 can be manufactured by the above-mentioned method for manufacturing the wiring board 1. In the wiring board 1, the metal layer 20 is formed in accordance with the size and arrangement of the light-emitting element 40, the interval between the pair of element electrodes 41, and the like.

[0087] (Placing conductive material) A conductive member 44 before bonding is placed on the metal layer 20.

[0088] (Placing the light-emitting element) The light emitting element 40 is arranged with the element electrode 41 facing the wiring board 1. The light emitting element 40 may be arranged in an array in the row and column directions on the wiring board 1. The element electrode 41 can be indirectly electrically connected to the metal layer 20 via a conductive member 44.

[0089] The light-transmitting member 42 is disposed in advance on the upper surface of the light-emitting element 40. The light-transmitting member 42 can be disposed by applying the material of the uncured light-transmitting member 42 by, for example, potting, spraying, inkjet printing, printing, or the like, and then curing it. The light-transmitting member 42 may be a member formed in a sheet or plate shape and disposed on the upper surface of the light-emitting element 40 via an adhesive. Note that the light-transmitting member 42 may be disposed on the upper surface of the light-emitting element 40 after the light-emitting element 40 on which the light-transmitting member 42 has not been disposed in advance is disposed on the wiring board 1.

[0090] (Placing covering materials) The covering member 43 is disposed on the upper surface of the wiring board 1 so as to expose the upper surface of the light-transmitting member 42. The covering member 43 is preferably disposed so as to cover the side surfaces of the light-emitting element 40 and the light-transmitting member 42, and also to cover the lower surface of the light-emitting element 40 and the side surfaces of the conductive member 44. The covering member 43 can be disposed, for example, by disposing a nozzle of a resin discharge device above the wiring board 1, discharging uncured resin material from the tip of the nozzle while moving the nozzle, and then curing the resin. The covering member 43 is preferably applied in multiple steps.

[0091] The upper surface of the covering member 43 is preferably formed to be flush with the upper surface of the light-transmitting member 42. The covering member 43 disposed between adjacent light-emitting elements 40 and the light-transmitting member 42 may be disposed so that the upper surface is partially recessed or raised. The raised covering member 43 can also be polished, ground, or the like to form the upper surface of the covering member 43 to be flush with the upper surface of the light-transmitting member 42. In this case, not only the upper surface of the covering member 43 but also the top of the light-transmitting member 42 may be polished, ground, or the like. After the covering member 43 is disposed, an assembly is formed in which a plurality of light-emitting devices 100 are aligned in the row and column directions.

[0092] (Individualize) The assembly of light emitting devices is cut to separate it into individual light emitting devices 100. The cutting lines are positioned in a lattice pattern on covering member 43 in a plan view. The cutting can be performed by, for example, a laser or a blade. EXAMPLES

[0093] The present disclosure will be described below with reference to examples, but the present disclosure is not limited to the following examples.

[0094] (Preparation of Conductive Paste) A powder of silver-copper alloy (weight ratio of silver:copper=72:28), an active metal powder (TiH2 powder), an inorganic filler (AlN powder), a resin (polyvinyl acetal resin), and an organic solvent (terpineol-based solvent) were used as the conductor paste of Examples 1 and 2 and Comparative Examples 1 and 2. The conductor paste was prepared by mixing 100 parts by mass of silver-copper alloy with 10 parts by mass of active metal powder, 10 parts by mass of inorganic filler, 0.5 parts by mass of resin, and 14 parts by mass of organic solvent.

[0095] (Making of wiring board) The conductive paste obtained above was applied to a Si3N4 substrate to a thickness of 80 μm. Next, the substrate coated with the conductive paste was heated at 100° C. for 30 minutes to dry, and a substrate having the conductive paste was prepared. The obtained substrate was fired under a reduced pressure Ar atmosphere (100 Pa), heated to about 850° C., and held at 850° C. for 0.5 hours. Thereafter, the conductive paste of Example 1 was cooled to 200° C. at 7.2° C. per minute. The conductive paste of Example 2 was cooled to 200° C. at 13.1° C. per minute. The conductive paste of Comparative Example 1 was cooled to 200° C. at 2.2° C. per minute, and the conductive paste of Comparative Example 2 was cooled to 200° C. at 1.1° C. per minute. Here, the cooling rate is expressed as the rate up to 200° C., but the cooling rate is the same even at the passing point of 400° C. The surface roughness (Ra) of the wiring substrates of Examples 1 and 2 and Comparative Example 1 was measured using a VR-5200 manufactured by Keyence. The results are shown in the table below. In addition, the cross section and surface of the metal layer were photographed by SEM. FIG. 5 is a cross-sectional image of the metal layer of the wiring board of Example 1. FIG. 6 is a planar image of the metal layer of the wiring board of Example 1. FIG. 7 is a cross-sectional image of the metal layer of the wiring board of Comparative Example 1. FIG. 8 is a planar image of the metal layer of the wiring board of Comparative Example 1.

[0096] [Table 1]

[0097] From the above results, the metal layer of Example 1 had a small surface roughness and was flat, and a lamellar structure was confirmed in cross-sectional view. The metal layer of Example 2 also had a small surface roughness and was flat, and a lamellar structure was confirmed in cross-sectional view, but the lamellar structure was only a part of it. On the other hand, the metal layer of Comparative Example 2 had the roughest surface roughness, and the unevenness was sufficiently confirmed even with the naked eye. The metal layer of Comparative Example 1 also had obvious unevenness on the surface, although not as much as the metal layer of Comparative Example 2. The metal layer of Comparative Example 1 had multiple protrusions formed in relatively small units in plan view, while the metal layer of Comparative Example 2 had one protrusion compared to several protrusions of Comparative Example 1, and the area of ​​each protrusion was large. The reason why multiple protrusions are formed in Comparative Examples 1 and 2 is unclear, but it is possible that some of the silver components evaporated due to firing under reduced pressure. In addition, when the molten material solidifies, it crystallizes around the base point, which may have created grain boundaries and caused the unevenness. For this reason, a slow cooling rate makes the surface of the metal layer more likely to become uneven, while a fast cooling rate makes it difficult for unevenness to form, resulting in a flat surface.

[0098] Embodiments of the present disclosure include the following: [Section 1] A ceramic substrate; a metal layer including silver and copper, the metal layer being disposed in contact with the ceramic substrate; A wiring board, wherein the metal layer has a lamellar structure of a silver-rich phase and a copper-rich phase in a cross-sectional view. [Section 2] Item 2. The wiring board according to item 1, wherein the surface roughness (Ra) of the metal layer is 60 μm or less. [Section 3] 3. The wiring board according to item 1 or 2, wherein the silver-rich phase has a silver content of 91.2% by weight or more and 94.0% by weight or less based on the total weight of silver and copper. [Section 4] 4. The wiring board according to any one of items 1 to 3, wherein the silver-rich phase has a copper content of 6.0% by weight or more and 8.8% by weight or less with respect to the total content of silver and copper. [Section 5] 5. The wiring board according to any one of items 1 to 4, wherein the content of silver in the copper-rich phase is 7.4% by weight or more and 8.0% by weight or less with respect to the total of silver and copper. [Section 6] 6. The wiring board according to any one of items 1 to 5, wherein the copper-rich phase has a copper content of 92.0% by weight or more and 92.6% by weight or less based on the total weight of silver and copper. [Section 7] 7. The wiring board according to any one of items 1 to 6, wherein the width of the silver-rich phase and the copper-rich phase is 0.1 μm or more and 5.0 μm or less in a cross-sectional view of the metal layer. [Section 8] 8. The wiring board according to any one of items 1 to 7, wherein, in a cross-sectional view of the metal layer, the aspect ratio of the copper-rich phase is in a range of 1:1 to 1:50. [Section 9] Item 9. The wiring board according to any one of items 1 to 8, wherein the metal layer includes at least one selected from titanium nitride and aluminum nitride. [Section 10] 10. The wiring board according to item 9, wherein in a cross-sectional view of the metal layer, an area of ​​the silver-rich phase and the copper-rich phase is 50% or more of an area of ​​the cross section. [Section 11] Item 11. The wiring board according to any one of items 1 to 10, wherein, in a cross-sectional view of the metal layer, an area of ​​the silver-rich phase is larger than an area of ​​the copper-rich phase. [Section 12] Item 12. The wiring board according to any one of items 1 to 11, wherein the ceramic substrate is a nitride-based ceramic substrate. [Section 13] Item 14. The wiring board according to any one of items 1 to 13, wherein the ceramic substrate is an aluminum nitride or silicon nitride substrate. [Section 14] A ceramic substrate; a metal layer including silver and copper, the metal layer being disposed in contact with the ceramic substrate; The surface roughness (Ra) of the metal layer is 60 μm or less, The surface of the metal layer is not polished. Wiring board. [Section 15] The wiring board according to at least one of items 1 to 14, a semiconductor element disposed on the metal layer. [Section 16] Providing a ceramic substrate; disposing a conductive paste layer containing silver and copper so as to contact the ceramic substrate; heating the ceramic substrate on which the conductive paste layer is disposed; cooling the heated ceramic substrate; and Including, In the heating of the ceramic substrate, the maximum temperature is 700°C or more and 900°C or less; In the step of cooling the ceramic substrate, the cooling rate to 400° C. is 3.0° C. / min or more. [Section 17] Item 17. The method for manufacturing a wiring board according to item 16, wherein the maximum temperature in heating the ceramic substrate is 800° C. or higher and 860° C. or lower. [Section 18] Item 18. The method for producing a wiring board according to item 16 or 17, wherein the cooling rate of the ceramic substrate is 7.0° C. / min or more. [Section 19] Item 19. The method for producing a wiring board according to any one of items 16 to 18, wherein the cooling rate of the ceramic substrate is 10° C. / min or less. [Section 20] 20. The method for manufacturing a wiring board according to any one of items 16 to 19, wherein, in heating the ceramic substrate, a heating time at the maximum temperature is 10 minutes or more and 1.0 hour or less. [Section 21] In the heating and cooling of the ceramic substrate, -2 21. The method for producing a wiring board according to any one of items 16 to 20, wherein heating and cooling are performed under a pressure of 300 Pa or more. [Section 22] Item 22. The method for manufacturing a wiring board according to any one of items 16 to 21, wherein the heating and cooling of the ceramic substrate are performed under an argon atmosphere. [Explanation of symbols]

[0099] 1...Wiring board 10...Ceramic substrate 11...First surface, 12...Second surface, 13...First plane part, 14...First arrangement part 20: metal layer, 21: silver-rich phase, 22: copper-rich phase 23: Phase derived from active metal, 24: Phase derived from inorganic filler 31...conductor paste layer, 40: light emitting element, 41: element electrode, 42: light-transmitting member, 43: covering member 44...conductive member, 100...light emitting device

Claims

1. A ceramic substrate; a metal layer including silver and copper, the metal layer being disposed in contact with the ceramic substrate; A wiring board, wherein the metal layer has a lamellar structure of a silver-rich phase and a copper-rich phase in a cross-sectional view.

2. The wiring board according to claim 1 , wherein the surface roughness (Ra) of the metal layer is 60 μm or less.

3. 2. The wiring board according to claim 1, wherein the silver content in the silver-rich phase with respect to the total of silver and copper is 91.2% by weight or more and 94.0% by weight or less.

4. 2. The wiring board according to claim 1, wherein the content of copper in the silver-rich phase with respect to the total of silver and copper is 6.0% by weight or more and 8.8% by weight or less.

5. 2. The wiring board according to claim 1, wherein the content of silver in the copper-rich phase with respect to the total of silver and copper is 7.4% by weight or more and 8.0% by weight or less.

6. 2. The wiring board according to claim 1, wherein the copper content in the copper-rich phase is 92.0% by weight or more and 92.6% by weight or less with respect to the total of silver and copper.

7. 2 . The wiring board according to claim 1 , wherein the width of the silver-rich phase and the copper-rich phase is 0.1 μm or more and 5.0 μm or less in a cross-sectional view of the metal layer.

8. 2. The wiring board according to claim 1, wherein the aspect ratio of the copper-rich phase in a cross-sectional view of the metal layer is in the range of 1:1 to 1:

50.

9. The wiring board according to claim 1 , wherein the metal layer includes at least one selected from the group consisting of titanium nitride and aluminum nitride.

10. 10. The wiring board according to claim 9, wherein in a cross-sectional view of the metal layer, an area of ​​the silver-rich phase and the copper-rich phase is 50% or more of an area of ​​the cross section.

11. The wiring board according to claim 1 , wherein an area of ​​the silver-rich phase is larger than an area of ​​the copper-rich phase in a cross-sectional view of the metal layer.

12. 2. The wiring board according to claim 1, wherein the ceramic substrate is a nitride-based ceramic substrate.

13. 2. The wiring board according to claim 1, wherein the ceramic substrate is an aluminum nitride substrate or a silicon nitride substrate.

14. A ceramic substrate; a metal layer including silver and copper, the metal layer being disposed in contact with the ceramic substrate; The surface roughness (Ra) of the metal layer is 60 μm or less, The surface of the metal layer is not polished. Wiring board.

15. The wiring board according to claim 1 , a semiconductor element disposed on the metal layer.

16. Providing a ceramic substrate; disposing a conductive paste layer containing silver and copper so as to contact the ceramic substrate; heating the ceramic substrate on which the conductive paste layer is disposed; cooling the heated ceramic substrate; and Including, In heating the ceramic substrate, the maximum temperature is 700° C. or more and 900° C. or less; In the step of cooling the ceramic substrate, the cooling rate to 400° C. is 3.0° C. / min or more.

17. The method for manufacturing a wiring board according to claim 16, wherein the maximum temperature in heating the ceramic substrate is 800° C. or higher and 860° C. or lower.

18. The method for manufacturing a wiring board according to claim 16, wherein the cooling rate of the ceramic substrate is 7.0° C. / min or more.

19. The method for manufacturing a wiring board according to claim 16, wherein the cooling rate of the ceramic substrate is 10° C. / min or less.

20. The method for manufacturing a wiring board according to claim 16, wherein in heating the ceramic substrate, a heating time at the maximum temperature is from 10 minutes to 1.0 hour.

21. In the heating and cooling of the ceramic substrate, －２ The method for manufacturing a wiring board according to claim 16, wherein the heating and cooling are performed under a pressure of from 0.1 Pa to 300 Pa.

22. 17. The method for manufacturing a wiring board according to claim 16, wherein the steps of heating the ceramic substrate and cooling the ceramic substrate are performed in an argon atmosphere.

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