Inner lead structure of flexible substrate

Abstract

To provide an inner lead structure of a flexible substrate.SOLUTION: An inner lead structure includes a flexible circuit board 110, a circuit layer 120 and a dummy lead layer 130. A chip mounting area 111a on the flexible circuit board 110 is used to mount a chip C. A plurality of conductive elements B of the chip C is disposed at a plurality of conductive connection points 111d on the chip mounting area 111a. The circuit layer 120 includes a plurality of inner leads 121. A connection end 121a of each of the inner leads 121 is located at one of the conductive connection points 111d and electrically connected to one of the conductive elements B. A space S is provided between the adjacent two inner leads 121. At least one of first dummy leads 131 of the dummy lead layer 130 is disposed in a space S having a distance greater than 50 μm. The space S is divided into a plurality of spaces S having distances less than 50 μm.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a flexible circuit board, and more particularly to an inner-lead structure of a flexible circuit board. [Background technology]

[0002] A flexible circuit board is a circuit board having flexibility, and the flexible circuit board has elasticity during mounting, and is becoming more and more applicable to current electronic products that are seeking to be lightweight and thin. A typical flexible circuit board has a flexible substrate and a patterned circuit located on the flexible substrate, the flexible substrate includes a chip mounting area for mounting a chip, and a partial patterned circuit is extended to connect to a plurality of bumps of the chip in the chip mounting area, and has a signal transmission function. Summary of the Invention [Problem to be solved by the invention]

[0003] The patterned circuit that is partially extended to the chip mounting area is called an inner lead, and the main purpose of the inner lead is to electrically connect the chip to the remaining patterned circuit. Since the spacing between the bumps on the chip is determined according to their function, the spacing between the bumps is not uniform and the distribution of spacing between the inner leads is also inconsistent.

[0004] The patterned circuit on the flexible substrate is formed by wet etching, which etches the metal layer covering the unpatterned photoresist with a flowing etchant to leave the metal layer covered by the patterned photoresist. Therefore, if the distribution of the gaps between the inner leads is inconsistent, the flow speed of the etchant becomes non-uniform due to the difference in the size of the channel space of the patterned photoresist, and the etching degree of the metal layer becomes non-uniform due to the non-uniform flow speed of the etchant, and the distribution of the width of the inner leads becomes non-uniform, and the cross section of the inner lead with a large gap due to the fast flow speed of the etchant is etched into a trapezoid with a narrow top and a wide bottom.

[0005] Therefore, the inventors believed that the above-mentioned drawbacks could be improved, and as a result of extensive research, they came to propose the present invention, which rationally and effectively improves the problems.

[0006] As a result of extensive research, the inventors have discovered that the above objective can be achieved by placing dummy leads between inner leads that are spaced apart widely, thereby making the space between the inner leads less than 50 μm and preventing the problem of uneven flow rate of the etching solution.

[0007] That is, the various aspects of the present invention for achieving the above object are as follows. The flexible substrate inner lead structure according to one embodiment of the present invention includes a flexible circuit substrate (110), a circuit layer (120), and a dummy lead layer (130). The flexible circuit substrate has an upper surface (111) including a chip mounting area (111a), and the chip mounting area is used to mount a chip. The chip has a plurality of conductive elements (B) mounted to a plurality of conductive connection points (111d) of the chip mounting area, and the circuit layer is mounted on the upper surface. The circuit layer has a plurality of inner leads (121), each of which has a connection end located in the chip mounting area, each of which is mounted to each of the conductive connection points and electrically connected to each of the conductive elements. There is a space (S) between two adjacent inner leads (121), and the distance between the partial spaces is greater than 50 μm, and the distance between the partial spaces is not greater than 50 μm. The dummy lead layer is disposed on the upper surface and has a plurality of first dummy leads (131), all of the first dummy leads are not electrically connected to any one of the conductive elements, at least one of the first dummy leads is disposed in the space having an interval greater than 50 μm, and the space is divided into a plurality of spaces having an interval not greater than 50 μm. Of the total number of the spaces, the proportion of the number of surplus spaces having no first dummy leads and having an interval greater than 50 μm is 0.5% or less. Effect of the Invention

[0008] As described above, the present invention has the following advantages. According to the present invention, by installing at least one first dummy lead in a space with a spacing greater than 50 μm, the space is divided into a plurality of spaces with a spacing not greater than 50 μm, and the proportion of surplus spaces where no first dummy lead is installed and with a spacing greater than 50 μm in the total number of spaces is 0.5% or less, thereby reducing the problem of the flow rate of the etching solution becoming faster in spaces with large spacing and preventing the inner lead from being etched into a trapezoid.

[0009] Other objects, configurations and effects of the present invention will become apparent from the following detailed description of the preferred embodiments of the present invention. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing an inner lead structure of a flexible substrate according to an embodiment of the present invention; [Diagram 2] 1 is a cross-sectional view showing an inner lead structure of a flexible substrate according to an embodiment of the present invention. [Diagram 3] 1 is a partially enlarged view showing an inner lead structure of a flexible substrate according to a first embodiment of the present invention. [Figure 4] 1 is a partial cross-sectional view showing an inner lead structure of a flexible substrate according to a first embodiment of the present invention. [Diagram 5] FIG. 11 is a partially enlarged view showing an inner lead structure of a flexible substrate according to a second embodiment of the present invention. [Figure 6] FIG. 11 is a partially enlarged view showing an inner lead structure of a flexible substrate according to a third embodiment of the present invention. [Figure 7] FIG. 11 is a partially enlarged view showing an inner lead structure of a flexible substrate according to a fourth embodiment of the present invention. [Figure 8] FIG. 11 is a partial cross-sectional view showing an inner lead structure of a flexible substrate according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments of the present invention will be described in detail. However, the present invention is not limited to these, and various modifications are possible within the scope of the description. The technical scope of the present invention also includes embodiments obtained by appropriately combining the technical means disclosed in the different embodiments.

[0012] First, an embodiment of an inner lead structure for a flexible substrate according to the present invention will be described with reference to FIGS.

[0013] FIG. 1 is a plan view showing an inner lead structure 100 of a flexible substrate according to an embodiment of the present invention. The inner lead structure 100 of a flexible substrate includes a flexible circuit substrate 110, a circuit layer 120, and a dummy lead layer 130. The flexible circuit substrate 110 has an upper surface 111. The circuit layer 120 and the dummy lead layer 130 are both disposed on the upper surface 111. In the drawing, the circuit layer 120 and the dummy lead layer 130 are all shown as blank, but in reality, the circuit layer 120 and the dummy lead layer 130 are composed of a plurality of fine circuits. The dummy lead layers 130 located on both sides of the circuit layer 120 do not have a signal transmission function, but are used to increase the strength of the flexible circuit substrate 110 and to perform different processes on the flexible circuit substrate 110.

[0014] Please also refer to FIG. 1. FIG. 2 is a cross-sectional view showing an inner lead structure 100 of a flexible substrate according to an embodiment of the present invention. The upper surface 111 of the flexible circuit substrate 110 is divided into a chip mounting area 111a, a transmission circuit arrangement area 111b, and an outer lead arrangement area 111c. The chip mounting area 111a is located in a position close to the center of the upper surface 111. The outer lead arrangement area 111c is located on the upper and lower two edges of the upper surface 111. The transmission circuit arrangement area 111b is located between the chip mounting area 111a and the outer lead arrangement area 111c. The chip mounting area 111a is used to mount a chip C having a plurality of conductive elements B. The conductive elements B are installed at a plurality of conductive connection points 111d of the chip mounting area 111a. The conductive elements B are bump parts or solder balls formed in advance on the chip C, but the present invention is not limited thereto.

[0015] The circuit layer 120 has a plurality of inner leads 121, a plurality of transmission circuits 122, and a plurality of outer leads 123, the inner leads 121 being adjacent to the chip mounting area 111a and partially extending to the chip mounting area 111a, the outer leads 123 being located in the outer lead arrangement area 111c, and the transmission circuits 122 being located in the transmission circuit arrangement area 111b. Both ends of each of the transmission circuits 122 are connected to each of the inner leads 121 and the outer leads 123, respectively, and are used to electrically connect each of the inner leads 121 and each of the outer leads 123. The inner leads 121, the transmission circuits 122, and the outer leads 123 are formed by subjecting copper foil electroplated on the upper surface 111 to patterned etching. <First Example>

[0016] Please also refer to FIG. 2. FIG. 3 is a partially enlarged view showing the chip mounting area 111a of the inner lead structure 100 of the flexible substrate according to the first embodiment of the present invention. The area above the horizontal dashed line in the figure is the chip mounting area 111a for mounting the chip. The area below the horizontal dashed line is the transmission circuit arrangement area 111b. The part where the inner lead 121 extends to the chip mounting area 111a is defined as the connection end 121a of each inner lead 121. Each connection end 121a is provided at each of the conductive connection points 111d, and is electrically connected to each of the conductive elements B when the chip C is mounted on the chip mounting area 111a. Each of the conductive elements B of the chip C is an alloy of tin and another metal, and when the chip C is mounted on the chip mounting area 111a by a thermocompression bonding method, each connection end 121a of the inner lead 121 and each of the conductive elements B are eutectic-bonded, and the chip C is electrically connected to the circuit layer 120. In this embodiment, there is a space S between two adjacent inner leads 121, and the interval of the partial space S is greater than 50 μm and the interval of the partial space S is not greater than 50 μm based on the difference in the interval between each of the conductive elements B of the chip C. Although only one space with an interval greater than 50 μm is illustrated in FIG. 3, in reality, all chip mounting areas 111a have multiple spaces with an interval greater than 50 μm due to the layout design of the conductive elements B of the chip C, and FIG. 3 only shows a partial schematic diagram thereof.

[0017] 3, the dummy lead layer 130 further includes a plurality of first dummy leads 131, all of which are not electrically connected to any one of the conductive elements B, and at least one first dummy lead 131 is provided in a space S having an interval greater than 50 μm, and the space S is divided into a plurality of spaces S having an interval not greater than 50 μm. Of the total number of spaces S, the proportion of surplus spaces S in which no first dummy lead 131 is provided and which have an interval greater than 50 μm is 0.5% or less. The ratio of the maximum interval to the minimum interval in the spaces S is less than 6, so that the spaces between the circuits adjacent to the chip mounting area 111a are similar.

[0018] Since the inner lead 121, the transmission circuit 122, and the outer lead 123 are formed by wet etching, in this embodiment, the first dummy lead 131 is disposed in a space S with an interval larger than 50 μm, and the ratio of the intervals S between the inner leads 121 that are not larger than 50 μm is 99.5%, so that the flow speed of the etching solution passing through the spaces S between the inner leads 121 during the etching process is similar, and the problem of uneven circuit width due to differences in the etching degree of each inner lead 121 is prevented. In addition, since the intervals of the spaces S between the inner leads 121 are not larger than 50 μm, the flow speed of the etching solution passing through the spaces S is relaxed, and the cross sections of the inner lead 121 and the first dummy lead 131 are both rectangular, preventing the cross section of the inner lead 121 from being etched into a trapezoid narrow at the top and wide at the bottom due to the flow speed of the etching solution being too fast.

[0019] 4, since wet etching is isotropic etching, the cross sections of the inner lead 121 and the first dummy lead 131 that are actually formed are not geometrically rectangular, but have an outer contour that approximates a rectangle. The definition of a rectangle in this specification refers to the fact that each of the inner leads 121 has a first exposed surface 121b and a first connecting surface 121c, the first connecting surface 121c is bonded to the upper surface 111 of the flexible circuit board 110, the difference between the width of the first connecting surface 121c and the width of the first exposed surface 121b is less than 2 μm, and similarly, the difference between the widths of the connecting surface and the exposed surface of each of the first dummy leads 131 is also less than 2 μm, and the outer contour approximates a rectangle.

[0020] Preferably, as shown in FIG. 3, the width W of each of the first dummy leads 131 is in the range of 6 to 100 μm, and the length L of each of the first dummy leads 131 is greater than 70 μm, to prevent each of the first dummy leads 131 from affecting the fluidity of the underfill below the subsequent chip, and the placement of each of the first dummy leads 131 prevents excessive stress concentration in the flexible circuit board 110. <Second Example>

[0021] 5 is a partially enlarged view showing an inner lead structure 100 of a flexible substrate according to a second embodiment of the present invention. In this embodiment, each of the first dummy leads 131 has a first line segment 131a and a second line segment 131b, and the first line segment 131a and the second line segment 131b are parallel to each of the inner leads 121. Between the first line segment 131a and the second line segment 131b, there is a setback space BS, and the width of the setback space BS is in the range of 10 to 30 μm. In this embodiment, each of the first dummy leads 131 is divided into two separate line segments, and the setback space BS between the two line segments allows the underfill to pass through, further preventing each of the first dummy leads 131 from affecting the flow of the underfill. <Third Example>

[0022] 6 is a partially enlarged view showing an inner lead structure 100 of a flexible circuit board according to a third embodiment of the present invention. Since the intervals of the spaces S are larger than 50 μm, in this embodiment, a plurality of first dummy leads 131 are provided in a single space S with an interval larger than 50 μm, and the space S is divided into a plurality of spaces S with an interval not larger than 50 μm. In one space S with an interval larger than 50 μm, a plurality of first dummy leads 131 are provided to shorten the width of each of the first dummy leads 131, thereby preventing the occurrence of a problem in which the stress of the flexible circuit board 110 is excessively concentrated due to the wide first dummy leads 131, causing peeling during thermocompression bonding of the chip C. <Fourth Example>

[0023] 7 shows a fourth embodiment of the present invention, in which the dummy lead layer 130 has at least one second dummy lead 132, and all of the second dummy leads 132 are not electrically connected to any one of the conductive elements B. The second dummy lead 132 is disposed in a space S having an interval greater than 50 μm. The second dummy lead 132 divides the space S into a space S having an interval not greater than 50 μm and a space S having an interval greater than 50 μm. In this embodiment, due to limitations in the circuit layout, it is not possible to divide the space S having an interval greater than 50 μm into a plurality of spaces S having an interval not greater than 50 μm by disposing one or more first dummy leads 131, so the second dummy lead 132 is disposed in the space S as a sacrificial circuit to protect the inner lead 121. Referring also to Figure 8, in the wet etching process, the flow rate of the etching liquid is fast in the space S divided by the second dummy lead 132 and the interval between them is greater than 50 μm, but the flow rate of the etching liquid is slow in the space S divided by the second dummy lead 132 and the interval between them is not greater than 50 μm. Therefore, due to the fast flow rate of the etching liquid, the cross section of the second dummy lead 132 is etched into a trapezoid that is narrow at the top and wide at the bottom. However, since the inner lead 121 adjacent to the second dummy lead 132 is the second dummy lead 132 and is adjacent to the space S and the interval between them is not greater than 50 μm, the flow rate of the etching liquid that etches the inner lead 121 is not too fast, and the cross section of the inner lead 121 adjacent to the second dummy lead 132 is rectangular.

[0024] In this embodiment, the second dummy lead 132 is a sacrificial circuit and is etched into a trapezoid, so that the second dummy lead 132 has a second exposed surface 132a and a second connecting surface 132b, the second connecting surface 132b is bonded to the upper surface 111 of the flexible circuit board 110, the width of the second connecting surface 132b is larger than the width of the second exposed surface 132a, and the difference between the width of the second connecting surface 132b and the width of the second exposed surface 132a is more than 2 μm.

[0025] 7 and 8, since each space S is located between two inner leads 121, when there is only one second dummy lead 132 in the space S, the inner lead 121 adjacent to the second dummy lead 132 is protected by the second dummy lead 132, but the inner lead 121 away from the other second dummy lead 132 is affected by the etching solution with a high flow rate. For this reason, in this embodiment, preferably, the dummy lead layer 130 has at least two second dummy leads 132, and the two second dummy leads 132 are disposed in the same space S with an interval of more than 50 μm, and the space S is divided by the two second dummy leads 132 into a plurality of spaces S with an interval of not more than 50 μm and a space S with an interval of more than 50 μm. Each space S with an interval of not more than 50 μm is located between each second dummy lead 132 and each inner lead 121, and the space S with an interval of more than 50 μm is located between the second dummy leads 132. In this embodiment, the second dummy lead 132 divides the space S, so that the inner leads 121 that are originally located on both sides of the space S are all adjacent to spaces S with an interval of no more than 50 μm, preventing them from being etched by an etching solution with a fast flow rate during etching, and preventing the cross section of the inner leads 121 from being etched into a trapezoid.

[0026] In an embodiment of the present invention, at least one first dummy lead 131 is installed in a space S with a spacing greater than 50 μm, thereby dividing the space S into a plurality of spaces S with spacing not greater than 50 μm, and the proportion of the number of surplus spaces S where no first dummy leads 131 are installed and with spacing greater than 50 μm in the total number of spaces S is set to 0.5% or less, thereby preventing the problem of the flow rate of the etching solution becoming faster in spaces with large spacing and further preventing the situation in which the inner lead 121 is etched into a trapezoid.

[0027] As described above, the present invention is not limited to the above-described embodiment, and can be embodied in various forms without departing from the spirit and scope of the present invention. [Explanation of symbols]

[0028] 100 Inner lead structure of flexible substrate 110 Flexible Circuit Board 111 Top surface 111a Chip mounting area 111b Transmission circuit layout area 111c Outer lead placement area 111d Conductive connection point 120 circuit layers 121 Inner Lead 121a Connection end 121b 1st exposed surface 121c First connection surface 122 Transmission Lines 123 Outer Lead 130 Dummy lead layer 131 First Dummy Lead 131a 1st line 131b 2nd line 132 Second Dummy Lead 132a 2nd exposed surface 132b Second connection surface C-chip B Conductive element S Space BS retreat space W width L Length

Claims

1. a flexible circuit board (110) having a top surface (111) including a chip mounting area (111a), the chip mounting area being used to mount a chip (C), the chip having a plurality of conductive elements (B), the conductive elements being attached to a plurality of conductive connection points (111d) of the chip mounting area; a circuit layer (120) disposed on the upper surface, the circuit layer having a plurality of inner leads (121), each connection end (121a) of the inner leads being located in the chip mounting area, each connection end being disposed at each conductive connection point and electrically connected to each conductive element, a space (S) being between two adjacent inner leads (121), a distance between the partial spaces being greater than 50 μm, and a distance between the partial spaces being less than 50 μm; and a dummy lead layer (130) disposed on the upper surface, the dummy lead layer having a plurality of first dummy leads (131), all of which are electrically unconnected to any one of the conductive elements, at least one of the first dummy leads being disposed in the space having a spacing greater than 50 μm, the space being divided into a plurality of spaces having spacing smaller than 50 μm, and the first dummy leads not being disposed in the total number of the spaces, and the proportion of the number of surplus spaces having spacing greater than 50 μm being 0.5% or less.

2. 2. The inner lead structure of a flexible substrate as described in claim 1, wherein the dummy lead layer has at least one second dummy lead (132), all of the second dummy leads being electrically unconnected to any one of the conductive elements, the second dummy lead being installed in the space where the spacing is greater than 50 μm, the space being divided by the second dummy lead into the space where the spacing is less than 50 μm and the space where the spacing is greater than 50 μm, and the cross section of the second dummy lead is trapezoidal.

3. The dummy lead layer has at least two of the second dummy leads, the two second dummy leads are installed in the same space with the spacing greater than 50 μm, the two second dummy leads are divided into a plurality of spaces with the spacing smaller than 50 μm and a space with the spacing greater than 50 μm, each space with the spacing smaller than 50 μm is located between each of the second dummy leads and each of the inner leads, and the space with the spacing greater than 50 μm is located between the second dummy leads.

4. The inner lead structure of a flexible substrate as described in claim 2 or 3, characterized in that each of the inner leads has a first exposed surface (121b) and a first connecting surface (121c), the first connecting surface is bonded to the upper surface of the flexible circuit substrate, and the difference between the width of the first connecting surface and the width of the first exposed surface is less than 2 μm.

5. 5. The inner lead structure of a flexible substrate as described in claim 4, characterized in that each of the second dummy leads has a second exposed surface (132a) and a second connecting surface (132b), the second connecting surface is bonded to the upper surface of the flexible circuit substrate, the width of the second connecting surface is larger than the width of the second exposed surface, and the difference between the width of the second connecting surface and the width of the second exposed surface is more than 2 μm.

6. 4. The inner lead structure of a flexible substrate according to claim 2, wherein each of the inner leads of the adjacent second dummy leads has a rectangular cross section.

7. 2. The inner lead structure of a flexible printed circuit board according to claim 1, wherein a ratio of the maximum spacing to the minimum spacing of the spaces is less than 6.

8. 2. The flexible substrate inner lead structure according to claim 1, wherein the width of each of the first dummy leads is in the range of 6 to 100 μm, and the length (L) of each of the first dummy leads is greater than 70 μm.

9. 2. The inner lead structure of a flexible substrate as described in claim 1, wherein each of the first dummy leads has a first line segment (131a) and a second line segment (131b), the first line segment and the second line segment are parallel to each of the inner leads, and a setback space (BS) is provided between the first line segment and the second line segment, and the width of the setback space is in the range of 10 to 30 μm.

10. 2. The inner lead structure of claim 1, wherein the first dummy leads are disposed in the space having a spacing greater than 50 μm, and the space is divided into a plurality of spaces having a spacing smaller than 50 μm.

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