Memory system and control method

Abstract

To provide a memory system capable of accessing a non-volatile memory without a die contention.SOLUTION: A controller of a memory system classifies a plurality of non-volatile memory dies into a first die group and a second die group so that each of the plurality of non-volatile memory dies connected to a plurality of channels belongs to only one die group. When the controller receives a first write command specifying a first name space from a host, the controller writes first data to be written into the first name space into a first write destination block selected from the first die group. When the controller receives a second write command specifying a second name space from the host, the controller writes second data to be written into the second name space into a second write destination block selected from the second die group.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The present invention relates to a technique for controlling a non-volatile memory. [Background technology]

[0002] In recent years, memory systems equipped with nonvolatile memories have become widespread.

[0003] One such memory system is the solid-state drive (SSD) based on NAND flash technology. SSDs are used as storage for various computers due to their low power consumption and high performance.

[0004] Typically, SSDs are equipped with many non-volatile memory dies to increase capacity. Each non-volatile memory die can operate independently, so each non-volatile memory can function as a unit of parallel processing. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2013 / 019057 Summary of the Invention [Problem to be solved by the invention]

[0006] However, operations on a single non-volatile memory die are usually not executed in parallel but are executed sequentially. Therefore, if a read request occurs to a non-volatile memory die during a write operation (die contention), the response time of the read request (read latency) may become very long.

[0007] Therefore, a new feature needs to be implemented to enable the host to access the SSD without die contention.

[0008] An object of the present invention is to provide a memory system and a control method capable of accessing a non-volatile memory without die contention. [Means for solving the problem]

[0009] According to an embodiment, a memory system connectable to a host includes a plurality of channels, a non-volatile memory including a plurality of non-volatile memory dies connected to the plurality of channels, each non-volatile memory die including a plurality of blocks, and a controller connected to the plurality of non-volatile memory dies via the plurality of channels, configured to control the plurality of non-volatile memory dies. The controller assigns a plurality of namespaces to the memory system, including at least a first namespace and a second namespace. Each of the plurality of namespaces includes a plurality of logical block addresses (LBAs) starting from 0. The controller classifies the plurality of non-volatile memory dies into a first die group and a second die group such that each of the plurality of non-volatile memory dies belongs to only one die group. When the controller receives a first write command from the host specifying the first namespace corresponding to the first die group, the controller writes first data to be written to the first namespace to a first destination block selected from the first die group. When the controller receives a second write command from the host specifying the second namespace corresponding to the second die group, the controller writes second data to be written to the second namespace to a second destination block selected from the second die group. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. [Diagram 2]FIG. 2 is a block diagram showing multiple non-volatile memory sets (NVM sets), each spanning multiple channels, obtained by sorting multiple NAND flash memory dies in the memory system of the embodiment. [Diagram 3] 3 is a block diagram showing the relationship between the block management corresponding to each NVM set of FIG. 2 and one or more regions (namespaces) corresponding to each NVM set. [Figure 4] FIG. 2 is a diagram for explaining host write / garbage collection operations for isolated NVM sets performed by the memory system of the embodiment. [Diagram 5] 11A and 11B are diagrams for explaining host write / garbage collection operations for a shared NVM set performed by the memory system of the embodiment. [Figure 6] FIG. 11 is a block diagram showing multiple NVM sets, each including a collection of NAND flash memory dies connected to the same channel, obtained by sorting multiple NAND flash memory dies in the memory system of the embodiment. [Figure 7] 7 is a block diagram showing the relationship between the block management corresponding to each NVM set of FIG. 6 and one or more regions (namespaces) corresponding to each NVM set. [Figure 8] FIG. 2 is a diagram illustrating a flash memory package that is applied to the memory system of the embodiment. [Figure 9] 9 is a cross-sectional view showing the structure of the flash memory package in FIG. 8. [Figure 10] A diagram showing the relationship between multiple NVM sets, each including a collection of NAND flash memory dies connected to the same channel, and one or more flash memory packages used as these NVM sets. [Figure 11] FIG. 13 is a diagram showing a portion of a garbage collection operation for a certain NVM subset performed by the memory system of the embodiment. [Figure 12] A figure showing the remaining part of the garbage collection operation for a certain NVM subset performed by the memory system of the same embodiment. [Figure 13] A figure showing the remaining part of the garbage collection operation for a certain NVM subset performed by the memory system of the same embodiment. [Figure 14] FIG. 2 is a diagram showing an NVM set-to-set copy operation executed by the memory system of the embodiment. [Figure 15] 15 is a diagram showing the relationship between the contents of the address translation table before the inter-NVM set copy operation of FIG. 14 and the contents of the address translation table after the inter-NVM set copy operation. [Figure 16] FIG. 2 is a diagram showing a portion of an NVM set-to-set copy operation executed by the memory system of the embodiment. [Figure 17] FIG. 13 is a diagram showing the remaining part of the NVM set-to-set copy operation executed by the memory system of the embodiment. [Figure 18] FIG. 13 is a diagram showing the remaining portion of the NVM set-to-set copy operation executed by the memory system of the embodiment. [Figure 19] 1 is a diagram for explaining an overview of an NVM set exchange operation executed by the memory system of the embodiment. [Figure 20] A diagram illustrating the host write / garbage collection operations performed for two NVM sets prior to an NVM set exchange operation. [Figure 21] A diagram to explain the host write / garbage collection operations performed between two NVM sets for an NVM set exchange operation. [Figure 22] 11 is a diagram showing an overview of a new NVM set creation operation executed by the memory system of the embodiment. [Diagram 23] A diagram for explaining the host write / garbage collection operations performed to create a new NVM set. [Figure 24] 11 is a diagram showing a part of a new NVM set creation operation executed by the memory system of the embodiment. [Diagram 25] FIG. 13 is a diagram showing the remaining part of the new NVM set creation operation executed by the memory system of the embodiment. [Figure 26] 13 is a diagram showing the remaining part of the new NVM set creation operation executed by the memory system of the embodiment. FIG. [Figure 27] FIG. 2 is a diagram showing an overview of an NVM set combining operation executed by the memory system of the embodiment. [Figure 28] A diagram illustrating host write / garbage collection operations performed for NVM set merging. [Figure 29] 11 is a flowchart showing a part of a procedure of a data write / read operation executed by the memory system of the embodiment. [Diagram 30] 11 is a flowchart showing the remaining steps of the data write / read operation performed by the memory system of the embodiment. [Diagram 31] 11 is a flowchart showing the procedure of a garbage collection operation executed for each NVM subset by the memory system of the embodiment. [Diagram 32] 11 is a flowchart showing the procedure of an NVM inter-set copy operation executed by the memory system of the embodiment. [Diagram 33] 11 is a flowchart showing another procedure of the NVM inter-set copy operation executed by the memory system of the embodiment. [Diagram 34] 11 is a flowchart showing the procedure of a new NVM set creation operation executed by the memory system of the embodiment. [Diagram 35] 11 is a flowchart showing another procedure of the new NVM set creation operation executed by the memory system of the embodiment. [Diagram 36] FIG. 2 is a block diagram showing an example of the configuration of a host applied to the memory system of the embodiment. [Figure 37] FIG. 2 is a block diagram showing an example of the configuration of a computer including the memory system and a host according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment will be described with reference to the drawings. First, with reference to FIG. 1, a configuration of an information processing system 1 including a memory system according to an embodiment will be described.

[0012] The memory system is a semiconductor storage device configured to write data to and read data from a non-volatile memory, and is implemented, for example, as a solid-state drive (SSD) 3 based on NAND flash technology.

[0013] The information processing system 1 includes a host (host device) 2 and an SSD 3. The host 2 is an information processing device such as a server or a personal computer. A typical example of a server that functions as the host 2 is a server in a data center.

[0014] In the case where the host 2 is realized by a server in a data center, the host (server) 2 may be connected to a number of end user terminals 51 via a network 50. The host 2 may provide various services to the end user terminals 51. A number of virtual machines may be executed on a physical server functioning as the host (server) 2. The virtual machines may function as virtual servers configured to provide various services to corresponding clients (end user terminals 51).

[0015] The SSD 3 can be used as the main storage of an information processing device (computing device) functioning as the host 2. The SSD 3 may be built into the information processing device, or may be connected to the information processing device via a cable or a network.

[0016] As an interface for interconnecting the host 2 and the SSD 3, SCSI, Serial Attached SCSI (SAS), ATA, Serial ATA (SATA), PCI Express (PCIe), Ethernet (registered trademark), Fibre channel, NVM Express (NVMe) (registered trademark), etc. may be used.

[0017] The SSD 3 includes a controller 4 and a non-volatile memory (NAND flash memory) 5. The SSD 3 may also include a random access memory, for example, a DRAM 6.

[0018] The NAND flash memory 5 includes a memory cell array including a plurality of memory cells arranged in a matrix. The NAND flash memory 5 may be a two-dimensional NAND flash memory or a three-dimensional NAND flash memory.

[0019] The memory cell array of the NAND flash memory 5 includes a plurality of blocks B0 to Bm-1. Each of the blocks B0 to Bm-1 is organized into a number of pages (here, pages P0 to Pn-1). The blocks B0 to Bm-1 function as an erase unit. A block may also be referred to as an "erase block" or a "physical block." Each of the pages P0 to Pn-1 includes a plurality of memory cells connected to the same word line. The pages P0 to Pn-1 are the units of data write and read operations.

[0020] The controller 4 is electrically connected to the NAND flash memory 5 via a NAND interface 13, such as a Toggle or an Open NAND Flash Interface (ONFI), and a plurality of channels (Ch). The NAND interface 13 functions as a NAND control circuit configured to control the NAND flash memory 5.

[0021] As shown in FIG. 2, the NAND flash memory 5 includes a plurality of NAND flash memory dies (shown as "NAND die" in FIG. 2). Each NAND flash memory die is a non-volatile memory die including a memory cell array including a plurality of blocks and a peripheral circuit that controls the memory cell array. Each NAND flash memory die can operate independently. Thus, the NAND flash memory die functions as a single parallel operating unit. The NAND flash memory die is also called a "NAND flash memory chip."

[0022] 2 illustrates a case where a plurality of channels Ch0, Ch1, Ch2, ... ChN are connected to the NAND interface 13, and the same number (e.g., K dies per channel, where K is an integer equal to or greater than 2) of NAND flash memory dies are connected to each of these channels Ch0, Ch1, Ch2, ... ChN. Each channel includes a communication line (memory bus) for communicating with the corresponding NAND flash memory die.

[0023] In Fig. 2, the NAND flash memory dies 600, 601, 602 to 606 are connected to a channel Ch0. The NAND flash memory dies 610, 611, 612 to 616 are connected to a channel Ch1. The NAND flash memory dies 620, 621, 622 to 626 are connected to a channel Ch2. Similarly, the NAND flash memory dies 640, 641, 642 to 646 are connected to a channel ChN.

[0024] The controller 4 controls the NAND flash memory 5 via channels Ch0, Ch1, Ch2, ..., ChN. The controller 4 can drive channels Ch0, Ch1, Ch2, ..., ChN simultaneously. That is, the NAND interface 13 includes N NAND control circuits corresponding to the channels Ch0, Ch1, Ch2, ..., ChN, respectively. The controller 4 can drive channels Ch0, Ch1, Ch2, ..., ChN independently of each other by using these NAND control circuits.

[0025] In this embodiment, the controller 4 classifies the K×N NAND flash memory dies 600-646 into a plurality of die groups such that each NAND flash memory die belongs to only one die group. Hereinafter, the die groups are referred to as "non-volatile memory subsets (NVM sets)."

[0026] 2, each NVM set spans multiple channels Ch0, Ch1, Ch2, ... ChN. For example, NVM set 60 includes NAND flash memory dies 600, 610, 620, ... 640 connected to channels Ch0, Ch1, Ch2, ... ChN, respectively. NVM set 61 includes NAND flash memory dies 601, 611, 621, ... 641 connected to channels Ch0, Ch1, Ch2, ... ChN, respectively. NVM set 62 includes NAND flash memory dies 602, 603, ... 605, 606 connected to channel Ch0, NAND flash memory dies 612, 613, ... 615, 616 connected to channel Ch1, NAND flash memory dies 622, 623, ... 625, 626 connected to channel Ch2, and NAND flash memory dies 642, 643, ... 645, 646 connected to channel ChN.

[0027] 2, the K×N NAND flash memory dies 600-646 are classified into a number of NVM sets each spanning a number of channels. In each NVM set, data write / read operations can be performed simultaneously on a maximum of N NAND flash memory dies.

[0028] Each of the multiple NVM sets can be associated with multiple areas that can be specified by the host 2. These multiple areas are logical areas that can be accessed by the host 2. The number of areas corresponding to each NVM set may be one, or may be two or more. Furthermore, the number of areas corresponding to each NVM set may be different for each NVM set.

[0029] The controller 4 can simultaneously execute multiple I / O commands (write commands or read commands) each specifying a different area corresponding to a different NVM set without die contention. Therefore, for example, even if a read command directed to an area corresponding to NVM set 61 is received from the host 2 while a data write operation to NVM set 60 is being executed, the controller 4 can immediately execute a data read operation corresponding to this read command without waiting for the completion of this data write operation.

[0030] In the SSD 3 shown in FIG. 1, the controller 4 can also function as a flash translation layer (FTL) configured to perform data management of the NAND flash memory 5 and block management of the NAND flash memory 5.

[0031] The data management executed by this FTL includes (1) management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 5, and (2) processing for concealing read / write in page units and erase operations in block units. A logical address is an address used by the host 2 to address the SSD 3. A logical block address (LBA) is usually used as this logical address.

[0032] The management of mapping between each logical block address (LBA) and each physical address is performed using a lookup table (LUT) that functions as an address conversion table (logical-physical address conversion table). A physical address corresponding to a certain LBA indicates a physical memory location in the NAND flash memory 5 where the data of this LBA is written. The lookup table (LUT) may be loaded from the NAND flash memory 5 to the DRAM 6 when the SSD 3 is powered on. In general, the size of each lookup table is relatively large. Therefore, at least a part of each lookup table may be stored in the DRAM 6 as an address conversion table cache.

[0033] In the NAND flash memory 5, data can be written to a page only once per erase cycle. Therefore, the controller 4 writes updated data corresponding to a certain LBA to a different physical storage location, not to the physical storage location where the previous data corresponding to this LBA is stored. The controller 4 then updates the corresponding look-up table (LUT) to associate this LBA with this different physical storage location. This invalidates the previous data corresponding to this LBA.

[0034] In this embodiment, a plurality of lookup tables (LUTs) 40, 41, 42, etc. are used. Basically, these lookup tables (LUTs) 40, 41, 42, etc. correspond to a plurality of NVM sets, respectively. Each lookup table may be associated with one area or one group of garbage collections.

[0035] Each NVM set includes at least one garbage collection group. A garbage collection group includes multiple blocks and is used as a unit on which garbage collection is performed. For an NVM set that includes only one garbage collection group, only one lookup table may be used. For an NVM set that includes multiple garbage collection groups, multiple lookup tables may be used.

[0036] The controller 4 further has a multi-namespace control function. The multi-namespace control function makes it possible to assign multiple logical address spaces (LBA spaces) to the SSD 3 so as to enable one storage device to be treated as if it were multiple drives.

[0037] Each of the above-mentioned multiple areas may be realized by a namespace. Each namespace corresponds to an area in the NAND flash memory 5. A logical address range (LBA range) is assigned to each namespace. The size of the LBA range (i.e., the number of LBAs) is variable for each namespace. Each LBA range starts from LBA0. Individual namespaces are identified by their namespace identifiers.

[0038] The write command from the host 2 includes an identifier for a specific namespace, that is, a namespace ID (NSID). The controller 4 determines the area to be accessed (namespace) where the write data is to be written based on the namespace ID in the write command from the host 2. Similarly, the read command from the host 2 also includes a namespace ID corresponding to a specific namespace. The controller 4 determines the area to be accessed (namespace) where the data is to be read based on the namespace ID in the read command from the host 2.

[0039] Block management includes bad block management, wear leveling, garbage collection, and the like.

[0040] Wear leveling is an operation for equalizing wear among each block.

[0041] Garbage collection is an operation for increasing the number of free blocks to which data can be written. In the garbage collection operation, the controller 4 copies only the valid data in some blocks, in which valid data and invalid data are mixed, to another block (e.g., a free block). Here, the valid data means data that is referenced by the LUT (i.e., data that is linked to a logical address as the latest data) and that may be read by the host 2 later. The invalid data means data that is no longer likely to be read by the host 2. For example, data associated with a certain logical address is valid data, and data that is not associated with any logical address is invalid data. Then, the controller 4 maps each of the LBAs of the copied valid data to the physical address to which the valid data is copied. A block that contains only invalid data as a result of valid data being copied to another block is released as a free block. This makes it possible for this block to be reused after the erase operation is executed.

[0042] Next, the configuration of the controller 4 will be described.

[0043] The controller 4 includes a host interface 11, a CPU 12, a NAND interface 13, and a DRAM interface 14. The CPU 12, the NAND interface 13, and the DRAM interface 14 are interconnected via a bus 10.

[0044] The host interface 11 is a host interface circuit configured to execute communication with the host 2. The host interface 11 may be, for example, a PCIe controller (NVMe controller). The host interface 11 receives various commands from the host 2 (write commands, read commands, various control commands, UNMAP commands, etc.).

[0045] The write command requests the SSD 3 to write data specified by this write command. The write command may include a start LBA, a transfer length, and an ID. The ID in the write command is an identifier for uniquely identifying an area where data is to be written. This ID may be a namespace ID. The read command requests the SSD 3 to read data specified by this read command. The read command may include a start LBA, a transfer length, and an ID. The ID in the read command is an identifier for uniquely identifying an area where data is to be read. This ID may be a namespace ID.

[0046] The CPU 12 is a processor configured to control the host interface 11, the NAND interface 13, and the DRAM interface 14. In response to power-on of the SSD 3, the CPU 12 loads a control program (firmware) from the NAND flash memory 5 or a ROM (not shown) into the DRAM 6, and executes the firmware to perform various processes. The firmware may be loaded onto an SRAM (not shown) in the controller 4. For example, the CPU 12 can execute command processing for processing various commands from the host 2, in addition to the above-mentioned FTL processing. The operation of the CPU 12 is controlled by the above-mentioned firmware executed by the CPU 12. A part or all of the FTL processing and the command processing may be executed by dedicated hardware in the controller 4.

[0047] The CPU 12 can function as an NVM set control unit 21, a garbage collection (GC) operation control unit 22, an inter-NVM set copy control unit 23, a new NVM set creation control unit 24, an NVM set exchange control unit 25, and an NVM set combination unit .

[0048] The NVM set control unit 21 classifies the K×N NAND flash memory dies 600-646 into a plurality of NVM sets so that each of the K×N NAND flash memory dies 600-646 belongs to only one NVM set. The NVM set control unit 21 then executes data write / read operations for one of the plurality of NVM sets in response to an I / O command from the host 2 that specifies any one of a plurality of regions including at least one region corresponding to each NVM set. For example, in a case where the plurality of NVM sets includes a first NVM set and a second NVM set, the NVM set control unit 21 executes data write / read operations for the first NVM set in response to a first I / O command from the host 2 that specifies at least one region corresponding to the first NVM set, and executes data write / read operations for the second NVM set in response to a second I / O command from the host 2 that specifies at least one region corresponding to the second NVM set.

[0049] In addition, the NVM set control unit 21 manages free blocks in the NAND flash memory 5 (multiple NAND flash memory dies) 5 individually for each NVM set by using a plurality of free block pools corresponding to the plurality of NVM sets. A free block means a block that does not hold valid data. For example, each free block belonging to a first NVM set is managed by a first free block pool corresponding to the first NVM set, and each free block belonging to a second NVM set is managed by a second free block pool corresponding to the second NVM set. During an operation to initialize the SSD 3, the NVM set control unit 21 places all blocks belonging to the first NVM set in the first free block pool, and places all blocks belonging to the second NVM set in the second free block pool.

[0050] For each of the multiple NVM sets, the NVM set control unit 21 performs the following operations: allocate one of the free blocks in the corresponding free block pool as a block to which user data (write data from the host 2, or data to be copied for garbage collection) should be written; write the user data into the allocated block; manage the block filled with the user data by a data block pool (also called an active block pool); and return blocks that are managed by the data block pool and do not hold valid data to the corresponding free block pool.

[0051] This allows blocks arranged in a free block pool corresponding to a certain NVM set to be used only by one or more areas corresponding to this NVM set, making it possible to ensure that die contention does not occur between multiple NVM sets. Note that a data block pool refers to a pool for managing each block that belongs to a corresponding NVM set and holds valid data.

[0052] In this embodiment, two types of NVM sets can be handled: an isolated NVM set and a shared NVM set.

[0053] A separated NVM set is an NVM set that includes only one garbage collection group (only one data block pool). In other words, a free block pool corresponding to a separated NVM set is a free block pool dedicated to a single data block pool that manages each block that belongs to the NVM set and holds valid data. In a separated NVM set, a single data block pool occupies the free block pool corresponding to the separated NVM set.

[0054] A shared NVM set is an NVM set including multiple garbage collection groups (multiple data block pools). In other words, a free block pool corresponding to a shared NVM set is a free block pool shared by multiple data block pools that belong to the NVM set and manage each of the blocks that hold valid data. In a shared NVM set, multiple data block pools share the free block pool corresponding to the shared NVM set.

[0055] A garbage collection (GC) operation control unit 22 executes garbage collection independently for each of the above-mentioned garbage collection groups.

[0056] In garbage collection of a separated NVM set, that is, garbage collection of blocks in a single data block pool belonging to the separated NVM set, the GC operation control unit 22 executes the following operations: (1) assigning one of the free blocks in the free block pool corresponding to the separated NVM set as a copy destination block, (2) copying only valid data from one or more blocks included in the data block pool and containing a mixture of valid data and invalid data to the copy destination block, and (3) returning a block that contains only invalid data due to the valid data being copied to the copy destination block to the free block pool corresponding to the separated NVM set. This allows a free block created by the GC of a certain separated NVM set to be used only by one or more areas corresponding to this NVM set, making it possible to guarantee that no die contention occurs between multiple NVM sets.

[0057] In garbage collection of a shared NVM set, that is, garbage collection of a group of blocks in one of a plurality of data block pools belonging to the shared NVM set, the GC operation control unit 22 executes the following operations: (1) assigning one of the free blocks in the free block pool corresponding to the shared NVM set as a copy destination block, (2) copying only valid data from one or more blocks included in one data block pool and containing a mixture of valid data and invalid data to the copy destination block, and (3) returning one or more blocks that have become only invalid data by copying valid data to the copy destination block to the free block pool corresponding to the shared NVM set. This allows a free block created by the GC of a certain shared NVM set to be used only by one or more areas corresponding to this shared NVM set, making it possible to guarantee that no die contention occurs between a plurality of NVM sets.

[0058] The NVM set-to-set copy control unit 23 executes an NVM set-to-set copy operation to equalize the wear (number of program / erase cycles) of each NVM set. This NVM set-to-set copy operation can be used, for example, to copy valid data stored in a separated NVM set having a high wear to a separated NVM set having a low wear. This makes it possible to equalize the wear of these NVM sets. The host 2 can send an NVM set-to-set copy command including parameters specifying the source NVM set and the destination NVM set to the SSD 3.

[0059] The inter-NVM set copy control unit 23 (1) selects a block that holds valid data from among blocks belonging to the source NVM set as a source block, (2) copies only the valid data in the source block to a destination block allocated from a free block pool corresponding to the destination NVM set, (3) updates a lookup table that manages mapping between each logical address and each physical address of the source NVM set, and maps a physical address indicating a physical storage location in the destination block to which the valid data is copied to a logical address corresponding to the copied valid data, (4) returns the source block to the free block pool corresponding to the source NVM set when valid data is no longer present in the source NVM set, and (5) repeats the operations (1) to (4) until no blocks holding valid data exist in the source NVM set. This makes it possible to move data (data with a high update frequency) in the source NVM set to a destination NVM set with a small number of program / erase cycles. As a result, a destination NVM set with a low degree of wear is used for writing data with a high update frequency. This makes it possible to delay the timing at which the number of program / erase cycles of the source NVM set reaches the limit value.

[0060] The new NVM set creation control unit 24 creates a new NVM set from another NVM set. For example, the new NVM set creation control unit 24 can create a part of a NAND flash memory die set in a certain NVM set as a new NVM set. This makes it possible to divide one NVM set into two NVM sets.

[0061] The NVM set exchange control unit 25 executes an NVM set exchange operation to equalize the wear (number of program / erase cycles) of each NVM set. This NVM set exchange operation can be used, for example, to exchange data between a separated NVM set having a high wear and a separated NVM set having a low wear. This makes it possible to equalize the wear of these NVM sets. The host 2 can send an NVM set exchange command to the SSD 3, which includes a parameter specifying two NVM sets (a first NVM set, a second NVM set) between which stored data should be exchanged.

[0062] The NVM set exchange control unit 25 executes an operation of copying only valid data in a first NVM set to a second NVM set, and an operation of copying only valid data in the second NVM set to the first NVM set.

[0063] In the operation of copying only the valid data in the first NVM set to the second NVM set, the NVM set exchange control unit 25 (1) selects a block that holds valid data from the blocks belonging to the first NVM set as a source block, (2) copies only the valid data in the source block to a destination block allocated from the free block pool corresponding to the second NVM set, (3) updates a lookup table that manages the mapping between each logical address and each physical address of the first NVM set, and maps a physical address indicating the physical memory location in the destination block to which the valid data was copied to the logical address corresponding to the copied valid data, (4) when there is no valid data left in the source block, returns the source block to the free block pool corresponding to the first NVM set, and (5) repeats the operations (6) to (9) until there are no more blocks holding valid data in the first NVM set.

[0064] In the operation of copying only the valid data in the second NVM set to the first NVM set, the NVM set exchange control unit 25 (1) selects a block that holds valid data from the blocks belonging to the second NVM set as a source block, (2) copies only the valid data in the source block to a destination block allocated from the free block pool corresponding to the first NVM set, (3) updates a lookup table that manages the mapping between each logical address and each physical address of the second NVM set, and maps a physical address indicating the physical memory location in the destination block to which the valid data was copied to the logical address corresponding to the copied valid data, (4) when there is no valid data left in the source block, returns the source block to the free block pool corresponding to the second NVM set, and (5) repeats the operations (1) to (4) until there are no blocks holding valid data left in the second NVM set.

[0065] This allows the wear of these two NVM sets to be equalized.

[0066] The NVM set combination unit 26 combines two or more NVM sets into one NVM set. The two or more NVM sets to be combined and the one NVM set to be combined can be specified by the host 2.

[0067] The NAND interface 13 controls the NAND flash memory 5 under the control of the CPU 12. The DRAM interface 14 is a DRAM controller configured to control the DRAM 6 under the control of the CPU 12. A part of the storage area of ​​the DRAM 6 is used as a write buffer (WB) for temporarily storing write data from the host 2. In this embodiment, a plurality of write buffers (WB) 30, 31, 32, . . . are used. At least one write buffer (WB) may be prepared for each NVM set. Another part of the storage area of ​​the DRAM 6 is used to store the above-mentioned lookup tables (LUTs) 40, 41, 42, . . .

[0068] FIG. 3 shows an example of the relationship between the block management corresponding to each NVM set in FIG. 2 and one or more regions (namespaces) corresponding to each NVM set.

[0069] The NVM set 60 includes a NAND flash memory die 600 connected to channel Ch0, a NAND flash memory die 610 connected to channel Ch1, a NAND flash memory die 620 connected to channel Ch2, ..., and a NAND flash memory die 640 connected to channel ChN. Each of the blocks (free blocks) that belong to the NVM set 60 and do not hold valid data is managed by a free block pool 80 corresponding to the NVM set 60. In the process of initializing the SSD 3, the controller 4 places all the blocks that belong to the NVM set 60, that is, all the blocks in the NAND flash memory dies 600, 610, 620, ..., 640, in the free block pool 80 corresponding to the NVM set 60.

[0070] The blocks belonging to the NVM set 60 are managed using a free block pool 80 and an NVM subset 90. The NVM subset 90 is a data block pool for managing each block that belongs to the NVM set 60 and holds valid data. A group of blocks included in this NVM subset 90 constitutes one garbage collection group.

[0071] The free block pool 80 is a free block pool dedicated to one NVM subset 90. Thus, the NVM set 60 functions as an NVM set (an isolated NVM set) that is exclusively used by one NVM subset 90. One write buffer (WB) 30 is associated with the NVM subset 90.

[0072] The NVM set 60 is used as a physical storage space for at least one area (namespace) that can be specified by the host 2. The NVM set 60 may be a physical storage space dedicated to only one namespace. In Fig. 3, a case is illustrated in which the NVM set 60 is used as a physical storage space for two namespaces 100 and 101.

[0073] The NVM set 61 includes a NAND flash memory die 601 connected to channel Ch0, a NAND flash memory die 611 connected to channel Ch1, a NAND flash memory die 621 connected to channel Ch2, ..., and a NAND flash memory die 641 connected to channel ChN. Each of the blocks (free blocks) that belong to the NVM set 61 and do not hold valid data is managed by a free block pool 81 corresponding to the NVM set 61. In the process of initializing the SSD 3, the controller 4 places all of the blocks that belong to the NVM set 61, that is, all of the blocks in the NAND flash memory dies 601, 611, 621, ..., 641, in the free block pool 81 corresponding to the NVM set 61.

[0074] The blocks belonging to the NVM set 61 are managed using a free block pool 81 and an NVM subset 91. The NVM subset 91 is a data block pool for managing each block that belongs to the NVM set 61 and holds valid data. A group of blocks included in this NVM subset 91 constitutes one garbage collection group. The free block pool 81 is a free block pool dedicated to one NVM subset 91. Therefore, the NVM set 61 functions as an NVM set exclusively used by one NVM subset 91 (a separated NVM set). One write buffer (WB) 31 is associated with the NVM subset 91.

[0075] The NVM set 61 is used as a physical storage space for at least one area (namespace). The NVM set 61 may be a physical storage space dedicated to only one namespace. In FIG. 3, the case where the NVM set 61 is used as a physical storage space for one namespace 102 is illustrated.

[0076] The NVM set 62 includes NAND flash memory dies 602, 603, ... 605, 606 connected to channel Ch0, NAND flash memory dies 612, 613, ... 615, 616 connected to channel Ch1, NAND flash memory dies 622, 623, ... 625, 626 connected to channel Ch2, ... NAND flash memory dies 642, 643, ... 645, 646 connected to channel ChN. Each of the blocks (free blocks) that belong to the NVM set 62 and do not hold valid data is managed by a free block pool 82 corresponding to the NVM set 62. In the process of initializing the SSD 3, the controller 4 places all the blocks that belong to the NVM set 62, that is, all the blocks in the NAND flash memory dies 602 to 646, in the free block pool 82 corresponding to the NVM set 62.

[0077] The blocks belonging to the NVM set 62 are managed using a free block pool 82 and NVM subsets 92, 93, 94, and 95. Each of the NVM subsets 92, 93, 94, and 95 is a data block pool for managing each of the blocks belonging to the NVM set 62 and holding valid data. The blocks included in the NVM subset 92 constitute one garbage collection group, the blocks included in the NVM subset 93 constitute another garbage collection group, the blocks included in the NVM subset 94 constitute yet another garbage collection group, and the blocks included in the NVM subset 95 constitute yet another garbage collection group. The free block pool 82 is a free block pool shared by the NVM subsets 92, 93, 94, and 95. Therefore, the NVM set 62 functions as a shared NVM set shared by the multiple NVM subsets 92 to 95. Associated with NVM subsets 92, 93, 94, and 95 are write buffers (WBs) 32, 33, 34, and 35, respectively.

[0078] The NVM set 62 is used as a physical storage space for at least one area (namespace). The NVM set 62 may be a physical storage space dedicated to only one namespace, or may be a physical storage space for multiple namespaces. In FIG. 3, a case is illustrated in which the NVM set 62 is used as a physical storage space for four namespaces 103, 104, 105, and 106.

[0079] 3 illustrates an example in which namespace 103 uses two NVM subsets 92, 93. For example, the LBA range corresponding to namespace 103 may be divided into two sub-LBA ranges. Write data corresponding to one sub-LBA range (e.g., cold data that is updated infrequently) may be written to an input block (destination block) for NVM subset 92 via write buffer (WB) 32. Write data corresponding to the other sub-LBA range (e.g., hot data (metadata) that is updated frequently) may be written to an input block (destination block) for NVM subset 93 via write buffer (WB) 33.

[0080] 3, a data write / read operation is performed on NVM set 60 in response to an I / O command from host 2 including the ID of namespace 100 or 101. A data write / read operation is performed on NVM set 61 in response to an I / O command from host 2 including the ID of namespace 102. A data write / read operation is performed on NVM set 62 in response to an I / O command from host 2 including the ID of any of namespaces 103 to 106. Therefore, NVM sets 60, 61, and 62 can be accessed simultaneously, and long latency (especially long read latency) caused by die contention can be suppressed.

[0081] In addition, garbage collection is performed independently for each NVM subset, so a namespace that occupies one or more NVM subsets is not affected (GC contention) by garbage collection of other NVM subsets used by other namespaces.

[0082] The shared NVM set 62 has the following characteristics:

[0083] Within the shared NVM set 62, the free block pool 82 is shared among multiple NVM subsets 92 to 95, so die contention may occur. However, when allocation of a new input block for a certain NVM subset is required, the controller 4 can select a block with a small number of program / erase cycles from the free blocks in the shared free block pool 82 and allocate the selected block as the new input block. This can make the consumption of each of the NVM subsets 92, 93, 94, and 95 uniform.

[0084] Moreover, the separated NVM sets 60 and 61 have the following characteristics.

[0085] Within each of the separated NVM sets 60 and 61, one NVM subset can occupy one free block pool. Therefore, if one namespace corresponds to this one NVM subset, this namespace can occupy the separated NVM set without die contention. However, since the separated NVM set does not share free blocks with other NVM sets, if the data stored in a particular separated NVM set is rewritten frequently, the wear of this NVM set may be higher than the wear of other NVM sets. Such uneven wear is a factor that reduces the lifespan of the SSD 3.

[0086] In this embodiment, a shared NVM set and a separated NVM set can coexist in one SSD 3. Therefore, for example, it is possible to use the shared NVM set and the separated NVM set depending on the workload.

[0087] In addition, in the case of Figure 3, the following environment is provided for each namespace.

[0088] <NVMセット60> Namespaces 100 and 101 share a single NVM subset 90. There is no die contention between namespaces 100 and 101 and other namespaces, but GC contention between namespaces 100 and 101 may occur.

[0089] <NVMセット61> Namespace 102 occupies one NVM subset 91. There is no die contention or GC contention between namespace 102 and other namespaces.

[0090] <NVMセット62> Namespace 103 occupies two NVM subsets 92, 93. Although die contention may occur between namespace 103 and other namespaces that use NVM set 62, there is no GC contention between namespace 103 and other namespaces.

[0091] Namespaces 104 and 105 share a single NVM subset 94. Die contention may occur between namespaces 104 and 105 and other namespaces that use NVM set 62. Also, GC contention may occur between namespaces 104 and 105, but not between namespaces 104 and 105 and other namespaces.

[0092] Namespace 106 occupies one NVM subset 95. Although die contention may occur between namespace 106 and other namespaces that use NVM set 62, there is no GC contention between namespace 106 and other namespaces.

[0093] Next, with reference to FIG. 4, the host write / garbage collection operations for the separated NVM sets 60, 61 will be described.

[0094] The upper left part of FIG. 4 illustrates a host write / garbage collection operation for NVM set 60.

[0095] (1) User input block allocation First, one free block in the free block pool 80 is allocated as a user input block 210. The user input block 210 is a block for writing write data from the host 2, and is also called a write destination block. Note that if the user input block 210 has already been allocated, this operation is not executed.

[0096] (2) Host write Write data from the host 2 is written from the write buffer 30 to the user input block 210. The write buffer 30 temporarily stores the write data associated with the namespace 100 or the namespace 101. Then, the lookup table corresponding to the NVM set 60 is updated, thereby mapping the logical address (LBA) corresponding to the write data to a physical address indicating the physical storage location in the user input block 210 where the write data has been written.

[0097] (3) Moving the user input block When the user input block 210 is filled with write data, the user input block 210 is moved to the NVM subset (data block pool) 90. In other words, the user input block 210 filled with data is managed by the NVM subset (data block pool) 90.

[0098] (4) GC input block allocation When garbage collection needs to be performed in NVM set 60, a garbage collection operation is performed for blocks in NVM subset 90 independently of other NVM sets. For example, it may be determined that a garbage collection operation is necessary when the number of blocks included in NVM subset 90 is greater than a certain threshold X1 corresponding to NVM subset 90. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 90. For example, a value remaining after subtracting a predetermined number from the total number of blocks that can be allocated for NVM subset 90 may be used as the certain threshold X1 corresponding to NVM subset 90.

[0099] When a garbage collection operation is required in the NVM set 60, one free block in the free block pool 80 is allocated as a GC input block 200. The GC input block 210 is a block to which valid data is copied in garbage collection, and is also called a copy destination block.

[0100] (5) Copy of valid data One or more blocks containing a mixture of valid and invalid data are selected as source blocks from among the blocks in NVM subset 90. Only the valid data in the selected blocks is copied to GC input block 200. Then, the lookup table corresponding to NVM set 60 is updated so that a logical address (LBA) corresponding to the copied valid data is mapped to a physical address indicating the physical storage location in GC input block 200 to which the valid data was copied.

[0101] (6) Moving the GC input block When the GC input block 200 is filled with valid data, the GC input block 200 is moved to the NVM subset 90. In other words, the GC input block 200 filled with valid data is managed by the NVM subset (data block pool) 90.

[0102] (7) Return of blocks Blocks that are managed by NVM subset 90 and that do not hold valid data are returned from NVM subset 90 to free block pool 80. A block that does not hold valid data is a block that has had all of its data invalidated by a host write or a block that has had all of its valid data copied to a destination block by a garbage collection operation.

[0103] The lower left part of FIG. 4 illustrates a host write / garbage collection operation for NVM set 61.

[0104] (1) User input block allocation One free block in the free block pool 81 is allocated as a user input block 211 .

[0105] (2) Host write Write data from the host 2 is written from the write buffer 31 to the user input block 211. The write buffer 31 temporarily stores the write data associated with the namespace 102. Then, the lookup table corresponding to the NVM set 61 is updated, whereby a logical address (LBA) corresponding to the write data is mapped to a physical address indicating the physical storage location in the user input block 211 where the write data has been written.

[0106] (3) Moving the user input block When the user input block 211 is filled with write data, the user input block 211 is moved to the NVM subset (data block pool) 91. In other words, the user input block 211 filled with data is managed by the NVM subset (data block pool) 91.

[0107] (4) GC input block allocation When garbage collection needs to be performed in NVM set 61, a garbage collection operation is performed for blocks in NVM subset 91, independently of other NVM sets. For example, it may be determined that a garbage collection operation is necessary when the number of blocks included in NVM subset 91 is greater than a certain threshold X1 corresponding to NVM subset 91. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 91. For example, a value remaining after subtracting a predetermined number from the total number of blocks that can be allocated for NVM subset 91 may be used as the certain threshold X1 corresponding to NVM subset 91.

[0108] When a garbage collection operation is required in the NVM set 61 , one free block in the free block pool 81 is allocated as a GC input block 201 .

[0109] (5) Copy of valid data One or more blocks containing a mixture of valid and invalid data are selected as source blocks from among the blocks in NVM subset 91. Only the valid data in the selected blocks is copied to GC input block 201. Then, the lookup table corresponding to NVM set 61 is updated, thereby mapping a logical address (LBA) corresponding to the copied valid data to a physical address indicating the physical storage location in GC input block 201 to which the valid data was copied.

[0110] (6) Moving the GC input block When the GC input block 201 is filled with valid data, the GC input block 201 is moved to the NVM subset 91. That is, the GC input block 201 filled with valid data is managed by the NVM subset (data block pool) 91.

[0111] (7) Return of blocks Blocks that are managed by NVM subset 91 and that do not hold valid data are returned from NVM subset 91 to free block pool 81. A block that does not hold valid data is a block whose entire data has been invalidated by a host write, or a block whose entire valid data has been copied to a destination block by a garbage collection operation.

[0112] 5 illustrates the host write / garbage collection operations performed for the shared NVM set 62. Assume here that the shared NVM set 62 includes only two NVM subsets 94, 95.

[0113] A host write / garbage collection operation for NVM subset 94 is performed as follows.

[0114] (1) User input block allocation One free block in the free block pool 82 is allocated as a user input block 214 .

[0115] (2) Host write Write data from host 2 is written from write buffer 34 to user input block 214. Write buffer 34 temporarily stores write data associated with namespace 104 or 105. The lookup table corresponding to NVM subset 94 is then updated, thereby mapping the logical address (LBA) corresponding to the write data to a physical address indicating the physical storage location in user input block 214 where the write data was written.

[0116] (3) Moving the user input block When the user input block 214 is filled with write data, the user input block 214 is moved to the NVM subset (data block pool) 94. In other words, the user input block 214 filled with data is managed by the NVM subset (data block pool) 94.

[0117] (4) GC input block allocation When garbage collection needs to be performed on NVM subset (data block pool) 94, a garbage collection operation is performed for the blocks in NVM subset 94 independently of other NVM sets and other NVM subsets in NVM set 62. For example, it may be determined that a garbage collection operation is necessary when the number of blocks included in NVM subset 94 is greater than a certain threshold X1 corresponding to NVM subset 94. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 94. For example, a value remaining after subtracting a predetermined number from the total number of blocks that can be allocated for NVM subset 94 may be used as the certain threshold X1 corresponding to NVM subset 94.

[0118] When a garbage collection operation is required in the NVM subset 94 , one free block in the free block pool 82 is allocated as a GC input block 204 .

[0119] (5) Copy of valid data One or more blocks containing a mixture of valid and invalid data are selected as source blocks from among the blocks in NVM subset 94. Only the valid data in the selected blocks is copied to GC input block 204. A lookup table corresponding to NVM subset 94 is then updated so that a logical address (LBA) corresponding to the copied valid data is mapped to a physical address indicating the physical storage location in GC input block 204 to which the valid data was copied.

[0120] (6) Moving the GC input block When the GC input block 204 is filled with valid data, the GC input block 204 is moved to the NVM subset 94. That is, the GC input block 204 filled with valid data is managed by the NVM subset (data block pool) 94.

[0121] (7) Return of blocks Blocks that are managed by NVM subset 94 and that do not hold valid data are returned from NVM subset 94 to free block pool 82. A block that does not hold valid data is a block that has had all of its data invalidated by a host write or has had all of its valid data copied to a destination block by a garbage collection operation.

[0122] Host write / garbage collection operations for NVM subset 95 are performed in a similar manner as host write / garbage collection operations for NVM subset 94 .

[0123] FIG. 6 shows another example of a configuration of multiple NVM sets.

[0124] 6, each NVM set includes a collection of NAND flash memory dies connected to the same channel. That is, NVM set 110 includes NAND flash memory dies 600, 601, 602, 603, ... 605, 606 connected to channel Ch0. NVM set 111 includes NAND flash memory dies 610, 611, 612, 613, ... 615, 616 connected to channel Ch1. NVM set 112 includes NAND flash memory dies 620, 621, 622, 623, ... 625, 626 connected to channel Ch2, and NAND flash memory dies 640, 641, 642, 643, ... 645, 646 connected to channel ChN.

[0125] 6, access to the NVM sets 110, 111, and 112 is performed through different channels. Therefore, even if a data write / read operation is being performed on any NAND flash memory die in one NVM set, a data write / read operation can be immediately performed on any NAND flash memory die in another NVM set.

[0126] 2 in which each NVM set spans multiple channels, one channel is shared between the NVM sets. Therefore, in the NVM set configuration of FIG. 2, if a write / read request to the NAND flash memory die 600 in the NVM set 60 and a write / read request to the NAND flash memory die 601 in the NVM set 61 occur simultaneously, an increase in latency may occur due to contention for access to the channel Ch0.

[0127] 6, access to the NVM sets 110, 111, and 112 is performed via different channels, so even if write / read requests to the NVM sets 110, 111, and 112 occur simultaneously, these write / read requests can be executed immediately. Therefore, the latency of the access request from the host 2 can be reduced.

[0128] However, in the NVM set configuration of Fig. 6, the peak I / O performance of each NVM set is limited to the performance of a single channel. Therefore, it is preferable to use the NVM set configuration of Fig. 6 in combination with a mechanism that can improve the performance of a single channel.

[0129] FIG. 7 shows the relationship between the block management corresponding to each NVM set in FIG. 6 and one or more regions (namespaces) corresponding to each NVM set.

[0130] The NVM set 110 may function as a separate NVM set, similar to the NVM set 60 in FIG. 2. In the process of initializing the SSD3, all blocks belonging to the NVM set 110 are placed in a free block pool 80 dedicated to the NVM subset 90. The NVM set 111 may function as a separate NVM set, similar to the NVM set 61 in FIG. 2. In the process of initializing the SSD3, all blocks belonging to the NVM set 111 are placed in a free block pool 81 dedicated to the NVM subset 91. The NVM set 112 may function as a shared NVM set, similar to the NVM set 62 in FIG. 2. In the process of initializing the SSD3, all blocks belonging to the NVM set 112 are placed in a free block pool 82 shared by the NVM subsets 92 to 95.

[0131] FIG. 8 shows a schematic diagram of a flash memory package that can be used as the NAND flash memory 5 mounted on the SSD 3. As shown in FIG.

[0132] This flash memory package 910 is a memory package that enables high-speed data input / output and reduced power consumption by using TSV (Through Silicon Via) technology that uses electrodes that vertically penetrate the inside of stacked NAND flash memory dies in the package. In the flash memory package 910, multiple stacked NAND flash memory dies are housed in a single package. Here, a case where eight NAND flash memory dies D0 to D7 are housed in a single package is illustrated as an example, but the number of NAND flash memory dies housed in a package is not limited to this example.

[0133] The flash memory package 910 includes a package substrate 911 such as a printed wiring board, an interface die (also called an interface chip) Ce, and the above-mentioned stacked NAND flash memory dies D0 to D7. A plurality of solder bumps 916 functioning as a plurality of external I / O terminals (electrodes) for inputting and outputting signals are arranged on the rear surface of the package substrate 911. These signals include an 8-bit wide I / O signal and various control signals (a plurality of chip enable signals CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE, a read enable signal RE, a plurality of ready / busy signals RB, etc.). The 8-bit wide I / O signal is used to transmit commands, addresses, data, etc. Part of the address may include a chip address. The NAND flash memory die to be accessed may be selected by a combination of the chip enable signal CE and the chip address.

[0134] An interface die Ce is disposed on the surface of the package substrate 911. The interface die Ce is connected to a plurality of solder bumps 916 via a wiring layer (not shown).

[0135] The stacked NAND flash memory dies D0 to D7 are interconnected by a large number of vertical vias 925. The interface die Ce transmits I / O signals, chip enable signals CE, command latch enable signals CLE, address latch enable signals ALE, write enable signals WE, read enable signals RE, and the like to the NAND flash memory dies D0 to D7 via the large number of vertical vias 925, and also receives I / O signals, ready / busy signals RB, and the like from the NAND flash memory dies D0 to D7 via the large number of vertical vias 925.

[0136] The interface die Ce may have a parallel / serial conversion circuit built in. The interface die Ce may convert an 8-bit I / O signal from the controller 4 into, for example, a 64-bit I / O signal using the parallel / serial conversion circuit, and transmit the 64-bit I / O signal to the NAND flash memory dies D0 to D7 through 64 specific vertical vias included in the multiple vertical vias 925.

[0137] Each of the vertical vias 925 includes a plurality of through electrodes V that penetrate the semiconductor substrate of each of the stacked NAND flash memory dies D0 to D7, and a plurality of bump electrodes (solder bumps) 919 that respectively connect the stacked NAND flash memory dies D0 to D7.

[0138] In conventional memory packages that use wire bonding, as the number of stacked dies increases, the parasitic capacitance and parasitic resistance of the package's external I / O terminals increase, making it difficult to operate the memory package at high frequencies.

[0139] 8, instead of bonding wires, the stacked NAND flash memory dies D0 to D7 are interconnected by a large number of vertical vias 925. This reduces the parasitic capacitance and parasitic resistance of the external I / O terminals, and enables each NAND flash memory die in the flash memory package 910 to operate at a high frequency.

[0140] FIG. 9 is a cross-sectional view of a flash memory package 910.

[0141] Stacked NAND flash memory dies D0 to D7 are mounted on the surface of the support substrate 912. A through electrode V is embedded in each of the NAND flash memory dies D0 to D7. The through electrode V is an electrode that penetrates a semiconductor substrate in the corresponding NAND flash memory die. The through electrodes V of two adjacent NAND flash memory dies are connected by a solder bump 919. In this case, on the surface of each NAND flash memory die, the through electrode V may be connected to the solder bump 919 via a wiring layer provided above the semiconductor substrate. In addition, the two adjacent NAND flash memory dies may be physically bonded to each other via an adhesive layer 915.

[0142] The interface die Ce is mounted on the back surface of the support substrate 912. A wiring layer 923 is formed on the support substrate 912. The interface die Ce is connected to the wiring layer 923 via a plurality of solder bumps 918. Each through electrode V of the bottom layer NAND flash memory die D0 is connected to the wiring layer 923. As a result, the interface die Ce is electrically connected to the NAND flash memory die D0 to D7.

[0143] The support substrate 912 is connected to the package substrate 911 via a plurality of solder bumps 917. The interface die Ce is sealed with a sealing resin 921. The NAND flash memory dies D0 to D7 are sealed with a sealing resin 922. The outer peripheries of the sealing resins 921 and 922 are sealed with a sealing resin 920, and the upper part of the sealing resin 922 is sealed with a metal plate 913.

[0144] FIG. 10 illustrates the relationship between the multiple NVM sets described in FIG. 6 and one or more flash memory packages used as these NVM sets. 10 illustrates a case where a large number of NAND flash memory dies in the NAND flash memory 5 are classified into two NVM sets 130 and 131. The NVM sets 130 and 131 correspond to the separated NVM sets 110 and 111 described in FIG. 6. The NVM set 130 includes NAND flash memory dies D0 to D7 each connected to a channel Ch0, and the NVM set 131 includes NAND flash memory dies D10 to D17 each connected to a channel Ch1.

[0145] The NAND flash memory dies D0 to D7 in the NVM set 130 are realized by a single flash memory package 910. In the flash memory package 910, as described in FIG. 8 and FIG. 9, the NAND flash memory dies D0 to D7 are stacked, and these NAND flash memory dies D0 to D7 are interconnected by a large number of vertical vias (each of the vertical vias includes a through electrode V and a solder bump 919). A plurality of external I / O terminals (solder bumps 916) provided on the back surface of the package substrate 911 of the flash memory package 910 are connected to a plurality of signal lines in the channel Ch0. These signal lines may include an 8-bit wide I / O signal line and a plurality of control signal lines for various control signals (a plurality of chip enable signals CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE, a read enable signal RE, a plurality of ready / busy signals RB, etc.). These signals received from the NAND interface 13 via the channel Ch0 are transmitted to the NAND flash memory dies D0 to D7 via the interface die Ce and a number of vertical vias.

[0146] Similarly, the NAND flash memory dies D10 to D17 in the NVM set 131 are also realized by a single flash memory package 930. The flash memory package 930 has a structure similar to that of the flash memory package 910. That is, in the flash memory package 930, the NAND flash memory dies D10 to D17 are stacked, and these NAND flash memory dies D10 to D17 are interconnected by a large number of vertical vias (each of the vertical vias includes a through electrode V and a solder bump 939). A plurality of external I / O terminals (solder bumps 936) provided on the back surface of the package substrate 931 of the flash memory package 930 are connected to a plurality of signal lines in the channel Ch1. These signal lines may include an 8-bit wide I / O signal line and a plurality of control signal lines for various control signals (a plurality of chip enable signals CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE, a read enable signal RE, a plurality of ready / busy signals RB, etc.). These signals received from the NAND interface 13 via the channel Ch1 are transmitted to the NAND flash memory dies D10 to D17 via the interface die Ce and a number of vertical vias.

[0147] The controller 4 executes a data write / read operation on the NVM set 130 via channel Ch0 in response to an I / O command from the host 2 that specifies an area (namespace) corresponding to the NVM set 130. The controller 4 also executes a data write / read operation on the NVM set 131 via channel Ch1 in response to an I / O command from the host 2 that specifies an area (namespace) corresponding to the NVM set 131.

[0148] In the configuration of Fig. 10, the peak I / O performance of each NVM set is limited to the performance of a single channel, but the performance of each channel is improved compared to the case of using a normal memory package in which multiple dies are connected by wire bonding. Therefore, the configuration of Fig. 10 makes it possible to simultaneously execute write / read requests to each of the NVM sets 130 and 131, and to minimize the decrease in the peak I / O performance of each NVM set.

[0149] Note that, in FIG. 10, an example is shown in which the multiple NAND flash memory dies included in each separated NVM set are realized by a memory package using a large number of TSVs, but the multiple NAND flash memory dies included in a shared NVM set can also be realized by a memory package using a large number of TSVs.

[0150] In addition, when a single memory package using multiple vertical vias (TSVs) supports two or more channels, multiple NAND flash memory dies included in two or more NVM sets corresponding to the two or more channels may be realized by the single memory package.

[0151] Next, the garbage collection operation for the NVM set 60 described with reference to FIGS. 2 and 3 will be specifically described with reference to FIGS.

[0152] 11 to 13, for ease of illustration, it is assumed that the NVM set 60 includes two NAND flash memory dies 1 to 2, and each die has two blocks including pages P1 to P4.

[0153] As shown in FIG. 11, a free block in the free block pool 80 (here, free block # 21 ) is allocated as a GC input block 200 .

[0154] Next, a block (block #11) containing a mixture of valid and invalid data is selected as a source block from NVM subset 90, and only the valid data in this selected source block (block #11) is copied to GC input block 200 (block #21).

[0155] In the case where valid data d1, d3 and invalid data d2, d4 are mixed in block #11, only valid data d1 and data d3 are copied to the GC input block 200 (block #21). At this time, data d1 is copied to page P1 of block #21, and data d3 is copied to page P2 of block #21.

[0156] When the valid data (data d1 and data d3) of block #11 is copied to the GC input block 200 (block #21), the data d1 and data d3 of block #11 are invalidated. As a result, block #11 is no longer a block that holds valid data, and is returned to the free block pool 80, as shown in FIG.

[0157] In the NVM subset 90, there is a block #12 in which valid data d5, d7 and invalid data d6, d8 are mixed. When the block #12 is selected as the copy source block, only the valid data (data d5 and data d7) of the block #12 is copied to the GC input block 200 (block #21). At this time, the data d5 is copied to page P3 of the block #21, and the data d7 is copied to page P4 of the block #21.

[0158] When the valid data (data d5 and data d7) of block #12 is copied to GC input block 200 (block #21), data d5 and data d7 of block #12 are invalidated. As a result, block #12 becomes a block that does not hold valid data, and as shown in FIG. 13, block #12 is returned to the free block pool 80. Also, when data d5 and data d7 are copied to GC input block 200 (block #21), block #21 is filled with valid data. In this case, block #21 is moved to NVM subset 90.

[0159] FIG. 14 shows an inter-NVM set copy operation. Here, the explanation will be given assuming that the NVM set 60 in FIG. 2 is the source NVM set, and the NVM set 61 in FIG. 2 is the destination NVM set. The host 2 can specify the source NVM set and the destination NVM set. The destination NVM set may be an NVM set that is not currently being used by the host 2. By using an NVM set that is not currently being used by the host 2 as the destination NVM set, it is possible to prevent hot data and cold data from being mixed in the destination NVM set due to the inter-NVM set copy operation. Note that if there is no NVM set that is not currently being used, the host 2 may send a command to the SSD 3 requesting the creation of a new NVM set.

[0160] The NVM set-to-set copy operation is performed in the following steps.

[0161] (1) User input block allocation In the destination NVM set (NVM set 61), one free block in the free block pool 81 is allocated as the user input block 211.

[0162] (2) Host write Write data from the host 2 is written from the write buffer 31 to the user input block 211. Normally, the write buffer 31 stores write data associated with the namespace 102 corresponding to the destination NVM set, but after an inter-NVM set copy operation is initiated, the write buffer 31 stores write data associated with the namespace 100 or 101 corresponding to the source NVM set. Then, the lookup table corresponding to the NVM subset 90 is updated, and a physical address indicating the physical storage location in the user input block 211 where the write data has been written is mapped to a logical address (LBA) corresponding to the write data.

[0163] In this way, before the NVM set-to-NVM set copy operation, the write data associated with namespace 101 or namespace 100 was written to user input block 210 of the source NVM set (NVM set 60), but after the NVM set-to-NVM set copy operation, the write data associated with namespace 101 or namespace 100 is written to user input block 211 of the destination NVM set (NVM set 61).

[0164] (3) Moving the user input block When the user input block 211 is filled with write data, the user input block 211 is moved to the NVM subset (data block pool) 91. In other words, the user input block 211 filled with data is managed by the NVM subset (data block pool) 91.

[0165] (4) GC input block allocation In the destination NVM set (NVM set 61), one free block in the free block pool 81 is allocated as the GC input block 201.

[0166] (5) Copying valid data from the source NVM set to the destination NVM set A block that holds valid data is selected as a source block from among the blocks in the NVM subset 90 of the source NVM set (NVM set 60). Then, only the valid data in this source block is copied to the GC input block (destination block) 201 of the destination NVM set (NVM set 61). In this case, first, valid data to be copied is selected from this source block. Then, this selected valid data is read from this source block and written to the GC input block (destination block) 201.

[0167] When valid data is copied to GC input block 201, a lookup table corresponding to NVM subset 90 is updated, thereby mapping a logical address (LBA) corresponding to the copied valid data to a physical address indicating the physical memory location within GC input block 201 to which the valid data was copied.

[0168] (6) Moving the GC input block In the destination NVM set (NVM set 61), when the GC input block 201 is filled with valid data from a block in the source NVM set (NVM set 60), the GC input block 201 is moved to the NVM subset 91. In other words, the GC input block 201 filled with valid data is managed by the NVM subset (data block pool) 91.

[0169] (7) Return of blocks In the destination NVM set (NVM set 61), blocks that are managed by NVM subset 91 and do not hold valid data are returned from NVM subset 91 to free block pool 81. For example, when all data held in a certain block in NVM subset 91 is invalidated by writing new write data to user input block 211, this block is returned from NVM subset 91 to free block pool 81.

[0170] (7)' Return of source block In a source NVM set (NVM set 60), when valid data in a source block is copied to GC input block 201, causing the source block to no longer contain valid data, the source block is returned from NVM subset 90 to free block pool 80.

[0171] This inter-NVM set copy operation can, for example, change the physical storage space for data (hot data) stored in the source NVM set to a destination NVM set with a smaller number of rewrites (smaller number of program / erase cycles). This allows wear leveling to be performed to equalize the wear between NVM sets.

[0172] Note that before the valid data selected to be copied is actually copied to the GC input block 201, write data (new data corresponding to this LBAx) having the same LBAx as the LBAx of this valid data may be written to the user input block 211. When the write data (new data corresponding to this LBAx) is written to the user input block 211, the lookup table corresponding to the NVM subset 90 is updated, whereby a physical address indicating the physical storage location in the user input block 211 where the write data has been written is mapped to the LBAx corresponding to this write data.

[0173] In this case, the selected valid data becomes old data that is no longer read by the host 2. Therefore, if write data having the same LBAx as that of the valid data selected to be copied is written to the user input block 211 before the valid data selected to be copied is actually copied to the GC input block 201, the copy operation of this valid data may be stopped. This makes it possible to prevent unnecessary copy operations from being executed.

[0174] Alternatively, instead of stopping the copy operation of the valid data, the copy operation of the selected valid data itself may be performed, but the lookup table corresponding to the NVM subset 90 may not be updated. This prevents the physical address corresponding to LBAx from being changed to a value indicating the physical storage location to which the valid data (old data) is copied. More specifically, each time valid data corresponding to a certain LBA is copied to the GC input block 201, it may be determined whether the physical address corresponding to this LBA corresponds to the source NVM set (NVM set 60) or the destination NVM set (NVM set 61) by referring to the lookup table. If this physical address corresponds to the destination NVM set (NVM set 61), it is recognized that new data corresponding to this LBA has been written to the user input block 211, and the lookup table is not updated. On the other hand, if this physical address corresponds to the source NVM set (NVM set 60), it is recognized that the copied valid data is the latest data corresponding to this LBA, and the lookup table is updated. By updating the lookup table, this LBA is mapped with a physical address that indicates the physical memory location where the valid data has been copied.

[0175] FIG. 15 shows the relationship between the contents of the address translation table before the inter-NVM set copy operation of FIG. 14 and the contents of the address translation table after the inter-NVM set copy operation. Before the inter-NVM set copy operation is performed, the LUT 40 corresponding to the NVM subset 90 holds only the physical address of the source NVM set (NVM set 60).

[0176] When an inter-NVM set copy operation is started from the source NVM set (NVM set 60) to the destination NVM set (NVM set 61), the physical addresses of the LUT 40 are updated sequentially. For example, when data d10 corresponding to LBA10 is copied from the source NVM set (NVM set 60) to the GC input block 201 of the destination NVM set (NVM set 61), a physical address indicating the physical storage location in the destination NVM set (NVM set 61) to which the data d10 is copied is mapped to LBA10 of the LUT 40. Thus, when the inter-NVM set copy operation is completed, the LUT 40 holds only the physical address of the NVM set 61.

[0177] In this way, by performing an NVM set-to-NVM set copy operation using a mechanism similar to GC, the controller 4 can read data requested by the host 2 from the destination NVM set (NVM set 61) by referencing the LUT 40 without performing any special processing to create address conversion information corresponding to the data copied to the destination NVM set (NVM set 61).

[0178] Next, the inter-NVM set copy operation will be specifically described with reference to FIGS.

[0179] 16 to 18, for simplicity, it is assumed that the NVM set 60 includes NAND flash memory dies 1 and 2, the NVM set 61 includes NAND flash memory dies 3 and 4, and each die has two blocks each including pages P1 to P4. It is also assumed that valid data is copied from the NVM set 60 to the NVM set 61.

[0180] As shown in FIG. 16, a free block (here, block #41) in the free block pool 81 in the destination NVM set (NVM set 61) is allocated as a GC input block 201.

[0181] Next, in the source NVM set (NVM set 60), a block that holds valid data from the blocks in NVM subset 90 is selected as the source block, and only the valid data in this selected source block (block #11) is copied to the GC input block 201 (block #41) of the destination NVM set (NVM set 61).

[0182] In the case where valid data d1, d3 and invalid data d2, d4 are mixed in block #11, only valid data d1 and data d3 are copied to the GC input block 201 (block #41). At this time, data d1 is copied to page P1 of block #41, and data d3 is copied to page P2 of block #41.

[0183] When the valid data (data d1 and data d3) of block #11 is copied to the GC input block 201 (block #41), the data d1 and data d3 of block #11 are invalidated. As a result, block #11 becomes a block that does not hold valid data, and as shown in FIG. 17, block #11 is returned to the free block pool 80.

[0184] In the NVM subset 90, there is a block #12 in which valid data d5, d7 and invalid data d6, d8 are mixed. When the block #12 is selected as the copy source block, only the valid data (data d5 and data d7) of the block #12 is copied to the GC input block 201 (block #41). At this time, the data d5 is copied to page P3 of the block #41, and the data d7 is copied to page P4 of the block #41.

[0185] When the valid data (data d5 and data d7) of block #12 is copied to GC input block 201 (block #41), data d5 and data d7 of block #12 are invalidated. As a result, block #12 becomes a block that does not hold valid data, and is returned to the free block pool 80, as shown in FIG. 18. Also, when data d5 and data d7 are copied to GC input block 201 (block #41), block #41 is filled with valid data. In this case, block #41 is moved to NVM subset 91.

[0186] FIG. 19 shows an overview of an NVM set exchange operation for exchanging data between two NVM sets (NVM set #1, NVM set #2).

[0187] Here, it is assumed that NVM set #1 is NVM set 60 and NVM set #2 is NVM set 61. It is also assumed that before the NVM set replacement operation, data A (data with a high update frequency) is stored in NVM set #1 (NVM set 60) and data B (data with a low update frequency) is stored in NVM set #2 (NVM set 61).

[0188] In this case, the number of rewrites (number of program / erase cycles) of NVM set #1 (NVM set 60) is greater than the number of rewrites (number of program / erase cycles) of NVM set #2 (NVM set 61). Here, the number of rewrites (number of program / erase cycles) of an NVM set may be represented by the average number of program / erase cycles of all blocks belonging to this NVM set, or may be represented by the total number of program / erase cycles of all blocks belonging to this NVM set.

[0189] For example, NVM set #1 (NVM set 60) can be rewritten 800 times during a 100-day period (number of program / erase cycles = 800), whereas NVM set #2 (NVM set 61) can be rewritten only 100 times during the same 100-day period (number of program / erase cycles = 100). If the limit value for the number of rewrites of each block is, for example, 1000 times, when 200 (= 1000 times - 800 times) rewrites (program / erase operations) are performed in NVM set #1, the number of rewrites of NVM set #1 will reach this limit value. In this case, it is highly likely that each block in NVM set #1 will no longer be able to function normally.

[0190] In this embodiment, an operation of exchanging data between NVM set #1 (NVM set 60) and NVM set #2 (NVM set 61) can be executed as necessary. For example, when 100 days have passed since the start of use of SSD3, data may be exchanged between NVM set #1 (NVM set 60) and NVM set #2 (NVM set 61) in response to a command from host 2 requesting an NVM set exchange.

[0191] In an NVM set replacement operation, valid data stored in NVM set #1 (NVM set 60) is copied to NVM set #2 (NVM set 61). Then, the lookup table corresponding to NVM set #1 (NVM set 60) is updated, so that the logical address (LBA) corresponding to the copied valid data is mapped to a physical address indicating the physical storage location in NVM set #2 (NVM set 61) to which the valid data was copied.

[0192] Furthermore, the valid data stored in NVM set #2 (NVM set 61) is copied to NVM set #1 (NVM set 60). Then, the lookup table corresponding to NVM set #2 (NVM set 61) is updated, whereby the logical address (LBA) corresponding to the copied valid data is mapped to a physical address indicating the physical storage location in NVM set #1 (NVM set 60) to which the valid data has been copied.

[0193] Once the NVM set exchange operation is complete, the physical storage space for Data A (data with a high update frequency) is changed to NVM Set #2 (NVM Set 61), and the physical storage space for Data B (data with a low update frequency) is changed to NVM Set #1 (NVM Set 60).

[0194] Immediately after completion of the NVM set exchange operation, the number of rewrites of NVM set #2 (NVM set 61) is 100, immediately after completion of the data exchange, the number of rewrites of NVM set #2 (NVM set 61) is 100, and the number of rewrites of NVM set #1 (NVM set 60) is 800.

[0195] After this, data A is updated at a high frequency again, which causes the number of rewrites of NVM set #2 to increase by 800 times in 100 days. Meanwhile, data B is also updated at a relatively low frequency, which causes the number of rewrites of NVM set #1 to increase by 100 times in 100 days. As a result, 200 days after the initial state (100 days after the NVM set was replaced), the number of rewrites of NVM set #2 (NVM set 61) will be 900 times, and the number of rewrites of NVM set #1 (NVM set 60) will be 900 times.

[0196] In this way, by executing the NVM set exchange operation, it is possible to equalize the number of times the blocks belonging to NVM set #1 (NVM set 60) and NVM set #2 (NVM set 61) are rewritten, and therefore it is possible to equalize the degree of wear between the NVM sets.

[0197] FIG. 20 illustrates the host write / garbage collection operations performed for the two NVM sets prior to the NVM set exchange operation. Before the execution of the NVM set exchange operation, host write / garbage collection operations are performed independently in NVM set #1 (NVM set 60) and NVM set #2 (NVM set 61), as described in detail in FIG.

[0198] FIG. 21 illustrates the host write / garbage collection operations performed between two NVM sets for an NVM set exchange operation. (1) User input block allocation In NVM set #1, one block in the free block pool 80 is allocated as a user input block 210. In addition, in NVM set #2, one block in the free block pool 81 is allocated as a user input block 211.

[0199] (2) Host write Write data from the host 2 is written from the write buffer 30 to the user input block 210. Normally, write data associated with the namespace 100 or namespace 101 corresponding to NVM set #1 (NVM set 60) is stored in the write buffer 30, but after an NVM set exchange operation is started, write data associated with the namespace 102 corresponding to NVM set #2 (NVM set 61) is stored in the write buffer 30. Then, the lookup table corresponding to NVM set #2 (NVM set 61) is updated, and a physical address indicating the physical storage location in the user input block 210 where the write data has been written is mapped to a logical address (LBA) corresponding to the write data.

[0200] In this way, before the NVM set replacement operation, the write destination of the write data associated with namespace 102 was user input block 211 of NVM set #2 (NVM set 61), but when the NVM set replacement operation is initiated, the write destination of the write data associated with namespace 102 is changed to user input block 210 of NVM set #1 (NVM set 60).

[0201] Furthermore, write data from the host 2 is written from the write buffer 31 to the user input block 211. Normally, the write buffer 31 stores write data associated with the namespace 102 corresponding to the NVM set #2 (NVM set 61), but after an NVM set exchange operation is started, the write buffer 31 stores write data associated with the namespace 100 or 101 corresponding to the NVM set #1 (NVM set 60). Then, the lookup table corresponding to the NVM set #1 (NVM set 60) is updated, and thus a physical address indicating the physical storage location in the user input block 211 where the write data has been written is mapped to a logical address (LBA) corresponding to the write data.

[0202] In this way, before the NVM set replacement operation, the write destination of write data associated with namespace 101 or namespace 100 was user input block 210 of NVM set #1 (NVM set 60), but when the NVM set replacement operation is initiated, the write destination of write data associated with namespace 101 or namespace 100 is changed to user input block 211 of NVM set #2 (NVM set 61).

[0203] (3) Moving the user input block When the user input block 210 is filled with write data, the user input block 210 is moved to the NVM subset (data block pool) 90. In other words, the user input block 210 filled with data is managed by the NVM subset (data block pool) 90.

[0204] Furthermore, when the user input block 211 is filled with write data, the user input block 211 is moved to the NVM subset (data block pool) 91. In other words, the user input block 211 filled with data is managed by the NVM subset (data block pool) 91.

[0205] (4) GC input block allocation In NVM set #1 (NVM set 60), one free block in the free block pool 80 is allocated as a GC input block 200.

[0206] In addition, in the NVM set (NVM set 61), one free block in the free block pool 81 is allocated as the GC input block 201.

[0207] (5) Exchange of valid data A block that holds valid data is selected as a source block from among the blocks in NVM subset 90 of the source NVM set (NVM set 60). Then, only the valid data in this source block is copied to GC input block 201 of NVM set #2 (NVM set 61). Then, the lookup table corresponding to NVM subset 90 is updated, whereby a logical address (LBA) corresponding to the copied valid data is mapped to a physical address indicating the physical storage location in GC input block 201 to which the valid data was copied.

[0208] A block that holds valid data is selected as a source block from among the blocks in NVM subset 91 of NVM set #2 (NVM set 61). Then, only the valid data in this source block is copied to GC input block 200 of NVM set #1 (NVM set 60). Then, the lookup table corresponding to NVM subset 91 is updated, whereby a logical address (LBA) corresponding to the copied valid data is mapped to a physical address indicating the physical storage location in GC input block 200 to which the valid data was copied.

[0209] (6) Moving the GC input block In NVM set #1 (NVM set 60), when GC input block 200 is filled with valid data from one or more blocks in NVM set #2 (NVM set 61), GC input block 200 is moved to NVM subset 90. In other words, GC input block 200 filled with valid data is managed by NVM subset (data block pool) 90.

[0210] Also, in NVM set #2 (NVM set 61), when GC input block 201 is filled with valid data from one or more blocks in NVM set #1 (NVM set 60), GC input block 201 is moved to NVM subset 91. That is, GC input block 201 filled with valid data is managed by NVM subset (data block pool) 91.

[0211] (7) Return of source block In NVM set #1 (NVM set 60), blocks that are managed by NVM subset 90 and do not hold valid data are returned from NVM subset 90 to free block pool 80. For example, when all data held by a block in NVM subset 90 is invalidated by writing new write data to user input block 210, the block is returned from NVM subset 90 to free block pool 80.

[0212] In NVM set #2 (NVM set 61), blocks that are managed by NVM subset 91 and do not hold valid data are returned from NVM subset 91 to free block pool 81. For example, when all data held by a certain block in NVM subset 91 is invalidated by writing new write data to user input block 211, this block is returned from NVM subset 91 to free block pool 81.

[0213] FIG. 22 shows an overview of the new NVM set creation operation. Assume now that an NVM set 160 including NAND flash memory dies 600-606, 610-616, 620-626, ... 640-646 is being used. A free block pool 180 exists in this NVM set 160. The free block pool 180 is shared by NVM subset 190B and NVM subset 190C. Furthermore, a write buffer 130B is provided corresponding to NVM subset 190B, and a write buffer 130C is provided corresponding to NVM subset 190C.

[0214] The controller 4 can create a new NVM set 161 from the NVM set 160, as shown in the lower part of Fig. 22. In this case, first, a NAND flash memory die to be reserved for the new NVM set 161 is determined from among a plurality of NAND flash memory dies included in the NVM set 160. In the example of Fig. 22, NAND flash memory dies 600, 610, 620, ... 640 are determined as the NAND flash memory dies for the NVM set 161. Valid data in these NAND flash memory dies 600, 610, 620, ... 640 are copied to a block group belonging to the remaining NAND flash memory dies in the NVM set 160.

[0215] This creates a free block pool 181 for the NVM set 161, an NVM subset 190A, and a write buffer 130A. Each of the free blocks in the NAND flash memory dies 600, 610, 620, ... 640 is managed by the free block pool 181 for the NVM set 161. The original NVM set 160 becomes a reduced NVM set. The free block pool 180 manages only the free blocks belonging to the remaining dies excluding the NAND flash memory dies 600, 610, 620, ... 640.

[0216] 23 illustrates the host write / garbage collection operations performed to create a new NVM set, assuming that a new NVM set 161 is created from an original NVM set 160 that contains two NVM subsets.

[0217] (1) User input block allocation One free block in free block pool 180 corresponding to original NVM set 160 is allocated as user input block 410 corresponding to NVM subset 190B. Also, one free block in free block pool 180 is allocated as user input block 411 corresponding to NVM subset 190C. Note that if user input blocks 410 and 411 have already been allocated, this operation is not performed.

[0218] (2) Host write Write data from host 2 is written from write buffer 130B to user input block 410. Then, the lookup table corresponding to NVM subset 190B is updated, thereby mapping the logical address (LBA) corresponding to the write data to a physical address indicating the physical memory location in user input block 410 where the write data was written.

[0219] Furthermore, write data from host 2 is written from write buffer 130C to user input block 411. Then, the lookup table corresponding to NVM subset 190C is updated, whereby a logical address (LBA) corresponding to the write data is mapped to a physical address indicating the physical storage location in user input block 411 where this write data has been written.

[0220] (3) Moving the user input block When the user input block 410 is filled with write data, the user input block 410 is moved to the NVM subset (data block pool) 190B. In other words, the user input block 410 filled with data is managed by the NVM subset (data block pool) 190B.

[0221] Furthermore, when the user input block 411 is filled with write data, the user input block 411 is moved to the NVM subset (data block pool) 190C. In other words, the user input block 411 filled with data is managed by the NVM subset (data block pool) 190C.

[0222] (4) GC input block allocation In the original NVM set (NVM set 160), one block from the free blocks in free block pool 180 is allocated as GC input block 400 corresponding to NVM subset 190B. Also, one block from the free blocks in free block pool 180 is allocated as GC input block 401 corresponding to NVM subset 190C.

[0223] (5) Copy of valid data From the blocks in NVM subset 190B (or NVM subset 190C), one or more blocks containing a mixture of valid data and invalid data are selected as source blocks, and only the valid data in the source blocks is copied to GC input block 400 (or GC input block 401). Then, the lookup table corresponding to NVM subset 190B (or NVM subset 190C) is updated, so that a logical address (LBA) corresponding to the copied valid data is mapped to a physical address indicating the physical storage location in GC input block 400 (or GC input block 401) to which the valid data was copied.

[0224] (6) Moving the GC input block When GC input block 400 (or GC input block 401) is filled with valid data, GC input block 400 (or GC input block 401) is moved to NVM subset 190B (or NVM subset 190C). In other words, the GC input block filled with valid data is managed by the corresponding NVM subset (data block pool).

[0225] (7) and (7)' Return of blocks Blocks that are managed by NVM subset 190B (or NVM subset 190C) and do not hold valid data are returned to the free blocks. In this case, blocks that do not belong to the die set to be assigned to new NVM set 161 are returned from NVM subset 190B (or NVM subset 190C) to free block pool 180. Meanwhile, blocks that do not belong to the die set to be assigned to new NVM set 161 are returned from NVM subset 190B (or NVM subset 190C) to the free block pool 181 of the new NVM set.

[0226] In the above description, a case where GC is performed on the entire original NVM set 160 has been described, but a block that holds valid data from among blocks belonging to a die set to be assigned to a new NVM set 161 may be preferentially selected as a copy source block, and only the valid data in this copy source block may be copied to a GC input block (copy destination block). This allows the new NVM set 161 to be created in a short time.

[0227] Next, the new NVM set creation operation will be specifically described with reference to Figures 24 to 26. In Figures 24 to 26, for simplicity of illustration, it is assumed that the NVM set 330 (NVM set A) includes NAND flash memory dies 1 to 4, and each die has two blocks each including pages P1 to P4.

[0228] First, from the NAND flash memory dies 1 to 4 belonging to the NVM set A, the NAND flash memory dies 1 to 2 to be reserved for the new NVM set B are determined.

[0229] 24, a block (here, block #41) in the free block pool 300 of NVM set A is allocated as the GC input block 320. Also, a block (here, block #11) that holds valid data from the blocks of NAND flash memory dies 1-2 reserved for NVM set B is selected as a copy source block, and the valid data in the selected copy source block (block #11) is copied to the GC input block 320 (block #41).

[0230] In the case where valid data d1, d3 and invalid data d2, d4 are mixed in block #11, only valid data d1 and data d3 are copied to the GC input block 320 (block #41). At this time, data d1 is copied to page P1 of block #41, and data d3 is copied to page P2 of block #41.

[0231] When the valid data (data d1 and data d3) of block #11 is copied to the GC input block 320 (block #41), the data d1 and data d3 of block #11 are invalidated. As a result, block #11 becomes a block that does not hold valid data, and therefore, as shown in FIG. 25, block #11 is returned to the free block pool 301 newly created for NVM set B (new NVM set).

[0232] Among the NAND flash memory dies reserved for NVM set B, there is a block #12 in which valid data d5, d7 and invalid data d6, d8 are mixed. When block #12 is selected as the copy source block, only the valid data (data d5 and data d7) of block #12 is copied to the GC input block 320 (block #41). At this time, data d5 is copied to page P3 of block #21, and data d7 is copied to page P4 of block #41.

[0233] When the valid data (data d5 and data d7) of block #12 is copied to the GC input block 320 (block #41), the data d5 and data d7 of block #12 are invalidated. As a result, block #12 becomes a block that does not hold valid data, and therefore block #12 is returned to the free block pool 301 of NVM set B (new NVM set) as shown in FIG.

[0234] FIG. 27 provides an overview of the NVM set combining operation. FIG. 27 illustrates the operation of combining NVM set #1 (NVM set 163) and NVM set #2 (NVM set 164) into NVM set #3 (NVM set 165).

[0235] NVM set #1 (NVM set 163) includes NAND flash memory dies 600, 610, 620, ... 640. NVM set #2 (NVM set 164) includes NAND flash memory dies 601, 611, 621, ... 641. NVM set #3 (NVM set 165) includes NAND flash memory dies 602-606, 612-616, 622-626, ... 642-646.

[0236] When NVM set #1 (NVM set 163) and NVM set #2 (NVM set 164) are combined with NVM set #3 (NVM set 165), free block pool 183 corresponding to NVM set #1 (NVM set 163) and free block pool 184 corresponding to NVM set #2 (NVM set 164) are also combined with free block pool 185 corresponding to NVM set #1 (NVM set 165). In addition, NVM subset 190A of NVM set #1 (NVM set 163) and NVM subset 190B of NVM set #2 (NVM set 164) are also combined with NVM subset 190C of NVM set #3 (NVM set 165).

[0237] FIG. 28 illustrates the host write / garbage collection operations performed for NVM set merging. Before an NVM set combining operation is performed, write data write operations and garbage collection operations are performed independently of each other in NVM sets #1 to #3.

[0238] (1) User input block allocation One free block in free block pool 183 is allocated as user input block 413. Also, one free block in free block pool 184 is allocated as user input block 414. Furthermore, one free block in free block pool 185 is allocated as user input block 415. Note that if user input blocks 413, 414, and 415 have already been allocated, this operation is not executed.

[0239] (2) Host write In NVM set #1 (NVM set 163), write data from host 2 is written from write buffer 130A to user input block 413. Write buffer 130A temporarily stores the write data associated with NVM subset 190A. Then, the lookup table corresponding to NVM set 163 is updated, whereby a physical address indicating the physical storage location in user input block 413 where the write data has been written is mapped to a logical address (LBA) corresponding to the write data.

[0240] Furthermore, in NVM set #2 (NVM set 164), write data from host 2 is written from write buffer 130B to user input block 414. Write buffer 130B temporarily stores the write data associated with NVM subset 190B. Then, the lookup table corresponding to NVM set 164 is updated, whereby a logical address (LBA) corresponding to the write data is mapped to a physical address indicating the physical storage location in user input block 414 where the write data has been written.

[0241] Furthermore, in NVM set #3 (NVM set 165), write data from host 2 is written from write buffer 130C to user input block 415. Write buffer 130C temporarily stores the write data associated with NVM subset 190C. Then, the lookup table corresponding to NVM set 165 is updated, whereby a physical address indicating the physical storage location in user input block 415 where the write data has been written is mapped to a logical address (LBA) corresponding to the write data.

[0242] (3) Moving the user input block In NVM set #3, when a user input block 415 is filled with write data, the user input block 415 is moved to NVM subset (data block pool) 190C. In other words, the user input block 415 filled with data is managed by NVM subset (data block pool) 190C.

[0243] Before the NVM set combining operation is performed, when user input block 413 is filled with write data in NVM set #1, the user input block 413 is moved to NVM subset (data block pool) 190A, and when user input block 414 is filled with write data in NVM set #2, the user input block 414 is moved to NVM subset (data block pool) 190B. However, after the NVM set combining operation is performed, the operation indicated by (3)' is performed instead of (3).

[0244] (3)' Move the user input block to the destination NVM set When a user input block 413 in NVM set #1 is filled with write data, the user input block 413 is moved to NVM subset 190C of NVM set #3. In other words, the user input block 413 filled with data is managed by NVM subset (data block pool) 190C.

[0245] Also, when a user input block 414 in NVM set #2 is filled with write data, the user input block 414 is moved to NVM subset 190C of NVM set #3. In other words, the user input block 414 filled with data is managed by NVM subset (data block pool) 190C.

[0246] (4) GC input block allocation When garbage collection needs to be performed in NVM subset (data block pool) 190A, a garbage collection operation is performed for blocks in NVM subset 190A, independently of other NVM sets. For example, it may be determined that a garbage collection operation is necessary when the number of blocks included in NVM subset 190A is greater than a certain threshold X1 corresponding to NVM subset 190A. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 190A. For example, a value remaining after subtracting a predetermined number from the total number of blocks that can be allocated for NVM subset 190A may be used as the certain threshold X1 corresponding to NVM subset 190A.

[0247] When a garbage collection operation is required in NVM subset 190A, one free block in free block pool 183 is allocated as GC input block 403.

[0248] Furthermore, when garbage collection needs to be performed in NVM subset (data block pool) 190B, a garbage collection operation is performed for blocks in NVM subset 190B, independently of other NVM sets. For example, it may be determined that a garbage collection operation is necessary when the number of blocks included in NVM subset 190B is greater than a certain threshold X1 corresponding to NVM subset 190B. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 190B. For example, the remaining value obtained by subtracting a predetermined number from the total number of blocks that can be allocated for NVM subset 190B may be used as the certain threshold X1 corresponding to NVM subset 190B.

[0249] When a garbage collection operation is required in NVM subset 190B, one free block in free block pool 184 is allocated as a GC input block 404.

[0250] When garbage collection needs to be performed in NVM subset (data block pool) 190C, a garbage collection operation is performed for blocks in NVM subset 190C independently of other NVM sets. For example, it may be determined that a garbage collection operation is necessary when the number of blocks included in NVM subset 190C is greater than a certain threshold X1 corresponding to NVM subset 190C. Threshold X1 may be determined based on the total number of blocks that can be allocated for NVM subset 190C. For example, a value remaining after subtracting a predetermined number from the total number of blocks that can be allocated for NVM subset 190C may be used as the certain threshold X1 corresponding to NVM subset 190C.

[0251] When a garbage collection operation is required in NVM subset 190C, one free block in free block pool 185 is allocated as a GC input block 405.

[0252] (5) Copy of valid data One or more blocks containing a mixture of valid and invalid data are selected as source blocks from among the blocks in NVM subset 190A. Only the valid data in the selected blocks is copied to GC input block 403. Then, a lookup table corresponding to NVM set 163 is updated so that a logical address (LBA) corresponding to the copied valid data is mapped to a physical address indicating the physical storage location in GC input block 403 to which the valid data was copied.

[0253] Additionally, one or more blocks containing a mixture of valid and invalid data are selected as source blocks from among the blocks in NVM subset 190B. Only the valid data in the selected blocks is copied to GC input block 404. Then, a lookup table corresponding to NVM set 164 is updated, thereby mapping a logical address (LBA) corresponding to the copied valid data to a physical address indicating the physical storage location in GC input block 404 to which the valid data was copied.

[0254] Furthermore, one or more blocks containing a mixture of valid and invalid data are selected as source blocks from among the blocks in NVM subset 190C. Only the valid data in the selected blocks is copied to GC input block 405. Then, a lookup table corresponding to NVM set 165 is updated so that a logical address (LBA) corresponding to the copied valid data is mapped to a physical address indicating the physical storage location in GC input block 405 to which the valid data was copied.

[0255] (6) Moving the GC input block In NVM set #3, when GC input block 405 is filled with valid data, GC input block 403 is moved to NVM subset 190C. That is, GC input block 405 filled with valid data is managed by NVM subset (data block pool) 190C.

[0256] Before the NVM set merging operation is performed, in NVM set #1, when GC input block 403 is filled with valid data, GC input block 403 is moved to NVM subset 190A, and in NVM set #2, when GC input block 404 is filled with valid data, GC input block 404 is moved to NVM subset 190B. However, after the NVM set merging operation is performed, the operation indicated by (6)' is performed instead of (6).

[0257] (6)' Move GC input blocks to the destination NVM set When the GC input block 403 in NVM set #1 is filled with valid data, the GC input block 403 is moved to the NVM subset 190C in NVM set #3. The user input block 403 filled with valid data is managed by the NVM subset (data block pool) 190C.

[0258] Also, when the GC input block 404 in the NVM set #2 is filled with valid data, the GC input block 404 is moved to the NVM subset 190C in the NVM set #3. The user input block 403 filled with valid data is managed by the NVM subset (data block pool) 190C.

[0259] (7) Return of blocks In NVM set #3, blocks that are managed by NVM subset 190C and do not hold valid data are returned from NVM subset 190C to free block pool 185. Blocks that do not hold valid data are blocks whose entire data has been invalidated by a host write, or blocks whose entire valid data has been copied to a destination block by a garbage collection operation.

[0260] Before the NVM set combining operation is performed, blocks in NVM set #1 that are managed by NVM subset 190A and do not hold valid data are returned from NVM subset 190A to free block pool 183, and blocks that are managed by NVM subset 190B and do not hold valid data are returned from NVM subset 190B to free block pool 184. However, after the NVM set combining operation is performed, the operation indicated by (7)' is performed instead of (7).

[0261] (7)' Move blocks of the NVM subset to the destination NVM set The blocks of NVM subset 190A are moved to NVM subset 190C of NVM set #3. That is, the blocks of NVM subset 190A are managed by NVM subset (data block pool) 190C.

[0262] Also, the blocks of NVM subset 190B are moved to NVM subset 190C of NVM set #3. That is, the blocks of NVM subset 190B are managed by NVM subset (data block pool) 190C.

[0263] (8) Move free blocks to the destination NVM set Free blocks in free block pool 183 of NVM set #1 are moved to free block pool 185 of NVM set #3. Also, free blocks in free block pool 184 of NVM set #2 are moved to free block pool 185 of NVM set #3.

[0264] The flowcharts of FIGS. 29 and 30 show the procedure of data write / read operations executed by the controller 4.

[0265] When a command is received from the host 2 (YES in step S101), the NVM set control unit 21 checks the namespace ID included in the received command (step S102). If an area corresponding to NVM set #1 is specified by the received command (YES in step S103), the NVM set control unit 21 determines that the NVM set #1 is the access target (step S104). For example, in a case where the namespace of NSID1 corresponds to NVM set #1, if the received command includes NSID1, it may be determined that an area corresponding to NVM set #1 has been specified.

[0266] If the received command is a write command (YES in step S105), NVM set control unit 21 determines whether or not allocation of a new user input block is necessary (step S106). If allocation of a new user input block is necessary (YES in step S106), NVM set control unit 21 allocates a free block in the free block pool of NVM set #1 as a user input block (step S107), and writes write data to the allocated user input block (step S108). If allocation of a new user input block is not necessary (NO in step S106), NVM set control unit 21 writes write data to the already allocated user input block (step S108).

[0267] When the write data is written to the user input block, the NVM set control unit 21 updates the LUT corresponding to the NVM set #1 (step S109). Then, the NVM set control unit 21 returns a write completion response to the host 2 (step S110).

[0268] If the received command is a read command (NO in step S105, YES in step S111), the NVM set control unit 21 refers to the LUT corresponding to NVM set #1 (step S112) and obtains a physical address corresponding to the start LBA in the read command. Based on this physical address, the NVM set control unit 21 reads the data specified by the read command from a block of the NVM subset belonging to NVM set #1 (step S113). Then, the NVM set control unit 21 returns the read data and a response indicating the completion of the read to the host 2 (step S114).

[0269] If the area corresponding to NVM set #1 is not specified by the received command (NO in step S103), the NVM set control unit 21 determines whether or not the area corresponding to NVM set #2 is specified by the received command (step S115). If the area corresponding to NVM set #2 is specified by the received command (YES in step S115), the NVM set control unit 21 determines NVM set #2 as the access target (step S116). For example, in a case where the namespace of NSID2 corresponds to NVM set #2, if the received command includes NSID2, it may be determined that the area corresponding to NVM set #2 is specified.

[0270] If the received command is a write command (YES in step S117), NVM set control unit 21 determines whether or not allocation of a new user input block is necessary (step S118). If allocation of a new user input block is necessary (YES in step S118), NVM set control unit 21 allocates a free block in the free block pool of NVM set #2 as a user input block (step S119), and writes write data to the allocated user input block (step S120). If allocation of a new user input block is not necessary (NO in step S118), NVM set control unit 21 writes write data to the already allocated user input block (step S120).

[0271] When the write data is written to the user input block, the NVM set control unit 21 updates the LUT corresponding to the NVM set #2 (step S121). Then, the NVM set control unit 21 returns a write completion response to the host 2 (step S122).

[0272] If the received command is a read command (NO in step S117, YES in step S123), the NVM set control unit 21 refers to the LUT corresponding to NVM set #2 (step S124) and obtains a physical address corresponding to the start LBA in the read command. Based on this physical address, the NVM set control unit 21 reads the data specified by the read command from a block of the NVM subset belonging to NVM set #2 (step S125). Then, the NVM set control unit 21 returns the read data and a read completion response to the host 2 (step S126).

[0273] The flowchart in FIG. 31 shows the procedure of a garbage collection operation executed by the GC operation control unit 22 for each NVM subset belonging to a certain NVM set.

[0274] The GC operation control unit 22 determines whether the number of blocks included in the NVM subset #1 belonging to the NVM set #1 has reached the threshold value X1 corresponding to the NVM subset #1 (step S201). If the number of blocks included in the NVM subset #1 belonging to the NVM set #1 has reached the threshold value X1 (YES in step S201), the GC operation control unit 22 starts GC of the NVM subset #1.

[0275] The GC operation control unit 22 first assigns a free block in the free block pool of the NVM set #1 as a copy destination block (step S202). Then, the GC operation control unit 22 selects a block containing a mixture of valid data and invalid data from the blocks of the NVM subset #1 as a copy source block (step S203).

[0276] Next, the GC operation control unit 22 copies only the valid data of the selected block (source block for copying) to the destination block for copying (step S204). Then, the GC operation control unit 22 updates the LUT corresponding to NVM subset #1 (step S205). After that, the GC operation control unit 22 returns the block (source block for copying) that has become invalid data only to the free block pool of NVM set #1 (step S206).

[0277] Subsequently, the GC operation control unit 22 determines whether or not the number of blocks included in NVM subset #1 has decreased to be equal to or less than the threshold value X2 (<X1) corresponding to NVM subset #1 (step S207). If the number of blocks included in NVM subset #1 has decreased to be equal to or less than the threshold value X2 (<X1) (YES in step S207), the GC operation control unit 22 ends the garbage collection operation. If the number of blocks included in NVM subset #1 has not decreased to be equal to or less than the threshold value X2 (<X1) (NO in step S207), the GC operation control unit 22 continues the garbage collection operation (steps S202 to S206).

[0278] The flowchart of FIG. 32 shows the procedure of the copy operation between NVM sets executed by the copy control unit 23 between NVM sets.

[0279] When a copy command between NVM sets from host 2 including parameters specifying the source NVM set and the destination NVM set is received (YES in step S301), the copy control unit 23 between NVM sets allocates a free block in the free block pool of the destination NVM set as the destination block for copying (step S302). Then, the copy control unit 23 between NVM sets selects a block having valid data from the blocks belonging to the source NVM set as the source block for copying (step S303).

[0280] Next, the NVM set copy control unit 23 copies valid data from the source block to the destination block (step S304). After the valid data is copied, the NVM set copy control unit 23 updates the LUT corresponding to the NVM subset of the source NVM set (step S305).

[0281] Next, the inter-NVM set copy control unit 23 returns the source block that no longer contains valid data to the free block pool of the source NVM set (step S306).

[0282] The inter-NVM set copy control unit 23 repeats the processes of steps S302 to S306 until there are no more blocks having valid data in the copy source NVM set (step S307).

[0283] The flowchart in Fig. 33 shows another procedure of the inter-NVM set copy operation executed by the inter-NVM set copy control unit 23. Here, it is assumed that a host write operation is permitted during the inter-NVM set copy operation.

[0284] When an inter-NVM set copy command including parameters specifying the source NVM set and the destination NVM set is received from the host 2 (YES in step S401), the inter-NVM set copy control unit 23 assigns a free block in the free block pool of the destination NVM set as a destination block (step S402).Then, the inter-NVM set copy control unit 23 selects a block having valid data from among the blocks belonging to the source NVM set as a source block (step S403).

[0285] Next, the NVM set copy control unit 23 copies valid data from the source block to the destination block (step S404). After the valid data is copied, the NVM set copy control unit 23 updates the LUT corresponding to the NVM subset of the source NVM set (step S405).

[0286] Next, the inter-NVM set copy control unit 23 returns the source block that no longer contains valid data to the free block pool of the source NVM set (step S406).

[0287] Next, the inter-NVM set copy control unit 23 determines whether or not there is no block having valid data in the copy source NVM set (step S407). If there is no block having valid data in the copy source NVM set (YES in step S407), the inter-NVM set copy control unit 23 ends the inter-NVM set copy operation.

[0288] On the other hand, if there is a block having valid data in the copy source NVM set (NO in step S407), the NVM set control unit 21 of the controller 4 determines whether or not write data for an NVM subset belonging to the copy source NVM set has been received (step S408). If write data for an NVM subset belonging to the copy source NVM set has not been received (NO in step S408), the process proceeds to step S402.

[0289] If write data for an NVM subset belonging to the source NVM set has been received (YES in step S408), the NVM control unit 21 assigns a free block in the free block pool of the destination NVM set as a write destination block (step S409). Then, the NVM control unit 21 writes the write data to the assigned block (step S410). When the write data is written, the NVM control unit 21 updates the LUT corresponding to the NVM subset belonging to the source NVM set (step S411).

[0290] Next, the controller 4 returns a write completion response to the host 2 (step S412). When the write completion response is returned to the host 2, the process proceeds to step S402.

[0291] The processes of steps S402 to S412 are repeated until no blocks having valid data remain in the copy source NVM set (step S407).

[0292] The flowchart in FIG. 34 shows the procedure of a new NVM set creation operation executed by new NVM set creation control unit 24.

[0293] When the new NVM set creation command is received (YES in step S501), the new NVM set creation control unit 24 determines a group of NAND flash memory dies to be reserved for the new NVM set from among all the NAND flash memory dies belonging to the original NVM set (step S502). The original NVM set may be created by the new NVM set creation command.

[0294] Next, the new NVM set creation control unit 24 assigns a free block of the free block pool of the original NVM set as a copy destination block (step S503).Then, the new NVM set creation control unit 24 selects a block that holds valid data from among the blocks belonging to the new NVM set (i.e., the blocks belonging to the group of the reserved NAND flash memory die) as a copy source block (step S504).

[0295] Next, the new NVM set creation control unit 24 copies valid data from the source block to the destination block (step S505). After the valid data is copied, the new NVM set creation control unit 24 updates the LUT corresponding to the NVM subset of the source NVM set (step S506). Next, the new NVM set creation control unit 24 returns the source block that no longer has valid data to the free block pool of the new NVM set (step S507).

[0296] Next, the new NVM set creation control unit 24 determines whether or not there is no block having valid data in the new NVM set (step S508). If there is no block having valid data in the new NVM set (YES in step S508), the new NVM set creation control unit 24 ends the new NVM set creation operation. If there is a block having valid data in the new NVM set (NO in step S508), the new NVM set creation control unit 24 continues the new NVM set creation operation (steps S503 to S507).

[0297] The processes of steps S503 to S507 are repeated until no blocks having valid data exist in the new NVM set.

[0298] 35 shows another procedure of the new NVM set creation operation executed by the new NVM set creation control unit 24. Here, a procedure is shown in which the new NVM set creation operation and the garbage collection operation in the original NVM set are executed in parallel.

[0299] When a new NVM set creation command is received (step S601), the new NVM set creation control unit 24 determines a group of NAND flash memory dies to be reserved for the new NVM set (step S602). Next, the new NVM set creation control unit 24 assigns a free block of the free block pool of the original NVM set as a copy destination block (step S603). Then, the new NVM set creation control unit 24 selects a block containing a mixture of valid data and invalid data as a copy source block from among blocks belonging to the original NVM set (step S604). In step S604, the new NVM set creation control unit 24 may preferentially select a block containing less valid data as a copy source block.

[0300] Next, the new NVM set creation control unit 24 copies valid data from the source block to the destination block (step S605). After the valid data is copied, the new NVM set creation control unit 24 updates the LUT corresponding to the NVM subset of the source NVM set (step S606).

[0301] Next, the new NVM set creation control unit 24 judges whether the physical location of the copy source block that no longer has valid data belongs to the new NVM set (step S607). If the physical location of the copy source block that no longer has valid data belongs to the new NVM set (YES in step S607), the new NVM set creation control unit 24 returns the copy source block that no longer has valid data to the free block pool of the new NVM set (step S608). If the physical location of the copy source block that no longer has valid data does not belong to the new NVM set (NO in step S607), the new NVM set creation control unit 24 returns the copy source block that no longer has valid data to the free block pool of the original NVM set (step S609).

[0302] Next, the new NVM set creation control unit 24 determines whether or not there is no block having valid data in the new NVM set (step S610). If there is no block having valid data in the new NVM set (YES in step S610), the new NVM set creation control unit 24 ends the new NVM set creation operation. If there is a block having valid data in the new NVM set (NO in step S610), the new NVM set creation control unit 24 executes the process of step S603.

[0303] The processes of steps S603 to S607 are repeated until no blocks having valid data exist in the new NVM set.

[0304] FIG. 36 shows an example of the hardware configuration of an information processing device (computing device) that functions as the host 2.

[0305] This information processing device is realized as a computing device such as a server, and includes a processor (CPU) 801, a main memory 802, a BIOS-ROM 803, a network controller 805, a peripheral interface controller 806, a controller 807, and an embedded controller (EC) 808.

[0306] The processor 801 is a CPU configured to control the operation of each component of this information processing device. This processor 801 executes various programs loaded from any one of the multiple SSDs 3 to the main memory 802. The main memory 802 is composed of a random access memory such as a DRAM. The programs may also include a setting program for issuing commands instructing the above-mentioned copying between NVM sets, exchanging NVM sets, creating a new NVM set, and combining NVM sets.

[0307] The processor 801 also executes a basic input / output system (BIOS) stored in a non-volatile memory, BIOS-ROM 803. The BIOS is a system program for controlling hardware.

[0308] The network controller 805 is a communication device such as a wired LAN controller, a wireless LAN controller, etc. The peripheral interface controller 806 is configured to perform communication with peripheral devices such as USB devices.

[0309] The controller 807 is configured to communicate with devices connected to the multiple connectors 807 A, respectively. Multiple SSDs 3 may be connected to the multiple connectors 807 A, respectively. The controller 807 is a SAS expander, a PCIe switch, a PCIe expander, a flash array controller, a RAID controller, or the like.

[0310] The EC 808 functions as a system controller configured to perform power management for the information processing device.

[0311] FIG. 37 shows an example of the configuration of an information processing device (server) including a plurality of SSDs 3 and a host 2.

[0312] This information processing device (server) includes a thin box-shaped housing 901 that can be housed in a rack. A large number of SSDs 3 may be disposed inside the housing 901. In this case, each SSD 3 may be removably inserted into a slot provided on a front surface 901A of the housing 901.

[0313] A system board (motherboard) 902 is disposed in a housing 901. Various electronic components including a CPU 801, a main memory 802, a network controller 805, and a controller 807 are mounted on the system board (motherboard) 902. These electronic components function as the host 2.

[0314] As described above, according to the present embodiment, the NAND flash memory dies are classified into a plurality of NVM sets so that each of the NAND flash memory dies belongs to only one NVM set. Then, in response to an I / O command from the host specifying at least one area (e.g., namespace) corresponding to each NVM set, a data write / read operation is executed for one of the plurality of NVM sets. Therefore, a plurality of I / O commands (write commands or read commands) each specifying a different area corresponding to a different NVM set can be executed simultaneously without die contention. Therefore, for example, even if a read command directed to an area corresponding to another NVM set is received from the host 2 during the execution of a data write operation for a certain NVM set, the controller 4 can immediately execute a data read operation corresponding to the read command without waiting for the completion of the data write operation.

[0315] In addition, the free blocks of the NAND flash memory 5 are managed individually for each NVM set by a plurality of free block pools corresponding to the plurality of NVM sets. Then, for each of the plurality of NVM sets, an operation of allocating one of the free blocks in the corresponding free block pool as an input block (user input block or GC input block), an operation of writing write data to the input block, an operation of managing the input block filled with the write data by an NVM subset, and an operation of returning a block managed by the NVM subset and not holding valid data to the corresponding free block pool are executed. In this way, by using free blocks corresponding to each of the plurality of NVM sets, it is possible to independently execute the allocation of the input block and the return of the free block for each NVM set. This makes it possible to prevent a block in a die belonging to a certain NVM set from being allocated as an input block for another NVM set. Therefore, it is possible to guarantee that no die contention occurs.

[0316] Furthermore, a shared NVM set in which a free block pool is shared by multiple NVM subsets (multiple garbage collection groups) and an isolated NVM set in which a free block pool is exclusively used by one NVM subset (one garbage collection group) can coexist within a single SSD 3.

[0317] In this embodiment, a NAND flash memory is exemplified as a nonvolatile memory. However, the function of this embodiment can be applied to, for example, MRAM (Magnetoresistive RAM). Random Access Memory), PRAM (Phase change The present invention can also be applied to various other non-volatile memories such as Random Access Memory (RAM), Resistive Random Access Memory (ReRAM), or Ferroelectric Random Access Memory (FeRAM).

[0318] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0319] 2...host, 3...SSD, 4...controller, 5...NAND flash memory, 21...NVM set control unit, 22...GC operation control unit, 23...NVM set copy control unit, 24...new NVM set creation control unit, 25...NVM replacement control unit, 26...NVM set combination unit, 60, 61, 62...NVM sets, 80, 81, 82...free block pool, 90, 91, 92, 93, 94, 95...NVM subsets.

Claims

1. 1. A memory system connectable to a host, comprising: Multiple channels and a non-volatile memory including a plurality of non-volatile memory dies connected to the plurality of channels, each non-volatile memory die including a plurality of blocks; a controller connected to the plurality of non-volatile memory dies via the plurality of channels and configured to control the plurality of non-volatile memory dies; The controller: assigning a plurality of namespaces to the memory system, the namespaces including at least a first namespace and a second namespace, each of the plurality of namespaces including a plurality of logical block addresses (LBAs) starting from 0; classifying the non-volatile memory dies into first die groups and second die groups such that each of the non-volatile memory dies belongs to only one die group; when a first write command specifying the first namespace corresponding to the first die group is received from the host, writing first data to be written in the first namespace to a first destination block selected from the first die group; and when a second write command specifying the second namespace corresponding to the second die group is received from the host, the second data to be written in the second namespace is written to a second destination block selected from the second die group. Memory system.

2. The controller:

2. The memory system of claim 1, configured to read data from the first die group without waiting for completion of the write operation of the second data when a first read command specifying the first namespace is received from the host during execution of the write operation of the second data.

3. a free block group belonging to the first die group is managed by a first free block pool corresponding to the first die group, and a free block group belonging to the second die group is managed by a second free block pool corresponding to the second die group; 2. The memory system of claim 1, wherein the first free block pool is a free block pool dedicated to a first data block pool that manages each of the blocks that belong to the first die group and hold valid data, and the second free block pool is a shared free block pool shared by a plurality of second data block pools that manage each of the blocks that belong to the second die group and hold valid data.

4. The controller: In garbage collection of the blocks in the first data block pool, an operation is performed in which one of the free blocks in the first free block pool is assigned as a first destination block, only valid data is copied from one or more blocks that are included in the first data block pool and contain a mixture of valid data and invalid data to the first destination block, and the one or more blocks that contain only invalid data as a result of copying the valid data to the first destination block are returned to the first free block pool; 4. The memory system according to claim 3, wherein in the garbage collection of blocks in one of the second data block pools, the memory system is configured to execute an operation of allocating one of the free blocks in the second free block pool shared by the plurality of second data block pools as a second destination block, copying only valid data from one or more blocks included in the one second data block pool and containing a mixture of valid data and invalid data to the second destination block, and returning the one or more blocks that have become only invalid data as a result of copying the valid data to the second destination block to the second free block pool.

5. a free block group belonging to the first die group is managed by a first free block pool corresponding to the first die group, and a free block group belonging to the second die group is managed by a second free block pool corresponding to the second die group; 2. The memory system of claim 1, wherein the first free block pool is a free block pool dedicated to a first data block pool that manages each of the blocks that belong to the first die group and hold valid data, and the second free block pool is a free block pool dedicated to a second data block pool that manages each of the blocks that belong to the second die group and hold valid data.

6. The controller: In garbage collection of the blocks in the first data block pool, an operation is performed in which one of the free blocks in the first free block pool is assigned as a first destination block, only valid data is copied from one or more blocks that are included in the first data block pool and contain a mixture of valid data and invalid data to the first destination block, and the one or more blocks that contain only invalid data as a result of copying the valid data to the first destination block are returned to the first free block pool; 6. The memory system according to claim 5, wherein in the garbage collection of the blocks in the second data block pool, the memory system is configured to execute an operation of allocating one of the free blocks in the second free block pool as a second destination block, copying only valid data from one or more blocks included in the second data block pool and containing a mixture of valid data and invalid data to the second destination block, and returning the one or more blocks that have become only invalid data as a result of copying the valid data to the second destination block to the second free block pool.

7. a free block group belonging to the first die group is managed by a first free block pool corresponding to the first die group, and a free block group belonging to the second die group is managed by a second free block pool corresponding to the second die group; 2. The memory system of claim 1, wherein the first free block pool is a shared free block pool shared by a plurality of first data block pools that belong to the first die group and manage each of blocks that hold valid data, and the second free block pool is a shared free block pool shared by a plurality of second data block pools that belong to the second die group and manage each of blocks that hold valid data.

8. The controller: In garbage collection of blocks in one of the first data block pools, an operation is performed in which one of the free blocks in the first free block pool shared by the plurality of first data block pools is assigned as a first destination block, only valid data is copied from one or more blocks in the one first data block pool containing a mixture of valid data and invalid data to the first destination block, and the one or more blocks which have become only invalid data as a result of copying the valid data to the first destination block are returned to the first free block pool; 8. The memory system according to claim 7, wherein the garbage collection of blocks in one of the second data block pools of the plurality of second data block pools is configured to execute an operation of allocating one of the free blocks in the second free block pool shared by the plurality of second data block pools as a second destination block, copying only valid data from one or more blocks included in the one second data block pool and containing a mixture of valid data and invalid data to the second destination block, and returning the one or more blocks that have become only invalid data as a result of copying the valid data to the second destination block to the second free block pool.

9. 2. The memory system of claim 1 , wherein the first die group includes a set of a plurality of first non-volatile memory dies respectively connected to the plurality of channels, and the second die group includes a set of a plurality of second non-volatile memory dies respectively connected to the plurality of channels.

10. 2. The memory system of claim 1, wherein the first die group includes a set of a plurality of first non-volatile memory dies each connected to a first channel of the plurality of channels, and the second die group includes a set of a plurality of second non-volatile memory dies each connected to a second channel of the plurality of channels.

11. 2. The memory system of claim 1, wherein a number of the non-volatile memory dies in the first die group is different from a number of the non-volatile memory dies in the second die group.

12. 2. The memory system of claim 1, wherein the controller determines, in response to receiving a command from the host, which of the plurality of non-volatile memory dies are included in the first die group and which are included in the second die group.

13. 1. A method for controlling a plurality of non-volatile memory dies connected to a plurality of channels in a memory system connectable to a host by a controller connected to the plurality of non-volatile memory dies via the plurality of channels, wherein each non-volatile memory die includes a plurality of blocks; allocating a plurality of namespaces to the memory system, the namespace including at least a first namespace and a second namespace; classifying the plurality of non-volatile memory dies into a first die group and a second die group such that each of the plurality of non-volatile memory dies belongs to only one die group; when a first write command specifying the first namespace corresponding to the first die group is received from a host, writing first data to be written in the first namespace to a first destination block selected from the first die group; when a second write command specifying the second namespace corresponding to the second die group is received from the host, writing second data to be written in the second namespace to a second write destination block selected from the second die group; A method of controlling a plurality of namespaces, each of which includes a plurality of logical block addresses (LBAs) starting from zero.

14. a free block group belonging to the first die group is managed by a first free block pool corresponding to the first die group, and a free block group belonging to the second die group is managed by a second free block pool corresponding to the second die group; 14. The control method according to claim 13, wherein the first free block pool is a free block pool dedicated to a first data block pool that manages each of the blocks that belong to the first die group and hold valid data, and the second free block pool is a shared free block pool shared by a plurality of second data block pools that manage each of the blocks that belong to the second die group and hold valid data.

15. In garbage collection of the blocks in the first data block pool, an operation is performed in which one of the free blocks in the first free block pool is assigned as a first destination block, only valid data is copied from one or more blocks that are included in the first data block pool and contain a mixture of valid data and invalid data to the first destination block, and the one or more blocks that contain only invalid data as a result of copying the valid data to the first destination block are returned to the first free block pool; 15. The control method according to claim 14, further comprising the steps of: in garbage collection of a group of blocks in one of the second data block pools of the plurality of second data block pools, allocating one of the free blocks in the second free block pool shared by the plurality of second data block pools as a second destination block; copying only valid data from one or more blocks included in the one second data block pool and containing a mixture of valid data and invalid data to the second destination block; and returning the one or more blocks that have become only invalid data as a result of copying the valid data to the second destination block to the second free block pool.

16. 14. The method of claim 13, wherein the first die group includes a set of a plurality of first non-volatile memory dies respectively connected to the plurality of channels, and the second die group includes a set of a plurality of second non-volatile memory dies respectively connected to the plurality of channels.

17. 14. The method of claim 13, wherein the first die group includes a set of a plurality of first non-volatile memory dies each connected to a first channel of the plurality of channels, and the second die group includes a set of a plurality of second non-volatile memory dies each connected to a second channel of the plurality of channels.

18. The control method of claim 13, further comprising: determining, in response to receiving a command from the host, which of the plurality of non-volatile memory dies are included in the first die group and which are included in the second die group, respectively, of the plurality of non-volatile memory dies.

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