Semiconductor device

Abstract

To provide a semiconductor device that can suppress variations in depth between mutually intersecting trenches and a T-shaped connection portion formed at the intersection of the trenches.SOLUTION: A semiconductor device includes a semiconductor chip having a first main surface 3 and a second main surface opposite to the first main surface, and a trench structure including a first trench 65 formed on the first main surface 3 and extending along a first direction X, a second trench 79 extending along a second direction Y perpendicular to the first direction X and connected to the first trench 65, and a T-shaped connection portion 80 formed at the connection portion of the first trench 65 with the second trench 79, and when a first inscribed circle 119 having a first radius R1 inscribed in both inner side walls of the first trench 65 and a second inscribed circle 120 having a second radius R2 inscribed in peripheral side walls 106 to 108 of the T-shaped connection portion 80 are defined, the second radius R2 is 80% or more and 130% or less of the first radius R1.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a first power transistor, a second power transistor, an active clamp circuit, and an active clamp cutoff circuit. The drain of the second power transistor is electrically connected to the drain of the first power transistor. The source of the second power transistor is electrically connected to the source of the first power transistor. The active clamp circuit is electrically connected to the drain and gate of the first power transistor, and is electrically connected to the drain and gate of the second power transistor. The active clamp cutoff circuit is electrically connected to the active clamp circuit and the gate of the second power transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2019 / 0260371 [Patent Document 2] International Publication No. 2022 / 210033

[0004] [overview] An embodiment of the present disclosure provides a semiconductor device capable of suppressing a decrease in breakdown voltage caused by the trench depth of a T-shaped connection portion becoming too deep.

[0005] One embodiment of the present disclosure provides a semiconductor device including a semiconductor chip having a first main surface and a second main surface opposite to the first main surface, and a trench structure including a first trench formed in the first main surface and extending along a first direction, a second trench extending along a second direction perpendicular to the first direction and connected to the first trench, and a T-shaped connection portion formed at a connection portion of the first trench with the second trench, wherein when a first inscribed circle having a first radius inscribed in both side walls of the first trench and a second inscribed circle having a second radius inscribed in a peripheral side wall of the T-shaped connection portion are defined, the second radius is 80% or more and 130% or less of the first radius. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. [Diagram 3] FIG. 3 is a plan view showing an example of a layout within the semiconductor chip shown in FIG. [Figure 4] FIG. 4 is an enlarged view of region IV shown in FIG. [Diagram 5] FIG. 5 is an enlarged view of region V shown in FIG. [Figure 6] FIG. 6 is an enlarged view of region VI shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. [Figure 11] FIG. 11 is an enlarged view of region XI shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along the line XII-XII shown in FIG. [Figure 13]FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. [Figure 14] FIG. 14 is an enlarged view of region A shown in FIG. 11, showing a first pattern of the T-shaped connector. [Figure 15] FIG. 15 is a cross-sectional view taken along the line XV-XV shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along the line XVI-XVI shown in FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. [Figure 18] FIG. 18 is a diagram showing a mask pattern used when forming the T-shaped connector of the first pattern in FIG. [Figure 19] FIG. 19 is an enlarged view of the area A shown in FIG. 11, showing a second pattern of the T-shaped connection portion. [Figure 20] FIG. 20 is a diagram showing a mask pattern used when forming the T-shaped connector of the second pattern in FIG. [Figure 21] FIG. 21 is an enlarged view of area A shown in FIG. 11, showing a third pattern of the T-shaped connection portion. [Figure 22] FIG. 22 is a diagram showing a mask pattern used when forming the T-shaped connector of the third pattern in FIG. [Figure 23] FIG. 23 is an enlarged view of region A shown in FIG. 11, showing a fourth pattern of the T-shaped connection portion. [Figure 24] FIG. 24 is a diagram showing a mask pattern used when forming the T-shaped connecting portion of the fourth pattern in FIG. [Diagram 25] FIG. 25 is an enlarged view of region A shown in FIG. 11, showing a fifth pattern of the T-shaped connection portion. [Figure 26] FIG. 26 is a diagram showing a mask pattern used when forming the T-shaped connector of the fifth pattern in FIG.

[0007] [Detailed Description] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] Fig. 1 is a plan view showing a semiconductor device 1 according to an embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example of a layout within a semiconductor chip 2 shown in Fig. 1.

[0009] 1 and 2, the semiconductor device 1 includes a semiconductor chip 2 formed in a rectangular parallelepiped shape in this embodiment. The semiconductor chip 2 is made of a chip containing Si (silicon). The semiconductor chip 2 may be made of a chip containing Si single crystal or SiC single crystal. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0010] The first main surface 3 is a device surface on which a functional device is formed. The second main surface 4 is a mounting surface and may be a ground surface having grinding marks. The first to fourth side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The first side surface 5A and the second side surface 5B extend in a second direction Y along the first main surface 3 and face a first direction X that intersects (specifically, perpendicular to) the second direction Y. The third side surface 5C and the fourth side surface 5D extend in the first direction X and face the second direction Y.

[0011] With reference to FIG. 3, the semiconductor device 1 includes a first device region 6 provided on the first main surface 3. The first device region 6 is an output region in which an output signal that is output to the outside is generated. In this embodiment, the first device region 6 is partitioned into a region on the first side surface 5A side of the first main surface 3. The first device region 6 may be partitioned into a quadrangle in plan view, or may be partitioned into a polygonal shape other than a quadrangle. The arrangement and planar shape of the first device region 6 are arbitrary and are not limited to a specific shape.

[0012] In the first device region 6, n (n≧2) insulated gate type main transistors 7 and m (m≧1) insulated gate type monitor transistors 8 are formed. The main transistors 7 may be called "gate split transistors", "power transistors", or "power MISFETs (Metal Insulator Semiconductor Field Effect Transistors)". The monitor transistors 8 are formed together with the main transistors 7 in a single first device region 6. In this embodiment, the monitor transistors 8 are formed in an inner portion (preferably a central portion) of the first device region 6 with a space from the periphery of the first device region 6, and are disposed adjacent to the main transistors 7. In this embodiment, the monitor transistors 8 are formed in a region surrounded by the main transistors 7.

[0013] Regarding the electrical configuration, circuit configuration, and operation of the main transistor 7 and the monitor transistor 8, the contents of the main transistor (8) and the monitor transistor (10) taught in, for example, paragraphs

[0016] to

[0113] and [FIGS. 4] to [9] of Patent Document 2 can be applied.

[0014] The semiconductor device 1 includes a second device region 9 provided in a region different from the first device region 6 on the first main surface 3. The second device region 9 is an input region to which an electrical signal is input from the outside. In this embodiment, the second device region 9 is defined in a region on the second side surface 5B side with respect to the first device region 6. The second device region 9 may be defined in a quadrangular shape in a plan view, or may be defined in a polygonal shape other than a quadrangular shape. The arrangement and planar shape of the second device region 9 are arbitrary and are not limited to a specific shape.

[0015] A control IC (Control Integrated Circuit) 10 as an example of a control circuit is formed in the second device region 9. The control IC 10 configures an IPD (Intelligent Power Device) together with the main transistor 7 and the monitor transistor 8. The IPD may also be referred to as an "IPM (Intelligent Power Module)."

[0016] The electrical configuration, circuit configuration, and operation of the control IC 10 can be adapted to the contents of the control IC (14) taught in, for example, paragraphs

[0016] to

[0113] and [Figures 4] to [9] of Patent Document 2.

[0017] 2 and 3, the semiconductor device 1 includes n main gate wirings 11 as an example of control wirings arranged on the first main surface 3. The n main gate wirings 11 are made of n wiring layers selectively routed in the interlayer insulating layer 12. The n main gate wirings 11 are electrically connected to the n gates of the main transistors 7 in a one-to-one correspondence in the first device region 6 while being electrically independent from one another.

[0018] The n main gate wirings 11 are each electrically connected to the control IC 10 in the second device region 9. The n main gate wirings 11 transmit n gate signals generated by the control IC 10 to the n gates of the main transistors 7 individually.

[0019] 2 and 3, semiconductor device 1 includes m monitor gate wirings 13 as an example of monitor control wirings arranged on first main surface 3. The m monitor gate wirings 13 are made of m wiring layers selectively routed in interlayer insulating layer 12. The m monitor gate wirings 13 are electrically connected to m gates of monitor transistors 8 in one-to-one correspondence in first device region 6 while being electrically independent from one another.

[0020] The m monitor gate wirings 13 are each electrically connected to the control IC 10 in the second device region 9. The m monitor gate wirings 13 individually transmit m monitor gate signals generated by the control IC 10 to the m gates of the monitor transistors 8.

[0021] 1 and 2, the semiconductor device 1 includes a plurality of terminal electrodes 14-19. In Fig. 1, the plurality of terminal electrodes 14-19 are indicated by hatching. The number, arrangement and planar shape of the plurality of terminal electrodes 14-19 may be adjusted to any form according to the specifications of the main transistor 7 and the specifications of the control IC 10, and are not limited to the form shown in Fig. 1. In this form, the plurality of terminal electrodes 14-19 include a drain terminal 14 (power supply terminal VBB), a source terminal 15 (output terminal OUT), an input terminal 16, a ground terminal 17, an enable terminal 18 and a sense terminal 19.

[0022] The drain terminal 14 is electrically connected to the drain of the main transistor 7, the drain of the monitor transistor 8, and the control IC 10. The drain terminal 14 transmits a power supply voltage VB to various circuits such as the drain of the main transistor 7, the drain of the monitor transistor 8, and the control IC 10. The source terminal 15 is electrically connected to the source of the main transistor 7 and the control IC 10. The source terminal 15 transmits an output current generated by the main transistor 7 to the outside.

[0023] The input terminal 16 transmits an input voltage that drives the control IC 10. The ground terminal 17 transmits a ground voltage GND. The enable terminal 18 transmits an electrical signal for enabling or disabling some or all of the functions of the control IC 10. The sense terminal 19 transmits an electrical signal for detecting abnormalities in the main transistor 7, the monitor transistor 8, the control IC 10, etc.

[0024] The drain terminal 14 directly covers the second main surface 4 of the semiconductor chip 2 and is electrically connected to the second main surface 4. The drain terminal 14 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain terminal 14 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in any manner.

[0025] The source terminal 15, the input terminal 16, the ground terminal 17, the enable terminal 18, and the sense terminal 19 are disposed on the interlayer insulating layer 12. The source terminal 15 is formed on the first device region 6 on the first main surface 3. The input terminal 16, the ground terminal 17, the enable terminal 18, and the sense terminal 19 are disposed on the first main surface 3 in a region outside the first device region 6 (specifically, the second device region 9). The terminal electrodes 15-19 may include at least one of a pure Al layer, a pure Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer. A plating layer may be formed on the outer surface of each of the terminal electrodes 15-19. The plating layer may include at least one of a Ni layer, a Pd layer, and an Au layer.

[0026] Fig. 4 is an enlarged view of region IV shown in Fig. 3. Fig. 5 is an enlarged view of region V shown in Fig. 4. Fig. 6 is an enlarged view of region VI shown in Fig. 4. Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 5. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 5. Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 5. Fig. 10 is a cross-sectional view taken along line XX shown in Fig. 5.

[0027] 4 to 10, the semiconductor device 1 includes a first semiconductor region 20 of n-type (first conductivity type) formed in a surface layer portion of the second main surface 4 of the semiconductor chip 2. The first semiconductor region 20 forms the drain of the main transistor 7 and the drain of the monitor transistor 8. The first semiconductor region 20 may be referred to as a "drain region." The first semiconductor region 20 is formed over the entire surface layer portion of the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0028] The n-type impurity concentration of the first semiconductor region 20 is 1×10 18 cm -3 More than 1×10 21 cm -3 The thickness of the first semiconductor region 20 may be 10 μm or more and 450 μm or less. The thickness of the first semiconductor region 20 is preferably 50 μm or more and 150 μm or less. In this embodiment, the first semiconductor region 20 is formed of an n-type semiconductor substrate (Si substrate).

[0029] The semiconductor device 1 includes an n-type second semiconductor region 21 formed in a surface layer portion of the first main surface 3 of the semiconductor chip 2. The second semiconductor region 21, together with the first semiconductor region 20, forms the drain of the main transistor 7 and the drain of the monitor transistor 8. The second semiconductor region 21 may be referred to as a "drift region." The second semiconductor region 21 is formed over the entire surface layer portion of the first main surface 3 so as to be electrically connected to the first semiconductor region 20, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0030] The second semiconductor region 21 has an n-type impurity concentration that is less than the n-type impurity concentration of the first semiconductor region 20. The n-type impurity concentration of the second semiconductor region 21 is 1×10 15 cm -3 More than 1×10 18 cm -3 The second semiconductor region 21 may have a thickness less than that of the first semiconductor region 20. The second semiconductor region 21 may have a thickness of 1 μm or more and 25 μm or less. The second semiconductor region 21 preferably has a thickness of 5 μm or more and 15 μm or less. In this embodiment, the second semiconductor region 21 is formed of an n-type epitaxial layer (Si epitaxial layer).

[0031] The semiconductor device 1 includes a trench separation structure 22 as an example of a region isolation structure that defines the first device region 6 on the first main surface 3. The trench isolation structure 22 may be referred to as a "DTI (deep trench isolation) structure." The trench isolation structure 22 is formed in a ring shape surrounding a portion of the first main surface 3 in a plan view, and defines the first device region 6 of a predetermined shape.

[0032] In this embodiment, trench isolation structure 22 is formed in a quadrangular ring shape having four sides parallel to first to fourth side surfaces 5A to 5D in a plan view, and defines a quadrangular first device region 6. Trench isolation structure 22 may have any planar shape and may be formed in a polygonal ring shape. First device region 6 may be defined in a polygonal shape according to the planar shape of trench isolation structure 22.

[0033] The trench isolation structure 22 has an isolation width WI and an isolation depth DI. The isolation width WI is the width in a direction perpendicular to the direction in which the trench isolation structure 22 extends in a plan view. The isolation width WI may be 0.5 μm or more and 2.5 μm or less. The isolation width WI is preferably 1.2 μm or more and 2 μm or less. The isolation depth DI may be 1 μm or more and 10 μm or less. The isolation depth DI is preferably 2 μm or more and 6 μm or less.

[0034] The aspect ratio DI / WI of trench isolation structure 22 may be greater than 1 and less than or equal to 5. The aspect ratio DI / WI is the ratio of the isolation depth DI to the isolation width WI. The aspect ratio DI / WI is preferably greater than or equal to 2. The bottom wall of trench isolation structure 22 is preferably spaced from the bottom of second semiconductor region 21 by a distance of 1 μm or more and 5 μm or less.

[0035] The trench isolation structure 22 has corners that connect the portion extending in the second direction Y and the portion extending in the first direction X in an arc shape (curved shape). In this embodiment, the four corners of the trench isolation structure 22 are formed in an arc shape. In other words, the first device region 6 is partitioned into a quadrangle having four corners that each extend in an arc shape. The corners of the trench isolation structure 22 preferably have a constant isolation width WI along the arc direction.

[0036] The trench isolation structure 22 has a single electrode structure including an isolation trench 23, an isolation insulating film 24 (isolation insulator), an isolation electrode 25, and an isolation cap insulating film 26. The isolation trench 23 is dug down from the first main surface 3 toward the second main surface 4. The isolation trench 23 is formed at an interval from the bottom of the second semiconductor region 21 toward the first main surface 3.

[0037] The isolation trench 23 includes a sidewall and a bottom wall. The angle that the sidewall of the isolation trench 23 forms with the first main surface 3 in the semiconductor chip 2 may be 90° or more and 92° or less. The isolation trench 23 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the isolation trench 23 are preferably formed in a curved shape. The entire bottom wall of the isolation trench 23 may be formed in a curved shape toward the second main surface 4.

[0038] The isolation insulating film 24 is formed on the wall surface of the isolation trench 23. Specifically, the isolation insulating film 24 is formed in the form of a film on the entire wall surface of the isolation trench 23, and defines a recess space within the isolation trench 23. The isolation insulating film 24 preferably includes a silicon oxide film. It is particularly preferable that the isolation insulating film 24 includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0039] The isolation insulating film 24 has an isolation thickness TI. The isolation thickness TI is the thickness along the normal direction of the wall surface of the isolation trench 23. The isolation thickness TI may be 0.1 μm or more and 1 μm or less. The isolation thickness TI is preferably 0.15 μm or more and 0.65 μm or less. The thickness of the portion of the isolation insulating film 24 covering the bottom wall of the isolation trench 23 may be less than the thickness of the portion covering the side wall of the isolation trench 23.

[0040] The separation electrode 25 is embedded in the separation trench 23 as an integrated member with the separation insulating film 24 sandwiched therebetween. In this embodiment, the separation electrode 25 includes conductive polysilicon. A source potential is applied to the separation electrode 25. The separation electrode 25 has an electrode surface (separation electrode surface) exposed from the separation trench 23. The electrode surface of the separation electrode 25 may be recessed in a curved shape toward the bottom wall of the separation trench 23.

[0041] The isolation cap insulating film 26 covers the electrode surface of the isolation electrode 25 in the isolation trench 23 in the form of a film. The isolation cap insulating film 26 prevents the isolation electrode 25 from shorting with other electrodes. The isolation cap insulating film 26 is continuous with the isolation insulating film 24. The isolation cap insulating film 26 preferably includes a silicon oxide film. It is particularly preferable that the isolation cap insulating film 26 includes a silicon oxide film made of an oxide of the isolation electrode 25. In other words, it is preferable that the isolation cap insulating film 26 includes an oxide of polysilicon, and the isolation insulating film 24 includes an oxide of single crystal silicon.

[0042] The semiconductor device 1 includes a p-type (second conductivity type) body region 27 formed in the surface layer portion of the first main surface 3 in the first device region 6. The p-type impurity concentration of the body region 27 is 1×10 16 cm -3 More than 1×10 18 cm -3The body region 27 is formed in the first device region 6 over the entire surface layer portion of the first main surface 3, and is in contact with the side wall of the trench isolation structure 22. The body region 27 is formed in a region on the first main surface 3 side with respect to the bottom wall of the trench isolation structure 22. The body region 27 is preferably formed in a region on the first main surface 3 side with respect to the intermediate portion of the trench isolation structure 22.

[0043] The semiconductor device 1 includes two systems (n=2) of main transistors 7 formed on the first main surface 3 in the first device region 6. The main transistors 7 are formed on the first main surface 3 at intervals from the trench isolation structure 22 in a plan view. The main transistors 7 include a plurality of unit transistors 28 formed collectively on the first main surface 3 in the first device region 6.

[0044] The number of unit transistors 28 is arbitrary. Fig. 4 shows an example in which 44 unit transistors 28 are formed. It is preferable that the number of unit transistors 28 is an even number. The unit transistors 28 are arranged in a line in the second direction Y in plan view, and are each formed in a band shape extending in the first direction X. The unit transistors 28 are formed in stripes extending in the first direction X in plan view.

[0045] Specifically, each of the unit transistors 28 is composed of a unit cell 29. Each unit cell 29 includes one trench structure 30 and a channel cell 31 controlled by the trench structure 30. The trench structure 30 may be referred to as a "gate structure" or a "trench gate structure." Each trench structure 30 constitutes the gate of each unit transistor 28. The channel cell 31 is a region where the opening and closing of a current path is controlled by the trench structure 30. In this embodiment, the unit cell 29 includes a pair of channel cells 31 formed on both sides of one trench structure 30.

[0046] The plurality of trench structures 30 are arranged at intervals in the second direction Y in a plan view, and are each formed in a strip shape extending in the first direction X. That is, the plurality of trench structures 30 are formed in a stripe shape extending in the first direction X in a plan view.

[0047] Each trench structure 30 has a trench width W and a trench depth D. The trench width W is the width in the direction (second direction Y) orthogonal to the direction in which the trench structure 30 extends. The trench width W is preferably less than the separation width WI of the trench isolation structure 22 (W < WI). The trench width W may be 0.5 μm or more and 2 μm or less. The trench width W is preferably 0.5 μm or more and 1.5 μm or less. Of course, the trench width W may be approximately equal to the separation width WI (W ≒ WI).

[0048] The trench depth D is preferably less than the separation depth DI of the trench isolation structure 22 (D < DI). The trench depth D may be 1 μm or more and 10 μm or less. The trench depth D is preferably 2 μm or more and 6 μm or less. Of course, the trench depth D may be approximately equal to the separation depth DI (D ≒ DI). The aspect ratio D / W of the trench structure 30 may be more than 1 and 5 or less. The aspect ratio D / W is the ratio of the trench depth D to the trench width W. The aspect ratio D / W is particularly preferably 2 or more. The bottom wall of the trench structure 30 is preferably spaced 1 μm or more and 5 μm or less from the bottom of the second semiconductor region 21.

[0049] The plurality of trench structures 30 are arranged at intervals of trench interval IT in the second direction Y. The trench interval IT is preferably set to a value at which depletion layers extending from the plurality of trench structures 30 are integrated below the bottom walls of the plurality of trench structures 30. The trench interval IT may be 0.25 times or more and 1.5 times or less of the trench width W. The trench interval IT is preferably not more than the trench width W (IT ≦ W). The trench interval IT may be 0.5 μm or more and 2 μm or less.

[0050] The configuration of one trench structure 30 will be described below. The trench structure 30 has a multi-electrode structure including a trench 32, an upper insulating film 33, a lower insulating film 34, an upper electrode 35, a lower electrode 36, and an intermediate insulating film 37. The trench 32 may be referred to as a "gate trench." The trench structure 30 includes a buried electrode (gate electrode) buried in the trench 32 with a buried insulator sandwiched therebetween. The buried insulator is composed of the upper insulating film 33, the lower insulating film 34, and the intermediate insulating film 37. The buried electrode is composed of the upper electrode 35 and the lower electrode 36.

[0051] The trench 32 is dug down from the first main surface 3 toward the second main surface 4. The trench 32 penetrates the body region 27 and is formed at an interval from the bottom of the second semiconductor region 21 toward the first main surface 3. The trench 32 includes a sidewall and a bottom wall. The angle that the sidewall of the trench 32 forms with the first main surface 3 in the semiconductor chip 2 may be 90° or more and 92° or less. The trench 32 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the trench 32 are preferably formed in a curved shape. The entire bottom wall of the trench 32 may be formed in a curved shape toward the second main surface 4.

[0052] The upper insulating film 33 covers the upper wall surface of the trench 32. Specifically, the upper insulating film 33 covers the upper wall surface located in a region on the opening side of the trench 32 with respect to the bottom of the body region 27. The upper insulating film 33 crosses the boundary between the second semiconductor region 21 and the body region 27. The upper insulating film 33 has a portion covering the body region 27 and a portion covering the second semiconductor region 21. The upper insulating film 33 preferably includes a silicon oxide film. It is particularly preferable that the upper insulating film 33 includes a silicon oxide film made of an oxide of the semiconductor chip 2. The upper insulating film 33 is formed as a gate insulating film.

[0053] The upper insulating film 33 has a first thickness T1. The first thickness T1 is the thickness along the normal direction of the wall surface of the trench 32. The first thickness T1 is less than the separation thickness TI of the separation insulating film 24 (T1 < TI). The first thickness T1 may be 0.01 μm or more and 0.05 μm or less. Preferably, the first thickness T1 is 0.02 μm or more and 0.04 μm or less.

[0054] The lower insulating film 34 covers the lower wall surface of the trench 32. Specifically, the lower insulating film 34 covers the lower wall surface located in the region on the bottom wall side of the trench 32 with respect to the bottom of the body region 27. The lower insulating film 34 partitions a recess space in the region on the bottom wall side of the trench 32. The lower insulating film 34 is in contact with the second semiconductor region 21. Preferably, the lower insulating film 34 includes a silicon oxide film. Particularly preferably, the lower insulating film 34 includes a silicon oxide film made of the oxide of the semiconductor chip 2.

[0055] The lower insulating film 34 has a second thickness T2. The second thickness T2 is the thickness along the normal direction of the wall surface of the trench 32. The second thickness T2 exceeds the first thickness T1 of the upper insulating film 33 (T1 < T2). The second thickness T2 may be approximately equal to the separation thickness TI of the separation insulating film 24 (T2 ≒ TI). The second thickness T2 may be 0.1 μm or more and 1 μm or less. Preferably, the second thickness T2 is 0.15 μm or more and 0.65 μm or less. In the lower insulating film 34, the thickness of the portion covering the bottom wall of the trench 32 may be less than the thickness of the portion covering the side wall of the trench 32.

[0056] The upper electrode 35 is embedded in the upper side (opening side) in the trench 32 with the upper insulating film 33 interposed therebetween. The upper electrode 35 is embedded in a strip shape extending in the first direction X in plan view. The upper electrode 35 faces the body region 27 and the second semiconductor region 21 with the upper insulating film 33 interposed therebetween. The facing area of the upper electrode 35 with respect to the body region 27 is larger than the facing area of the upper electrode 35 with respect to the second semiconductor region 21. The upper electrode 35 includes conductive polysilicon.

[0057] The upper electrode 35 has an electrode surface (embedded electrode surface) exposed from the trench 32. The electrode surface of the upper electrode 35 may be curved and recessed toward the bottom wall of the trench 32.

[0058] The lower electrode 36 is embedded in the lower side (bottom wall side) within the trench 32 with the lower insulating film 34 interposed therebetween. The lower electrode 36 is embedded in a strip shape extending in the first direction X in a plan view. The lower electrode 36 has a thickness (length) exceeding the thickness (length) of the upper electrode 35 in the depth direction of the trench 32. The lower electrode 36 faces the second semiconductor region 21 with the lower insulating film 34 interposed therebetween. The lower electrode 36 has an upper end portion protruding from the lower insulating film 34 toward the first main surface 3 side. The upper end portion of the lower electrode 36 engages with the bottom portion of the upper electrode 35 and faces the upper insulating film 33 while sandwiching the bottom portion of the upper electrode 35 in the lateral direction along the first main surface 3.

[0059] The lower electrode 36 contains conductive polysilicon. In this form, the lower electrode 36 is formed as a gate electrode. The lower electrode 36 is fixed to the same potential as the upper electrode 35. The intermediate insulating film 37 is interposed between the upper electrode 35 and the lower electrode 36 and electrically insulates the upper electrode 35 and the lower electrode 36. Specifically, the intermediate insulating film 37 covers the lower electrode 36 exposed from the lower insulating film 34 in the region between the upper electrode 35 and the lower electrode 36. The intermediate insulating film 37 is continuous with the upper insulating film 33 and the lower insulating film 34. The intermediate insulating film 37 preferably includes a silicon oxide film. Particularly preferably, the intermediate insulating film 37 includes a silicon oxide film made of an oxide of the lower electrode 36.

[0060] The intermediate insulating film 37 has an intermediate thickness TM in the normal direction Z. The intermediate thickness TM is less than the second thickness T2 of the lower insulating film 34 (TM < T2). The intermediate thickness TM may be 0.01 μm or more and 0.05 μm or less. Preferably, the intermediate thickness TM is 0.02 μm or more and 0.04 μm or less.

[0061] The pair of channel cells 31 are formed in strip shapes extending in the first direction X on both sides of each trench structure 30. The pair of channel cells 31 have a length in the first direction X that is less than the length of the trench structure 30. The entire area of ​​the pair of channel cells 31 faces the upper electrode 35 with the upper insulating film 33 interposed therebetween. Each of the pair of channel cells 31 has a channel width equivalent to 1 / 2 the trench interval IT.

[0062] The pair of channel cells 31 includes at least one n-type source region 38 formed in a surface layer portion of the body region 27. The number of source regions 38 included in the pair of channel cells 31 is arbitrary. In this embodiment, the pair of channel cells 31 each includes a plurality of source regions 38. All of the source regions 38 included in each unit cell 29 form the sources of the unit transistors 28.

[0063] The n-type impurity concentration of the source region 38 exceeds the n-type impurity concentration of the second semiconductor region 21. The n-type impurity concentration of the source region 38 is 1×10 18 cm -3 More than 1×10 21 cm -3 The source regions 38 are formed in a region on the first main surface 3 side at intervals from the bottom of the body region 27, and face the upper electrode 35 with the upper insulating film 33 interposed therebetween. The source regions 38 are arranged at intervals in the first direction X in each channel cell 31. That is, the source regions 38 are arranged at intervals along the corresponding trench structure 30 on both sides of the trench structure 30.

[0064] The pair of channel cells 31 includes at least one p-type contact region 39 formed in a region different from the source region 38 in the surface layer portion of the body region 27. The number of contact regions 39 included in the pair of channel cells 31 is arbitrary. In this embodiment, the pair of channel cells 31 each includes a plurality of contact regions 39. The p-type impurity concentration of the contact region 39 exceeds the p-type impurity concentration of the body region 27. The p-type impurity concentration of the contact region 39 is 1×1018 cm -3 More than 1×10 21 cm -3 It may be the following.

[0065] The multiple contact regions 39 are formed in a region on the first main surface 3 side at intervals from the bottom of the body region 27, and face the upper electrode 35 with the upper insulating film 33 interposed therebetween. The multiple contact regions 39 are alternately formed with the multiple source regions 38 in the first direction X so as to sandwich one source region 38 therebetween. In other words, the multiple contact regions 39 are arranged at intervals along the corresponding trench structures 30 on both sides of the trench structures 30.

[0066] The pair of channel cells 31 includes a plurality of channel regions 40 formed between the plurality of source regions 38 and the second semiconductor region 21 in the body region 27. The on / off of the plurality of channel regions 40 in the pair of channel cells 31 is controlled by a single trench structure 30. The plurality of channel regions 40 included in the pair of channel cells 31 form a single channel of a unit transistor 28. As a result, one unit cell 29 functions as one unit transistor 28.

[0067] In this embodiment, the two unit cells 29 arranged on both sides in the second direction Y in the first device region 6 do not include a source region 38 in the channel cell 31 on the trench isolation structure 22 side. With such a structure, it is possible to suppress leakage current between the trench structure 30 and the trench isolation structure 22. In this embodiment, the two unit cells 29 arranged on both sides include only a contact region 39 (hereinafter referred to as the "outermost contact region 39") in the channel cell 31 on the trench isolation structure 22 side. The outermost contact region 39 is formed at an interval from the trench isolation structure 22 toward the trench structure 30, and is connected to the sidewall of the corresponding trench structure 30. The outermost contact region 39 may be formed in a strip shape extending along the sidewall of the corresponding trench structure 30.

[0068] The semiconductor device 1 includes a third semiconductor region 41 formed in a surface layer portion of the first main surface 3 of the semiconductor chip 2. The third semiconductor region 41 is formed in the first device region 6 at a distance from the trench isolation structure 22 toward the inside. In this embodiment, the third semiconductor region 41 is formed in a surface layer portion of the second semiconductor region 21 at a distance from the boundary between the first semiconductor region 20 and the second semiconductor region 21 toward the first main surface 3. As a result, the lower portion and the outer periphery of the third semiconductor region 41 are surrounded by the second semiconductor region 21. The third semiconductor region 41 faces the first semiconductor region 20 across the second semiconductor region 21 in the normal direction Z, and faces the trench isolation structure 22 across the second semiconductor region 21 in the second direction Y and the first direction X.

[0069] The third semiconductor region 41 is of n-type, similar to the first semiconductor region 20 and the second semiconductor region 21. The third semiconductor region 41, together with the first semiconductor region 20 and the second semiconductor region 21, forms the drain of the main transistor 7 and the drain of the monitor transistor 8. The third semiconductor region 41 may be referred to as a "first drift layer", and the second semiconductor region 21 may be referred to as a "second drift layer".

[0070] The third semiconductor region 41 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region. The n-type impurity concentration of the third semiconductor region 41 is 1×10 16 cm -3 More than 1×10 19 cm -3 It may be the following.

[0071] As described above, in the semiconductor device 1, the multiple trench structures 30 are arranged at intervals in the second direction Y in a plan view, and are each formed in a strip shape extending in the first direction X. In relation to the multiple trench structures 30, the third semiconductor region 41 is formed so as to surround the side walls and bottom walls of the multiple trench structures 30. The third semiconductor region 41 covers the side walls and bottom walls of the multiple trench structures 30, and may be exposed from the side walls and bottom walls of the multiple trench structures 30 and in contact with the upper insulating film 33 and the lower insulating film 34.

[0072] The third semiconductor region 41 may cover all the side walls and bottom walls of the multiple trench structures 30, or may selectively cover some of the multiple trench structures 30. For example, the third semiconductor region 41 has an outer circumferential end portion 42 at a position via one or more trench structures 30 from the trench isolation structure 22. In other words, the side walls and bottom walls of the one or more trench structures 30 interposed between the third semiconductor region 41 and the trench isolation structure 22 are not covered by the third semiconductor region 41, but are covered by the second semiconductor region 21.

[0073] The position of the outer circumferential end 42 of the third semiconductor region 41 may be between adjacent trench structures 30. The position of the outer circumferential end 42 may coincide with the position of the sidewall of the outermost trench structure 30 of the multiple trench structures 30 covered with the third semiconductor region 41. The position of the outer circumferential end 42 may coincide with the position of the sidewall of the innermost trench structure 30 of the multiple trench structures 30 that is not covered with the third semiconductor region 41. The trench structure 30 covered with the third semiconductor region 41 may be selected arbitrarily. For example, the trench structure 30 covered with the third semiconductor region 41 may be continuous or discontinuous in the second direction Y.

[0074] In this embodiment, the third semiconductor region 41 continuously covers the sidewalls and bottom wall of the trench structures 30 except for the trench structures 30 on both ends adjacent to the trench isolation structure 22 .

[0075] The third semiconductor region 41 has a base portion 43 in contact with the bottom walls of the multiple trench structures 30, and multiple protruding portions 44 that protrude from the base portion 43 toward the first main surface 3 and in contact with the side walls of the trench structures 30. The protruding portions 44 are in contact with the body region 27 and form a boundary with the body region 27.

[0076] The lower part of the base portion 43 and the outer peripheral end 42 of the protruding portion 44 are surrounded by the second semiconductor region 21. The base portion 43 and the second semiconductor region 21 form a boundary with a space between them and the bottom wall of the trench 32 and the first semiconductor region 20. The protruding portion 44 and the second semiconductor region 21 form a boundary with a space between them and a pair of opposing lower insulating films 34. The boundary between the protruding portion 44 and the second semiconductor region 21 is preferably located at the center of the pair of opposing lower insulating films 34.

[0077] The main transistor 7 includes two (n=2) system transistors 7A, 7B formed collectively in the first device region 6. The two system transistors 7A, 7B include a first system transistor 7A and a second system transistor 7B. The first system transistor 7A includes a plurality of (22 in this embodiment) first unit transistors 28A selectively organized as individual control targets from the plurality of unit transistors 28.

[0078] The second system of transistors 7B includes a plurality of second unit transistors 28B (22 in this embodiment) selectively systematized as targets for individual control from the plurality of unit transistors 28 excluding the first unit transistors 28A. The number of second unit transistors 28B may be different from the number of first unit transistors 28A. The number of second unit transistors 28B is preferably equal to the number of first unit transistors 28A.

[0079] For example, the "unit cell 29", "trench structure 30", "channel cell 31", "trench 32", "upper insulating film 33", "lower insulating film 34", "upper electrode 35", "lower electrode 36", "intermediate insulating film 37", "source region 38", "contact region 39", and "channel region 40" of the first unit transistor 28A may be referred to as the "first unit cell 29A", "first trench structure 30A", "first channel cell 31A", "first trench 32A", "first upper insulating film 33A", "first lower insulating film 34A", "first upper electrode 35A", "first lower electrode 36A", "first intermediate insulating film 37A", "first source region 38A", "first contact region 39A", and "first channel region 40A", respectively. Of these, only the first unit cell 29A is shown, and the others are omitted, for clarity of the drawings.

[0080] The "unit cell 29", "trench structure 30", "channel cell 31", "trench 32", "upper insulating film 33", "lower insulating film 34", "upper electrode 35", "lower electrode 36", "intermediate insulating film 37", "source region 38", "contact region 39", and "channel region 40" of the second unit transistor 28B may be referred to as the "second unit cell 29B", "second trench structure 30B", "second channel cell 31B", "second trench 32B", "second upper insulating film 33B", "second lower insulating film 34B", "second upper electrode 35B", "second lower electrode 36B", "second intermediate insulating film 37B", "second source region 38B", "second contact region 39B", and "second channel region 40B", respectively. Of these, only the second unit cell 29B is shown, and the others are omitted, for clarity of the drawings.

[0081] Each of the first system transistors 7A is composed of α (α≧2) first unit transistors 28A (first unit cells 29A) arranged adjacent to each other on the first main surface 3 in a plan view. The multiple first system transistors 7A are arranged at intervals in the second direction Y in a plan view.

[0082] Each of the second system transistors 7B is composed of β (β≧2) second unit transistors 28B (second unit cells 29B) arranged adjacent to each other on the first main surface 3 in a plan view. The second system transistors 7B are arranged adjacent to the first system transistors 7A in a plan view. Specifically, the second system transistors 7B are arranged in regions between adjacent first system transistors 7A in a plan view. More specifically, the second system transistors 7B are arranged alternately with the first system transistors 7A along the second direction Y in a manner that sandwiches one first system transistor 7A in a plan view.

[0083] The number of first unit transistors 28A included in one first system transistor 7A may be one (α=1), and the number of second unit transistors 28B included in one second system transistor 7B may be one (β=1). In other words, the multiple second unit transistors 28B may be arranged alternately with the multiple first unit transistors 28A in a manner that sandwiches one unit transistor 28 between them in a plan view.

[0084] In each first unit cell 29A, the multiple contact regions 39 formed in one channel cell 31 may face the multiple contact regions 39 formed in the other channel cell 31 across the corresponding trench structure 30. In each first system transistor 7A, the multiple contact regions 39 arranged on one trench structure 30 side may face a region between the multiple contact regions 39 arranged on the other trench structure 30 side in the second direction Y.

[0085] In each of the first system transistors 7A, the contact regions 39 formed in the region between the pair of trench structures 30 may be arranged to be shifted from one another in the first direction X in a plan view. The contact regions 39 may face the source regions 38 in the second direction Y in a plan view.

[0086] In each second unit cell 29B, the multiple contact regions 39 formed in one channel cell 31 may face the multiple contact regions 39 formed in the other channel cell 31 across the corresponding trench structure 30. In each second system transistor 7B, the multiple contact regions 39 arranged on one trench structure 30 side may face a region between the multiple contact regions 39 arranged on the other trench structure 30 side in the second direction Y.

[0087] In each second system transistor 7B, the contact regions 39 formed in the region between the pair of trench structures 30 may be arranged to be shifted from each other in the first direction X in a plan view. The contact regions 39 may face the source regions 38 in the second direction Y in a plan view.

[0088] The main transistor 7 includes a plurality of pairs (11 pairs in this embodiment, a total of 22) of first trench connection structures 45 formed on the first main surface 3 in the first device region 6. The plurality of pairs of first trench connection structures 45 each include a first trench connection structure 45 on one side (the first side surface 5A side) and a first trench connection structure 45 on the other side (the second side surface 5B side) that face each other with a corresponding first system transistor 7A therebetween in the first direction X.

[0089] The first trench connection structures 45 on one side and the other side connect the ends of the multiple (a pair in this embodiment) trench structures 30 in an arch shape in plan view. The pair of first trench connection structures 45 constitute one annular trench structure together with the multiple (a pair in this embodiment) trench structures 30 constituting one first system transistor 7A.

[0090] The first trench connection structure 45 has a connection width WC and a connection depth DC. The connection width WC is a width in a direction perpendicular to the direction in which the first trench connection structure 45 extends. The connection width WC is preferably approximately equal to the trench width W of the trench structure 30 (WC≈W). The connection depth DC is preferably approximately equal to the trench depth D of the trench structure 30 (DC≈D). The aspect ratio DC / WC of the first trench connection structure 45 is preferably approximately equal to the aspect ratio D / W of the trench structure 30 (DC / WC≈D / W). The bottom wall of the first trench connection structure 45 is preferably spaced from the bottom of the second semiconductor region 21 by a distance of 1 μm or more and 5 μm or less. Note that the connection width WC may be wider than the trench width W (WC>W), and the connection depth DC may be deeper than the trench depth D (DC>D).

[0091] The first trench connection structure 45 has a single electrode structure including a first connection trench 46, a first connection insulating film 47, a first connection electrode 48, and a first cap insulating film 49. The first connection trench 46 extends in an arch shape so as to communicate with ends of the multiple trenches 32 in a plan view, and is dug down from the first main surface 3 toward the second main surface 4. The first connection trench 46 is formed at an interval from the bottom of the second semiconductor region 21 toward the first main surface 3.

[0092] The first connection trench 46 includes a sidewall and a bottom wall. The angle that the sidewall of the first connection trench 46 forms with the first main surface 3 in the semiconductor chip 2 may be 90° or more and 92° or less. The first connection trench 46 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the first connection trench 46 are preferably formed in a curved shape. The entire bottom wall of the first connection trench 46 may be formed in a curved shape toward the second main surface 4. The sidewall and bottom wall of the first connection trench 46 are smoothly connected to the sidewall and bottom wall of the trench 32.

[0093] The first connection insulating film 47 is formed on the wall surface of the first connection trench 46. Specifically, the first connection insulating film 47 is formed in a film shape over the entire wall surface of the first connection trench 46, and partitions a recessed space within the first connection trench 46. The first connection insulating film 47 is connected to the upper insulating film 33 and the lower insulating film 34 at the communication portion of the first connection trench 46 and the trench 32. The first connection insulating film 47 includes a silicon oxide film. It is particularly preferable that the first connection insulating film 47 includes a silicon oxide film made of the oxide of the semiconductor chip 2.

[0094] The first connection insulating film 47 has a third thickness T3. The third thickness T3 is the thickness along the normal direction of the wall surface of the first connection trench 46. The third thickness T3 exceeds the first thickness T1 of the upper insulating film 33 (T1 < T3). The third thickness T3 may be approximately equal to the second thickness T2 of the lower insulating film 34 (T2 ≒ T3). The third thickness T3 may be approximately equal to the separation thickness TI of the separation insulating film 24 (T3 ≒ TI). The third thickness T3 may be 0.1 μm or more and 1 μm or less. Preferably, the third thickness T3 is 0.15 μm or more and 0.65 μm or less. In the first connection insulating film 47, the thickness of the portion covering the bottom wall of the first connection trench 46 may be less than the thickness of the portion covering the side wall of the first connection trench 46.

[0095] The first connection electrode 48 is embedded in the first connection trench 46 as an integral body with the first connection insulating film 47 interposed therebetween. In this form, the first connection electrode 48 includes conductive polysilicon. The first connection electrode 48 is connected to the lower electrode 36 at the communication portion of the first connection trench 46 and the trench 32.

[0096] The first connection electrode 48 is electrically insulated from the upper electrode 35 with the intermediate insulating film 37 interposed therebetween. That is, the first connection electrode 48 is composed of a lead-out portion led out from the trench 32 to the first connection trench 46 with the first connection insulating film 47 and the intermediate insulating film 37 interposed therebetween at the lower electrode 36.

[0097] The first connection electrode 48 has an electrode surface (first connection electrode surface) exposed from the first connection trench 46. The electrode surface of the first connection electrode 48 may be recessed in a curved shape toward the bottom wall of the first connection trench 46.

[0098] The first cap insulating film 49 covers the electrode surface of the first connecting electrode 48 in the first connecting trench 46 in the form of a film. The first cap insulating film 49 suppresses the first connecting electrode 48 from being short-circuited with other electrodes. The first cap insulating film 49 is continuous with the first connecting insulating film 47. The first cap insulating film 49 preferably includes a silicon oxide film. It is particularly preferable that the first cap insulating film 49 includes a silicon oxide film made of an oxide of the first connecting electrode 48. In other words, it is preferable that the first cap insulating film 49 includes an oxide of polysilicon, and the first connecting insulating film 47 includes an oxide of silicon single crystal.

[0099] The main transistor 7 includes a plurality of pairs (11 pairs in this embodiment, a total of 22) of second trench connection structures 50 formed on the first main surface 3 in the first device region 6. The plurality of pairs of second trench connection structures 50 each include a second trench connection structure 50 on one side (the first side surface 5A side) and a second trench connection structure 50 on the other side (the second side surface 5B side) that face each other with a corresponding second system transistor 7B interposed therebetween in the first direction XY.

[0100] The second trench connection structures 50 on one side and the other side connect, in a plan view, the ends of a plurality (a pair in this embodiment) of trench structures 30 in an arch shape. The pair of second trench connection structures 50 constitute one annular trench structure together with the plurality (a pair in this embodiment) of trench structures 30 constituting one second system transistor 7B.

[0101] The second trench connection structure 50 has a connection width WC and a connection depth DC, similar to each of the first trench connection structures 45. The second trench connection structure 50 has a single electrode structure including a second connection trench 51, a second connection insulating film 52, a second connection electrode 53, and a second cap insulating film 54. The second connection trench 51 extends in an arch shape so as to communicate with the ends of the multiple trenches 32 in a plan view, and is dug down from the first main surface 3 toward the second main surface 4. The second connection trench 51 is formed at an interval from the bottom of the second semiconductor region 21 toward the first main surface 3.

[0102] The second connection trench 51 includes a side wall and a bottom wall. The angle that the side wall of the second connection trench 51 forms with the first main surface 3 in the semiconductor chip 2 may be 90° or more and 92° or less. The second connection trench 51 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the second connection trench 51 are preferably formed in a curved shape. The entire bottom wall of the second connection trench 51 may be formed in a curved shape toward the second main surface 4. The side wall and the bottom wall of the second connection trench 51 are smoothly connected to the side wall and the bottom wall of the trench 32.

[0103] The second connection insulating film 52 is formed on the wall surface of the second connection trench 51. Specifically, the second connection insulating film 52 is formed in a film shape on the entire wall surface of the second connection trench 51, and defines a recess space in the second connection trench 51. The second connection insulating film 52 is connected to the upper insulating film 33 and the lower insulating film 34 at the communicating portion between the second connection trench 51 and the trench 32. The second connection insulating film 52 includes a silicon oxide film. It is particularly preferable that the second connection insulating film 52 includes a silicon oxide film made of an oxide of the semiconductor chip 2. The second connection insulating film 52 has a third thickness T3, similar to the first connection insulating film 47.

[0104] The second connection electrode 53 is embedded as a single unit in the second connection trench 51 with the second connection insulating film 52 sandwiched therebetween. In this embodiment, the second connection electrode 53 includes conductive polysilicon. The second connection electrode 53 is connected to the lower electrode 36 at the communicating portion between the second connection trench 51 and the trench 32.

[0105] The second connection electrode 53 is electrically insulated from the upper electrode 35 with the intermediate insulating film 37 sandwiched therebetween. In other words, the second connection electrode 53 is composed of an extension portion that is extended from the trench 32 to the second connection trench 51 in the lower electrode 36 with the second connection insulating film 52 and the intermediate insulating film 37 sandwiched therebetween.

[0106] The second connection electrode 53 has an electrode surface (second connection electrode surface) exposed from the second connection trench 51. The electrode surface of the second connection electrode 53 may be recessed toward the bottom wall of the second connection trench 51 in a curved shape.

[0107] The second cap insulating film 54 covers the electrode surface (second connecting electrode surface) of the second connecting electrode 53 in the second connecting trench 51 in the form of a film. The second cap insulating film 54 suppresses the second connecting electrode 53 from being short-circuited with another electrode. The second cap insulating film 54 is continuous with the second connecting insulating film 52. The second cap insulating film 54 preferably includes a silicon oxide film. It is particularly preferable that the second cap insulating film 54 includes a silicon oxide film made of an oxide of the second connecting electrode 53. In other words, it is preferable that the second cap insulating film 54 includes an oxide of polysilicon, and the second connecting insulating film 52 includes an oxide of silicon single crystal.

[0108] Fig. 11 is an enlarged view of region XI shown in Fig. 4. Fig. 12 is a cross-sectional view taken along line XII-XII shown in Fig. 11. Fig. 13 is a cross-sectional view taken along line XIII-XIII shown in Fig. 11.

[0109] 11 to 13, the semiconductor device 1 includes two systems (m=n=2) of monitor transistors 8 formed on the first main surface 3 of the first device region 6. As shown in FIG. 4, the monitor transistors 8 are formed together with the main transistors 7 on the first main surface 3 of the first device region 6. The monitor transistors 8 are formed in an inner part (preferably a central part) of the first device region 6 at a distance from the trench isolation structure 22 in a plan view. The monitor transistors 8 are preferably arranged so as to be sandwiched between a plurality of unit transistors 28 in the first direction X in a plan view.

[0110] In this embodiment, the monitor transistor 8 includes a plurality of (four in this embodiment) unit monitor transistors 55 formed on the first main surface 3 of the first device region 6. That is, the plurality of unit monitor transistors 55 are formed together with the plurality of unit transistors 28 on the first main surface 3 of the first device region 6. The number of unit monitor transistors 55 is arbitrary, but it is preferable that there be an even number.

[0111] In this embodiment, the plurality of unit monitor transistors 55 include a plurality (two in this embodiment) of systemized first unit monitor transistors 55A and a plurality (two in this embodiment) of systemized second unit monitor transistors 55B. That is, the plurality of first unit monitor transistors 55A constitute the first system monitor transistors 12A, and the plurality of second unit monitor transistors 55B constitute the second system monitor transistors 12B.

[0112] The following describes the configuration of the first unit monitor transistor 55 A. The configuration of the second unit monitor transistor 55 B is similar to that of the first unit monitor transistor 55 A, so a description thereof will be omitted.

[0113] The multiple first unit monitor transistors 55A are arranged in a line in the second direction Y in plan view, and are each formed in a band shape extending in the first direction X. The multiple first unit monitor transistors 55A are formed in a stripe shape extending in the first direction X in plan view. It is preferable that the multiple first unit monitor transistors 55A are formed using partial regions of the multiple first unit transistors 28A.

[0114] That is, specifically, the multiple first unit monitor transistors 55A are preferably incorporated into some of the multiple first unit transistors 28A. In this embodiment, the multiple first unit monitor transistors 55A separate one first unit transistor 28A into a region on one side and a region on the other side in the second direction Y in a plan view, and are located on an extension of the region on one side and the region on the other side of the first unit transistor 28A.

[0115] Specifically, each of the multiple first unit monitor transistors 55A is composed of a unit monitor cell 56. Each unit monitor cell 56 includes one monitor trench structure 57 and a monitor channel cell 58 controlled by the monitor trench structure 57. The monitor trench structure 57 may be referred to as a "monitor gate structure" or a "monitor trench gate structure."

[0116] The multiple monitor trench structures 57 are arranged at intervals in the second direction Y in a plan view, and are each formed in a band shape extending in the first direction X. That is, the multiple monitor trench structures 57 are formed in a stripe shape extending in the first direction X in a plan view. The multiple monitor trench structures 57 are each connected to the multiple first trench structures 30A in a one-to-one correspondence with respect to the first direction X.

[0117] The following describes the configuration of one monitor trench structure 57. The monitor trench structure 57 has a multi-electrode structure including a monitor trench 59, an upper monitor insulating film 60, a lower monitor insulating film 61, an upper monitor electrode 62, a lower monitor electrode 63, and a middle monitor insulating film 64.

[0118] The monitor trench 59 is dug down from the first main surface 3 toward the second main surface 4, and is formed in a band shape extending in the second direction Y so as to communicate with the trench 32 in a plan view. In this embodiment, the trench 32 and the monitor trench 59 extend continuously in a band shape in the second direction Y while maintaining the same width. The integrated trench of the trench 32 and the monitor trench 59 may be collectively referred to as a first trench 65.

[0119] The monitor trench 59 penetrates the body region 27 and is formed at a distance from the bottom of the second semiconductor region 21 toward the first main surface 3.

[0120] The monitor trench 59 includes a sidewall and a bottom wall. The angle that the sidewall of the monitor trench 59 forms with the first main surface 3 in the semiconductor chip 2 may be 90° or more and 92° or less. The monitor trench 59 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the monitor trench 59 are preferably formed in a curved shape. The entire bottom wall of the monitor trench 59 may be formed in a curved shape toward the second main surface 4.

[0121] The upper monitor insulating film 60 covers the upper wall surface of the monitor trench 59. Specifically, the upper monitor insulating film 60 covers the upper wall surface located in a region on the opening side of the monitor trench 59 with respect to the bottom of the body region 27. The upper monitor insulating film 60 crosses the boundary between the second semiconductor region 21 and the body region 27. The upper monitor insulating film 60 has a portion covering the body region 27 and a portion covering the second semiconductor region 21. The covering area of ​​the upper monitor insulating film 60 with respect to the body region 27 is larger than the covering area of ​​the upper monitor insulating film 60 with respect to the second semiconductor region 21.

[0122] The upper monitor insulating film 60 is continuous with the upper insulating film 33 at the communicating portion between the trench 32 and the monitor trench 59. The upper monitor insulating film 60 forms one insulating film together with the upper insulating film 33. The upper monitor insulating film 60 preferably contains the same insulating material (silicon oxide film) as the upper insulating film 33. The upper monitor insulating film 60 is formed as a gate insulating film. Like the upper insulating film 33, the upper monitor insulating film 60 has a first thickness T1.

[0123] The lower monitor insulating film 61 covers the lower wall surface of the monitor trench 59. Specifically, the lower monitor insulating film 61 covers the lower wall surface located in a region on the bottom wall side of the monitor trench 59 with respect to the bottom of the body region 27. The lower monitor insulating film 61 defines a recess space in the region on the bottom wall side of the monitor trench 59. The lower monitor insulating film 61 is in contact with the second semiconductor region 21.

[0124] The lower monitor insulating film 61 is continuous with the lower insulating film 34 at the communicating portion between the trench 32 and the monitor trench 59. The lower monitor insulating film 61 forms one insulating film together with the lower insulating film 34. The lower monitor insulating film 61 preferably contains the same insulating material (silicon oxide film) as the lower insulating film 34. Like the lower insulating film 34, the lower monitor insulating film 61 has a second thickness T2.

[0125] The upper monitor electrode 62 is embedded in the upper side (opening side) of the monitor trench 59 with the upper monitor insulating film 60 in between. The upper monitor electrode 62 is embedded in a strip shape extending in the first direction X in a plan view. The upper monitor electrode 62 faces the body region 27 and the second semiconductor region 21 with the upper monitor insulating film 60 in between. The facing area of ​​the upper monitor electrode 62 with respect to the body region 27 is larger than the facing area of ​​the upper monitor electrode 62 with respect to the second semiconductor region 21.

[0126] The upper monitor electrode 62 is connected to the upper electrode 35 at the communicating portion between the trench 32 and the monitor trench 59. The upper monitor electrode 62 forms one electrode with the upper electrode 35. The upper monitor electrode 62 preferably contains the same electrode material (conductive polysilicon) as the upper electrode 35. The upper monitor electrode 62 is formed as a gate electrode.

[0127] A gate signal is input to the upper monitor electrode 62 via the upper electrode 35. The upper monitor electrode 62 has an electrode surface (buried monitor electrode surface) exposed from the monitor trench 59. The electrode surface of the upper monitor electrode 62 may be recessed in a curved shape toward the bottom wall of the monitor trench 59. It is preferable that the electrode surface of the upper monitor electrode 62 is located closer to the bottom wall of the monitor trench 59 than the depth position of the electrode surface of the separation electrode 25 in the depth direction of the monitor trench 59.

[0128] The lower monitor electrode 63 is embedded in the lower side (bottom wall side) of the monitor trench 59 with the lower monitor insulating film 61 in between. The lower monitor electrode 63 is embedded in a strip shape extending in the first direction X in a plan view. The lower monitor electrode 63 has a thickness (length) that exceeds the thickness (length) of the upper monitor electrode 62 in the depth direction of the monitor trench 59. The lower monitor electrode 63 faces the second semiconductor region 21 with the lower monitor insulating film 61 in between. The lower monitor electrode 63 has an upper end that protrudes from the lower monitor insulating film 61 towards the first main surface 3 side.

[0129] The upper end of the lower monitor electrode 63 engages with the bottom of the upper monitor electrode 62 and faces the upper monitor insulating film 60 across the bottom of the upper monitor electrode 62 in the lateral direction along the first main surface 3. The lower monitor electrode 63 is connected to the lower electrode 36 at the communicating portion between the trench 32 and the monitor trench 59. The lower monitor electrode 63 forms one electrode with the lower electrode 36. The lower monitor electrode 63 preferably contains the same electrode material (conductive polysilicon) as the lower electrode 36. In this embodiment, the lower monitor electrode 63 is formed as a gate electrode. A gate signal is input to the lower monitor electrode 63 via the lower electrode 36.

[0130] Intermediate monitor insulating film 64 is interposed between upper monitor electrode 62 and lower monitor electrode 63, and electrically insulates upper monitor electrode 62 from lower monitor electrode 63. Specifically, intermediate monitor insulating film 64 covers lower monitor electrode 63 exposed from lower monitor insulating film 61 in the region between upper monitor electrode 62 and lower monitor electrode 63. Intermediate monitor insulating film 64 is continuous with upper monitor insulating film 60 and lower monitor insulating film 61.

[0131] The intermediate monitor insulating film 64 is continuous with the intermediate insulating film 37 at the communicating portion between the trench 32 and the monitor trench 59. The intermediate monitor insulating film 64 preferably contains the same insulating material (silicon oxide film) as the intermediate insulating film 37. The intermediate monitor insulating film 64 has an intermediate thickness TM, similar to the intermediate insulating film 37. In this manner, the monitor trench structure 57 is formed in a manner that can be regarded as a part of the trench structure 30.

[0132] In this embodiment, the monitor channel cell 58 is formed in a strip shape extending along the corresponding monitor trench structure 57 in a region partitioned by the two monitor trench structures 57. The monitor channel cell 58 has a length in the first direction X that is less than the length of the monitor trench structure 57. The entire area of ​​the monitor channel cell 58 faces the upper monitor electrode 62 with the upper monitor insulating film 60 interposed therebetween. The monitor channel cell 58 has a channel width equivalent to 1 / 2 the trench interval IT.

[0133] The monitor channel cell 58 includes at least one n-type monitor source region 66 formed in a surface layer portion of the body region 27. The number of monitor source regions 66 included in the monitor channel cell 58 is arbitrary. In this embodiment, the monitor channel cell 58 includes a plurality of monitor source regions 66.

[0134] The n-type impurity concentration of the multiple monitor source regions 66 is approximately equal to the n-type impurity concentration of the source region 38. The multiple monitor source regions 66 are formed in a region on the first main surface 3 side at intervals from the bottom of the body region 27, and face the upper monitor electrode 62 with the upper monitor insulating film 60 in between. The multiple monitor source regions 66 are arranged at intervals in the first direction X in the monitor channel cell 58. That is, the multiple monitor source regions 66 are arranged at intervals along the corresponding monitor trench structures 57.

[0135] The monitor channel cell 58 includes at least one p-type monitor contact region 67 formed in a region different from the monitor source region 66 in the surface layer portion of the body region 27. The number of monitor contact regions 67 included in the monitor channel cell 58 is arbitrary. In this embodiment, the monitor channel cell 58 includes a plurality of monitor contact regions 67. The p-type impurity concentration of the monitor contact region 67 is approximately equal to the p-type impurity concentration of the contact region 39.

[0136] The multiple monitor contact regions 67 are formed in a region on the first main surface 3 side at intervals from the bottom of the body region 27, and face the upper monitor electrode 62 across the upper monitor insulating film 60. The multiple monitor contact regions 67 are formed alternately with the multiple monitor source regions 66 in the first direction X so as to sandwich one monitor source region 66 therebetween. In other words, the multiple monitor contact regions 67 are arranged at intervals along the corresponding monitor trench structures 57.

[0137] The monitor channel cell 58 includes a plurality of monitor channel regions 68 formed between a plurality of monitor source regions 66 and the second semiconductor region 21 in the body region 27. The on / off of the plurality of monitor channel regions 68 in the monitor channel cell 58 is controlled by one monitor trench structure 57. The plurality of monitor channel regions 68 included in the monitor channel cell 58 form one channel of the first unit monitor transistor 55A. Thus, one unit monitor cell 56 functions as one first unit monitor transistor 55A.

[0138] The monitor transistor 8 includes a plurality of monitor trench connection structures 69 (a pair, two in total, in this embodiment) formed on the first main surface 3 in the first device region 6. The plurality of monitor trench connection structures 69 are formed in a region between two monitor trench structures 57 constituting the first system transistor 7A. The plurality of monitor trench connection structures 69 are formed at intervals so as to sandwich the monitor channel cell 58 from the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y.

[0139] The multiple monitor trench connection structures 69 are connected to the two monitor trench structures 57 constituting the first system transistor 7A, and electrically isolate the monitor channel cell 58 from the channel cell 31. That is, the multiple monitor trench connection structures 69 separate the region sandwiched by the two monitor trench structures 57 from the region sandwiched by the two trench structures 30. That is, the multiple monitor trench connection structures 69 divide the first system transistor 7A into three regions.

[0140] As a result, the first system transistor 7A is physically separated into a first mesa portion 70 in which the unit cell 29 (main transistor 7) is formed, and a second mesa portion 71 in which the unit monitor cell 56 (monitor transistor 8) is formed. The second mesa portion 71 faces the first mesa portion 70 on both sides in the first direction X, with the monitor trench connection structure 69 interposed therebetween.

[0141] The multiple monitor trench connection structures 69 and the multiple monitor trench structures 57 form an annular trench structure. Like the trench structure 30, each monitor trench connection structure 69 has a trench width W and a trench depth D. The trench width W of the monitor trench connection structure 69 is the width of the monitor trench connection structure 69 in the first direction X.

[0142] Each monitor trench connection structure 69 has a multi-electrode structure including a monitor connection trench 72 , an upper monitor connection insulating film 73 , a lower monitor connection insulating film 74 , an upper monitor connection electrode 75 , a lower monitor connection electrode 76 and a middle monitor connection insulating film 77 .

[0143] Monitor connection trench 72, upper monitor connection insulating film 73, lower monitor connection insulating film 74, upper monitor connection electrode 75, lower monitor connection electrode 76, and intermediate monitor connection insulating film 77 have structures corresponding to monitor trench 59, upper monitor insulating film 60, lower monitor insulating film 61, upper monitor electrode 62, lower monitor electrode 63, and intermediate monitor insulating film 64 of monitor trench structure 57. Structures in monitor trench connection structure 69 that differ from monitor trench structure 57 will be described below.

[0144] The monitor connection trench 72 communicates with the monitor trench 59. That is, the monitor connection trench 72 also communicates with the trench 32. The upper monitor connection insulating film 73 is connected to the upper insulating film 33 and the upper monitor insulating film 60 at the communicating portion between the monitor trench 59 and the monitor connection trench 72. The lower monitor connection insulating film 74 is connected to the lower insulating film 34 and the lower monitor insulating film 61 at the communicating portion between the monitor trench 59 and the monitor connection trench 72.

[0145] The upper monitor connection electrode 75 is connected to the upper electrode 35 and the upper monitor electrode 62 at the communicating portion between the monitor trench 59 and the monitor connection trench 72. The lower monitor connection electrode 76 is connected to the lower electrode 36 and the lower monitor electrode 63 at the communicating portion between the monitor trench 59 and the monitor connection trench 72. The intermediate monitor connection insulating film 77 is connected to the intermediate insulating film 37 and the intermediate monitor insulating film 64 at the communicating portion between the monitor trench 59 and the monitor connection trench 72.

[0146] That is, in this embodiment, the trench structure 30, the monitor trench structure 57, and the monitor trench connecting structure 69 are integrally formed to form one integral trench structure 78 that is continuous with one another.

[0147] The monitor connection trench 72 perpendicular to the first trench 65, which is an integral trench of the trench 32 and the monitor trench 59, may be referred to as a second trench 79 in contrast to the first trench 65. In the integral trench structure 78, the connection portion between the first trench 65 and the second trench 79 is a T-shaped connection portion 80.

[0148] The T-shaped connection portion 80 may be, for example, a region surrounded by imaginary lines 81, 82 of one side wall of the first trench 65, an extension line of the other side wall of the first trench 65 (a first imaginary line 81 crossing the second trench 79 in the first direction X), and an extension line of one side wall and the other side wall of the second trench 79 (a second imaginary line 82 crossing the first trench 65 in the second direction Y, respectively).

[0149] The first virtual line 81 may be a straight line connecting the corners of the first mesa portion 70 and the second mesa portion 71. The first mesa portion 70 and the second mesa portion 71 each have a pair of corners 83, 84 facing each other in the first direction X with the second trench 79 in between. The pair of corners of the first mesa portion 70 may be referred to as first corners 83, and the pair of corners of the second mesa portion 71 may be referred to as second corners 84. The first virtual line 81 connects the first corners 83 and the second corners 84 at both ends of the second trench 79 in the second direction Y.

[0150] The second virtual line 82 may be a straight line extending from the first corner 83 and the second corner 84 toward one side wall of the first trench 65. The second virtual line 82 crosses the first trench 65 in the second direction Y and connects the first corner 83 and the second corner 84 to one side wall of the first trench 65.

[0151] The semiconductor device 1 includes a body space 85 formed along the inner edge (inner peripheral wall) of the trench isolation structure 22 in the first device region 6. The body space 85 is made of a part of the body region 27. The body space 85 is formed in a band shape extending along the main transistor 7 in a plan view. Specifically, the body space 85 is formed in a ring shape surrounding the main transistor 7 in a plan view.

[0152] The semiconductor device 1 includes a field insulating film 86 that partially covers the first main surface 3 in the first device region 6. The field insulating film 86 is formed on the trench isolation structure 22 side at an interval from the main transistor 7 in a plan view, and covers the periphery of the trench isolation structure 22. That is, the field insulating film 86 covers the body space 85 (body region 27). The field insulating film 86 faces the second semiconductor region 21 (first semiconductor region 20) at the periphery of the first device region 6 with the body space 85 (body region 27) in between. The field insulating film 86 includes a silicon oxide film. It is particularly preferable that the field insulating film 86 includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0153] The field insulating film 86 is formed in a band shape extending along the inner edge (inner wall) of the trench isolation structure 22 in a plan view. In this embodiment, the field insulating film 86 is formed in a ring shape extending along the inner wall of the trench isolation structure 22 in a plan view, and surrounds the inner part of the first device region 6 over the entire circumference. The field insulating film 86 has a side extending in one direction (first direction X) in a plan view, and a side extending in an intersecting direction (second direction Y) intersecting the one direction. The field insulating film 86 is continuous with the isolation insulating film 24 on the inner edge (inner wall) side of the trench isolation structure 22. The first device region 6 is partitioned by the trench isolation structure 22 in the semiconductor chip 2, and is partitioned by the field insulating film 86 on the semiconductor chip 2.

[0154] The field insulating film 86 has a thickness that exceeds the first thickness T1 of the upper insulating film 33. The thickness of the field insulating film 86 preferably exceeds the intermediate thickness TM of the intermediate insulating film 37. The thickness of the field insulating film 86 may be approximately equal to the second thickness T2 of the lower insulating film 34. The thickness of the field insulating film 86 may be approximately equal to the isolation thickness TI of the isolation insulating film 24. The thickness of the field insulating film 86 may be 0.1 μm or more and 1 μm or less. The thickness of the field insulating film 86 is preferably 0.15 μm or more and 0.65 μm or less.

[0155] The semiconductor device 1 includes a main surface insulating film 87 that selectively covers the first main surface 3 in the first device region 6. The main surface insulating film 87 includes a silicon oxide film. It is particularly preferable that the main surface insulating film 87 includes a silicon oxide film made of an oxide of the semiconductor chip 2. The main surface insulating film 87 covers the region outside the trench structure 30, the first trench connection structure 45, the second trench connection structure 50, and the field insulating film 86 on the first main surface 3, and is continuous with the upper insulating film 33, the first connection insulating film 47, the second connection insulating film 52, and the field insulating film 86.

[0156] The main surface insulating film 87 has a thickness less than that of the field insulating film 86. The thickness of the main surface insulating film 87 is preferably one-fifth or less of the thickness of the field insulating film 86. The thickness of the main surface insulating film 87 may be approximately equal to the first thickness T1 of the upper insulating film 33. The thickness of the main surface insulating film 87 may be not less than 0.01 μm and not more than 0.05 μm. The thickness of the main surface insulating film 87 is preferably not less than 0.02 μm and not more than 0.04 μm.

[0157] The semiconductor device 1 includes the aforementioned interlayer insulating layer 12 covering the first main surface 3. The semiconductor device 1 includes a plurality of plug electrodes 88-93 embedded in the interlayer insulating layer 12. The plurality of plug electrodes 88-93 include a plurality of first plug electrodes 88, a plurality of second plug electrodes 89, a plurality of third plug electrodes 90, a plurality of fourth plug electrodes 91, a plurality of fifth plug electrodes 92, and at least one (one in this embodiment) sixth plug electrode 93. The plurality of plug electrodes 88-93 may be made of tungsten plug electrodes. In some of the accompanying drawings, the plurality of plug electrodes 88-93 are simply shown by X marks or lines.

[0158] Each of the multiple first plug electrodes 88 is made of a source plug electrode for the isolation electrode 25. The multiple first plug electrodes 88 are embedded in a portion of the interlayer insulating layer 12 that covers the trench isolation structure 22. The multiple first plug electrodes 88 are embedded at intervals along the isolation electrode 25 and are each electrically connected to the isolation electrode 25. The multiple first plug electrodes 88 may be arranged or have any shape. One or more first plug electrodes 88 extending in a strip or ring shape in a plan view may be formed on the isolation electrode 25.

[0159] The second plug electrodes 89 are each composed of a gate plug electrode for the upper electrodes 35. The second plug electrodes 89 are each embedded in a portion of the interlayer insulating layer 12 that covers the trench structures 30. In this embodiment, the second plug electrodes 89 are electrically connected to both ends of the upper electrodes 35, respectively. The second plug electrodes 89 may be arranged or shaped as desired. One or more second plug electrodes 89 extending in a strip shape along the upper electrode 35 in a plan view may be formed on each upper electrode 35.

[0160] The multiple third plug electrodes 90 are each composed of a source plug electrode for the multiple channel cells 31. The multiple third plug electrodes 90 are embedded in a portion of the interlayer insulating layer 12 that covers the multiple channel cells 31. The multiple third plug electrodes 90 are electrically connected to the multiple source regions 38 and the multiple contact regions 39, respectively. The multiple third plug electrodes 90 may be arranged or have any shape.

[0161] The multiple fourth plug electrodes 91 are each composed of a source plug electrode for the multiple outermost contact regions 39. The multiple fourth plug electrodes 91 are embedded in the interlayer insulating layer 12 in a portion covering the multiple outermost contact regions 39. The multiple fourth plug electrodes 91 are embedded at intervals along each of the outermost contact regions 39 and are electrically connected to each of the outermost contact regions 39. The multiple fourth plug electrodes 91 may be arranged or shaped as desired. One or more fourth plug electrodes 91 extending in a strip shape along the outermost contact region 39 in a plan view may be formed on each of the outermost contact regions 39.

[0162] The plurality of fifth plug electrodes 92 are each composed of a gate plug electrode for the plurality of first connection electrodes 48 and the second connection electrodes 53. The plurality of fifth plug electrodes 92 are embedded in a portion of the interlayer insulating layer 12 that covers the plurality of first connection electrodes 48 and the second connection electrodes 53. Each of the fifth plug electrodes 92 is electrically connected to the plurality of first connection electrodes 48 and the second connection electrodes 53. The arrangement and shape of the plurality of fifth plug electrodes 92 are arbitrary. One or more fifth plug electrodes 92 extending in a strip shape along the plurality of first connection electrodes 48 and the second connection electrodes 53 in a plan view may be formed on the plurality of first connection electrodes 48 and the second connection electrodes 53.

[0163] The sixth plug electrode 93 is a source plug electrode for the monitor channel cell 58. The sixth plug electrode 93 is embedded in a portion of the interlayer insulating layer 12 that covers the monitor channel cell 58. The sixth plug electrode 93 is electrically connected to the plurality of monitor source regions 66 and the plurality of monitor contact regions 67. The sixth plug electrode 93 may be arranged or shaped as desired. The plurality of sixth plug electrodes 93 may be arranged at intervals along the monitor channel cell 58 in a plan view.

[0164] The semiconductor device 1 includes one or more main source wirings 94 arranged in the interlayer insulating layer 12. The one or more main source wirings 94 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more main source wirings 94 are selectively routed in the interlayer insulating layer 12, electrically connected to the separation electrode 25 via a plurality of first plug electrodes 88, and electrically connected to the source region 38 and the contact region 39 via a plurality of third plug electrodes 90 and a plurality of fourth plug electrodes 91. The one or more main source wirings 94 are electrically connected to the source terminal 15 described above.

[0165] The semiconductor device 1 includes one or more monitor source wirings 95 arranged in the interlayer insulating layer 12. The one or more monitor source wirings 95 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more monitor source wirings 95 are selectively routed in the interlayer insulating layer 12 and electrically connected to the monitor channel cell 58 via a sixth plug electrode 93.

[0166] The semiconductor device 1 includes the aforementioned n main gate wirings 11 formed in an interlayer insulating layer 12. The n main gate wirings 11 are selectively routed within the interlayer insulating layer 12. The n main gate wirings 11 are each electrically connected to one or more trench structures 30 (unit transistors 28) to be organized as individual control targets in the first device region 6, and are electrically connected to the aforementioned control IC 10 in the second device region 9.

[0167] The semiconductor device 1 includes the above-mentioned m monitor gate wirings 13 formed in the interlayer insulating layer 12. The m monitor gate wirings 13 are selectively routed within the interlayer insulating layer 12.

[0168] Next, first to fifth patterns of the shape of the T-shaped connection part 80 will be described with reference to Figs. 14 to 26. The shape of the T-shaped connection part 80 is not limited to the first to fifth patterns described below, and may be formed in various shapes. Figs. 14 to 26 mainly show reference symbols of the configurations shown in Fig. 11 that are necessary for explaining the shape of the T-shaped connection part 80, and omit reference symbols that are not particularly necessary for the explanation.

[0169] [First pattern] Fig. 14 is an enlarged view of region A shown in Fig. 11, and shows a first pattern of the T-shaped connection portion 80. Fig. 15 is a cross-sectional view taken along line XV-XV shown in Fig. 14. Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in Fig. 14. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 14. In Fig. 14, the trench portion of the semiconductor chip 2 is shown hatched, and the mesa portion is shown in white.

[0170] In the following, the trenches formed in the semiconductor chip 2 are mainly referred to as a first trench 65 formed by the integrated trench of the trench 32 and the monitor trench 59, and a second trench 79 formed by the monitor connection trench 72.

[0171] As described above, the T-shaped connection portion 80 may be a region surrounded by one side wall 101 of the first trench 65, the first imaginary line 81, and the second imaginary line 82 in a plan view.

[0172] One sidewall 101 of the first trench 65 is one of a pair of sidewalls constituting the first trench 65, and is a sidewall that extends continuously along the first direction X via the T-shaped connecting portion 80. The one sidewall 101 forms a part of the sidewall of the T-shaped connecting portion 80, and faces the second trench 79 in the second direction Y via the T-shaped connecting portion 80. The one sidewall 101 of the first trench 65 forms a first sidewall structure portion 103 that spans both the first mesa portion 70 and the second mesa portion 71 in the first direction X.

[0173] The sidewall opposite to the one sidewall 101 of the first trench 65 is the other sidewall 102 of the first trench 65. The other sidewall 102 is the sidewall of the first trench 65 separated by the second trench 79 at the T-shaped connection portion 80. In relation to the pair of first mesa portion 70 and second mesa portion 71 facing each other in the first direction X with the second trench 79 in between, the other sidewall 102 on the first mesa portion 70 side and the other sidewall 102 on the second mesa portion 71 side are formed.

[0174] The first virtual line 81 is an extension of the other sidewall 102 of the first trench 65. More specifically, the first virtual line 81 is a straight line connecting the other sidewall 102 on the first mesa portion 70 side and the other sidewall 102 on the second mesa portion 71 side. In this embodiment, the first virtual line 81 is a straight line that crosses the second trench 79 in the first direction X in a plan view and is parallel to one sidewall 101 of the first trench 65.

[0175] The second virtual line 82 may be a straight line extending from each of one sidewall 104 and the other sidewall 105 of the second trench 79 toward one sidewall 101 of the first trench 65. One sidewall 104 of the second trench 79 may be the sidewall on the first mesa portion 70 side of a pair of sidewalls constituting the second trench 79. The other sidewall 105 of the second trench 79 may be the sidewall on the second mesa portion 71 side.

[0176] Around the T-shaped connection portion 80, peripheral sidewalls 106-108 are formed by a portion of each sidewall of the first trench 65 and the second trench 79. In this embodiment, the peripheral sidewalls 106-108 of the T-shaped connection portion 80 may include a first peripheral sidewall 106 consisting of a portion of one sidewall 101 of the first trench 65, a second peripheral sidewall 107 formed by the first corner portion 83, and a third peripheral sidewall 108 formed by the second corner portion 84.

[0177] The first peripheral sidewall 106 may be, for example, a portion of one sidewall 101 of the first trench 65 that faces the second trench 79 in the second direction Y. The first peripheral sidewall 106 extends continuously between the region on the first mesa portion 70 side and the region on the second mesa portion 71 side along the first direction X via the T-shaped connection portion 80.

[0178] The second peripheral sidewall 107 may be a sidewall formed at an intersection between the other sidewall 102 on the first mesa portion 70 side of the first trench 65 and one sidewall 104 of the second trench 79. In this embodiment, the second peripheral sidewall 107 is a first corner sidewall 109 formed at the first corner portion 83 of the first mesa portion 70 facing the T-shaped connecting portion 80. The first corner sidewall 109 is formed in a substantially circular shape selectively protruding obliquely toward the T-shaped connecting portion 80 in a plan view.

[0179] More specifically, the first corner sidewall 109 is formed in a circular shape that bulges inward of the second trench 79 relative to the second virtual line 82 in the first direction X and inward of the first trench 65 relative to the first virtual line 81 in the second direction Y. The planar shape of the first corner sidewall 109 is not limited to a perfect circle as shown in Fig. 14, but may be an ellipse in a plan view or a substantially circular shape that is a slight deformation of a perfect circle. The planar shape of the first corner sidewall 109 varies in various ways depending on the etching conditions used when the first trench 65 and the second trench 79 are formed.

[0180] 16, first corner sidewall 109 is formed in a columnar shape maintaining the above-mentioned substantially circular planar shape from first main surface 3 of semiconductor chip 2 to the bottoms of first trench 65 and second trench 79. In other words, first corner sidewall 109 may be a substantially cylindrical first columnar portion 111 rising from the bottoms of first trench 65 and second trench 79.

[0181] The third peripheral sidewall 108 may be a sidewall formed at an intersection between the other sidewall 102 on the second mesa portion 71 side of the first trench 65 and the other sidewall 105 of the second trench 79. In this embodiment, the third peripheral sidewall 108 is a second corner sidewall 110 formed at the second corner portion 84 of the second mesa portion 71 facing the T-shaped connecting portion 80. The second corner sidewall 110 is formed in a substantially circular shape selectively protruding obliquely toward the T-shaped connecting portion 80 in a plan view.

[0182] More specifically, the second corner sidewall 110 is formed in a circular shape that bulges inward of the second trench 79 relative to the second virtual line 82 in the first direction X and inward of the first trench 65 relative to the first virtual line 81 in the second direction Y. The planar shape of the second corner sidewall 110 is not limited to a perfect circle as shown in Fig. 14, but may be an ellipse in a plan view or a substantially circular shape that is a slight deformation of a perfect circle. The planar shape of the second corner sidewall 110 varies in various ways depending on the etching conditions when the first trench 65 and the second trench 79 are formed.

[0183] Although not shown, the second corner sidewall 110, like the first corner sidewall 109, is formed in a columnar shape maintaining the above-mentioned substantially circular planar shape from the first main surface 3 of the semiconductor chip 2 to the bottoms of the first trench 65 and the second trench 79. In other words, the second corner sidewall 110 may be a substantially cylindrical second columnar portion 112 rising from the bottoms of the first trench 65 and the second trench 79.

[0184] The first sidewall structure 103 includes a protruding portion 113 that selectively protrudes toward the inside of the T-shaped connecting portion 80 and has an apex inside the T-shaped connecting portion 80. The protruding portion 113 forms the first peripheral sidewall 106. More specifically, the protruding portion 113 is a protruding portion sidewall 114 formed by one sidewall 101 of the first trench 65 selectively protruding toward the inside of the first trench 65. On the other hand, a portion of the one sidewall 101 of the first trench 65 other than the protruding portion sidewall 114 is a flat sidewall 115 that extends parallel to the other sidewall 102 of the first trench 65.

[0185] The protrusion 113 (protrusion side wall 114) has both ends located in portions facing the T-shaped connecting portion 80 in the first side wall structure 103. The protrusion 113 may include a pair of inclined portions 116 formed within ranges from both ends of the protrusion 113 facing the first columnar portion 111 and the second columnar portion 112, and a straight portion 117 connecting the pair of inclined portions 116 and extending parallel to the first direction X.

[0186] In this embodiment, the pair of inclined portions 116 are formed in an arc shape that protrudes toward the inside of the first trench 65. One inclined portion 116 faces the first columnar portion 111 in the second direction Y, sandwiching the T-shaped connecting portion 80 therebetween. The other inclined portion 116 faces the second columnar portion 112 in the second direction Y, sandwiching the T-shaped connecting portion 80 therebetween.

[0187] The straight portion 117 is a flat sidewall extending parallel to the other sidewall 102 of the first trench 65 from one inclined portion 116 to the other inclined portion 116. The straight portion 117 does not have an apex that is farthest from the one sidewall 101 of the first trench 65, and is formed entirely at a constant distance from the one sidewall 101. Therefore, the straight portion 117 may entirely be the apex of the protrusion 113.

[0188] When a symmetry axis 118 is defined that passes through the top (straight line portion 117) of the protrusion 113 and extends along the second direction Y, the protrusion 113 has a shape that is linearly symmetrical with respect to the symmetry axis 118. In this embodiment, since the entire straight line portion 117 is the top of the protrusion 113, the symmetry axis 118 may be a normal line to the straight line portion 117.

[0189] As described above, since the first columnar portion 111, the second columnar portion 112, and the protrusion portion 113, each of which protrudes inwardly of the trench, are formed in the T-shaped connection portion 80, the first trench 65 and the second trench 79 have selectively narrow widths in the T-shaped connection portion 80.

[0190] For example, a width WT1 of the first trench 65 in the T-shaped connection portion 80 is narrower than a first width W1 between one sidewall 101 (flat sidewall 115) and the other sidewall 102 of the first trench 65. The width WT1 may be the distance between the first columnar portion 111 and the protrusion 113 in the second direction Y. Furthermore, a width WT2 of the second trench 79 in the T-shaped connection portion 80 is narrower than a second width W2 between one sidewall 104 and the other sidewall 105 of the second trench 79. The width WT2 may be the distance between the first columnar portion 111 and the second columnar portion 112.

[0191] Since the first trench 65 and the second trench 79 have a selectively narrow width at the T-shaped connection portion 80, when the two inscribed circles, the first inscribed circle 119 and the second inscribed circle 120 shown in FIG. 14, are virtually defined, the following conditions are set.

[0192] The first inscribed circle 119 is a circle having a first radius R1 inscribed in both inner side walls of the first trench 65. In this embodiment, the first inscribed circle 119 is a circle that touches one side wall 101 (flat side wall 115) and the other side wall 102 of the first trench 65 at at least two points.

[0193] The second inscribed circle 120 is a circle having a second radius R2 inscribed in the peripheral side walls 106-108 of the T-shaped connection portion 80. In this embodiment, the second inscribed circle 120 is a circle tangent to at least three points located on one side wall 101 of the first trench 65 (straight portion 117 of the convex portion 113), the first columnar portion 111, and the second columnar portion 112.

[0194] With respect to the first inscribed circle 119 and the second inscribed circle 120, the second radius R2 is preferably 80% or more and 130% or less of the first radius R1. Furthermore, the second radius R2 is more preferably 90% or more and 110% or less of the first radius R1. In this embodiment, the second radius R2 is, for example, 80% or more and 90% or less of the first radius R1.

[0195] Fig. 18 is a diagram showing a mask pattern used when forming the T-shaped connection portion 80 of the first pattern in Fig. 14. In Fig. 18, the mask portion of the first mask 121 is shown by hatching, and the opening portion is shown by white. Note that the first mask 121 shown in Fig. 18 is for a positive photoresist 121A. When a negative photoresist is used, the mask portion (hatching) and the opening portion (white) in Fig. 18 may be reversed.

[0196] The T-shaped connection portion 80 shown in Fig. 14 can be formed, for example, by etching the semiconductor chip 2 using a photoresist 121A patterned by exposure and development through a first mask 121 shown in Fig. 18. The first mask 121 has an opening 122 corresponding to the region where the first trench 65 and the second trench 79 are to be formed. Therefore, the region where the first mesa portion 70 and the second mesa portion 71 that define the first trench 65 and the second trench 79 are to be formed is covered with the first mask 121 (photoresist 121A).

[0197] The first mask 121 has a first portion 123 and a second portion 124 which respectively cover the regions where the first mesa portion 70 and the second mesa portion 71 are to be formed. A first protrusion 126 corresponding to the first columnar portion 111 is formed at an end portion in the second direction Y of the first portion 123. A second protrusion 127 corresponding to the second columnar portion 112 is formed at an end portion in the second direction Y of the second portion 124.

[0198] Unlike the first columnar section 111 and the second columnar section 112, which are each substantially circular in plan view, the first protrusion 126 and the second protrusion 127 are each formed to be substantially rectangular in plan view. The etching gas supplied to the first main surface 3 of the semiconductor chip 2 advances in the horizontal direction of the semiconductor chip 2 in addition to the thickness direction of the semiconductor chip 2. At the corners of the first protrusion 126 and the second protrusion 127, etching advances from both the first direction X and the second direction Y, as shown by the arrows 128 in FIG. 18. As a result, the portions of the semiconductor chip 2 covered by the first protrusion 126 and the second protrusion 127 are formed to be substantially circular in plan view.

[0199] The first mask 121 further has a third portion 125 covering a region where the protrusion 113 is to be formed. A pair of corners 129 are formed at both ends of the third portion 125 in the first direction X. As with the first protrusion 126 and the second protrusion 127, etching also progresses at the corners 129 from both sides in the first direction X and the second direction Y, as shown by arrows 128 in FIG. 18. As a result, the portion of the semiconductor chip 2 covered by the corners 129 is formed into a generally arc shape in plan view.

[0200] As described above, as shown in FIG. 14, the second radius R2 of the second inscribed circle 120 is 80% or more and 130% or less of the first radius R1 of the first inscribed circle 119. This reduces the error in the trench width between the first trench 65 and the second trench 79 and the T-shaped connection portion 80, so that the error in the etching rate due to the difference in the trench width can be reduced. As a result, the error in the trench depth between the first trench 65 and the second trench 79 and the T-shaped connection portion 80 can be reduced. For example, as shown in FIG. 15, the depth of the first trench 65 and the second trench 79 can be made almost the same as the depth of the T-shaped connection portion 80. As a result, the decrease in the withstand voltage caused by the trench depth of the T-shaped connection portion 80 becoming too deep can be suppressed.

[0201] Unlike this embodiment, when the second radius R2 of the second inscribed circle 120 is considerably larger than the first radius R1 of the first inscribed circle 119, the trench width at the T-shaped connection portion 80 is substantially larger than the first width W1 of the first trench 65 and the second width W2 of the second trench 79. Therefore, the etching rate at the T-shaped connection portion 80 is selectively increased, and the T-shaped connection portion 80 is selectively deepened. As a result, the distance between the bottom of the trench at the T-shaped connection portion 80 and the drain terminal 14 becomes closer, and the breakdown voltage is likely to decrease. However, by adopting the shape of the T-shaped connection portion 80 of this embodiment, the variation in trench depth can be reduced, and the decrease in the breakdown voltage can be suppressed.

[0202] In particular, in this embodiment, since the main transistor 7 is an output transistor that controls a relatively large current, the effect of suppressing the decrease in withstand voltage is large. Also, as shown in Figures 15 to 17, when a third semiconductor region 41 with a relatively high concentration (higher concentration than the second semiconductor region as an epitaxial layer) is formed at the bottom of the first trench 65 and the second trench 79, including the T-shaped connection portion 80, the withstand voltage of the element is likely to decrease. Even when such a third semiconductor region 41 is formed, the trench depth of the T-shaped connection portion 80 is not selectively deep, so that the decrease in withstand voltage can be suppressed.

[0203] In addition, in this embodiment, the first mesa 70 and the second mesa 71 are adjacent to each other with the T-shaped connection 80 in between, which suppresses variations in trench depth around the main transistor 7 and the monitor transistor 8. This makes it possible to equalize the withstand voltages of the main transistor 7 and the monitor transistor 8, thereby improving the controllability of the transistors.

[0204] Furthermore, the first corner 83 of the first mesa 70 is a first columnar section 111 that is circular in plan view, and the second corner 84 of the second mesa 71 is a second columnar section 112 that is circular in plan view. This makes it possible to prevent the electric field from concentrating at the first corner 83 and the second corner 84. This makes it possible to further prevent a decrease in the breakdown voltage.

[0205] Moreover, the protrusion 113 is not formed over a wide area from the T-shaped connection portion 80 to the outside in the first direction X, but is contained within the range of the T-shaped connection portion 80. This makes it possible to maintain a constant trench width in the portion of the first trench 65 other than the T-shaped connection portion 80. As a result, it is possible to suppress the occurrence of variations in the depth of the first trench 65 in the portion other than the T-shaped connection portion 80.

[0206] [Second pattern] FIG. 19 is an enlarged view of the area A shown in FIG. 11, showing a second pattern of the T-shaped connector 80. As shown in FIG.

[0207] The T-shaped connection portion 80 of the second pattern differs from the first pattern in that the diameters of the first columnar portion 111 and the second columnar portion 112 in a plan view are smaller than the first columnar portion 111 and the second columnar portion 112 of the first pattern in Fig. 14. In this embodiment, the second radius R2 is, for example, 95% or more and 105% or less of the first radius R1.

[0208] This allows the widths WT1, WT2 of the T-shaped connection portion 80 to be closer to the first width W1 of the first trench 65 and the second width W2 of the second trench 79 than in the first pattern of Fig. 14. As a result, the error in the trench widths of the first trench 65 and the second trench 79, and the T-shaped connection portion 80 can be further reduced.

[0209] In the T-shaped connection portion 80 of the second pattern, the pair of inclined portions 116 of the convex portion 113 are formed as a pair of inclined surfaces 130 extending from both ends of the convex portion 113 toward the inside of the T-shaped connection portion 80. The pair of inclined surfaces 130 and the straight portion 117 are continuous with each other via a round portion 131 that is arcuate in plan view.

[0210] Fig. 20 is a diagram showing a mask pattern used when forming the T-shaped connection portion 80 of the second pattern in Fig. 19. In Fig. 20, the mask portion of the second mask 132 is shown by hatching, and the opening portion is shown by white. Note that the second mask 132 shown in Fig. 20 is for a positive photoresist 132A. When a negative photoresist is used, the mask portion (hatching) and the opening portion (white) in Fig. 20 may be reversed.

[0211] The T-shaped connection portion 80 shown in Fig. 19 can be formed, for example, by etching the semiconductor chip 2 using a photoresist 132A patterned by exposure and development through a second mask 132 shown in Fig. 20. The second mask 132 differs from the first mask 121 shown in Fig. 17 in that the corners of the first protrusion 126 and the second protrusion 127 are missing at an angle of, for example, about 45°. Similarly, the corner 129 of the third portion 125 is missing at an angle of, for example, about 45°.

[0212] This allows the first protrusion 126 and the second protrusion 127 to be close to a circular shape in plan view. If the first protrusion 126 and the second protrusion 127 are substantially circular in plan view, etching can be uniformly progressed from the periphery of the first protrusion 126 and the second protrusion 127 toward the inside even when etching proceeds in the horizontal direction. Therefore, etching can be performed in a shape that generally follows the pattern of the second mask 132. As a result, by appropriately designing the planar sizes of the first protrusion 126, the second protrusion 127, and the third portion 125, the second radius R2 of the second inscribed circle 120 can be accurately brought close to the first radius R1 of the first inscribed circle 119. In other words, the shape after etching can be easily predicted.

[0213] [Third pattern] FIG. 21 is an enlarged view of the area A shown in FIG. 11, showing a third pattern of the T-shaped joint 80. As shown in FIG.

[0214] In the T-shaped connection portion 80 of the third pattern, the first corner sidewall 109 of the first mesa portion 70 and the second corner sidewall 110 of the second mesa portion 71 are formed in a circular arc shape in plan view. Unlike the first columnar portion 111 and the second columnar portion 112 of the first and second patterns, the first corner sidewall 109 and the second corner sidewall 110 do not protrude toward the inside of the first trench 65 and the second trench 79. The first corner sidewall 109 and the second corner sidewall 110 smoothly connect the other sidewall 102 of the first trench 65 and the one sidewall 104 and the other sidewall 105 of the second trench 79. In other words, each corner of the first mesa portion 70 and the second mesa portion 71 is formed in a round shape in plan view.

[0215] Moreover, the protrusion 113 has both ends at a portion facing the T-shaped connecting portion 80, and is formed in an arc shape in a plan view that selectively protrudes toward the inside of the T-shaped connecting portion 80. In this embodiment, the substantially semicircular protrusion 113 having a diameter smaller than the second width W2 of the second trench 79 selectively protrudes from one side wall 101 of the first trench 65.

[0216] In this embodiment, the second radius R2 is, for example, 120% or more and 130% or less of the first radius R1. That is, the difference between the first radius R1 and the second radius R2 is larger than in the first and second patterns. However, unlike the first and second patterns, the first corner sidewall 109 and the second corner sidewall 110 do not have a structure that selectively protrudes, and therefore the corners of the first mesa portion 70 and the second mesa portion 71 can be formed in a simple structure. As a result, the number of places where the electric field is concentrated can be reduced, and therefore a decrease in the breakdown voltage can be sufficiently suppressed.

[0217] Furthermore, the first mesa portion 70 and the second mesa portion 71 do not have the first columnar portion 111 and the second columnar portion 112, respectively, but have the protrusion 113. Therefore, for example, the distance between the center of the T-shaped connection portion 80 (for example, near the position where the protrusion 113 is formed) and the first corner sidewall 109 and the second corner sidewall 110 can be made smaller than when the protrusion 113 is not formed. As a result, it is possible to prevent the etching rate in the T-shaped connection portion 80 from being selectively increased.

[0218] Fig. 22 is a diagram showing a mask pattern used when forming the T-shaped connection portion 80 of the third pattern in Fig. 21. The third mask 133 shown in Fig. 22 is for a positive photoresist 133A. When a negative photoresist is used, the mask portion (hatched) and the opening portion (white) in Fig. 22 may be reversed.

[0219] The T-shaped connection portion 80 shown in Fig. 21 can be formed, for example, by etching the semiconductor chip 2 using a photoresist 133A patterned by exposure and development through a third mask 133 shown in Fig. 22. The third mask 133 differs from the first mask 121 shown in Fig. 17 in that the first protrusion 126 and the second protrusion 127 are not formed at the corners 134, 135 of the first portion 123 and the second portion 124. Instead, each of the corners 134, 135 of the first portion 123 and the second portion 124 is missing at an angle of, for example, about 45°.

[0220] Moreover, the third portion 125 of the third mask 133 is formed in a generally triangular shape when viewed from above, which makes it possible to form the convex portion 113 having an arc shape when viewed from above.

[0221] [Fourth pattern] FIG. 23 is an enlarged view of the area A shown in FIG. 11, showing a fourth pattern of the T-shaped joint 80. As shown in FIG.

[0222] The T-shaped connection portion 80 of the fourth pattern is different from the third pattern in that the size of the convex portion 113 in a plan view is larger than the convex portion 113 of the third pattern in Fig. 11. More specifically, the protrusion amount P4 in the second direction Y from one side wall 101 of the first trench 65 is larger than the protrusion amount P3 in the third pattern. In terms of shape, the convex portion 113 of the fourth pattern has a pair of inclined portions 136 extending from both ends of the convex portion 113 toward the inside of the T-shaped connection portion 80, an arc-shaped round portion 137 connecting the tips of the pair of inclined portions 136, and a straight portion 138 connected to the pair of inclined portions 136 via the round portion 137.

[0223] The pair of inclined portions 136 are formed as a pair of inclined surfaces extending from both ends of the protrusion 113 toward the inside of the T-shaped connection portion 80. In addition, the straight portion 138 is a flat sidewall extending from one inclined portion 136 to the other inclined portion 136 in parallel to the other sidewall 102 of the first trench 65.

[0224] In this embodiment, the second radius R2 is, for example, 100% or more and 110% or less of the first radius R1. This allows the widths WT1, WT2 of the T-shaped connection portion 80 to be closer to the first width W1 of the first trench 65 and the second width W2 of the second trench 79 than in the third pattern. As a result, the error in the trench widths of the first trench 65 and the second trench 79, and the T-shaped connection portion 80 can be further reduced.

[0225] Furthermore, as the protrusion amount P4 of the convex portion 113 increases, the width of the mesa portion 139 sandwiched by the first trenches 65 selectively increases. Therefore, in an element that can tolerate an increase in the width of the mesa portion 139, the widths WT1, WT2 of the T-shaped connection portion 80 can be made close to the first width W1 of the first trench 65 and the second width W2 of the second trench 79, and a sufficient effect can be obtained.

[0226] Fig. 24 is a diagram showing a mask pattern used when forming the T-shaped connection portion 80 of the fourth pattern in Fig. 23. The fourth mask 140 shown in Fig. 24 is for a positive photoresist 140A. When a negative photoresist is used, the mask portion (hatched) and the opening portion (white) in Fig. 24 may be reversed.

[0227] The T-shaped connection portion 80 shown in Fig. 23 can be formed, for example, by etching the semiconductor chip 2 using a photoresist 140A patterned by exposure and development through a fourth mask 140 shown in Fig. 24. The fourth mask 140 differs from the third mask 133 shown in Fig. 22 in that a protrusion amount P4 of the third portion 125 of the fourth mask 140 is larger than a protrusion amount P3 of the third portion 125 of the third mask 133.

[0228] [5th ​​pattern] FIG. 25 is an enlarged view of the area A shown in FIG. 11, showing a fifth pattern of the T-shaped joint 80. As shown in FIG.

[0229] The T-shaped connection portion 80 of the fifth pattern differs from the third pattern in that the shape of the convex portion 113 is the same as that of the second pattern shown in Fig. 19. That is, the convex portion 113 of the fifth pattern has a pair of inclined portions 116 (inclined surfaces 130) extending from both ends of the convex portion 113 toward the inside of the T-shaped connection portion 80, an arc-shaped round portion 131 connecting the tips of the pair of inclined portions 116, and a straight portion 117 connected to the pair of inclined portions 116 via the round portions 131.

[0230] In this embodiment, the second radius R2 is, for example, 120% or more and 130% or less of the first radius R1. The difference between the widths WT1, WT2 of the T-shaped connection portion 80 and the first width W1 of the first trench 65 and the second width W2 of the second trench 79 is approximately the same as that of the third pattern shown in FIG. 21. However, unlike the third pattern, the shape of the protrusion 113 is not entirely arc-shaped, but the protrusion 113 has a pair of inclined portions 116 and a straight portion 117. This makes it easy to predict the shape after etching.

[0231] Fig. 26 is a diagram showing a mask pattern used when forming the T-shaped connection portion 80 of the fifth pattern in Fig. 25. The fifth mask 141 shown in Fig. 26 is for a positive photoresist 141A. When a negative photoresist is used, the mask portion (hatched) and the opening portion (white) in Fig. 26 may be reversed.

[0232] The T-shaped connection portion 80 shown in Fig. 25 can be formed, for example, by etching the semiconductor chip 2 using a photoresist 141A patterned by exposure and development through a fifth mask 141 shown in Fig. 26. The fifth mask 141 differs from the third mask 133 shown in Fig. 22 in that the third portion 125 is the same as the second mask 132 (see Fig. 20).

[0233] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0234] For example, in the above embodiment, two systems of main transistors 7 and monitor transistors 8 are shown. However, three or more systems of main transistors 7 and monitor transistors 8 may be employed.

[0235] In the above embodiment, the upper electrode 35 and the lower electrode 36 are at the same potential. However, the source potential may be applied to the lower electrode 36.

[0236] For example, in the above embodiment, an example was described in which the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing the n-type region with a p-type region and the p-type region with an n-type region in the above description and the attached drawings.

[0237] The embodiments of the present disclosure are illustrative in all respects and should not be construed as limiting, and are intended to include modifications in all respects.

[0238] The following characteristics can be extracted from the description of this specification and the drawings.

[0239] [Appendix 1-1] A semiconductor chip (2) having a first main surface (3) and a second main surface (4) opposite to the first main surface (3); a trench structure (30) including a first trench (65) formed in the first main surface (3) and extending along a first direction (X), a second trench (79) extending along a second direction (Y) perpendicular to the first direction (X) and connected to the first trench (65), and a T-shaped connection portion (80) formed at a connection portion of the first trench (65) with the second trench (79), A semiconductor device (1), wherein, when a first inscribed circle (119) having a first radius (R1) inscribed in both inner side walls of the first trench (65) and a second inscribed circle (120) having a second radius (R2) inscribed in peripheral side walls (106-108) of the T-shaped connection portion (80) are defined, the second radius (R2) is 80% or more and 130% or less of the first radius (R1).

[0240] According to this configuration, the error in the trench width between the first trench (65) and the T-shaped connection portion (80) is reduced, so that the error in the etching rate due to the difference in the trench width can be reduced. As a result, the error in the trench depth between the first trench (65) and the T-shaped connection portion (80) can be reduced, so that a decrease in the breakdown voltage caused by the trench depth of the T-shaped connection portion (80) being too deep can be suppressed.

[0241] [Appendix 1-2] the peripheral side walls (106-108) include one side wall (101) of the first trench (65), and a pair of corner side walls (109, 110) formed at an intersection between a pair of other side walls (102) of the first trench (65) separated by the second trench (79) and both side walls (104, 105) of the second trench (79); The semiconductor device (1) described in Appendix 1-1, wherein the second inscribed circle (120) is defined as a circle tangent to at least three points located on each of the one side wall (101) and the pair of corner side walls (109, 110) of the first trench (65).

[0242] [Appendix 1-3] The semiconductor device (1) according to appendix 1-1 or 1-2, wherein the second radius (R2) is equal to or greater than 90% and equal to or less than 110% of the first radius (R1).

[0243] This configuration further reduces the error in trench width between the first trench (65) and the T-shaped connection portion (80), thereby further reducing the error in etching rate due to differences in trench width. As a result, it is possible to further suppress a decrease in breakdown voltage caused by the trench depth of the T-shaped connection portion (80) becoming too deep.

[0244] [Appendix 1-4] a first sidewall structure (103) that forms the one sidewall (101) of the first trench (65) that extends continuously along the first direction (X) via the T-shaped connection portion (80); The semiconductor device (1) according to any one of Appendix 1-1 to Appendix 1-3, wherein the first side wall structure (103) has a protrusion (113) that selectively protrudes toward the inside of the T-shaped connecting portion (80) and has an apex inside the T-shaped connecting portion (80).

[0245] [Appendix 1-5] The semiconductor device (1) described in Appendix 1-4, wherein when an axis of symmetry (118) is defined that passes through the apex and extends along the second direction (Y), the convex portion (113) has a shape that is linearly symmetrical with respect to the axis of symmetry (118).

[0246] [Appendix 1-6] The protrusion (113) has two ends located in a portion of the first side wall structure (103) facing the T-shaped connection portion (80), The semiconductor device (1) according to Appendix 1-4 or Appendix 1-5, wherein the one sidewall (101) of the first trench (65) includes a convex sidewall (114) formed between the two ends of the convex portion (113) and a flat sidewall (115) extending parallel to the other sidewall (102) of the first trench (65) from the two ends of the convex portion (113).

[0247] According to this configuration, since the protrusions (113) are selectively formed at the T-shaped connections (80) in the trench structure (30), the trench width of the first trench (65) can be kept constant, thereby making it possible to suppress variations in the trench depth of the first trench (65).

[0248] [Appendix 1-7] a first mesa portion (70) sandwiched between a plurality of the first trenches (65) arranged at intervals in the second direction (Y) and in which a first transistor (7) is formed; a second mesa portion (71) that is partitioned by two adjacent first trenches (65) and a plurality of second trenches (79) connecting the two first trenches (65), is physically separated from the first mesa portion (70), and has a second transistor (8) formed therein; The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-6, wherein the first mesa portion (70) and the second mesa portion (71) are adjacent to each other with the T-shaped connection portion (80) interposed therebetween.

[0249] According to this configuration, the first mesa portion (70) and the second mesa portion (71) are adjacent to each other with the T-shaped connection portion (80) therebetween, so that it is possible to suppress variations in trench depth around the first transistor (7) and the second transistor (8). This makes it possible to equalize the withstand voltages of the first transistor (7) and the second transistor (8), thereby improving the controllability of the transistors.

[0250] [Appendix 1-8] The semiconductor device (1) according to any one of claims 1 to 7, wherein the trench structure (30) includes a trench gate structure (30) that commonly controls the current of the first transistor (7) and the second transistor (8).

[0251] [Appendix 1-9] a mesa structure (70, 71) sandwiched between two of the first trenches (65) arranged at an interval in the second direction (Y); the second trench (79) connects between the two first trenches (65) and physically separates the mesa structure (70, 71) into a first mesa portion (70) on one side of the second trench (79) and a second mesa portion (71) on the other side; the peripheral side walls (106-108) include one side wall (101) of a first trench (65) extending continuously along the first direction (X) via the T-shaped connection portion (80), a first corner side wall (109) formed at a corner of the first mesa portion (70) facing the T-shaped connection portion (80), and a second corner side wall (110) formed at a corner of the second mesa portion (71) facing the T-shaped connection portion (80); The semiconductor device (1) described in Appendix 1-1, wherein the second inscribed circle (120) is defined as a circle tangent to at least three points located on each of the one sidewall (101), the first corner sidewall (109), and the second corner sidewall (110) of the first trench (65).

[0252] [Appendix 1-10] a first columnar portion (111) having a substantially circular shape in a plan view is formed at a corner of the first mesa portion (70) and selectively protrudes obliquely toward the T-shaped connection portion (80); The semiconductor device (1) according to claim 1-9, wherein the first corner sidewall (109) is formed by a sidewall of the first columnar section (111).

[0253] According to this configuration, since the first corner side wall (109) has a substantially circular shape, it is possible to prevent the electric field from concentrating on the first corner side wall (109), thereby further preventing a decrease in the withstand voltage.

[0254] [Appendix 1-11] a second columnar portion (112) having a substantially circular shape in a plan view is formed at a corner of the second mesa portion (71) and selectively protrudes obliquely toward the T-shaped connection portion (80); The semiconductor device (1) according to any one of claims 1 to 10, wherein the second corner sidewall (110) is formed by a sidewall of the second columnar section (112).

[0255] According to this configuration, since the second corner side wall (110) is substantially circular, it is possible to prevent the electric field from concentrating on the second corner side wall (110). This makes it possible to further prevent a decrease in the withstand voltage. [Appendix 1-12] The semiconductor device (1) according to Appendix 1-11, wherein the one side wall (101) of the first trench (65) has two end portions at portions facing the first columnar portion (111) and the second columnar portion (112) across the T-shaped connecting portion (80) in the second direction (Y), and has a protrusion (113) selectively protruding toward the inside of the T-shaped connecting portion (80).

[0256] According to this configuration, since the protrusions (113) are selectively formed at the T-shaped connections (80) in the trench structure (30), the trench width of the first trench (65) can be kept constant, thereby making it possible to suppress variations in the trench depth of the first trench (65).

[0257] [Appendix 1-13] The semiconductor device (1) described in Appendix 1-12, wherein the convex portion (113) includes a pair of inclined portions (116) formed within a range from both end portions of the convex portion (113) facing the first columnar portion (111) and the second columnar portion (112), and a straight portion (117) connecting the pair of inclined portions (116) and extending parallel to the first direction (X).

[0258] According to this configuration, an obtuse angle can be formed between the straight portion (117) and the inclined portion (116) of the protrusion (113), thereby preventing the electric field from concentrating at the corner of the protrusion (113), thereby further preventing a decrease in the withstand voltage.

[0259] [Appendix 1-14] The semiconductor device (1) described in Appendix 1-9, wherein at least one of the first corner sidewall (109) and the second corner sidewall (110) is formed in an arc shape in a plan view connecting the other sidewall (102) of the first trench (65) and the sidewall (104, 105) of the second trench (79).

[0260] According to this configuration, at least one of the first corner side wall (109) and the second corner side wall (110) is arc-shaped, which can prevent the electric field from concentrating on the corner side wall (109, 110), thereby further preventing a decrease in the breakdown voltage.

[0261] [Appendix 1-15] The semiconductor device (1) described in Appendix 1-14, wherein the one side wall (101) of the first trench (65) has both ends at a portion facing the T-shaped connection portion (80), and has an arc-shaped convex portion (113) selectively protruding toward the inside of the T-shaped connection portion (80).

[0262] According to this configuration, since the protrusions (113) are arc-shaped, concentration of an electric field on the protrusions (113) can be suppressed.

[0263] [Appendix 1-16] The semiconductor device (1) according to Appendix 1-14, wherein the one side wall (101) of the first trench (65) has a protrusion (113) having both ends at a portion facing the T-shaped connection portion (80), the protrusion (113) including a pair of inclined portions (136) extending from the both ends toward the inside of the T-shaped connection portion (80) and an arc-shaped round portion (137) connecting the tips of the pair of inclined portions (136).

[0264] According to this configuration, since the tip of the protrusion (113) is the arc-shaped rounded portion (137), concentration of an electric field at the tip of the protrusion (113) can be suppressed.

[0265] [Appendix 1-17] The semiconductor device (1) according to Appendix 1-14, wherein the one side wall (101) of the first trench (65) has a protruding portion (113) having both ends at a portion facing the T-shaped connection portion (80), the protruding portion (113) including a pair of inclined portions (116) extending from the both ends toward the inside of the T-shaped connection portion (80), and a straight portion (117) connecting tip ends of the pair of inclined portions (116) and extending parallel to the first direction (X).

[0266] [Appendix 1-18] a first semiconductor region (20, 21) of a first conductivity type formed in a surface layer portion of the first main surface (3); a body region (27) of a second conductivity type formed in a surface layer portion of the first semiconductor region (20, 21); a trench gate structure (30) as the trench structure (30) formed to penetrate the body region (27) and reach the first semiconductor region (20, 21) and having a gate electrode (35); a main transistor (7) formed in the first mesa portion (70) and generating an output current in the body region (27) by controlling the trench gate structure (30); a monitor transistor (8) that generates a monitor current corresponding to the output current in the body region (27) by controlling the trench gate structure (30); The semiconductor device (1) according to any one of Appendix 1-9 to Appendix 1-17, wherein the body region (27) is electrically and physically separated into a monitor body region (27) for the monitor transistor (8) and a main body region (27) for the main transistor (7) by the first trench (65) and the second trench (79).

[0267] [Appendix 1-19] The semiconductor device (1) described in Appendix 1-18 includes a bottom impurity region (41) of a first conductivity type formed at the bottom of the T-shaped connection portion (80) and having an impurity concentration higher than the impurity concentration of the first semiconductor region (20, 21). [Explanation of symbols]

[0268] 1: Semiconductor device 2: Semiconductor chips 3: First main surface 4: Second main surface 5A: 1st side 5B: 2nd side 5C: 3rd side 5D: 4th side 6: First device area 7: Main transistor 7A: First system transistor 7B: Second system transistor 8: Monitor transistor 9: Second device area 10: Control IC 11: Main gate wiring 12: Interlayer insulation layer 12A: 1st system monitor transistor 12B: Second system monitor transistor 13: Monitor gate wiring 14: Drain terminal 15: Source terminal 16: Input terminal 17: Ground terminal 18: Enable terminal 19: Sense terminal 20: First semiconductor region 21: Second semiconductor region 22: Trench isolation structure 23: Isolation trench 24: Isolation insulating film 25: Separation electrode 26: Isolation cap insulating film 27: Body region 28: Unit transistor 28A: First unit transistor 28B: Second unit transistor 29: Unit cell 29A: First unit cell 29B: Second unit cell 30: Trench structure 30A: First trench structure 30B: Second trench structure 31: Channel cell 31A: 1st channel cell 31B: Second channel cell 32: Trench 32A: First trench 32B: Second trench 33: Upper insulating film 33A: First upper insulating film 33B: Second upper insulating film 34: Lower insulating film 34A: First lower insulating film 34B: Second lower insulating film 35: Upper electrode 35A: 1st upper electrode 35B: 2nd upper electrode 36: Lower electrode 36A: 1st lower electrode 36B: 2nd lower electrode 37: Intermediate insulating film 37A: First intermediate insulating film 37B: Second intermediate insulating film 38: Source area 38A: First source region 38B: Second source region 39: Contact area 39A: First contact area 39B: Second contact region 40: Channel region 40A: First channel region 40B: Second channel region 41: Third semiconductor region 42: Outer edge 43: Base part 44:Protrusion 45: First trench connection structure 46: First connection trench 47: First connection insulating film 48: First connection electrode 49: First cap insulating film 50: Second trench connection structure 51: Second connection trench 52: Second connection insulating film 53: Second connection electrode 54: Second cap insulating film 55: Unit monitor transistor 55A: First unit monitor transistor 55B: Second unit monitor transistor 56: Unit monitor cell 57: Monitor trench structure 58: Monitor channel cell 59: Monitor Trench 60: Upper monitor insulating film 61: Lower monitor insulating film 62: Upper monitor electrode 63: Lower monitor electrode 64: Intermediate monitor insulating film 65: First trench 66: Monitor source area 67: Monitor contact area 68: Monitor channel area 69: Monitor trench connection structure 70: First Mesa 71: Second Mesa 72: Monitor connection trench 73: Upper monitor connection insulating film 74: Lower monitor connection insulating film 75: Upper monitor connection electrode 76: Lower monitor connection electrode 77: Intermediate monitor connection insulating film 78: Integrated trench structure 79: Second trench 80: T-shaped connection 81: First virtual line 82: Second virtual line 83 :1st corner 84:Second corner 85: Body Space 86: Field insulating film 87: Main surface insulating film 88: First plug electrode 89: Second plug electrode 90: Third plug electrode 91: 4th plug electrode 92: 5th plug electrode 93: 6th plug electrode 94: Main source wiring 95: Monitor source wiring 101: One side wall 102: other side wall 103:First side wall structure 104: One side wall 105: other side wall 106: First surrounding side wall 107: Second surrounding side wall 108: Third surrounding side wall 109: First corner side wall 110: Second corner side wall 111: 1st columnar part 112:Second columnar part 113: Convex 114: Convex side wall 115 :Flat side wall 116: Inclined part 117: Straight section 118: Axis of symmetry 119: First inscribed circle 120: Second inscribed circle 121: First Mask 122 :Aperture 123 :1st part 124 :Second part 125: 3rd part 126: 1st protrusion 127:Second protrusion 128: Arrow 129: Corner 130: Inclined surface 131: Round section 132: 2nd mask 133: 3rd Mask 134: Corner 135: Corner 136: Inclined part 137: Round section 138: Straight section 139: Mesa 140: 4th Mask 141: 5th Mask R1: First radius R2: 2nd radius

Claims

1. a semiconductor chip having a first major surface and an opposite second major surface; a trench structure including a first trench formed in the first main surface and extending along a first direction, a second trench extending along a second direction perpendicular to the first direction and connected to the first trench, and a T-shaped connection portion formed at a connection portion of the first trench and the second trench, A semiconductor device, wherein when a first inscribed circle having a first radius inscribed in both inner side walls of the first trench and a second inscribed circle having a second radius inscribed in a peripheral side wall of the T-shaped connection portion are defined, the second radius is greater than or equal to 80% and less than 130% of the first radius.

2. the peripheral sidewall includes one sidewall of the first trench and a pair of corner sidewalls formed at an intersection between a pair of other sidewalls of the first trench separated by the second trench and both sidewalls of the second trench, 2 . The semiconductor device according to claim 1 , wherein the second inscribed circle is defined as a circle tangent to at least three points located on each of the one sidewall and the pair of corner sidewalls of the first trench.

3. The semiconductor device according to claim 1 , wherein the second radius is equal to or greater than 90% and equal to or less than 110% of the first radius.

4. a first sidewall structure portion that forms the one sidewall of the first trench that extends continuously along the first direction via the T-shaped connection portion; 2. The semiconductor device according to claim 1, wherein said first sidewall structure has a protrusion that selectively protrudes toward an inside of said T-shaped connecting portion and has an apex inside said T-shaped connecting portion.

5. The semiconductor device according to claim 4 , wherein, when an axis of symmetry is defined to pass through the apex and extend along the second direction, the protrusion has a shape that is linearly symmetrical with respect to the axis of symmetry.

6. the protrusion has two ends located at a portion of the first sidewall structure facing the T-shaped connection portion, 6. The semiconductor device according to claim 5, wherein the one sidewall of the first trench includes a convex sidewall formed between the two ends of the convex portion, and a flat sidewall extending parallel to the other sidewall of the first trench from the two ends of the convex portion.

7. a first mesa portion in which a first transistor is formed and which is sandwiched between a plurality of the first trenches arranged at intervals in the second direction; a second mesa portion that is partitioned by two adjacent first trenches and a plurality of second trenches connecting the two first trenches, is physically separated from the first mesa portion, and has a second transistor formed therein; 7. The semiconductor device according to claim 1, wherein the first mesa portion and the second mesa portion are adjacent to each other with the T-shaped connection portion therebetween.

8. 8. The semiconductor device according to claim 7, wherein said trench structure includes a trench gate structure commonly controlling currents of said first transistor and said second transistor.

9. a mesa structure sandwiched between two of the first trenches arranged at an interval in the second direction; the second trench connects between the two first trenches and physically separates the mesa structure into a first mesa portion on one side of the second trench and a second mesa portion on the other side of the second trench; the peripheral sidewall includes one sidewall of a first trench extending continuously along the first direction via the T-shaped connection portion, a first corner sidewall formed at a corner of the first mesa portion facing the T-shaped connection portion, and a second corner sidewall formed at a corner of the second mesa portion facing the T-shaped connection portion, 2 . The semiconductor device according to claim 1 , wherein the second inscribed circle is defined as a circle tangent to at least three points located on the one sidewall, the first corner sidewall, and the second corner sidewall of the first trench.

10. a first columnar portion having a substantially circular shape in a plan view is formed at a corner of the first mesa portion and selectively protrudes obliquely toward the T-shaped connection portion; The semiconductor device according to claim 9 , wherein the first corner sidewall is formed by a sidewall of the first columnar portion.

11. a second columnar portion having a substantially circular shape in a plan view is formed at a corner of the second mesa portion and selectively protrudes obliquely toward the T-shaped connection portion; The semiconductor device according to claim 10 , wherein the second corner sidewall is formed by a sidewall of the second columnar section.

12. 12. The semiconductor device according to claim 11, wherein the one sidewall of the first trench has two ends at portions facing the first columnar portion and the second columnar portion across the T-shaped connection portion in the second direction, and has a protrusion that selectively protrudes toward an inside of the T-shaped connection portion.

13. 13. The semiconductor device according to claim 12, wherein the convex portion includes a pair of inclined portions formed within a range from the two end portions of the convex portion facing the first columnar portion and the second columnar portion, and a straight portion connecting the pair of inclined portions and extending parallel to the first direction.

14. 10. The semiconductor device according to claim 9, wherein at least one of the first corner sidewall and the second corner sidewall is formed in an arc shape connecting the other sidewall of the first trench and the sidewall of the second trench in a plan view.

15. 15. The semiconductor device according to claim 14, wherein the one sidewall of the first trench has both ends at a portion facing the T-shaped connection portion and has an arc-shaped convex portion selectively protruding toward the inside of the T-shaped connection portion.

16. 15. The semiconductor device according to claim 14, wherein the one side wall of the first trench has a convex portion having both ends facing the T-shaped connection portion, the convex portion including a pair of inclined portions extending from the both ends toward the inside of the T-shaped connection portion, and an arc-shaped round portion connecting the tips of the pair of inclined portions.

17. 15. The semiconductor device according to claim 14, wherein the one side wall of the first trench has a convex portion having both ends facing the T-shaped connection portion, the convex portion including a pair of inclined portions extending from the both ends toward the inside of the T-shaped connection portion, and a straight portion connecting the tips of the pair of inclined portions and extending parallel to the first direction.

18. a first semiconductor region of a first conductivity type formed in a surface layer portion of the first main surface; a body region of a second conductivity type formed in a surface layer portion of the first semiconductor region; a trench gate structure as the trench structure, the trench gate structure being formed to penetrate the body region and reach the first semiconductor region and having a gate electrode; a main transistor formed in the first mesa portion and configured to generate an output current in the body region by controlling the trench gate structure; a monitor transistor that generates, in the body region, a monitor current corresponding to the output current by controlling the trench gate structure; The semiconductor device according to any one of claims 9 to 17, wherein the body region is electrically and physically separated into a monitor body region for the monitor transistor and a main body region for the main transistor by the first trench and the second trench.

19. 20. The semiconductor device according to claim 18, further comprising a bottom impurity region of a first conductivity type formed at a bottom of said T-shaped connection portion and having an impurity concentration higher than an impurity concentration of said first semiconductor region.

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