Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing a change in the characteristics of transistors and abruptly changing an output signal without increasing the W / L of the transistors.SOLUTION: Two transistors are connected in parallel between wiring, to which a low potential is supplied, and an output terminal. When the low potential is to be output from the output terminal, both of the two transistors are turned on and then one of the transistors is turned off. Thus, a change in the characteristics of the transistors can be suppressed and an output signal can be abruptly changed without increasing the W / L of the transistors.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a display device including the semiconductor device. The present invention relates to a sequential circuit and a semiconductor device such as a shift register having the sequential circuit. [Background technology]

[0002] In recent years, the development of sequential circuits consisting of transistors of the same polarity has been actively promoted. In addition, Patent Document 1 discloses a sequential circuit capable of suppressing changes in transistor characteristics. It is being done.

[0003] FIG. 17A shows the configuration of a conventional sequential circuit. The conventional sequential circuit includes a transistor T13. and a transistor T14 and a transistor T15 connected in parallel. In the sequential circuit, transistor T13 is turned on, transistor T14 and transistor When T15 is turned off, the first clock signal C1 is output. If 1 is at a high level, the first scan signal Vg1 becomes at a high level (see FIG. 17(B)). Then, in the odd frame, transistor T13 is turned off and transistor T1 4 is turned on and transistor T15 is turned off, outputting the first supply voltage VSS. (See FIG. 17C). In the even-numbered frames, the transistor T13 is turned off. This turns off transistor T14 and turns on transistor T15, thereby forming a first supply. In this way, the transistors are turned on in the odd-numbered frames. By turning off transistor T15 in the even frame and turning off transistor T14 in the even frame, Changes in the characteristics of the transistors T14 and T15 are suppressed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-004167 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in a conventional sequential circuit, one of two transistors connected in parallel is turned off. Two transistors connected in parallel to drive only the other transistor. Therefore, the W of the transistor (W is the channel width ) / L (L is the channel length) becomes large. If / L is not large enough, the output signal will change slowly, resulting in delayed or dull output signals. There was a problem that the

[0006] In view of the above, one embodiment of the present invention is to suppress a change in the characteristics of a transistor and A semiconductor device capable of changing an output signal sharply without increasing the W / L ratio is provided. Another object of the present invention is to provide a semiconductor device including a novel circuit configuration. One of the objectives is to provide a device for detecting the presence of other objectives. However, it is not necessary for one embodiment of the present invention to solve all of these problems. Problems other than these will be obvious from the description, drawings, claims, etc. It is clear that the specification, drawings, claims, etc. do not reveal any other problems. It is possible to extract [Means for solving the problem]

[0007] One aspect of the present invention is a first transistor having a first signal input to one of a source and a drain. A first potential is input to the transistor and either the source or the drain, and the other of the source or the drain is A second transistor electrically connected to the other of the source and drain of the first transistor. and one of the source or drain of the first transistor is connected to one of the source or drain of the second transistor. The other of the source and drain is electrically connected to the source or drain of the first transistor. a third transistor electrically connected to the other of the first and second transistors; and a means for controlling the on / off of the first transistor and the second transistor. The semiconductor device is a driving method for driving a first signal through a first transistor. a first step of outputting the first potential through a second transistor and a third transistor; a second step of outputting the first potential through a second transistor; a first period having a third step; and outputting a first signal through a first transistor. a fourth step of inputting the first potential through the second transistor and the third transistor; a fifth step of outputting the first potential through a third transistor; and a sixth step of outputting the first potential through a third transistor. and a second period having the steps of:

[0008] In one aspect of the present invention, in a first period, a first step, a second step and a third step are performed. Each of the steps is carried out two or more times, and in the second period, the fourth step, the fifth step, Each of the first and sixth steps may be performed two or more times. In this case, the channel width of the second transistor is 90% or less of the channel width of the third transistor. In the above aspect of the present invention, the first transistor The channel width of the first transistor is greater than the channel width of the second transistor, and the channel width of the third transistor is greater than the channel width of the second transistor. The width of the channel of the transistor may be larger than that of the transistor.

[0009] In one embodiment of the present invention, one of a source and a drain is electrically connected to a first wiring. a first transistor, the other of which is electrically connected to a second wiring; The drain of the transistor is electrically connected to the first wiring, and the other of the source or the drain is electrically connected to the second wiring. A second transistor electrically connected to the wiring, and a first terminal of the second transistor a first switch electrically connected to the gate of the second transistor; a second terminal of the first switch electrically connected to the second terminal of the first switch; The second switch has a first terminal electrically connected to the third wiring and a second terminal electrically connected to the first transistor. a third switch electrically connected to the gate of the transistor; and a third wiring and a first terminal electrically connected to the third wiring and a second wiring. a fourth transistor having a second terminal electrically connected to the gate of the second transistor; and a switch.

[0010] In one embodiment of the present invention, one of the source and the drain is connected to a fourth wiring, The other of the drains is connected to the second terminal of the first switch, and the gate is connected to the fourth wire. a third transistor, one of a source and a drain of which is connected to the second wiring, a fourth transistor, the other of whose drains is connected to the second terminal of the first switch; In addition, the above-mentioned aspect of the present invention may have a first switch and a fourth switch. a first period during which the first switch is on and the second switch and the third switch are off; the first switch and the fourth switch are off, and the second switch and the third switch are on. and a second period in which the first period is Effect of the Invention

[0011] According to one embodiment of the present invention, a change in characteristics of a transistor can be suppressed and This semiconductor device can make the output signal change steeper without increasing the W / L of the Another embodiment of the present invention is a semiconductor device including a novel circuit configuration. can be provided. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 shows the configuration of a sequential circuit. [Diagram 2] 1 is a timing chart of a sequential circuit. [Diagram 3] 1 is a timing chart of a sequential circuit. [Figure 4] FIG. 1 is a diagram showing the operation of a sequential circuit. [Diagram 5] FIG. 1 is a diagram showing the operation of a sequential circuit. [Figure 6] FIG. 1 is a diagram showing the operation of a sequential circuit. [Figure 7] FIG. 1 is a diagram showing the operation of a sequential circuit. [Figure 8] FIG. 1 shows the configuration of a sequential circuit. [Figure 9] FIG. 1 shows the configuration of a sequential circuit. [Figure 10] FIG. 1 shows the configuration of a sequential circuit. [Figure 11] FIG. 2 is a diagram showing a configuration of a shift register. [Figure 12] FIG. 2 is a diagram showing the configuration of a panel. [Figure 13] 1A and 1B are diagrams illustrating a cross-sectional structure of a transistor. [Figure 14] 1A and 1B are a top view and a cross-sectional view of a liquid crystal display device. [Figure 15]FIG. [Figure 16] FIG. 1 shows the configuration of a sequential circuit. [Figure 17] FIG. 1 illustrates the configuration and operation of a conventional sequential circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiment.

[0014] The present invention can be applied to any semiconductor device using transistors, such as integrated circuits, RF tags, and display devices. The category of integrated circuits includes semiconductor devices. , DSP (Digital Signal Processor), Microcontroller LSI (Large Scale Integrated Circuit), including FPGA (Field Programmable Gate Array) and CPLD Programmable logic circuits (PLDs) such as complex PLDs The display device includes the following: A light-emitting device in which each pixel has a light-emitting element, typically an organic light-emitting diode (OLED). Placement, electronic paper, DMD (Digital Micromirror Device) , PDP (Plasma Display Panel), FED (Field Emi This category includes the use of digital displays (DSPs) and other display devices.

[0015] In this specification, the term "display device" refers to a display device in which display elements such as liquid crystal elements and light emitting elements are formed into pixels. The panel is a module with ICs, including a controller, mounted on the panel. This category includes both.

[0016] In this specification, the term "connection" means electrical connection, and the term "connection" means a state in which a current, a voltage, or a potential is Therefore, the connected state corresponds to a direct connection. It does not necessarily refer to the state in which a current, voltage or potential is available or is transmitted through circuit elements such as wires, resistors, diodes, and transistors. This also includes the state where the components are indirectly connected through a circuit diagram. Even when elements are connected to each other, in reality, for example, part of the wiring functions as an electrode. In some cases, a single conductive film may have the functions of multiple components. In the specification, the term "connection" refers to a state in which one conductive film has the functions of multiple components. If so, it will also be included in that category.

[0017] The source of a transistor is a source region that is a part of a semiconductor film that functions as an active layer. The source electrode of a transistor is a region connected to the semiconductor film. The drain is a part of the semiconductor film, or a drain region connected to the semiconductor film. The term "gate" refers to a gate electrode.

[0018] The source and drain of a transistor are determined by the polarity of the transistor and the terminals. The name is changed depending on the level of the potential applied. Generally, n-channel transistors are In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In addition, in a p-channel transistor, the terminal to which a low potential is applied is called a drain. The terminal to which the high potential is applied is called the drain, and the terminal to which the high potential is applied is called the source. Assuming that the source and drain are fixed, explain the connection relationship of the transistor. In some cases, the source and drain are named according to the above potential relationship. Replace.

[0019] (Embodiment 1) In this embodiment, a sequential circuit (also referred to as a semiconductor device) according to one embodiment of the present invention will be described. do.

[0020] FIG. 1A shows a sequential circuit according to this embodiment. The sequential circuit in FIG. M1, transistor M2a, transistor M2b, switch S3a, switch S3b, The switch S4 includes a switch S4a, a switch S4b, and a circuit 10.

[0021] The transistor M1 has a first terminal (also referred to as one of a source and a drain) connected to a wiring 11. The second terminal (also referred to as the other of the source and drain) is connected to a wiring 12, and the gate The first terminal of the transistor M2a is connected to the line 13. The second terminal is connected to the wiring 12, and the gate is connected to the node N2a. M2b has a first terminal connected to the wiring 13, a second terminal connected to the wiring 12, and a gate The switch S3a has a first terminal connected to the node N3 and a second terminal connected to the node N4. The switch S3b has a first terminal connected to the node N3 and a second terminal connected to the node N2a. The switch S4a has a first terminal connected to a node N2b and a second terminal connected to a node N2b. The switch S4b has a first terminal connected to the line 14 and a second terminal connected to the node N2a. The first terminal is connected to the wiring 14, and the second terminal is connected to the node N2b. The first terminal is connected to the wiring 15, the second terminal is connected to the wiring 14, and the third terminal is connected to the node N 1, and the fourth terminal is connected to a node N3.

[0022] The circuit 10 supplies a potential to the node N1 for controlling the on / off of the transistor M1. Specifically, the circuit 10 has a function of supplying a voltage to a node N1 when a transistor M1 is turned on. After supplying a potential to the node N1, the circuit 10 sets the node N1 in a floating state. The circuit 1 has a function of supplying a potential to the node N1 at which the transistor M1 is turned off. 0 controls the on or off of the transistor M2a or the transistor M2b at the node N3. Specifically, the circuit 10 has a function of supplying a potential to the node N3. It also has the function of supplying a potential that turns on the transistor M2a or the transistor M2b. The circuit 10 supplies a potential to the node N3 at which the transistor M2a or the transistor M2b is turned off. The potential supplied from the circuit 10 to the node N3 is supplied via the switch S3a If switch S3b is on, it is supplied to node N2a, and if switch S3b is on, it is supplied to node N2b. In addition, the connection relationship of the circuit 10 can be appropriately changed depending on the configuration of the circuit 10. Cut.

[0023] The transistors in the sequential circuit have the same polarity. There are N-channel and P-channel types. In this embodiment, for convenience, the transistors M1, The transistor M2a and the transistor M2b are N-channel types.

[0024] The transistor controls the conduction or non-conduction between the connection destination of the first terminal and the connection destination of the second terminal. For example, the transistor M1 controls the conduction between the wiring 11 and the wiring 12 or The transistor M2a controls the conduction or non-conduction between the wiring 13 and the wiring 12. The transistor M2b has a function of controlling non-conduction between the wiring 13 and the wiring 12. Or, it has a function of controlling non-conduction.

[0025] In addition, in the transistor, the voltage between the connection destination of the gate and the connection destination of the first terminal or the second terminal is For example, the transistor M1 has a function of holding a potential difference between the wiring 12 and the node N1. It has the function of maintaining the potential difference between them.

[0026] The transistor may be replaced with a switch. a first terminal of the transistor corresponds to a second terminal of the switch; For example, a first terminal of the transistor M2a is connected to the wiring 13, and a second terminal of the transistor M2a is connected to the wiring 1. The first terminal of the transistor M2b may be replaced by a switch connected to the wiring 1. 3 and a switch having a first terminal connected to wiring 12.

[0027] A signal or a potential is input to the wiring, and the wiring transmits the input signal or potential. For example, a signal or potential of the wiring 11 has a function of increasing the potential of the wiring 12. It is preferable that the signal or potential of the wiring 13 has a function of decreasing the potential of the wiring 12. The wiring 14 controls the on / off state of the transistor M2a. function, a function of controlling the on / off of transistor M2b, or a function of controlling circuit 10 The signal or potential of the wiring 15 preferably has a function of controlling the circuit 10. It is preferable to do so.

[0028] In this embodiment, for convenience, a signal CK1 (also called a clock signal) is input to the wiring 11. A signal OUT (also called an output signal) is output from the wiring 12, and a potential V1 (also referred to as a first potential) is supplied to the wiring 14, and a signal RE (also referred to as a reset signal) is supplied to the wiring 14. A signal SP (also called a start signal) is input to the wiring 15. For convenience, the signals CK1, SP, and RE have high and low levels. The low level potential is potential V1, and the high level potential is potential V2. (also referred to as a second potential). The potential V2 is a potential higher than the potential V1.

[0029] Next, the operation of the sequential circuit of FIG.

[0030] 2 and 3 are timing charts for explaining the operation of the sequential circuit of FIG. 1(A). The timing charts of FIG. 2 and FIG. 3 have a period Ta and a period Tb. FIG. 2 shows a timing chart of a period Ta having periods T1a to T4a. FIG. 3 shows a timing chart of a period Tb having periods T1b to T4b. 2 and 3 show the relationship between the switches S3a and S4b and the ON / OFF state of the switches S3a and S4b. The on / off relationship of the switch S3b and the switch S4a, the signal CK1, the signal SP, the signal RE, The potential VN1 of node N1, the potential VN2a of node N2a, the potential VN2b of node N2b, and the signal OUT.

[0031] 4 to 7 show the operation of the sequential circuit of FIG. 1A in each period (also called each step). 4(A) shows the period T1a, FIG. 4(B) shows the period T2a, and FIG. 5(A) shows the period T 3a, FIG. 5(B) is the period T4a, FIG. 6(A) is the period T1b, FIG. 6(B) is the period T2b, FIG. 7(A) shows the operation of the sequential circuit of FIG. 1(A) during period T3b, and FIG. 7(B) shows the operation of the sequential circuit of FIG. 1(A) during period T4b. A schematic diagram is shown.

[0032] First, the operation during the period Ta will be described. Switch S4b is on, and switch S3b and switch S4a are off.

[0033] In the period T1a, the signal CK1 goes low, the signal SP goes high, and the signal R E goes low. A potential that turns on the transistor M1 is applied to the node N1 from the circuit 10. Then, the power supply from the circuit 10 to the node N1 turns on the transistor M1. The potential of node N1 is floating because the supply of potential from the transistor is stopped. Since transistor M1 is held at a potential that turns it on, transistor M1 remains on. In addition, the node N2a is supplied with a potential at which the transistor M2a is turned off by the switch S 3a. This turns off the transistor M2a. Also, the node N2 b is supplied with the signal RE via the switch S4b. Since the signal RE is at a low level, In addition, the signal CK1 is applied to the wiring 12 to the transistor M1 Since the signal CK1 is at a low level, the potential of the wiring 12 is set to the potential V1. In other words, the signal OUT becomes low level.

[0034] During the period T2a, the signal CK1 goes high, the signal SP goes low, and the signal R E remains at a low level. The supply of potential from the circuit 10 to the node N1 remains stopped. Therefore, node N1 remains floating and transistor M1 remains on. In addition, the node N2a is supplied with a potential at which the transistor M2a is turned off by the switch S3 from the circuit 10. a remains supplied so that transistor M2a remains off. The signal RE remains supplied to the node N2b via the switch S4b. Since the signal remains at a low level, the transistor M2b remains off. The signal CK1 remains supplied to the output of the FET M1 through the transistor M1. Since the signal OUT is at a high level, the potential of the wiring 12 becomes the potential V2. become.

[0035] The node N1 is in a floating state, and the transistor M1 is connected between the wiring 12 and the node N1. Since the potential difference between the wiring 12 and the node N1 is maintained, the potential of the wiring 12 increases as the potential of the node N1 increases. This is the so-called bootstrap operation. The potential of the first terminal of the transistor M1 (for example, potential V2) and the threshold voltage of the transistor M1 Since the potential of the wiring 12 can be increased to a value exceeding the sum of the potentials V1 and V2, the potential of the wiring 12 can be increased to a potential V2. can.

[0036] During a period T3a, the signal CK1 goes to a low level, and the signal SP remains at a low level. The signal RE becomes high level. The node N1 has a potential that turns off the transistor M1. 10, the transistor M1 is turned off. The potential at which the transistor M2a is turned on is supplied from the circuit 10 via the switch S3a. The transistor M2a is turned on. Also, the signal RE is applied to the node N2b through the switch S4b. Since the signal RE is high, the transistor M2b That is, both the transistor M2a and the transistor M2b are turned on. In addition, a potential V1 is applied to the wiring 12 to supply a potential to both the transistor M2a and the transistor M2b. Therefore, the potential of the wiring 12 becomes the potential V1. It becomes extremely high level.

[0037] The potential V1 is applied to the wiring 12 via both the transistor M2a and the transistor M2b. Therefore, by increasing the W / L of the transistors M2a and M2b, Therefore, the fall time of the signal OUT can be shortened.

[0038] During the period T4a, the signal CK1 alternates between high and low levels, and the signal SP alternates between low and high levels. The node N1 remains at the low level and the signal RE goes low. Since the potential to turn off the transistor M1 remains supplied from the circuit 10, the transistor M1 remains off. In addition, the node N2a receives a potential that switches on the transistor M2a from the circuit 10. Transistor M2a remains on because the power supply remains supplied through switch S3a. Furthermore, the signal RE remains supplied to the node N2b via the switch S4b. Since the signal RE is at a low level, the transistor M2b is turned off. The potential V1 is supplied to the wiring 12 through the transistor M2a. It remains at 1. That is, the signal OUT remains at a low level.

[0039] Note that the period T4a is longer than the periods T1a to T3a and occupies most of the operation period. And the transistor M2b is off during the period T4a. This shortens the time that transistor M2b is on, suppressing changes in the characteristics of transistor M2b. It is possible.

[0040] Next, the operation during the period Tb will be described. During the period Tb, the switches S3a and Switch S4b is off, and switch S3b and switch S4a are on.

[0041] In the period T1b, the signal CK1 goes low, the signal SP goes high, and the signal R E goes low. A potential that turns on the transistor M1 is applied to the node N1 from the circuit 10. Then, the power supply from the circuit 10 to the node N1 turns on the transistor M1. The potential of node N1 is floating because the supply of potential from the transistor is stopped. Since transistor M1 is held at a potential that turns it on, transistor M1 remains on. In addition, the node N2b is supplied with a potential at which the transistor M2b is turned off by the switch S 3b. This turns off the transistor M2b. Also, the node N2 A signal RE is supplied to a through a switch S4a. Since the signal RE is at a low level, In addition, the signal CK1 is applied to the wiring 12 to the transistor M1 Since the signal CK1 is at a low level, the potential of the wiring 12 is set to the potential V1. In other words, the signal OUT becomes low level.

[0042] In the period T2b, the signal CK1 goes to a high level, the signal SP goes to a low level, and the signal R E remains at a low level. The supply of potential from the circuit 10 to the node N1 remains stopped. Therefore, node N1 remains floating and transistor M1 remains on. In addition, the node N2b receives a potential at which the transistor M2b is turned off from the circuit 10 through the switch S3. b, transistor M2b remains off. The signal RE remains supplied to the node N2a via the switch S4a. Since the signal remains at a low level, the transistor M2a remains off. The signal CK1 remains supplied to the output of the FET M1 through the transistor M1. Since the signal OUT is at a high level, the potential of the wiring 12 becomes the potential V2. become.

[0043] The node N1 is in a floating state, and the transistor M1 is connected between the wiring 12 and the node N1. Since the potential difference between the wiring 12 and the node N1 is maintained, the potential of the wiring 12 increases as the potential of the node N1 increases. This is the so-called bootstrap operation. The potential of the first terminal of the transistor M1 (for example, potential V2) and the threshold voltage of the transistor M1 Since the potential of the wiring 12 can be increased to a value exceeding the sum of the potentials V1 and V2, the potential of the wiring 12 can be increased to a potential V2. can.

[0044] In a period T3b, the signal CK1 goes to a low level, the signal SP remains at a low level, The signal RE becomes high level. The node N1 has a potential that turns off the transistor M1. 10, the transistor M1 is turned off. The potential at which the transistor M2b is turned on is supplied from the circuit 10 via the switch S3b. The transistor M2b is turned on. Also, the signal RE is applied to the node N2a through the switch S4a. Since the signal RE is high, the transistor M2a That is, both the transistor M2a and the transistor M2b are turned on. In addition, a potential V1 is applied to the wiring 12 to supply a potential to both the transistor M2a and the transistor M2b. Therefore, the potential of the wiring 12 becomes the potential V1. It becomes extremely high level.

[0045] The potential V1 is applied to the wiring 12 via both the transistor M2a and the transistor M2b. Therefore, by increasing the W / L of the transistors M2a and M2b, Therefore, the fall time of the signal OUT can be shortened.

[0046] During the period T4b, the signal CK1 alternates between high and low levels, and the signal SP alternates between low and high levels. The node N1 remains at the low level and the signal RE goes low. Since the potential to turn off the transistor M1 remains supplied from the circuit 10, the transistor M1 remains off. In addition, the node N2b receives a potential from the circuit 10 that turns on the transistor M2b. Since the power supply remains supplied through switch S3b, transistor M2b remains on. Furthermore, the signal RE remains supplied to the node N2a via the switch S4a. Since the signal RE is at a low level, the transistor M2a is turned off. The potential V1 is supplied to the wiring 12 through the transistor M2b. It remains at 1. That is, the signal OUT remains at a low level.

[0047] Note that the period T4b is longer than the periods T1b to T3b and occupies most of the operation period. The transistor M2a is off during the period T4b. This shortens the time that the transistor M2a is on, suppressing changes in the characteristics of the transistor M2a. It is possible.

[0048] As described above, the sequential circuit of FIG. 1A can suppress the change in the characteristics of the transistor. At the same time, the fall time of the output signal is shortened without increasing the W / L of the transistor. It can be made easier.

[0049] The potential at which the transistor M1 is turned on is the potential at the first terminal or the second terminal of the transistor M1. The voltage at the terminal of the transistor M1 exceeds the sum of the voltage at the terminal of the transistor M2 (for example, the voltage V1). The potential at which the transistor M1 is turned off is the potential at the first terminal or is less than the sum of the potential of the second terminal (for example, potential V1) and the threshold voltage of transistor M1. For example, the potential at which the transistor M1 is turned off is the potential V1. The potential at which the transistor M2a or the transistor M2b is turned on is the potential at which the transistor M2a or the transistor M2b is turned on. a or the potential of the first terminal of the transistor M2b (for example, potential V1) and the potential of the first terminal of the transistor M2a or a value exceeding the sum of the threshold voltage of the transistor M2b. The potential at which the transistor M2a or the transistor M2b is turned on is the potential V2. The potential at which the transistor M2a or the transistor M2b is turned off is The potential of the first terminal of the transistor M2b (for example, potential V1) and the potential of the transistor M2a or For example, the threshold voltage of transistor M2a or M2b is less than the sum of the threshold voltages of transistors M2a and M2b. The potential at which the transistor M2b is turned off is the potential V1. The potential at which M1 is turned off is the potential at which the transistor M2a or the transistor M2b is turned off. The potential at which the transistor M2a is turned on may be equal to or different from the potential at which the transistor M2a is turned on. may be equal to or different from the potential at which the transistor M2b turns on. In addition, the potential at which the transistor M2a turns off is equal to the potential at which the transistor M2b turns off. They may be the same or different.

[0050] The above-described operation is merely an example, and is not intended to be limiting. During the period T1a, a potential that turns on the transistor M2a is supplied to the node N2a. A potential that turns on transistor M2b in the first input may be supplied to node N2b. In the case of the transistor M2a, during the period T1a, the transistor M2a is turned on and the potential V1 is applied to the transistor In the period T1b, the potential is supplied to the wiring 12 through the transistor M2a. b is turned on, and the potential V1 is supplied to the wiring 12 via the transistor M2b.

[0051] In addition, the circuit 10 stops supplying potential to the node N1 during periods T4a and T4b. In this case, the node N1 is in a floating state during the period T4a and the period T4b. The potential of the node N1 is the potential during the period T3a or T3b (when the transistor M1 is off). Therefore, transistor M1 remains off since the potential at

[0052] In addition, the circuit 10 stops supplying potential to the node N3 during periods T4a and T4b. In this case, during the period T4a, the node N3 and the node N2a are in a floating state. Since the potential of the node N2a is maintained at a potential at which the transistor M2a is turned on, In the period T4b, the transistor M2a remains on. N2b becomes floating. The potential of node N2b becomes the potential at which transistor M2b turns on. Therefore, transistor M2b remains on.

[0053] The W (W is the channel width) / L (L is the channel length) of the transistor M1 is shown in FIG. It is preferable that the transistor in the sequential circuit is the largest. The W / L of the transistor M1 is greater than the W / L of the transistor M2a and the transistor M2b. In addition, when the circuit 10 includes a transistor, the W / L of the transistor M1 is preferably is preferably larger than the W / L of the transistors included in the circuit 10.

[0054] In addition, the W / L of the transistor M2a is approximately equal to the W / L of the transistor M2b. For example, the W / L of the transistor M2a is preferably within ±1 of the W / L of the transistor M2b. It is preferable that the difference is within 0%. More preferably, the difference is within ±5%.

[0055] In this specification, W / L may be replaced with W. This is because the channel lengths are often equal or approximately equal.

[0056] The period Ta and the period Tb are switched during the period T4a or T4b. Specifically, during the period T4a, the switch S3a and the switch S4b The switch S3b and the switch S4a change from off to on. In addition, during the period T4b, the switches S3b and S4a are turned from off to on. It is preferable that the switch S3a and the switch S4b are turned from on to off. In this way, it is possible to prevent malfunctions caused by switching between the periods Ta and Tb.

[0057] After the switches S3a and S4b are turned from on to off, the switch S3b and switch S4a may be turned from off to on. After the switch S4a is turned from on to off, the switches S3a and S4b are turned from off to on. That is, the switches S3a, S3b, S4a and S4b may be connected to the In this way, the fourth terminal of the circuit 10 may have a period during which the switch S4b is off. This can prevent electrical continuity between the wiring 14 and the wiring 15.

[0058] In addition, the period T1a to the period T4a are repeated multiple times (for example, 100 times or more, more preferably 200 times). 300 times or more, and more preferably 300 times or more), the period Ta is switched to the period Tb. It is preferable to repeat the period T1b to the period T4b multiple times (100 times or more, Preferably, the number of times is 200 or more, more preferably, 300 or more, and then the period Tb is It is preferable that the period Ta is switched from the period T1a to the period T 4a in a plurality of units (for example, 100 units or more, more preferably 200 units or more, and even more preferably Preferably, the period Tb has the number of the period T1b to the period T2b. T4b or more (100 or more, more preferably 200 or more, even more preferably In this way, the switching between the period Ta and the period Tb can be performed with ease. However, if the number of repetitions is too large, the power consumption can be reduced. This may cause variations in the characteristics of the transistors M2a and M2b. Therefore, the number of times the periods T1a to T4a are repeated, or the number of times the periods T1b to T4b are repeated, The number of repetitions is less than 1000 times, more preferably less than 700 times, and even more preferably less than 500 times. It is preferable that the number of times is less than one.

[0059] Note that a transistor can be used as the switch. ) are switches S3a, S3b, S4a and S4b. The transistors M3a, M3b, M4a and M4 The sequential circuits to which transistors M3a, M3b, and M3c are applied are shown. Transistor M4a and transistor M4b have the same polarity as transistor M1. A first terminal of the resistor M3a is connected to the node N3, and a second terminal of the resistor M3a is connected to the node N2a. The first terminal of the transistor M3b is connected to the node N 3, a second terminal is connected to the node N2b, and a gate is connected to the wiring 16b. The transistor M4a has a first terminal connected to the wiring 14 and a second terminal connected to the node N2a. The first terminal of the transistor M4b is connected to the line 16b, and the gate of the transistor M4b is connected to the line 16b. A transistor having a first terminal connected to the line 14, a second terminal connected to the node N2b, and a gate connected to the wiring 16a. The signal or potential of the wiring 16a controls the on / off state of the transistor M3a. It is preferable that the transistor M4b has a function of controlling the on / off of the transistor M4b. The signal or potential of the wiring 16b controls the on / off state of the transistor M3b. It is preferable that the transistor M4a has a function of controlling the on / off of the transistor M4a. In this embodiment, for convenience, the signal SELa is input to the wiring 16a, and the wiring 16 It is assumed that the signal SELb is input to b.

[0060] During the period Ta, the signal SELa is at a high level and the signal SELb is at a low level. Therefore, transistors M3a and M4b are on, and transistors M3b and During a period Tb, the signal SELa is at a low level, and the transistor M4a is off. The signal SELb is at a high level. Therefore, the transistors M3a and M4b is off, and transistor M3b and transistor M4a are on. The transistor M3a, the transistor M3b, the transistor M4a, and the transistor M4b , switch S3a, switch S3b, switch S4a and switch S4b, respectively. Therefore, the sequential circuit of FIG. 1(B) is controlled to be on or off at the timing of FIG. ) can perform the same operation as the sequential circuit of FIG. 1(A), and therefore has the same effect as the sequential circuit of FIG. It plays a key role.

[0061] The low-level potential of the signals SELa and SELb may be set to the potential V1. However, the present invention is not limited to this, and the low level potentials of the signals SELa and SELb may be set to less than the potential V1. This allows the potential difference between the gate and source of the transistor to be 0[ V], it is possible to suppress changes in the transistor characteristics.

[0062] The high-level potential of the signals SELa and SELb may be set to the potential V2. However, the present invention is not limited to this, and the high-level potential of the signal SELa and the signal SELb may be set higher than the potential V2. In this way, the potentials of the nodes N2a and N2b can be increased. It is possible.

[0063] After the signal SELa goes from high to low, the signal SELb goes low. Also, the signal SELb may go from high to low. After the signal SELa goes from low to high, the signal S There may be a period during which the signals ELa and SELb are at a low level. This can prevent electrical continuity between the fourth terminal of the semiconductor device 10 and the wiring 14.

[0064] It should be noted that the W / L of the transistor M3a is approximately equal to the W / L of the transistor M3b. For example, the W / L of the transistor M3a is preferably within ±1 of the W / L of the transistor M3b. It is preferable that the difference is within 0%. More preferably, it is within ±5%. It is preferable that the W / L of the transistor M4a is approximately equal to the W / L of the transistor M4b. For example, the W / L of transistor M4a is within ±10% of the W / L of transistor M4b. It is preferable that the difference is within ±5%. More preferably, the difference is within ±5%. The W / L of 1 is the transistor M3a, the transistor M3b, the transistor M4a, and the transistor M4b. It is preferable that the W / L of the transistor M2a and the transistor M4b is larger than that of the transistor M2a and the transistor M4b. The W / L of the transistor M2b is It is preferable that the W / L of the transistor M4a and the transistor M4b is larger than that of the transistor M4a. The W / L of the transistor M4a and the transistor M4b is It is preferable that W / L of b is larger than W / L of b.

[0065] This embodiment can be implemented in appropriate combination with the configurations described in other embodiment modes. Cut.

[0066] (Embodiment 2) In this embodiment, a circuit that can be applied to the sequential circuit 10 of the first embodiment will be described. I will explain this in more detail.

[0067] The circuit 10 in FIG. 8A includes a transistor M5, a transistor M6, and a circuit 20. Transistor M5 and transistor M6 have the same polarity as transistor M1. A first terminal of the transistor M5 is connected to the wiring 15, and a second terminal of the transistor M5 is connected to the node N1. The gate of the transistor M6 is connected to the wiring 15. The first terminal of the transistor M6 is connected to the wiring 13. The second terminal is connected to the node N1, and the gate is connected to the wiring 14. One terminal is connected to a node N1, and the second terminal is connected to a node N3.

[0068] The circuit 20 supplies a transistor M2a or a transistor M2b to a node N3 in response to the potential of the node N1. The second transistor M2b has a function of supplying a potential for controlling the on / off of the second transistor M2b. When the potential of the node N1 is low (for example, during periods T3a, T3b, and T4a During a period T4b, the transistor M2a or the transistor M2b is connected to the node N3. The circuit 20 has a function of supplying a potential that turns on the node N1. At some time (e.g., period T1a, period T1b, period T2a, or period T2b, etc.), node N3 has a function of supplying a potential to turn off the transistor M2a or the transistor M2b. In addition, the input terminal of the circuit 20 is connected to the node N1, and the output terminal is connected to the node N3. The inverter circuit may be replaced with an inverter circuit.

[0069] During periods T1a and T1b, transistor M5 is turned on and transistor M6 The signal SP is supplied to the node N1 via the transistor M5. Since P is at a high level, the potential of the node N1 rises. The threshold voltage of transistor M5 is subtracted from the potential of the gate of transistor M5 (for example, potential V2). When this voltage reaches this value, the transistor M5 is turned off, and the node N1 is thus left floating. In addition, the circuit 20 sets a potential at which the transistor M2a or the transistor M2b is turned off as a node. The power supply will be supplied to N3.

[0070] During periods T2a and T2b, transistor M5 remains off, and transistor The transistor M6 remains off. Also, the circuit 20 does not turn on the transistor M2a or the transistor M 2b remains supplied to node N3 at a potential that turns it off.

[0071] During periods T3a and T3b, transistor M5 remains off and transistor The potential V1 is supplied to the node N1 through the transistor M6. Therefore, the potential of the node N1 becomes the potential V1. A potential that turns on the transistor M2b is supplied to the node N3.

[0072] During periods T4a and T4b, transistor M5 remains off and transistor In addition, the circuit 20 is configured such that the transistor M2a or the transistor M2b is turned on. The potential at which the transistor is turned on remains supplied to the node N3.

[0073] The circuit 10 in FIG. 8B is different from that in FIG. 8A in that the transistor M7a and the transistor The difference is that the transistor M7a and the transistor M7b are transistors The first terminal of the transistor M7a is connected to the wiring 13. , a second terminal is connected to the node N1, and a gate is connected to the node N2a. A first terminal of the transistor M7b is connected to the wiring 13, a second terminal of the transistor M7b is connected to the node N1, and a gate The port is connected to node N2b.

[0074] In the periods T1a, T2a, T1b, and T2b, the transistors M7a and The transistor M7b is off. During the period T4a, the transistors M7a and M7b are on. In the period T4b, the transistor M7a is on and the transistor M7b is off. In this case, the transistor M7a is off and the transistor M7b is on. In the circuit 10, the potential V1 is This makes it easier to maintain the potential of the node N1 at the potential V1.

[0075] The circuit 10 in FIG. 9A is different from the circuit in FIG. 8A in that the gate of the transistor M5 is connected to the wiring 17 The signal or potential of the wiring 17 is connected to the transistor M5. It is preferable that the wiring 17 has a function of controlling the ON / OFF state. The signal CK2 is input. The signal CK2 is an inverted version of the signal CK1. For example, the signal CK2 has a period T1a and a period T It is at a high level during periods T1b, at a low level during periods T2a and T2b, and at a low level during period T3 a and T3b, the level is high or low, and the level is low in periods T4a and T4b. The high level and the low level are repeated.

[0076] During periods T1a and T1b, the transistor M5 is turned on. is supplied to node N1 via transistor M5. Since signal SP is at a high level, However, the potential of the node N1 rises when the potential of the node N1 is When the potential of the transistor M1 becomes equal to the potential of the transistor M2 (for example, potential V2) minus the threshold voltage of the transistor M5, During periods T2a and T2b, the transistor M5 is turned off. M5 is off. In addition, in periods T3a and T3b, the signal CK2 is at a high level. If so, the transistor M5 is on. Therefore, the signal SP is On the other hand, if the signal CK2 is at a low level, the transistor M5 During periods T4a and T4b, the transistor M5 is turned on and off. If the transistor M5 is on, the signal SP is input through the transistor M5. In the circuit 10 of FIG. 9A, in the periods T4a and T4b, Since the signal SP is at a low level, the node N This makes it easier to maintain the potential of 1 at potential V1.

[0077] The circuit 10 in FIG. 9B is different from the circuit in FIG. 8A in that the first terminal of the transistor M5 is connected to the wiring The difference is that the signal or potential of the wiring 18 turns on the transistor M1. In this embodiment, for convenience, the potential V2 is supplied to the wiring 18. It shall be so.

[0078] During the periods T1a and T1b, the transistor M5 is on. is supplied to node N1 via transistor M5, so the potential at node N1 rises. However, when the potential of the node N1 is changed from the potential of the gate of the transistor M5 (for example, the potential V2), When the voltage drops below the threshold voltage of transistor M5, transistor M5 turns off. In the periods T2a to T4a and the periods T2b to T4b, In the circuit 10 of FIG. 9B, during the periods T1a and T1b, The potential V2 is supplied to the node N1. Therefore, the current flowing through the wiring 15 can be reduced. can.

[0079] In FIG. 8B, the gate of the transistor M5 is connected to the wiring 17 as in FIG. 9A. Alternatively, the first terminal of the transistor M5 may be connected to the wiring 18 as in FIG. 9B. In particular, in FIG. 8B, the gate of the transistor M5 is connected to the wiring 17. Then, during periods T4a and T4b, transistor M7a or transistor The potential V1 supplied via the transistor M7b is supplied to the wiring 15 via the transistor M5. This makes it easier to maintain the potential of the wiring 15 at the potential V1.

[0080] In addition, in FIG. 8(A), FIG. 8(B), and FIG. 9(B), the first terminal of the transistor M5 may be connected to the wiring 17. In this way, for example, during the period T1a, part of the period T4a, During T1b or part of period T4b, the potential of the first terminal of the transistor M5 is low. Therefore, the change in the characteristics of the transistor M5 can be suppressed.

[0081] In addition, in FIG. 8(A), FIG. 8(B) and FIG. 9(B), the first terminal is connected to the wiring 15. a transistor having a second terminal connected to the node N1 and a gate connected to the wiring 17; In this case, the same effect as that of the circuit 10 in FIG. Cut.

[0082] In addition, in FIG. 8(A), FIG. 8(B) and FIG. 9(A), the first terminal is a wiring 18 or a wiring 17, a second terminal connected to the node N1, and a gate connected to the wiring 15. A transistor may be newly provided. In this case, the same effect as that of the circuit 10 in FIG. 9B can be obtained. It is possible.

[0083] As shown in FIG. 9A, the first terminal of the circuit 10 is connected to the wiring 15, and the second terminal is In the case where the transistor has a gate connected to the line N1 and a gate connected to the line 17, Diester M6 may be omitted.

[0084] In the circuit 10 described above, the first terminal of the transistor M6 is connected to the wiring 11. Good too.

[0085] Note that in the above-described circuit 10, the first terminal of the circuit 20 may be connected to the wiring 12.

[0086] In the above-described circuit 10, the first terminal of the transistor M6 is connected to the wiring 18 or the wiring 1. 7, and the second terminal of the transistor M6 may be connected to the node N3. A first terminal is connected to the wiring 18 or the wiring 17, a second terminal is connected to the node N3, and a gate Alternatively, a transistor having a first terminal connected to the wiring 14 may be provided. The second terminal is connected to the line 18 or the wiring 17, the second terminal is connected to the node N2a, and the gate is connected to the wiring 1. A transistor connected to the line 4 and a first terminal connected to the line 18 or the line 17 and a second A transistor having a terminal connected to the node N2b and a gate connected to the wiring 14, It may also be provided in.

[0087] Next, a circuit that can be applied to the circuit 20 will be described.

[0088] The circuit 20 in FIG. 10A includes a transistor M8 and a transistor M9. Transistor M8 and transistor M9 have the same polarity as transistor M1. 8 has a first terminal connected to the wiring 18 and a second terminal connected to a second terminal of the circuit 20. The first terminal of the transistor M9 is connected to the wiring 13, and the gate of the transistor M9 is connected to the wiring 18. The second terminal is connected to the second terminal of the circuit 20, and the gate is connected to the first terminal of the circuit 20. In the periods T1a, T2a, T1b, and T2b, the transistor The transistor M8 is on, and the transistor M9 is on. During periods T3b and T4b, transistor M8 is turned on and then off. StaM9 is off.

[0089] The first terminal of the transistor M8 may be connected to the wiring 11 or the wiring 17. The gate of the transistor M8 may be connected to the wiring 11 or the wiring 17. Both the first terminal and the gate of the transistor M8 may be connected to the wiring 11 or the wiring 17.

[0090] The circuit 20 in FIG. 10B includes transistors M10 to M13. Transistors M10 to M13 have the same polarity as transistor M1. The resistor M10 has a first terminal connected to the wiring 18 and a second terminal connected to the second terminal of the circuit 20. The transistor M11 has a first terminal connected to the wiring 13 and a second terminal The transistor is connected to the second terminal of the circuit 20 and the gate is connected to the first terminal of the circuit 20. The transistor M12 has a first terminal connected to the wiring 18 and a second terminal connected to the The first terminal of the transistor M13 is connected to the gate of the transistor M14, and the gate of the transistor M14 is connected to the wiring 18. is connected to the wiring 13, the second terminal is connected to the gate of the transistor M10, and the gate The first terminal of the circuit 20 is connected to the first terminal of the circuit 20. At b, transistor M10 is off and transistor M11 is on. Transistor M12 is on and transistor M13 is on. During periods T3b and T4b, the transistor M10 is on. Transistor M11 is off, transistor M12 is on and then off, and transistor M1 3 is off.

[0091] The first terminal of the transistor M10, the first terminal of the transistor M12, and the The gate of the transistor M12 may be connected to the wiring 11 or the wiring 17. In this way, during the period T4 During periods T4a and T4b, the circuit 20 outputs a signal that alternates between high and low levels. Therefore, the characteristic changes of the transistors M2a and M2b can be suppressed. It can be suppressed.

[0092] The circuit 20 in FIG. 10C includes transistors M14 to M18 and a capacitor element C. Transistors M14 to M18 have the same polarity as transistor M1. The transistor M14 has a first terminal connected to the wiring 18 and a second terminal connected to the circuit The first terminal of the transistor M15 is connected to the wiring 13. The second terminal is connected to the second terminal of the circuit 20, and the gate is connected to the first terminal of the circuit 20. The transistor M16 has a first terminal connected to the wiring 18 and a gate connected to the transistor A first terminal of the transistor M17 is connected to the gate of the line 13. The second terminal of the transistor M16 is connected to the second terminal of the transistor M17, and the gate of the transistor M17 is connected to the first terminal of the transistor M18. The first terminal of the transistor M18 is connected to the wiring 13, and the second terminal of the transistor M19 is connected to the wiring 14. The terminal of the transistor M14 is connected to the gate of the transistor M14, and the gate of the transistor M14 is connected to the first terminal of the circuit 20. The capacitance element C has a first electrode connected to a first terminal of the circuit 20 and a second electrode connected to a transistor. The second terminal of the transistor M16 is connected to the second terminal of the transistor M17. During a period T2b, the transistor M14 is off and the transistor M15 is on. Therefore, transistor M16 is off, transistor M17 is on, and transistor M18 is on. In periods T3a, T4a, T3b, and T4b, Transistor M14 is on, transistor M15 is off, and transistor M16 is on, transistor M17 is off, and transistor M18 is off. The circuit 20 in FIG. 10(C) controls the capacitive coupling of the capacitive element C during periods T3a and T3b. The second transistor M14 and the second transistor M16 are turned on using the The rise time of the potential of the terminal can be shortened. Since the timing at which transistor M2b turns on can be advanced, the output of the signal OUT The fall time can be made shorter.

[0093] This embodiment can be implemented in appropriate combination with the configurations described in other embodiment modes. Cut.

[0094] (Embodiment 3) In this embodiment, a shift register circuit to which a sequential circuit according to one embodiment of the present invention is applied will be described. He explains.

[0095] FIG. 11 shows a shift register circuit according to the present embodiment. The shift register circuit in FIG. The sequential circuits 30 are N (N is a natural number of 3 or more). Only sequential circuits 0[1] to 30[3] are shown.

[0096] In the shift register circuit of FIG. 11, the sequential circuit of FIG. 1B is applied as the sequential circuit 30. In the sequential circuit 30[i] (i is 2 or more and N-1 or less), the signal SOUT[ i-1] is input to the wiring 16a, the signal SELa is input to the wiring 16b, and the signal SE Lb is input, the signal SOUT[i+1] is input to the wiring 14, and the potential V 1 is input, and a signal SOUT[i] is output from the wiring 12. In the circuit 30, the signal SCK1 is input to the wiring 11, and in the even-numbered sequential circuits 30 A signal SCK2 is input to the wiring 11. Compared to [i], the difference is that the signal SSP is input to the wiring 11. 30[N] is different from the sequential circuit 30[i] in that the wiring 14 is connected to a reset signal or a signal SSP The difference is where the is entered.

[0097] The signal SCK1 is a signal similar to the signal CK1, and the signal SCK2 is a signal similar to the signal CK2. The signal SSP is a start pulse for the shift register circuit, and is the same as the signal SP. Moreover, the signal SOUT is a signal similar to the signal OUT.

[0098] In addition, when the circuit 10 is connected to the wiring 17 as shown in FIG. In the odd-numbered sequential circuit 30, the signal SCK2 is input to the wiring 17, and the even-numbered sequential circuit 3 In the case of 0, the signal SCK1 is input to the wiring 17.

[0099] In addition, when the circuit 10 is configured to have the wiring 18 connected as shown in FIG. In the sequential circuit 30 of each stage, the potential V2 may be supplied to the wiring 18.

[0100] This embodiment can be implemented in appropriate combination with the configurations described in other embodiment modes. Cut.

[0101] (Embodiment 4) In this embodiment mode, a panel structure using a liquid crystal element as a display element will be shown as an example.

[0102] The panel 60 shown in FIG. 12A includes a pixel section 61, a scanning line driving circuit 63, and a signal line driving circuit 64. The pixel section 61 has a plurality of pixels 62 and a circuit for selecting the pixels 62 for each row. a plurality of scanning lines G for supplying image signals to selected pixels 62; Each pixel 62 has at least one of the scanning lines G and at least one of the signal lines S. The scanning line driving circuit 63 outputs a signal to the scanning line G. The signal line driving circuit 64 outputs an image signal to the signal line S.

[0103] The scanning line driving circuit 63 has a shift register circuit. The output signal of the shift register circuit is are sequentially input to the scanning line G. A sequential circuit according to one embodiment of the present invention can be applied.

[0104] The type and number of wirings provided in the pixel section 61 depend on the configuration, number and arrangement of the pixels 62. Specifically, in the case of the pixel section 61 shown in FIG. The pixels 62 in a row are arranged in a matrix, and the signal lines S1 to Sx and the scanning line G1 10 shows an example in which the scanning lines Gy are arranged within the pixel portion 61.

[0105] FIG. 12B shows an example of the configuration of a pixel 62. The pixel 62 includes a liquid crystal element 65 and a transistor. The liquid crystal element 65 has a first electrode (also called a pixel electrode) and a second electrode 66 and a capacitance element 67. ) and a second electrode (also called a counter electrode), and a liquid to which a voltage is applied between the first electrode and the second electrode. and a liquid crystal layer containing a crystalline material. The transistor 66 has a signal at either the source or the drain. The other of the source and drain is connected to one of the signal lines S1 to Sx. The gate of the transistor 65 is connected to one of the scanning lines G1 to Gy. The transistor 66 controls electrical continuity or non-conduction between the signal line S and the first electrode of the liquid crystal element 65. The first electrode of the capacitor 67 is connected to the first electrode of the liquid crystal element 65. The first electrode of the liquid crystal element 65 is connected to a capacitance line (not shown). The capacitance line is connected to the capacitance electrode.

[0106] In addition, the second electrode of the liquid crystal element 65 may be common to each pixel 62. In the element 62, the second electrode of the capacitance element 67 may be connected to the same capacitance wiring. The same common potential as that of the second electrode of the liquid crystal element 65 may be supplied to the capacitance line.

[0107] The pixel 62 may include a transistor, a diode, a resistive element, a capacitive element, an inductor, etc. Other elements may also be included.

[0108] In one embodiment of the present invention, in the pixel 62, the charge stored in the liquid crystal element 65 and the capacitor 67 is A transistor with low off-state current is used as a switch for retaining the accumulated charge. Specifically, in the case of the pixel 62 shown in FIG. The small current prevents charge from leaking through transistor 66. Therefore, the potential corresponding to the image signal applied to the liquid crystal element 65 and the capacitance element 67 can be more reliably held. Therefore, the transparency of the liquid crystal element 65 can be reduced by the leakage of electric charges during one frame period. This prevents the transmittance from changing, thereby improving the quality of the displayed image. In addition, when the off-current of the transistor 66 is small, the charge leaks through the transistor 66. This can prevent the capacitance element 67 from becoming too large, thereby making it possible to reduce the area of ​​the capacitance element 67. This increases the transmittance of the panel 60, thereby improving the light supply efficiency of the backlight, frontlight, etc. The loss of light supplied from the supply unit within the panel 60 is reduced, and the consumption power of the liquid crystal display device is reduced. The power can be reduced.

[0109] In this embodiment, a panel using a liquid crystal element as a display element has been described. A light-emitting element may be used as the display element. ing Diode) and OLED (Organic Light Emitting D This category includes elements whose brightness is controlled by current or voltage, such as LEDs. For example, an OLED has at least an EL layer, an anode, and a cathode. The EL layer is composed of a single layer or multiple layers between the anode and cathode. Among these layers, at least a light-emitting layer containing a light-emitting substance is included. When the potential difference between the anode and the cathode becomes equal to or greater than the threshold voltage Vth of the light-emitting element, the The current causes electroluminescence. Luminescence (fluorescence) when returning from the single excited state to the ground state and when returning from the triplet excited state to the ground state This includes luminescence (phosphorescence).

[0110] By applying a sequential circuit according to one embodiment of the present invention to the scan line driver circuit 63, The fall time of the signal can be shortened. Therefore, the image signal corresponding to another row is This prevents the image from being input to the pixel 62, so that a more accurate image signal can be maintained. This makes it possible to improve the display quality.

[0111] Note that when the sequential circuit according to one embodiment of the present invention is applied to the scan line driver circuit 63, the pixel 62 The transistor 66 preferably has the same polarity as the transistor M1. The transistors provided on the same substrate as the scan line driver circuit 63 have the same polarity as the transistor M1. It is preferable that there is.

[0112] This embodiment can be implemented in appropriate combination with the configurations described in other embodiment modes. Cut.

[0113] (Embodiment 5) In the semiconductor device according to one embodiment of the present invention, a silicon substrate is formed of amorphous, microcrystalline, polycrystalline, or single crystal. A transistor having a channel forming region in a semiconductor film such as silicon or germanium is used. It may be a material with a wider band gap than silicon and a lower intrinsic carrier density than silicon. A transistor having a channel formation region in a semiconductor film lower than the above may be used.

[0114] Silicon is produced by vapor phase growth methods such as plasma CVD or sputtering. The amorphous silicon is then crystallized by laser annealing or other processes. Polycrystalline silicon, which is made by injecting hydrogen ions into a single crystal silicon wafer, and single crystal silicon, which is made by peeling off the surface layer. Crystalline silicon or the like can be used.

[0115] Impurities such as moisture or hydrogen, which act as electron donors, are reduced, and oxygen deficiencies are eliminated. The highly purified oxide semiconductor (purified OS) is Therefore, the oxide semiconductor film is highly purified. A transistor having a channel formation region has an extremely small off-state current and high reliability.

[0116] Specifically, the present invention relates to an on-state transistor having a channel formation region in a highly purified oxide semiconductor film. The small fringe current can be proven by various experiments. For example, 0 6 Even with a device with a channel length of 10 μm, the voltage between the source and drain electrodes is In the drain voltage range of 1V to 10V, the off-state current was measured by the semiconductor parameter analyzer. Below the riser measurement limit, i.e. 1×10 -13 It is possible to obtain a characteristic of A or less. In this case, the off-current normalized by the transistor channel width is 100zA / In addition, the capacitance element is connected to the transistor, and the A circuit that controls the charge flowing in or out of the capacitance element with the transistor is used to The current was measured. is used for the channel formation region, and the charge amount per unit time of the capacitance element is used to determine the transistor The off-state current of the transistor was measured. It was found that an even smaller off-state current of several tens of yA / μm could be obtained when the voltage was 3 V. Therefore, a transistor in which a highly purified oxide semiconductor film is used for a channel formation region can be obtained. The off-state current of the transistor using crystalline silicon is significantly smaller than that of the transistor using crystalline silicon.

[0117] Unless otherwise specified, in this specification, the off-state current is In this case, the drain is set to a higher potential than the source and gate, and the source potential is set to the base potential. The current that flows between the source and drain when the gate potential is below zero when the gate is held constant Alternatively, in this specification, the off-state current refers to a p-channel transistor. In this case, the drain is set to a lower potential than the source and gate, and the source potential is set to the base potential. The current that flows between the source and drain when the gate potential is equal to or greater than 0 when the gate potential is set to the reference potential. This means that:

[0118] Next, an example of a transistor including a channel formation region in an oxide semiconductor film will be described with reference to FIG. This will be described with reference to the following.

[0119] FIG. 13A shows a transistor 201 provided in a pixel and a transistor 202 provided in a driver circuit. The cross-sectional structure of the resistor 202 is shown as an example.

[0120] The transistor 201 shown in FIG. 13A is provided on an insulating surface and functions as a gate. A conductive film 204 is formed on the insulating film 205. A conductive film 204 is formed on the insulating film 205. A semiconductor film 206 is provided at a position overlapping with the semiconductor film 204, and a source 13, a conductive film 207 and a conductive film 208 functioning as a drain or a gate. In (A), an insulating film 209 and an insulating layer 208 are formed on a semiconductor film 206, a conductive film 207, and a conductive film 208. The transistor 201 is provided with an insulating film 20 9 and the insulating film 210 may be included as components thereof. An insulating film 211 is provided on the insulating film 209, the insulating film 210, An opening is provided in the insulating film 211, and the insulating film 211 is provided with A conductive film 203 connected to the conductive film 207 is provided.

[0121] The conductive film 203 functions as a first electrode of a display element. The liquid crystal layer has a first electrode and a second electrode, and an electric field is applied to the liquid crystal layer by the first electrode and the second electrode. Therefore, when the liquid crystal element is formed over the transistor 201, in addition to the conductive film 203, A conductive film functioning as a display element and a liquid crystal layer may be provided over the insulating film 211. When the device is an OLED, the conductive film 203, which functions as either an anode or a cathode, is applied. The conductive film that functions as the other of the anode and the cathode and the EL layer are covered with an insulating film 211. It should be placed on top.

[0122] Note that by using a resin for the insulating film 211, unevenness may occur on the surface on which the conductive film 203 is formed. In other words, the flatness of the surface on which the conductive film 203 is formed can be improved. Specifically, the insulating film 211 can be made of acrylic resin, epoxy resin, benzocyclobutene, Organic materials such as polyimide and polyamide can be used. In addition to the above materials, silicone resins and the like can be used. By laminating a plurality of insulating films, the insulating film 211 can be formed with higher flatness.

[0123] The conductive film 203 is made of indium oxide or indium tin oxide (ITO). indium tin oxide), silicon or silicon oxide-containing indium oxide oxide Tin oxide, Indium zinc oxide, Tin oxide Indium oxide containing zinc oxide and indium oxide containing nitrogen, Al-Zn-based oxide semi-conductor Conductor, Zn-based oxide semiconductor containing nitrogen, Sn-Zn-based oxide semiconductor containing nitrogen, Gold (Au), Platinum (Pt), Nickel (Ni), Tungsten (W), Chromium (Cr), Molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd) In addition to titanium (Ti), elements in the first or second group of the periodic table, namely lithium Alkali metals such as lithium (Li) and cesium (Cs), as well as magnesium (Mg), calcium (Ca) Alkaline earth metals such as calcium (Ca), strontium (Sr), and alloys containing these metals (MgAg, AlLi), europium (Eu), ytterbium (Yb) and other rare earth elements The conductive film 203 may be made of, for example, stainless steel. After forming a conductive film using the above material by a sputtering method, a deposition method, or the like, a photolithography method is performed. The conductive film is processed into a desired shape by etching using a filler method, thereby forming the conductive film. This can be done.

[0124] The transistor 202 shown in FIG. 13A is provided on an insulating surface and functions as a gate. A conductive film 212 is formed on the insulating film 205. A semiconductor film 213 is provided at a position overlapping with the semiconductor film 212, and a source 13, a conductive film 214 and a conductive film 215 functioning as a drain or a gate. In (A), an insulating film 209 and an insulating layer 211 are formed on a semiconductor film 213, a conductive film 214, and a conductive film 215. The insulating film 209 and the insulating film 210 are laminated in order. An insulating film 211 made of resin is provided thereon.

[0125] Note that in FIG. 13A, The conductive film 203 that functions as an electrode of the liquid crystal element in the pixel is insulated. With the above-mentioned configuration, one conductive film may be formed as desired by etching or the like. By processing the conductive film 203 into a shape, a conductive film that functions as a back gate is formed. Therefore, the back gate and the semiconductor device can be formed without increasing the manufacturing process of the semiconductor device. A conductive film that functions as a back gate can be provided. In the latter case, the gate ( The front gate and the back gate may be given the same potential, or the back gate may be given the same potential. A fixed potential such as a ground potential may be applied only to the gate. By controlling the potential, the threshold voltage of the transistor 202 can be controlled. By providing a back gate, the channel formation area is increased, resulting in an increase in drain current. In addition, by providing a back gate, a depletion layer is easily formed in the semiconductor film. Therefore, the S value can be improved.

[0126] In FIG. 13A, the insulating film 211 is not provided between the semiconductor film 206 and the semiconductor film 213. The insulating film 209 and the insulating film 210 are provided. The insulating film provided between the semiconductor film 213 and the insulating film 211 may be a single film or a three-layer film. The above multiple layers may be used.

[0127] The insulating film 210 contains oxygen in an amount equal to or greater than the stoichiometric composition, and the oxygen is removed by heating. It is preferable that the insulating film has a function of supplying a part of the insulating film to the semiconductor film 206. The insulating film 210 preferably has few defects. Typically, the insulating film 210 has a silicon The spin density of the signal at g=2.001 due to the dangling bond of 1 8 spins / cm 3 However, it is preferable that the insulating film 210 is not thicker than the semiconductor film 20. 6 and the semiconductor film 213, the insulating film 210 may be damaged when the insulating film 210 is formed. When a photoresist is applied, as shown in FIG. 13A, the insulating film 209 is formed on the semiconductor film 206 and the It is preferable to provide the insulating film 209 between the semiconductor film 213 and the insulating film 210. The damage to the body membrane 206 is smaller than that of the insulating film 210, and the oxygen permeability is also improved. However, the semiconductor film 206 and the semiconductor film 207 are preferably insulating films having a function of 13, while minimizing damage to the semiconductor film 206 and the semiconductor film 213. If the contact insulating film 210 can be formed, the insulating film 209 is not necessarily provided. is also good.

[0128] It is preferable that the insulating film 209 has few defects. Typically, the insulating film 209 has the following characteristics as determined by ESR measurement: The spin density of the signal at g=2.001 due to the silicon dangling bond is 3 ×10 17 spins / cm 3 It is preferable that the thickness of the insulating film 209 is less than 100 nm. If the density of defects is high, oxygen will be bonded to the defects, and the amount of oxygen in the insulating film 209 will increase. This is because the amount of transmission decreases.

[0129] In addition, there are few defects at the interfaces between the insulating film 209 and the semiconductor film 206 and between the insulating film 209 and the semiconductor film 213. Preferably, and typically, the direction of the magnetic field is applied parallel to the film surface to measure the ESR. g= The spin density of the signal appearing at 1.93 is 1×10 17 spins / cm 3 Further detection It is preferably equal to or lower than the lower limit.

[0130] Specifically, the insulating film 209 or the insulating film 210 is a silicon oxide film or a silicon oxynitride film. A Con membrane can be used.

[0131] Next, as shown in FIG. 13B, an insulating film 210 and an insulating layer are further added to the cross-sectional structure shown in FIG. When an insulating film 217 is provided between the film 211 and the transistor 201, 1 shows an example of a cross-sectional structure of a conductive film 203 and a transistor 202 connected to an insulating film 203. It is desirable that the boundary layer 217 has a blocking effect to prevent the diffusion of oxygen, hydrogen, and water. Alternatively, it is preferable that the insulating film 217 has a blocking effect to prevent the diffusion of hydrogen and water. I wish.

[0132] The higher the density of the insulating film, the more dense it is, and the fewer the dangling bonds it has, making it more chemically stable. Insulating films that exhibit a blocking effect against oxygen, hydrogen, and water include, for example, For example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, oxide yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. The insulating film that exhibits the blocking effect against hydrogen and water can be formed by, for example, a nitride film. Silicon, silicon oxynitride, etc. can be used.

[0133] When the insulating film 217 has a blocking effect against water, hydrogen, etc., the insulating film 21 using a resin is 1, water, hydrogen, and other impurities present outside the panel may enter the semiconductor film 206 or the semiconductor film The oxide film 206 or the semiconductor film 213 can be prevented from penetrating into the semiconductor film 213. When a semiconductor is used, some of the water or hydrogen that penetrates the oxide semiconductor acts as an electron donor. ), the insulating film 217 having the above blocking effect can be used to In order to prevent the threshold voltages of the transistors 201 and 202 from shifting due to the generation of donors, This can be done.

[0134] When an oxide semiconductor is used for the semiconductor film 206 or the semiconductor film 213, the insulating film 217 is The blocking effect of the above prevents oxygen from diffusing from the oxide semiconductor to the outside. As a result, oxygen vacancies that serve as donors in the oxide semiconductor can be reduced. The threshold voltages of the transistors 201 and 202 are shifted by the generation of donors. This can prevent this from happening.

[0135] The adhesion between the insulating film 217 and the insulating film 211 is higher than the adhesion between the insulating film 210 and the insulating film 211. In this case, the insulating film 217 can prevent the insulating film 211 from peeling off.

[0136] When oxide semiconductor films are used as the semiconductor films 206 and 213, The conductor preferably contains at least indium (In) or zinc (Zn). In addition, in order to reduce variations in electrical characteristics of transistors using the oxide semiconductor, It is preferable to have gallium (Ga) in addition to the above as a stabilizer. It is preferable to have tin (Sn) as a stabilizer. It is preferable that the alloy contains hafnium (Hf) as a stabilizer. It is preferable that the alloy contains zirconium (Zr) as a stabilizer. ) is preferably included.

[0137] Among oxide semiconductors, In-Ga-Zn oxides and In-Sn-Zn oxides are carbon Unlike silicon nitride, gallium nitride, or gallium oxide, sputtering and wet deposition methods This makes it possible to create transistors with excellent electrical characteristics, and is also suitable for mass production. Also, unlike silicon carbide, gallium nitride, or gallium oxide, The In-Ga-Zn oxide is used to form a transistor having excellent electrical characteristics on a glass substrate. It is also possible to manufacture larger substrates.

[0138] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru It may contain one or more of the elements tetraethium (Lu).

[0139] For example, oxide semiconductors include indium oxide, gallium oxide, tin oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, S n-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, I n-Hf-Zn oxide, In-La-Zn oxide, In-Pr-Zn oxide, In -Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In- Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-H O-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb -Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, In- Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide are used. It is possible.

[0140] For example, In-Ga-Zn oxide means an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In addition, metal elements other than In, Ga, and Zn In-Ga-Zn oxides have a sufficiently high resistance when no electric field is present, and therefore, The flow can be made sufficiently small and the mobility is also high.

[0141] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) The oxides of In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having a molecular ratio or an oxide having a composition close to that.

[0142] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0143] In one embodiment of the present invention, the crystal structure may be a single crystal, a polycrystal (also called a polycrystalline structure), or an amorphous structure. An oxide semiconductor film having such a state can be used for a transistor. The oxide semiconductor film is CAAC-OS (C Axis Aligned Crystal The film is a thin film of 1000 .mu.m thick, ...

[0144] The CAAC-OS film is neither completely single crystalline nor completely amorphous. The crystal parts contained in the OS film are small enough to fit inside a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the The boundary between the crystal and the crystalline part is not clear. Therefore, the CAAC-OS film does not have any in-boundary defects. The resulting decrease in electron mobility is suppressed.

[0145] The crystal parts in the CAAC-OS film have c-axes that are normal vectors to the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the ab plane and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. In this specification, when it is simply described as vertical, it means that The range of 5° to 95° is also included. This also includes the range from 1° to 5°.

[0146] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part becomes amorphous in the impurity-added region. It may also be pawned.

[0147] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (the shape of the film on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, the directions may differ from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0148] The electrical characteristics of transistors using CAAC-OS films change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0149] The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions in the sputtering target cleave from the ab plane, forming a -b: The particles peel off as plate-like or pellet-like sputtered particles with surfaces parallel to the surface. In this case, the plate-like sputtered particles may be crystalline and may be crystalline. By reaching the plate, a CAAC-OS film can be formed.

[0150] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0151] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber is In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0152] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably The deposition temperature is set to 200°C or higher and 500°C or lower. When a plate-shaped sputtered particle reaches a substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0153] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0154] As an example of a sputtering target, an In-Ga-Zn oxide target is The following is shown:

[0155] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified molar ratio and pressurized. Then, it is heated at a temperature between 1000℃ and 1500℃ to produce polycrystalline In-G The target is a-Zn oxide. X, Y, and Z are any positive numbers. , the predetermined molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z Powder, 2 :2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The type of powder and the molar ratio of the powder to be mixed depend on the sputtering target to be prepared. The setting can be changed as appropriate depending on the kit.

[0156] The semiconductor film 206 and the semiconductor film 213 are made of metal oxides having different atomic ratios of metals. A plurality of oxide semiconductor films formed using the target are stacked. For example, the atomic ratio of the target is In:Ga:Zn = 1:1:1, and the second oxide semiconductor film has In:Ga:Zn = 3:1:2. The atomic ratio of the target may be In:Ga Zn=1:3:2, the second oxide semiconductor film is In:Ga:Zn=3:1:2, the third The oxide semiconductor film may be formed so that the composition satisfies In:Ga:Zn=1:1:1.

[0157] Alternatively, the semiconductor film 206 and the semiconductor film 213 may be formed of metal oxide targets containing different metals. A plurality of oxide semiconductor films formed using the same may be stacked.

[0158] This embodiment can be implemented in appropriate combination with the configurations described in other embodiment modes. Cut.

[0159] (Embodiment 6) Taking a liquid crystal display device as an example, the appearance of a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. FIG. 14A shows a substrate 4001 and a substrate 4006 sealed with a sealing material 4005. FIG. 14(B) is a top view of the liquid crystal display device bonded to the substrate. FIG. 14(C) corresponds to a cross-sectional view taken along the dashed line B1-B2 in FIG. 14(A). In addition, in FIG. 14, FFS (Fringe Field Static) 1 illustrates a liquid crystal display device in a switching mode.

[0160] A pixel portion 4002 and a pair of scanning line driver circuits 4004 are provided on a substrate 4001. In addition, a sealing material 4005 is provided so that the pixel portion 4002 and the scanning line driver circuit 40 A substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. 4004 is sealed by a substrate 4001, a sealing material 4005, and a substrate 4006. In addition, in a region on the substrate 4001 that is different from the region surrounded by the sealing material 4005, A signal line driver circuit 4003 is mounted.

[0161] Note that a sequential circuit according to one embodiment of the present invention can be applied to the scan line driver circuit 4004. This allows the W / L of the transistor to be reduced, which in turn allows the frame to be made smaller. do.

[0162] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a substrate 4001. In FIG. 14B, a transistor 4010 included in a pixel portion 4002 and a transistor 4022 included in the scan line driver circuit 4004. In FIG. 14C, a transistor 4010 included in the pixel portion 4002 is illustrated.

[0163] In the pixel portion 4002 and the scanning line driver circuit 4004, a transistor 4010 and a transistor An insulating film 4020 made of resin is provided on the resistor 4022. A first electrode 4021 of a liquid crystal element 4023 and a conductive film 4024 are provided on the liquid crystal element 4020. The conductive film 4024 functions as a discharge path for charges accumulated in the insulating film 4020. Alternatively, the conductive film 4024 and the insulating film 4020 can be formed in the transistor 4022. The conductive film 4024 can be used as a component to function as a back gate.

[0164] An insulating film 4025 is provided on the insulating film 4020, the first electrode 4021, and the conductive film 4024. It is preferable that the insulating film 4025 has a high blocking effect against water, hydrogen, etc. The insulating film 4025 may be a silicon nitride film, a silicon nitride oxide film, or the like. do.

[0165] As shown in FIG. 14B and FIG. 14C, in one embodiment of the present invention, the insulating film 4020 is The insulating film 4025 on the insulating film 4020 is removed at the edge of the panel. Between the sealing material 4005 and the substrate 4001, the transistor 4010 and the transistor 4011 are The insulating film 4026 functions as a gate insulating film of the gate insulating film 022.

[0166] When the insulating film 4025 and the insulating film 4026 have a high blocking effect against water, hydrogen, and the like, The insulating film 4025 and the insulating film 4026 are in contact with each other at the edge of the panel, so that the insulating film 4025 and the insulating film 4026 are in contact with each other at the edge of the panel. Water, hydrogen, etc., enters the transistor 4010 and the transistor 4020 from the sealing material 4005. This can prevent the metal particles 4022 from penetrating into the semiconductor films that the metal particles 4022 have.

[0167] A second electrode 4027 of the liquid crystal element 4023 is provided on the insulating film 4025. A liquid crystal layer 4028 is provided between the second electrode 4027 and the insulating film 4025 and the substrate 4006. The liquid crystal element 4023 includes a first electrode 4021, a second electrode 4027, and a liquid crystal It has layer 4028.

[0168] In the liquid crystal element 4023, the value of the voltage applied between the first electrode 4021 and the second electrode 4027 is Accordingly, the orientation of the liquid crystal molecules contained in the liquid crystal layer 4028 changes, and the transmittance changes. The liquid crystal element 4023 changes its pixel voltage in response to the potential of an image signal applied to the first electrode 4021. By controlling the transmittance, it is possible to display gradations.

[0169] In one embodiment of the present invention, for example, a thermotropic liquid crystal or Alternatively, a liquid crystal material classified as a lyotropic liquid crystal can be used. For example, nematic liquid crystal, smectic liquid crystal, cholesteric liquid crystal, or dispersive liquid crystal may be used. A liquid crystal material classified as a cotic liquid crystal can be used. Alternatively, the liquid crystal layer can be, for example, Liquid crystal materials classified as ferroelectric liquid crystals or antiferroelectric liquid crystals can be used. The liquid crystal layer may be made of, for example, a main chain type polymer liquid crystal, a side chain type polymer liquid crystal, or a composite type polymer liquid crystal. Liquid crystal materials classified as polymer liquid crystals such as polymer liquid crystals or low molecular weight liquid crystals can be used. Alternatively, the liquid crystal layer may be made of a liquid crystal material classified as polymer dispersed liquid crystal (PDLC). It can be used.

[0170] In addition, a liquid crystal exhibiting a blue phase without using an alignment film may be used in the liquid crystal layer. When the temperature of a cholesteric liquid crystal is increased, the cholesteric phase changes to the isotropic phase. The blue phase appears only in a narrow temperature range, so The temperature range is improved by adding chiral agents and UV-curable resins. The liquid crystal composition containing the above has a short response time of 1 msec or less and is optically isotropic, so that alignment is possible. This is preferable because no processing is required and the viewing angle dependency is small.

[0171] In one embodiment of the present invention, a color filter is used in a liquid crystal display device. It is also possible to display an image of one color, or to sequentially light up multiple light sources that emit light of different hues. A color image may be displayed.

[0172] In addition, image signals from the signal line driver circuit 4003 and various control signals and The power supply potential is supplied to the scanning line driver circuit 4004 via wirings 4030 and 4031. Or it is provided to the pixel portion 4002.

[0173] In this embodiment, FFS (Fringe Field Switching) is used as a method for driving the liquid crystal. The example above shows the case where the switching mode is used, but the liquid crystal driving method can be the TN ( Twisted Nematic) mode, STN (Super Twisted Ne matic) mode, VA (Vertical Alignment) mode, MVA ( Multi-domain Vertical Alignment mode, IPS ( In-Plane Switching mode, OCB (Optically Com pensated birefringence mode, blue phase mode, TBA(T transverse bend alignment mode, VA-IPS mode, E CB(Electrically Controlled Birefringence) ) mode, FLC (Ferroelectric Liquid Crystal) mode AFLC (AntiFerroelectric Liquid Crystal) Mode, PDLC (Polymer Dispersed Liquid Crystal l) mode, PNLC (Polymer Network Liquid Crystal l) mode, guest host mode, ASV (Advanced Super View) It is also possible to apply a mode.

[0174] This embodiment can be implemented in appropriate combination with the configurations described in other embodiment modes. Cut.

[0175] (Embodiment 7) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, personal digital assistants, e-books, video cameras, digital cameras, etc. Talstill camera, goggle-type display (head-mounted display), navigation audio systems, audio playback devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, printer-combination machines, automated teller machines (AT M), vending machines, etc. Specific examples of these electronic devices are shown in Figure 15.

[0176] FIG. 15A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, The display unit 5003 or the display unit 5004, or other circuits A semiconductor device according to one embodiment of the present invention can be used for the circuit. The portable game machine has two display units 5003 and 5004. The number of display units that the game machine has is not limited to this.

[0177] FIG. 15B shows a display device, which includes a housing 5201, a display portion 5202, a support stand 5203, and the like. The semiconductor device according to one embodiment of the present invention is used in the display portion 5202 or other circuits. Display devices include those for personal computers, those for receiving TV broadcasts, This includes all display devices for displaying information, such as advertisements.

[0178] FIG. 15C shows a notebook personal computer, which includes a housing 5401 and a display unit 5402. The display unit 5402 includes a keyboard 5403, a pointing device 5404, and the like. A semiconductor device according to one embodiment of the present invention can be used in the above-mentioned circuits or other circuits.

[0179] FIG. 15D shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit, and a 5603, a second display unit 5604, a connection unit 5605, and operation keys 5606. The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other via a connection portion 5602. 5605, and the angle between the first housing 5601 and the second housing 5602 is The first display unit 5603 is connected to the The switching is performed according to the angle between the first housing 5601 and the second housing 5602 at the portion 5605. The first display unit 5603 or the second display unit 5604, or other The semiconductor device according to one embodiment of the present invention can be used for the circuit. At least one of the first display unit 5603 and the second display unit 5604 is provided with a function as a position input device. The position input function may be realized by using a semiconductor device. This can be added by providing a touch panel to the device, or as a position input device. The function of is to provide a photoelectric conversion element, also called a photosensor, in the pixel portion of a semiconductor device. can also be added.

[0180] FIG. 15E shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 58. 03, operation keys 5804, a lens 5805, a connection part 5806, etc. 4 and a lens 5805 are provided in a first housing 5801, and a display unit 5803 is provided in a second housing. The first housing 5801 and the second housing 5802 are connected to each other via a connection portion. The first housing 5801 and the second housing 5802 are connected by a joint 5806. The display unit 5803 is connected to a connection unit 5806. According to the angle between the first housing 5801 and the second housing 5802 in the portion 5806 The semiconductor according to one embodiment of the present invention may be used in the display portion 5803 or other circuits. The device can be used.

[0181] Here, one embodiment of the present invention includes the following semiconductor device in its category.

[0182] One aspect of the present invention is a transistor M2a, a transistor M2b, a switch S3a, a switch The semiconductor device includes a transistor S3b, a switch S4a, and a switch S4b. M2a has a first terminal connected to the wiring 13 and a second terminal connected to the wiring 12. The transistor M2b has a first terminal connected to the wiring 13 and a second terminal connected to the wiring 12. The second terminal of the switch S3a is connected to the gate of the transistor M2a. The first terminal of the switch S3b is connected to the first terminal of the switch S3a, and the second terminal of the switch S3b is connected to the The first terminal of the switch S4a is connected to the gate of the transistor M2b. The switch S4b is connected to the first terminal of the transistor M2a and the second terminal of the transistor M2b is connected to the gate of the transistor M2a. The first terminal is connected to the wiring 14, and the second terminal is connected to the gate of the transistor M2b (FIG. 16(A)).

[0183] In the semiconductor device, the switches S3a and S4b are on, and the switch S During a period Ta, the switches S3a and S4b are turned off. and a period Tb during which the switches S3b and S4a are on. In addition, the switches S3a, S3b, S4a, and S4b may be It may have periods when it is off.

[0184] In the above semiconductor device, the potential of the first terminal of the switch S3a is turned on during the period Ta. The potential of the wiring 14 is the value at which the transistor M2a turns on, and the potential of the wiring 14 is the value at which the transistor M2b turns on. The potential of the first terminal of the switch S3a is a value that is set by the transistor M2a being turned on during a period T3a. The potential of the wiring 14 is a value at which the transistor M2b is turned on, and the potential of the wiring 14 is a value at which the transistor M2b is turned off. In addition, the period Tb may include a period Tb when the potential of the first terminal of the switch S3b is The potential of the wiring 14 is the value at which the transistor M2a is turned on. and the potential of the first terminal of the switch S3b is such that the transistor M2b The potential of the wiring 14 is a value at which the transistor M2a is turned on, and the potential of the wiring 14 is a value at which the transistor M2a is turned off. 4b.

[0185] The semiconductor device may include a transistor M8 and a transistor M9. The transistor M8 has a first terminal connected to the wiring 18 and a second terminal connected to the switch S3a. The transistor M9 is connected to the first terminal of the first The first terminal is connected to the wiring 13, and the second terminal is connected to the first terminal of the switch S3a (FIG. 16(B)).

[0186] In addition, one embodiment of the present invention is a transistor M1, a transistor M2a, and a transistor M2 The semiconductor device has a first terminal connected to a wiring 11, The second terminal is connected to the wiring 12. The first terminal of the transistor M2a is connected to the wiring 13. The first terminal of the transistor M2b is connected to the line 12, and the second terminal of the transistor M2b is connected to the line 13. 13, and the second terminal is connected to the wiring 12 (see FIG. 16(C)). In the semiconductor device, the transistor M1 is on, and the transistors M2a and M2b are The period during which M2b is off (period T1a, period T2a, period T1b, or period T2b), Transistor M1 is off, and transistors M2a and M2b are on. A period (for example, period T3a or period T3b), transistor M1 and transistor M2b A period during which the transistor M1a is off and the transistor M2a is on (for example, period T4a) and a period during which the transistor M1b is on (for example, period T5a). During the period when the transistors M1 and M2a are off and the transistor M2b is on ( For example, period T4b).

[0187] This embodiment can be implemented in appropriate combination with the configurations described in other embodiment modes. Cut. [Explanation of symbols]

[0188] C1 Clock signal C Capacitive element CK1 signal CK2 signal G scan line G1 scan line Gy scan line M1 Transistor M2a Transistor M2b Transistor M3a Transistor M3b Transistor M4a Transistor M4b Transistor M5 Transistor M6 Transistor M7a Transistor M7b Transistor M8 Transistor M9 Transistor M10 Transistor M11 Transistor M12 Transistor M13 Transistor M14 Transistor M15 Transistor M16 Transistor M17 Transistor M18 Transistor N1 Node N2a Node N2b Node N3 Node S signal line Sx signal line S1 signal line S3a Switch S3b Switch S4a Switch S4b Switch SCK1 signal SCK2 signal Ta Period Tb Period T1a Period T1b period T2a period T2b period T3a period T3b period T4a Period T4b Period T13 Transistor T14 transistor T15 transistor V1 potential V2 potential Vg1 scan signal VN1 potential VN2a potential VN2b potential SP signal RE signal OUT signal SELa Signal SELb signal SSP signal SOUT signal 10 Circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16a Wiring 16b Wiring 17 Wiring 18 Wiring 20 Circuit 30 sequential circuits 60 Panels 61 Pixel section 62 pixels 63 Scanning line driving circuit 64 Signal line driver circuit 65 Liquid crystal element 66 Transistor 67 Capacitive element 201 Transistor 202 Transistor 203 Conductive Film 204 Conductive Film 205 Insulating film 206 Semiconductor Film 207 Conductive Film 208 Conductive Film 209 Insulating Film 210 Insulating film 211 Insulating film 212 Conductive Film 213 Semiconductor Film 214 Conductive Film 215 Conductive Film 217 Insulating Film 4001 Board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Encapsulating material 4006 Substrate 4010 Transistor 4018 FPC 4020 Insulating film 4021 Electrode 4022 Transistor 4023 Liquid crystal element 4024 Conductive film 4025 Insulating film 4026 Insulating film 4027 Electrode 4028 Liquid crystal layer 4030 Wiring 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Case 5202 Display section 5203 Support stand 5401 Case 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 Case 5602 Case 5603 Display section 5604 Display section 5605 Connection 5606 Operation key 5801 Case 5802 Case 5803 Display section 5804 Operation key 5805 Lens 5806 Connection

Claims

1. The semiconductor device includes first to seventh transistors and first to fourth switches, one of a source and a drain of the first transistor is always electrically connected to an output signal line; the other of the source and the drain of the first transistor is always electrically connected to a first clock signal line; one of the source and the drain of the second transistor is always electrically connected to the output signal line; the other of the source and the drain of the second transistor is always electrically connected to a first power supply line; one of a source and a drain of the third transistor is always electrically connected to the output signal line; the other of the source and the drain of the third transistor is always electrically connected to the first power supply line; one of a source and a drain of the fourth transistor is always electrically connected to a gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a first signal line; a gate of the fourth transistor is always electrically connected to a second clock signal line; one of a source and a drain of the fifth transistor is always electrically connected to a gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the first power supply line; the gate of the fifth transistor is always electrically connected to the second signal line; one of a source and a drain of the sixth transistor is always electrically connected to the first power supply line; the other of the source and the drain of the sixth transistor is always electrically connected to one of the source and the drain of the seventh transistor; a gate of the sixth transistor is always electrically connected to a gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to a second power supply line; a gate of the seventh transistor is always electrically connected to the second power supply line; a first terminal of the first switch always electrically connected to a gate of the second transistor; a second terminal of the first switch always electrically connected to one of a source and a drain of the seventh transistor; a first terminal of the second switch always electrically connected to a gate of the second transistor; a second terminal of the second switch always electrically connected to the second signal line; a first terminal of the third switch always electrically connected to a gate of the third transistor; a second terminal of the third switch always electrically connected to one of a source and a drain of the seventh transistor; a first terminal of the fourth switch always electrically connected to a gate of the third transistor; The second terminal of the fourth switch is always electrically connected to the second signal line.

2. The semiconductor device includes first to seventh transistors and first to fourth switches, one of a source and a drain of the first transistor is always electrically connected to an output signal line; the other of the source and the drain of the first transistor is always electrically connected to a first clock signal line; one of the source and the drain of the second transistor is always electrically connected to the output signal line; the other of the source and the drain of the second transistor is always electrically connected to a first power supply line; one of a source and a drain of the third transistor is always electrically connected to the output signal line; the other of the source and the drain of the third transistor is always electrically connected to the first power supply line; one of a source and a drain of the fourth transistor is always electrically connected to a gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a first signal line; a gate of the fourth transistor is always electrically connected to a second clock signal line; one of a source and a drain of the fifth transistor is always electrically connected to a gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the first power supply line; the gate of the fifth transistor is always electrically connected to the second signal line; one of a source and a drain of the sixth transistor is always electrically connected to the first power supply line; the other of the source and the drain of the sixth transistor is always electrically connected to one of the source and the drain of the seventh transistor; a gate of the sixth transistor is always electrically connected to a gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to a second power supply line; a gate of the seventh transistor is always electrically connected to the second power supply line; a first terminal of the first switch always electrically connected to a gate of the second transistor; a second terminal of the first switch always electrically connected to one of a source and a drain of the seventh transistor; a first terminal of the second switch always electrically connected to a gate of the second transistor; a second terminal of the second switch always electrically connected to the second signal line; a first terminal of the third switch always electrically connected to a gate of the third transistor; a second terminal of the third switch always electrically connected to one of a source and a drain of the seventh transistor; a first terminal of the fourth switch always electrically connected to a gate of the third transistor; a second terminal of the fourth switch is always electrically connected to the second signal line; At least one of the first to seventh transistors includes an oxide semiconductor in a channel formation region.

3. The semiconductor device includes first to seventh transistors and first to fourth switches, one of a source and a drain of the first transistor is always electrically connected to an output signal line; the other of the source and the drain of the first transistor is always electrically connected to a first clock signal line; one of the source and the drain of the second transistor is always electrically connected to the output signal line; the other of the source and the drain of the second transistor is always electrically connected to a first power supply line; one of a source and a drain of the third transistor is always electrically connected to the output signal line; the other of the source and the drain of the third transistor is always electrically connected to the first power supply line; one of a source and a drain of the fourth transistor is always electrically connected to a gate of the first transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a first signal line; a gate of the fourth transistor is always electrically connected to a second clock signal line; one of a source and a drain of the fifth transistor is always electrically connected to a gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the first power supply line; the gate of the fifth transistor is always electrically connected to the second signal line; one of a source and a drain of the sixth transistor is always electrically connected to the first power supply line; the other of the source and the drain of the sixth transistor is always electrically connected to one of the source and the drain of the seventh transistor; a gate of the sixth transistor is always electrically connected to a gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to a second power supply line; a gate of the seventh transistor is always electrically connected to the second power supply line; a first terminal of the first switch always electrically connected to a gate of the second transistor; a second terminal of the first switch always electrically connected to one of a source and a drain of the seventh transistor; a first terminal of the second switch always electrically connected to a gate of the second transistor; a second terminal of the second switch always electrically connected to the second signal line; a first terminal of the third switch always electrically connected to a gate of the third transistor; a second terminal of the third switch always electrically connected to one of a source and a drain of the seventh transistor; a first terminal of the fourth switch always electrically connected to a gate of the third transistor; a second terminal of the fourth switch is always electrically connected to the second signal line; at least one of the first to seventh transistors includes an oxide semiconductor in a channel formation region; The semiconductor device, wherein the oxide semiconductor is indium oxide.

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