Photodetection device, and photodetection system

Abstract

To provide a photodetection device that can improve the time resolution of photodetection.SOLUTION: A photodetection device comprises a trench separation part that is provided on a substrate and is arranged between a plurality of photoelectric conversion elements. The plurality of photoelectric conversion elements each include an avalanche diode. The avalanche diode includes: a first semiconductor region of a first conductivity type arranged at a first depth from a first surface of the substrate; a second semiconductor region of a second conductivity type arranged at a second depth; and a third semiconductor region arranged at a third depth and having an impurity density lower than the impurity density of the first semiconductor region and the second semiconductor region. The trench separation part includes: an electric conductor; and an insulator arranged between the electric conductor and the avalanche diode. A second conductivity type layer in which electric charges of the second conductivity type are stored is formed on a side wall of the trench separation part, and the second conductivity type layer and the second semiconductor region are in contact with each other.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a photodetection device and a photodetection system that perform photoelectric conversion. [Background technology]

[0002] There is known a photodetector device including a pixel array in which multiple SPAD (Single Photon Avalanche Diode) pixels are arranged in a plane. In a SPAD pixel, avalanche multiplication of photocharges caused by a single photon occurs in a PN junction region in a semiconductor region.

[0003] Patent Document 1 discloses that in a semiconductor substrate having an avalanche diode, an inter-pixel separator that separates adjacent pixels is composed of a metal film and an insulating film. Patent Document 1 also discloses a configuration in which a P-type semiconductor region is provided that is composed of a pinning layer that is continuously formed so as to contact the insulating film and form a part of the incident surface of the substrate, and a hole accumulation layer that is formed inside the pinning layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-88488 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the photodetector described in Patent Document 1, there is a possibility that the time it takes for the photocharges generated in the semiconductor region to reach the PN junction region where avalanche multiplication occurs varies. One of the reasons for this is assumed to be that it is difficult to create a potential gradient for the signal charge in the P-type semiconductor region, which causes variation in the time it takes for the photocharges in the P-type semiconductor region to leave the P-type semiconductor region. This causes variation in the time it takes to complete detection of the photocharges, lowering the time resolution of photodetection. [Means for solving the problem]

[0006] a pixel array section in which a plurality of photoelectric conversion elements are arranged in a two-dimensional array in a planar view on a substrate; and a trench isolation section provided on the substrate and arranged between the plurality of photoelectric conversion elements, each of the plurality of photoelectric conversion elements including an avalanche diode, the avalanche diode being arranged at a first depth from a first surface of the substrate and including a first semiconductor region of a first conductivity type having a charge of the same conductivity type as a signal charge as a majority carrier, and a second semiconductor region having a distance from the first surface of the substrate longer than the first depth and a distance to a second surface opposite to the first surface shorter than the distance to the first surface. the trench isolation portion includes a conductor and an insulator disposed between the conductor and the avalanche diode, and a second semiconductor region of a second conductivity type arranged at a depth, and a third semiconductor region arranged at a third depth deeper than the first depth and shallower than the second depth, the third semiconductor region having an impurity concentration lower than the impurity concentrations of the first semiconductor region and the second semiconductor region, the trench isolation portion includes a conductor and an insulator disposed between the conductor and the avalanche diode, and a second conductivity type layer in which charges of the second conductivity type possessed by the third semiconductor region are accumulated is formed on a sidewall of the trench isolation portion, and the second conductivity type layer and the second semiconductor region are configured to be in contact with each other.

[0007] a pixel array section in which a plurality of photoelectric conversion elements are arranged in a two-dimensional array in a planar view on a substrate; and a trench isolation section provided on the substrate and arranged between the plurality of photoelectric conversion elements, each of the plurality of photoelectric conversion elements including an avalanche diode, the avalanche diode including: a first semiconductor region of a first conductivity type arranged at a first depth from a first surface of the substrate, the first semiconductor region having a majority carrier of charge of the same conductivity type as a signal charge; a second semiconductor region of a second conductivity type arranged at a second depth that is longer from the first surface of the substrate than the first depth and has a distance to a second surface opposite to the first surface shorter than the distance to the first surface; and a third semiconductor region of the first conductivity type arranged at a third depth that is deeper than the first depth and shallower than the second depth, the third semiconductor region having an impurity concentration lower than the impurity concentration of the first semiconductor region, the trench isolation section including a conductor and an insulator arranged between the conductor and the avalanche diode, and the trench isolation section is in contact with the third semiconductor region.

[0008] The pixel array section has a plurality of photoelectric conversion elements arranged in a two-dimensional array in a planar view on a substrate, and a trench isolation section provided on the substrate and arranged between the plurality of photoelectric conversion elements, each of the plurality of photoelectric conversion elements including an avalanche diode, the avalanche diode including a first semiconductor region of a first conductivity type arranged at a first depth from a first surface of the substrate and having a charge of the same conductivity type as a signal charge as a majority carrier, and a second semiconductor region of a second conductivity type arranged at a second depth that is longer from the first surface of the substrate than the first depth and has a distance to a second surface opposite the first surface shorter than the distance to the first surface, and the trench isolation section is provided with a dielectric layer made of at least one of a hafnium oxide layer, an aluminum oxide layer, a zirconium oxide layer, a titanium oxide layer, a tantalum oxide layer, and a ruthenium oxide layer.

[0009] The pixel array section has a plurality of photoelectric conversion elements arranged in a two-dimensional array in a planar view on a substrate, and a trench isolation section provided on the substrate and arranged between the plurality of photoelectric conversion elements, each of the plurality of photoelectric conversion elements including an avalanche diode, the avalanche diode including a first semiconductor region of a first conductivity type arranged at a first depth from a first surface of the substrate and having a charge of the same conductivity type as a signal charge as a majority carrier, and a second semiconductor region of a second conductivity type arranged at a second depth that is longer from the first surface of the substrate than the first depth and has a distance to a second surface opposite the first surface that is shorter than the distance to the first surface, and a dielectric having a negative fixed charge is arranged in the trench isolation section.

[0010] The semiconductor device comprises a pixel array section in which a plurality of photoelectric conversion elements are arranged in a two-dimensional array in a planar view on a substrate, and a trench isolation section provided on the substrate and arranged between the plurality of photoelectric conversion elements, each of the plurality of photoelectric conversion elements including an avalanche diode, a first dielectric layer consisting of at least one of a hafnium oxide layer, an aluminum oxide layer, a zirconium oxide layer, a titanium oxide layer, a tantalum oxide layer, and a ruthenium oxide layer is arranged in the trench isolation section, the substrate has a first surface and a second surface opposite to the first surface, and a second dielectric layer consisting of at least one of a hafnium oxide layer, an aluminum oxide layer, a zirconium oxide layer, a titanium oxide layer, a tantalum oxide layer, and a ruthenium oxide layer is arranged on the second surface of the substrate.

[0011] The device comprises a pixel array section in which a plurality of photoelectric conversion elements are arranged in a two-dimensional array in a planar view on a substrate, and a trench isolation section provided on the substrate and arranged between the plurality of photoelectric conversion elements, each of the plurality of photoelectric conversion elements includes an avalanche diode, a first dielectric having a negative fixed charge is arranged in the trench isolation section, the substrate has a first surface and a second surface opposite to the first surface, and a second dielectric having a negative fixed charge is arranged on the second surface of the substrate. Effect of the Invention

[0012] According to the present invention, it is possible to provide a light detection device capable of improving the time resolution of light detection. [Brief description of the drawings]

[0013] [Figure 1] Photodetector block diagram [Diagram 2] Blocks of pixels [Diagram 3] Schematic plan view of a SPAD pixel according to the first embodiment. [Figure 4] Schematic cross-sectional view of a SPAD pixel according to the first embodiment. [Diagram 5] Potential diagram of the SPAD of the first embodiment [Figure 6] FIG. 1 is a diagram for explaining a comparative example. [Figure 7] Schematic plan view of a SPAD pixel according to the second embodiment [Figure 8] Schematic cross-sectional view of a SPAD pixel according to the second embodiment. [Figure 9] Schematic plan view of a SPAD pixel according to the third embodiment. [Figure 10] Schematic cross-sectional view of a SPAD pixel according to the third embodiment. [Figure 11] Schematic plan view of a SPAD pixel according to the fourth embodiment. [Figure 12] Schematic cross-sectional view of a SPAD pixel according to embodiment 4. [Figure 13] Schematic plan view of a SPAD pixel according to the fifth embodiment. [Figure 14] Schematic cross-sectional view of a SPAD pixel according to the fifth embodiment. [Figure 15] 13 is a schematic cross-sectional view of a SPAD pixel according to a modification of the fifth embodiment. [Figure 16] Schematic cross-sectional view of a SPAD pixel according to the sixth embodiment. [Figure 17] 13 is a schematic cross-sectional view of a SPAD pixel according to a modification of the sixth embodiment. [Figure 18] Schematic cross-sectional view of a SPAD pixel according to embodiment 7. [Figure 19] Potential diagram of the SPAD pixel of embodiment 7 [Figure 20] Block diagram of a light detection system according to an eighth embodiment [Figure 21]Block diagram of a light detection system according to a ninth embodiment [Figure 22] Block diagram of a light detection system according to a tenth embodiment. [Figure 23] Block diagram of an optical detection system according to an eleventh embodiment [Figure 24] Flowchart of the optical detection system of embodiment 11 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The following embodiments are intended to embody the technical ideas of the present invention, and are not intended to limit the present invention. The sizes and positional relationships of the components shown in the drawings may be exaggerated to clarify the description. In the following description, the same components may be designated by the same reference numerals, and the description may be omitted.

[0015] A configuration common to the photodetector in each embodiment will be described with reference to Figures 1 and 2. The photodetector has a SPAD pixel including an avalanche diode. The conductivity type of the charge used as the signal charge among the charge pairs generated in the avalanche diode is called the first conductivity type. The conductivity type opposite to the first conductivity type is called the second conductivity type. In the following, an example will be described in which the signal charge is an electron, the first conductivity type is an N type, and the second conductivity type is a P type, but the signal charge may be a hole, the first conductivity type is a P type, and the second conductivity type is an N type.

[0016] 1 is a block diagram of a photodetector 1000. The photodetector 1000 has a pixel array section 111, a horizontal scanning circuit section 105, signal lines 104, and a vertical scanning circuit section 103.

[0017] In the pixel array section 111, a plurality of avalanche diodes constituting SPAD pixels 110 (hereinafter referred to as pixels) are arranged in a two-dimensional array in a planar view. Each pixel 110 is composed of a photoelectric conversion section 101 and a pixel signal processing section 102. Note that it is sufficient for the pixel 110 to include at least the photoelectric conversion section 101. Specifically, the pixel 110 is one of the configurations including the photoelectric conversion section 101 and arranged repeatedly. The photoelectric conversion section 101 converts light into an electrical signal. The pixel signal processing section 102 outputs the converted electrical signal to a signal line 104.

[0018] A vertical scanning circuit section 103 and a horizontal scanning circuit section 105 supply control pulses to each pixel 110. The vertical scanning circuit section 103 uses logic circuits such as a shift register and an address decoder.

[0019] The signal line 104 supplies a digital signal output from the pixel 110 selected by the vertical scanning circuit unit 103 to a circuit subsequent to the pixel 110 as a potential signal.

[0020] 1, the pixels 110 in the pixel array section 111 may be arranged one-dimensionally. Also, the vertical scanning circuit section 103 and the horizontal scanning circuit section 105 may divide the pixel array section 111 into blocks of a plurality of pixel columns and arrange the pixels for each block. Also, the vertical scanning circuit section 103 and the horizontal scanning circuit section 105 may be arranged for each pixel column.

[0021] The function of the pixel signal processing unit 102 does not necessarily need to be provided for each pixel 110. For example, one pixel signal processing unit 102 may be shared by a plurality of pixels 110, and signal processing may be performed sequentially. In addition, at least a part of the pixel signal processing unit 102 may be provided on a semiconductor substrate (second substrate) different from the photoelectric conversion unit 101 in order to increase the aperture ratio of the photoelectric conversion unit 101. In this case, the photoelectric conversion unit 101 and the pixel signal processing unit 102 are electrically connected via a connection wiring provided for each pixel. It is preferable to arrange the avalanche diode of the photoelectric conversion unit 101 on the first substrate, and arrange the other components on the second substrate. In each of the following embodiments, an example will be described in which the avalanche diode is provided on the first substrate, circuits such as a waveform shaping unit are provided on the second substrate, and the first substrate and the second substrate are laminated. The vertical scanning circuit unit 103, the horizontal scanning circuit unit 105, and the signal line 104 may be provided on the second substrate.

[0022] 2 is a block diagram of a pixel 110 including an equivalent circuit in this embodiment. In FIG. 2, one pixel 110 is composed of a photoelectric conversion unit 101 and a pixel signal processing unit .

[0023] The photoelectric conversion section 101 includes one or more arrayed avalanche diodes 201 , a quenching element 202 , and a waveform shaping section 203 .

[0024] The avalanche diode 201 generates pairs of charges according to incident light through photoelectric conversion. The avalanche diode 201 is a photoelectric conversion element. A potential based on a potential VH higher than the potential VL supplied to the anode is supplied to the cathode of the avalanche diode 201. A potential is supplied to the anode and cathode of the avalanche diode 201 so that a reverse bias is applied so that photons incident on the avalanche diode 201 are avalanche multiplied. By performing photoelectric conversion in a state where such a reverse bias potential is supplied, the charges generated by the incident light undergo avalanche multiplication, generating an avalanche current.

[0025] When a reverse bias potential is applied, and the potential difference between the anode and cathode is greater than the breakdown voltage, the avalanche diode operates in the Geiger mode. The avalanche diode that uses the Geiger mode operation to quickly detect weak signals at the single photon level is called a SPAD (Single Photon Avalanche Diode).

[0026] The quench element 202 is connected to a power supply that supplies a high potential VH and the avalanche diode 201. The quench element 202 is composed of a resistive element such as a P-type MOS transistor or a poly resistor. The quench element 202 may also be composed of a plurality of MOS transistors connected in series. When the photocurrent is multiplied by avalanche multiplication in the avalanche diode 201, a current obtained by the multiplied charge flows to a connection node between the avalanche diode 201 and the quench element 202. Due to a voltage drop caused by this current, the potential of the cathode of the avalanche diode 201 drops, and the avalanche diode 201 no longer forms an avalanche. This stops the avalanche multiplication of the avalanche diode 201. Thereafter, the potential VH of the power supply is supplied to the cathode of the avalanche diode 201 via the quench element 202, and the potential supplied to the cathode of the avalanche diode 201 returns to the potential VH. That is, the operating region of the avalanche diode 201 returns to Geiger mode operation. In this way, the quench element 202 functions as a load circuit (quench circuit) when charge is multiplied by avalanche multiplication, and has a function of suppressing avalanche multiplication (quench operation). In addition, after suppressing avalanche multiplication, the quench element has a function of making the operating region of the avalanche diode return to Geiger mode.

[0027] The waveform shaping unit 203 is connected to a connection node between the node of the avalanche diode 201 and the node of the quench element 202. It shapes the potential change of the cathode of the avalanche diode 201 obtained when a photon is detected, and outputs a rectangular pulse signal. For example, an inverter circuit is used as the waveform shaping unit 203. Although an example in which one inverter is used as the waveform shaping unit 203 has been shown, a circuit in which multiple inverters are connected in series may also be used. Not limited to an inverter, other circuits having a waveform shaping effect may also be used.

[0028] The pixel signal processing unit 102 includes a processing circuit 204 .

[0029] The processing circuit 204 is connected to the waveform shaping unit 203. The pulse signal output from the waveform shaping unit 203 is subjected to signal processing by the processing circuit 204. When the processing circuit 204 is, for example, an N-bit counter (N: a positive integer), it is possible to count up to approximately 2 to the power of N pulse signals generated by a single photon. The counted signal is held as a detected signal. Furthermore, when a reset control pulse is supplied via a control line, the signal held in the processing circuit 204 is reset.

[0030] The output of the processing circuit 204 is connected to the signal line 104. Here, a selection circuit may be provided in the processing circuit 204 so that the pixel signals can be read out at a desired timing, or the signal may be output constantly by being directly connected to the signal line 104. A control pulse Ctrl is supplied to the processing circuit 204 from the vertical scanning circuit unit 103 in FIG. 1 via a control line, and the control pulse Ctrl provides a clock for signal processing of the output of the processing circuit 204 and switches whether or not the output of the processing circuit 204 is output to the signal line 104.

[0031] A switch such as a transistor may be disposed between the quench element 202 and the avalanche diode 201 to switch between a mode in which the avalanche diode 201 can perform avalanche multiplication and a mode in which the avalanche diode 201 cannot perform avalanche multiplication. Similarly, the supply of the high potential VH or the low potential VL to the avalanche diode 201 may be electrically switched using a switch such as a transistor. Also, a switch such as a transistor may be disposed between the photoelectric conversion unit 101 and the pixel signal processing unit 102 to control the input of a signal from the photoelectric conversion unit 101 to the processing circuit 204.

[0032] In a pixel array section 111 in which a plurality of pixels 110 are arranged in a matrix, the output of the processing circuit 204 may be reset row by row in sequence, and a signal may be acquired by a rolling shutter operation in which the output signal of the processing circuit 204 is output row by row in sequence.

[0033] Alternatively, the signal may be acquired by a global electronic shutter operation in which the counts of the processing circuit 204 of all pixel rows are reset simultaneously and the signals held in the processing circuit 204 are output row by row in sequence. When the global electronic shutter operation is performed, it is advisable to provide a means for switching between a case where the counting of the processing circuit 204 is performed and a case where it is not performed. The switching means is, for example, the switch described above.

[0034] 2 may be configured to acquire the pulse detection timing. In this case, a time to digital converter (hereinafter, a TDC) and a memory are used in place of the counter circuit in the processing circuit 204.

[0035] At this time, the generation timing of the pulse signal output from the waveform shaping unit 203 is converted into a digital signal by the TDC. To measure the timing of the pulse signal, the TDC is supplied with a control pulse Ref (reference signal) from the vertical scanning circuit unit 103 in Fig. 1 via a drive line. The TDC acquires, as a digital signal, a signal obtained when the input timing of the signal output from each pixel via the waveform shaping unit 203 is converted into a relative time based on the control pulse pREF.

[0036] The photodetector of each embodiment will be described below.

[0037] <Embodiment 1> Fig. 3 is a schematic plan view of the SPAD pixel in embodiment 1, and Fig. 4 is a schematic cross-sectional view taken along line XX' of the SPAD pixel in embodiment 1. The avalanche diode in this embodiment is disposed on a semiconductor substrate 15 (first substrate).

[0038] The semiconductor substrate 15 has a first surface 15a and a second surface 15b facing the first surface 15a. For example, the first surface 15a is the surface of the semiconductor substrate 15 on which a wiring layer is formed. In this embodiment, light is incident from the second surface 15b. FIG. 3 is a plan view of the first surface 15a of the semiconductor substrate 15, and also shows contact plugs connected to each semiconductor region. In this specification, "plan view" refers to a view from a direction perpendicular to a plane parallel to the first surface 15a of the substrate. Also, a cross section refers to a surface in a direction perpendicular to the plane. Also, in this specification, "depth" refers to a direction from the first surface 15a toward the second surface 15b.

[0039] The thickness of the semiconductor substrate 15 can be appropriately set depending on the wavelength at which light is detected. The color of light detected by the light detection device can be set according to the purpose, such as blue, green, green, infrared light, etc. The peak wavelength of the light detected by the light detection device can be set, for example, within the range of 350 nm or more and 1000 nm or less.

[0040] 3 shows four photoelectric conversion elements that are part of four SPAD pixels, and a trench isolation 16 between the photoelectric conversion elements. In this specification, the area partitioned by the trench isolation 16 described below corresponds to the photoelectric conversion element of the SPAD pixel. One photoelectric conversion element is composed of an avalanche diode including at least one avalanche multiplication region. From another perspective, the photoelectric conversion element refers to one of the components repeatedly arranged in the pixel array section.

[0041] 3 shows a first conductive type semiconductor region 71 (first semiconductor region), a second conductive type semiconductor region 72, and a semiconductor region 75 (third semiconductor region) disposed between the semiconductor region 71 and the semiconductor region 72, which are included in the avalanche diode of this embodiment. Contact plugs connected to each semiconductor region are also shown. Although it cannot be seen from the first surface 15a, for ease of explanation, FIG. 3 shows a region in which a second conductive type semiconductor region 74 (fourth semiconductor region) is disposed.

[0042] The semiconductor region 71 constitutes the cathode of the avalanche diode. A plurality of contact plugs 21 are connected to the semiconductor region 71. The contact plugs 21 supply a potential to the cathode of the avalanche diode through a wiring layer. The plurality of contact plugs 21 are provided in the center of the region surrounded by a trench isolation portion described later and around the center in a plan view. The contact plugs 21 provided around the center are provided at positions that do not overlap with the line connecting the diagonally arranged contact plugs 23. By connecting the plurality of contact plugs 21 to the semiconductor region 71, it is possible to suppress a decrease in the read speed of signals that contribute to the avalanche multiplication position of the semiconductor region 71. In addition, by arranging the contact plugs 21 at positions away from the contact plugs 23, it becomes easy to layout the distance between the wirings connected to the anode and cathode to which a high voltage is applied large, and the reliability of the element is improved.

[0043] The semiconductor region 72 constitutes the anode of the avalanche diode. The contact plug 23 is connected to the semiconductor region 72. The semiconductor region 72 is disposed at a corner of the photoelectric conversion element.

[0044] Between the photoelectric conversion elements, trench isolation parts 16 are formed. The trench isolation parts 16 are arranged so as to surround the photoelectric conversion elements in a plan view. In FIG. 3, the shape of the photoelectric conversion elements is a rectangle, but is not limited thereto. The trench isolation parts 16 according to this embodiment include a conductor 16a and an insulator 16b.

[0045] The conductor 16a is made of, for example, a metal that reflects or absorbs light. Examples of metals that reflect light include tungsten, aluminum, and copper. Reflecting light refers to, for example, reflecting 30% or more of light of a specific wavelength. The specific wavelength is the wavelength of light that the photodetector mainly detects.

[0046] The insulator 16b may be, for example, silicon oxide. The insulator 16b is disposed between the conductor 16a and the avalanche diode. In other words, the insulator 16b is disposed between the conductor 16a and the semiconductor region of the semiconductor substrate.

[0047] Fig. 4 shows a cross-sectional view taken along line X-X' of Fig. 3. In Fig. 4, the photoelectric conversion element includes a first conductivity type semiconductor region 71, a second conductivity type semiconductor region 72, a second conductivity type semiconductor region 74, a semiconductor region 75, and a second conductivity type semiconductor region 76 (second semiconductor region). A strong electric field is applied to the PN junction region between the semiconductor region 71 and the semiconductor region 74, and an avalanche multiplication region is formed by the semiconductor region 71 and the semiconductor region 74. Each semiconductor region is a region to which impurities have been added by ion implantation, or a region to which impurities have been added during the preparation and epitaxial growth of the semiconductor substrate.

[0048] Semiconductor region 71 and semiconductor region 72 are disposed at a first depth D1, which is a first distance from first surface 15a of substrate 15. As described above, semiconductor region 75 is disposed between semiconductor region 71 and semiconductor region 72. In this specification, disposing an m-th semiconductor region at an n-th depth means, for example, that a region (peak) with the highest implanted impurity concentration is disposed at the n-th depth. Note that the peak does not necessarily have to be disposed at the n-th depth, and design errors and manufacturing errors are also allowed.

[0049] The semiconductor region 75 is a semiconductor region of a first conductivity type having a lower impurity concentration than the semiconductor region 71. By disposing the semiconductor region 75 between the semiconductor region 71 and the semiconductor region 72, charges near the semiconductor region 75 can be easily moved to a position closer to the contact plug 21.

[0050] The impurity concentration of the semiconductor region 71 is set to be lower than the impurity concentration of the semiconductor region 71. For example, the impurity concentration of the semiconductor region 71 is 6.0×10 18 [atms / cm 3 ] or more, the impurity concentration of the semiconductor region 75 is 1.0×10 18 [atms / cm 3 At this time, the impurity concentration of the semiconductor region 72 is set to 6.0×10 18 [atms / cm 3 The impurity concentration of the semiconductor region 74 is 1.0×10 18 [atms / cm 3 ] below.

[0051] A semiconductor region 74 is formed at a fourth depth D4 deeper than the first depth D1. The semiconductor region 74 is a semiconductor region of a second conductivity type having a lower impurity concentration than the semiconductor region 72. As described above, the semiconductor region 72 forms an avalanche multiplication region between itself and the semiconductor region 71.

[0052] At a third depth D3 deeper than the first depth D1, a semiconductor region 75 is disposed. In FIG. 4, the semiconductor region 75 is a semiconductor region of a first conductivity type having a lower impurity concentration than the semiconductor region 71.

[0053] A second conductive type semiconductor region 76 is disposed at a second depth D2 that is deeper from the first surface 15a than the first depth. The second depth D2 has a distance (second distance) from the first surface 15a that is longer than the first distance, and a distance (third distance) to the second surface 15b that is shorter than the second distance. The second depth D2 is deeper than the fourth depth D4 and the third depth D3. In FIG. 4, the second depth is located near the second surface 15b. The semiconductor region 76 and the semiconductor region 72 are electrically connected via a second conductive type layer 80, which will be described later. This makes it possible to create a potential that makes it easy to move the signal charge in the semiconductor region 75 to the avalanche multiplication region formed by the semiconductor region 71 and the semiconductor region 74. Therefore, the signal charge generated near the second conductive type layer 80 can also be moved to the avalanche multiplication region, and the decrease in the aperture ratio can be suppressed.

[0054] Between the pixels, trench isolation portions 16 are arranged. The trench isolation portions 16 according to this embodiment are formed so as to penetrate from the second surface 15b to the first surface 15a of the semiconductor substrate 15. As described above, the trench isolation portions 16 have a conductor 16a and an insulator 16b.

[0055] The conductor 16a is connected to the wiring pattern 31a included in the first wiring layer 31 via the contact plug 25. A predetermined potential Vt1 is supplied to the contact plug 25 via the wiring pattern 31a. The predetermined potential Vt1 is a potential at which a second conductive type layer 80 in which a second conductive type charge is accumulated is formed near a region where the semiconductor of the substrate 15 and the insulator 16a are in contact. In FIG. 4, the semiconductor region 75 is a semiconductor region of the first conductive type, so the second conductive type layer 17 is an inversion layer. When the first conductive type is N type, the potential Vt1 supplied to the contact plug 25 is a potential lower than 0V, and when the first conductive type is P type, the potential Vt1 is a potential higher than 0V.

[0056] A contact plug 21 is connected to the semiconductor region 71. A predetermined potential Vt2 is supplied to the contact plug 21 via the wiring pattern 31b. A contact plug 23 is connected to the semiconductor region 72. A predetermined potential Vt3 is supplied to the contact plug 23 via the wiring pattern 31c. The potentials Vt2 and Vt3 are such that a reverse bias voltage is supplied to the semiconductor region 71 and the semiconductor regions 72 and 74.

[0057] The wiring pattern 31b to which the contact plug 21 is connected preferably has a width greater than the width of the semiconductor region 71. From another perspective, the wiring pattern 31b is preferably disposed so as to cover the semiconductor region 71 in a plan view, and more preferably covers the entire region of the semiconductor region 71. This allows light that passes through the semiconductor substrate 15 and heads toward the wiring layer 30 to be efficiently returned to the semiconductor substrate 15.

[0058] When the first conductivity type is N-type, the relationship between the potentials Vt1, Vt2, and Vt3 is potential Vt1≦potential Vt3<potential Vt2. When the first conductivity type is P-type, the inequality is reversed. Each potential is set relative to a common reference potential (e.g., 0V). The potential Vt1 is a potential at which the second conductivity type layer 80 is formed on the sidewall of the trench isolation portion 16 and avalanche multiplication does not occur between the second conductivity type layer 80 and the semiconductor region 75. The potential Vt1 can be set, for example, within a range of −50V to −5V.

[0059] It is not necessary to constantly supply the predetermined potential Vt1 to the contact plug 25, but it is sufficient that the predetermined potential Vt1 is supplied for at least a part of the period during which the photoelectric conversion element receives light. It is preferable that the predetermined potential Vt1 is supplied for the entire period during which the photoelectric conversion element receives light.

[0060] In this embodiment, the second conductive type layer 80 is not formed on the sidewall of the trench isolation 16 during a period when the contact plug 25 is not supplied with the predetermined potential Vt1. That is, the trench isolation 16 and the first conductive type semiconductor region 75 are in contact with each other during a period when the contact plug 25 is not supplied with the predetermined potential Vt1. Then, when the contact plug 25 is supplied with the predetermined potential Vt1, the second conductive type layer 80 is formed between the insulator 16a and the semiconductor region 75. The second conductive type layer 80 is formed on the sidewall of the trench isolation 16 in a region that is in contact with the first conductive type semiconductor region (a region that is not in contact with the second conductive type semiconductor region).

[0061] By forming the second conductive type layer 80, the semiconductor region 72 and the semiconductor region 76 are connected by the second conductive type layer 80. Therefore, the semiconductor region 76 is supplied with a potential supplied from the contact plug 23 via the second conductive type layer 80.

[0062] 5(A) and 5(B) show potential diagrams for the first-conductivity-type charge when the second-conductivity-type layer is formed and when it is not formed. When the second-conductivity-type layer is formed, the potential Vt1 is supplied to the contact plug 25. When the second-conductivity-type layer is not formed, the potential Vt1 is not supplied to the contact plug 25. FIG. 5(A) is a potential diagram of Y-Y' in FIG. 4, and FIG. 5(B) is a potential diagram of Z-Z' in FIG. 4. The potential when the second-conductivity-type layer 80 is formed is shown by a solid line, and the potential when the second-conductivity-type layer 80 is not formed is shown by a dashed line. As described above, when the second-conductivity-type layer 80 is formed, the potential Vt2 supplied from the contact plug 23 is supplied to the semiconductor region 76. Therefore, as shown in FIG. 5(A), the potential of the second-conductivity-type layer 80 can be increased and the potential of the semiconductor region 75 can be decreased. 5B, the potential can be lowered from the second surface 15b toward the first surface 15a. That is, the potential can be lowered toward the avalanche multiplication region. This makes it easier to move signal charges to the avalanche multiplication region, and improves the time resolution of light detection.

[0063] Here, the effect of supplying the potential of the contact plug 23 to the semiconductor region 76 via the second conductivity type layer 80 will be described in comparison with a comparative embodiment shown in Fig. 6. As shown in Fig. 6(A), in the comparative embodiment, a semiconductor region 54 of the second conductivity type is formed on the side wall of the trench isolation portion 16. The semiconductor region 54 is formed by injecting an impurity from the first surface 15a or the second surface 15b of the semiconductor substrate using a photomask or the like.

[0064] FIG. 6B shows the potential for the first conductive charge of Y-Y' in FIG. 6A. As shown in FIG. 6B, the region in which the second conductive semiconductor region 54 is arranged has a flatter potential for the signal charge than that of this embodiment. As shown in FIG. 6A, the charge that is avalanche multiplied and read out as a signal is divided into a drift component and a diffusion component. The drift component is a signal charge that does not stay in the semiconductor region 54 or the semiconductor region 6 but moves toward the avalanche multiplication region. The diffusion component is a signal charge that stays in the semiconductor region 54 or the semiconductor region 6 for a certain time and then moves toward the avalanche multiplication region slower than the drift component. As shown in FIG. 6C, the probability of the drift component is generally high, but if there is a diffusion component, the signal charge arrives late at the avalanche multiplication region, forming a diffusion tail. This deteriorates the time resolution (timing jitter).

[0065] Therefore, in this embodiment, a second conductivity type layer 80 is formed on the sidewall of the trench isolation 16, and a potential is supplied to the semiconductor region 76 via the second conductivity type layer 80. This makes it possible to eliminate the flat portion of the potential at Y-Y'. The concentration of the second conductivity type impurity at the portion on the sidewall of the trench isolation 16 with the lowest concentration is 5×10 17 cm -3 The following is the result.

[0066] In the comparative embodiment, the semiconductor region 54 is formed by implantation. In general, when an impurity is implanted at the same impurity concentration, the impurity spreads more when implanted into a deep portion than when implanted into a shallow portion. In other words, the width of the second conductivity type semiconductor region is more likely to be wider in a deep portion than in a shallow portion. Therefore, the width of the semiconductor region 54 is more likely to be wider in the deeper portion, and a region with a flat potential is more likely to be formed.

[0067] On the other hand, according to the present embodiment, since the second conductive type layer 80 is formed by supplying the potential Vt1, the region in which the second conductive type charges become majority carriers can be narrowed compared to the case of forming the semiconductor region 54. Therefore, it is possible to reduce the diffusion component.

[0068] As described above, the wide region of the semiconductor region 54 is formed regardless of the peak wavelength of the light to be photoelectrically converted, but this is more noticeable in the case of infrared light. A photodetector that photoelectrically converts infrared light needs to have a thick semiconductor substrate 15. For example, the thickness of the semiconductor substrate 15 may be set to 3.5 μm or more and 15 μm or less. Therefore, the distance from the surface where the impurities are injected to the deep part of the semiconductor substrate tends to be longer than that in the case of visible light, and the width of the semiconductor region 54 tends to be wider. Therefore, in a photodetector that photoelectrically converts infrared light, the improvement in time resolution of this embodiment is more noticeable. Note that even when the light to be photoelectrically converted is visible light, the effect of improving time resolution can be obtained because a wide region of the semiconductor region 54 is formed.

[0069] The aperture ratio of the photoelectric conversion element is preferably, for example, 50% or more and 100% or less. This allows the photoelectrically converted charges to be read out efficiently. The aperture ratio is generally determined by the area ratio between the photoelectric conversion element and the avalanche multiplication region. The avalanche multiplication region is a strong electric field region of the PN junction. In the case of a structure capable of collecting charges in the lateral direction as in the second embodiment, the aperture ratio is determined by the area ratio between the photoelectric conversion element and the photoelectric conversion region.

[0070] The width of the second conductive type layer 80 is preferably the same from the first surface 15a to the second surface 15b. The width of the second conductive type layer 80 is, for example, 1 nm or more and 100 nm or less. Note that the width of the second conductive type layer 80 is not limited to this because it changes depending on the supplied potential Vt1.

[0071] The signal read out from the photoelectric conversion element is sent to a waveform shaping section 203 disposed on the semiconductor substrate 40 .

[0072] The semiconductor substrate 15 and the semiconductor substrate 40 are electrically and mechanically joined via the wiring patterns 33a and 34a of the wiring layer 30. The wiring patterns 33a and 34a are made of, for example, Cu.

[0073] It is preferable that the conductor 16a is formed from the same depth as the first surface 15a to the same depth as the second surface 15b, but is not limited thereto. The conductor 16a may be formed from the first surface 15a to a depth partway through the semiconductor substrate 15, and may not be formed from the depth partway through to the depth of the second surface 15b. For example, the conductor 16a may not be formed at the same depth as the semiconductor region 76.

[0074] In the above description, the semiconductor region 75 is a semiconductor region of the first conductivity type, but the semiconductor region 75 may be a semiconductor region of the second conductivity type. When the semiconductor region 75 is a semiconductor region of the second conductivity type, the second conductivity type layer 80 is an accumulation layer. The potential Vt2 supplied to the contact plug 21 is a potential lower than 0V. When the first conductivity type is N type, the relationship between the potentials is potential Vt1≦potential Vt3<potential Vt2. When the second conductivity type layer 80 is an accumulation layer, the potential Vt2 is preferably −50V or more and −5V or less.

[0075] In addition, in this embodiment, the avalanche multiplication region is formed by the semiconductor region 71 and the semiconductor region 74, but this is not limiting. For example, even if the semiconductor region 74 is not provided and the avalanche multiplication region is formed by the semiconductor region 76, the semiconductor region 75, and the semiconductor region 71, the effects of the present invention can be obtained.

[0076] As described above, according to the photodetector of the first embodiment, it is possible to suppress a decrease in the time resolution of signal readout, as compared to the photodetector of the comparative embodiment.

[0077] <Embodiment 2> Fig. 7 is a schematic plan view of a SPAD pixel in embodiment 2, and Fig. 8 is a schematic cross-sectional view taken along line X-X' of the SPAD pixel in Fig. 7. The avalanche diode of this embodiment differs from embodiment 1 in that a semiconductor region 74 is formed so as to contact a side wall of a trench. Also, it differs from embodiment 1 in that the area of ​​the semiconductor region 71 is smaller than that of embodiment 1, and a first conductivity type semiconductor region 73 having a lower impurity concentration than the semiconductor region 71 is disposed between the semiconductor region 71 and the semiconductor region 72. In the following, the same reference numerals are used for configurations similar to those of embodiment 1, and description thereof may be omitted.

[0078] As shown in FIG. 7, the semiconductor region 71 has a smaller area than the semiconductor region 71 of the first embodiment. For example, the width of the semiconductor region 71 can be 1 / 30 to 1 / 3 of the pixel pitch, and preferably 1 / 20 to 1 / 4 of the pixel pitch. For example, the width of the semiconductor region 71 can be 0.2 μm to 2 μm. The avalanche multiplication region is the region where the semiconductor region 71 and the semiconductor region 74 overlap in a plan view and the vicinity thereof. In this way, by reducing the area of ​​the semiconductor region 71, the depletion layer region formed by the semiconductor region 71 and the semiconductor region 74 can be reduced. Therefore, the avalanche multiplication region can be reduced, and the dark count rate can be reduced.

[0079] In FIG. 8, the semiconductor region 74 is disposed in contact with the trench isolation portion 16. That is, the semiconductor region 74 is formed over the entire surface of the region partitioned by the trench isolation portion 16 in a plan view. At this time, the potential height is changed in the semiconductor region 74 due to the influence of the semiconductor region 71. Specifically, the potential height of the region of the semiconductor region 74 that overlaps with the semiconductor region 71 in a plan view is lower than the potential height of the region that does not overlap with the semiconductor region 71 in a plan view. This allows the signal charges to be efficiently collected in the avalanche multiplication region, and the aperture ratio can be made higher than that of the first embodiment. For example, the photoelectric conversion element of this embodiment can have an aperture ratio of 70% or more and 100% or less.

[0080] In this embodiment, the semiconductor region 72 and the semiconductor region 74 are in contact with each other. The potential Vt3 is also supplied to the semiconductor region 74 via the contact plug 23. The second conductivity type layer 80 connects the semiconductor region 74 and the semiconductor region 76.

[0081] The semiconductor region 73 is disposed so as to surround the semiconductor region 71 in a plan view. The semiconductor region 73 is a region that relieves an electric field that may occur between the semiconductor region 71 and the semiconductor region 72.

[0082] The semiconductor region 74 does not need to be formed over the entire surface of the region partitioned by the trench isolation portion. Although details will be described later, the semiconductor region 74 may not be formed in the region overlapping the semiconductor region 71. Even in this case, the signal charges can be efficiently collected in the avalanche multiplication region.

[0083] According to the photodetector of this embodiment, as in the first embodiment, it is possible to suppress a decrease in time resolution of signal readout compared to the photodetector of the comparative embodiment. Moreover, according to this embodiment, it is possible to reduce noise compared to the first embodiment. In this embodiment, since the area of ​​the semiconductor region 71 is small, it is possible to reduce noise. Moreover, in this embodiment, it is possible to efficiently collect signal charges in the avalanche multiplication region, thereby improving sensitivity.

[0084] <Embodiment 3> Fig. 9 is a schematic plan view of a SPAD pixel in embodiment 3, and Fig. 10 is a schematic cross-sectional view taken along line X-X' of the SPAD pixel in Fig. 9. In the SPAD pixel of this embodiment, the trench isolation does not penetrate the semiconductor substrate 15, and the positions at which the semiconductor regions 72 and the contact plugs 23 are arranged and the number of them are different from those of embodiment 2. Also, the SPAD pixel of this embodiment differs from embodiment 2 in that the semiconductor regions 74 are not formed over the entire surface of the region partitioned by the trench isolation in a plan view. In the following, the same reference numerals are used for configurations similar to those of embodiment 2, and description thereof may be omitted.

[0085] As shown in FIG. 10, in this embodiment, the trench isolation 16 does not penetrate the semiconductor substrate 15. In other words, the formation of the trench is stopped halfway through the semiconductor substrate 15. One end of the trench on the second surface 15b side is in contact with the semiconductor region 76. The semiconductor region 76 is not separated by the trench isolation 16. In other words, the trench isolation 16 has a side surface and a top surface. The semiconductor region 76 is formed continuously in the multiple photoelectric conversion elements and is shared by the multiple photoelectric conversion elements.

[0086] 9, a plurality of photoelectric conversion elements share a semiconductor region 72 and a contact plug 23. That is, a potential is supplied from the semiconductor region 72 and the contact plug 23 arranged in one photoelectric conversion element to the second conductive type layer 80 and the semiconductor region 76 of the plurality of photoelectric conversion elements. When a potential is supplied to the contact plug 23 provided in a certain photoelectric conversion element, the semiconductor region 72 and the semiconductor region 76 are electrically connected via the second conductive type layer 80. Since the semiconductor region 76 is continuously formed in the plurality of photoelectric conversion elements, a potential is supplied from the contact plug 23 to the second conductive type layer 80 of each photoelectric conversion element from the semiconductor region 76.

[0087] In a pixel in which trench isolation 16 and semiconductor region 72 are arranged, trench isolation 16 and semiconductor region 72 are preferably arranged in plan view near the photoelectric conversion element that shares contact plug 23. This reduces the parasitic resistance of the electrical path through which potential is supplied from contact plug 23 to semiconductor region 72 of the shared photoelectric conversion element, making it possible to suppress performance degradation due to an instantaneous voltage drop caused by an avalanche current.

[0088] According to the photodetector of this embodiment, as in the above-mentioned embodiments, it is possible to suppress the decrease in the time resolution of signal readout compared to the photodetector of the comparative embodiment. Furthermore, when the trench isolation portion 16 penetrates the semiconductor substrate 15, it is necessary to provide a contact plug 23 for each photoelectric conversion element, which makes it difficult to reduce the area of ​​the pixel array portion. According to this embodiment, since the contact plug 23 is shared by multiple photoelectric conversion elements, it is possible to reduce the area of ​​the pixel array portion compared to the case where the trench isolation portion 16 penetrates the semiconductor substrate 15.

[0089] <Embodiment 4> Fig. 11 is a schematic plan view of a SPAD pixel in embodiment 4, and Fig. 12 is a schematic cross-sectional view taken along line X-X' of the SPAD pixel in Fig. 11. The SPAD pixel in this embodiment differs from embodiment 2 in that a potential is also supplied from the second surface 15b. In the following, the same components as those in embodiment 2 are denoted by the same reference numerals, and description thereof may be omitted.

[0090] In the fourth embodiment, a contact plug 27 that supplies a potential to the conductor 16a and a contact plug 29 that supplies a potential to the semiconductor region 76 are connected to the second surface 15b of the semiconductor substrate 15. It is preferable that the same potential is supplied to the contact plugs 23, 25, 27, and 29. This allows the device to be operated with two power sources, a power source that supplies a potential to the contact plug 21 and a power source that supplies a potential to the contact plugs 23, 25, 27, and 29.

[0091] According to the photodetector of this embodiment, as in the above-mentioned embodiments, the deterioration of the time resolution of the signal readout can be suppressed compared to the photodetector of the comparative embodiment. In addition, by arranging the contact plugs 27 and 29, the potential can be supplied from both the first surface 15a and the second surface 15b. Therefore, even if the semiconductor substrate 15 is deep, the potential can be stably supplied to the conductor 16a and the semiconductor region 76.

[0092] <Embodiment 5> Fig. 13 is a schematic plan view of a SPAD pixel in embodiment 5, and Fig. 14 is a schematic cross-sectional view taken along line X-X' of the SPAD pixel in Fig. 13. The SPAD pixel of this embodiment differs from embodiment 2 in that a second conductive type layer is formed in the trench isolation portion 16 using a dielectric having a negative fixed charge. In the following description, the same components as those in embodiment 2 are denoted by the same reference numerals, and description thereof may be omitted.

[0093] The trench isolation 16 according to this embodiment includes a dielectric 16c having a negative fixed charge. In FIG. 14, the dielectric 16c (dielectric layer) is disposed between the insulator 16b and the photoelectric conversion element. That is, the photoelectric conversion element and the dielectric 16c are in contact with each other. A metal oxide layer is suitable as the dielectric 16c having a negative fixed charge. By disposing the dielectric 16c having a negative fixed charge near the sidewall of the trench isolation 16, a second conductive type charge is accumulated on the sidewall of the trench isolation 16, and a second conductive type layer 80 is formed.

[0094] The dielectric 16c is, for example, a hafnium oxide layer, an aluminum oxide layer, a zirconium oxide layer, a titanium oxide layer, a tantalum oxide layer, or a ruthenium oxide layer, and is preferably an aluminum oxide layer or a hafnium oxide layer. The width of the dielectric 16c is preferably 5 nm to 20 nm.

[0095] 14, the dielectric 16c is disposed so that the sidewall of the trench isolation 16 and the dielectric 16c are in contact with each other, but the configuration of the trench isolation 16 is not limited to this. Even with the configuration of the trench isolation 16 described below, it is possible to obtain the effects of this embodiment.

[0096] For example, a thin insulator 16b may be disposed between the dielectric 16c and the sidewalls of the trench isolation 16. In this case, the thickness of the insulator is less than 50 nm. This thin dielectric 16b may be, for example, a silicon oxide layer.

[0097] Moreover, the trench isolation 16 may be composed of only the dielectric 16. That is, the entire trench of the trench isolation 16 may be filled with the dielectric 16c. Even in this case, the second conductive type layer 80 can be formed. From the viewpoint of suppressing crosstalk between pixels, the trench isolation 16 preferably has layers with different refractive indices as shown in FIG. 14. This can reduce the light incident from the second surface 15b and the light due to avalanche emission from traveling toward the adjacent pixel. Although the trench isolation 16 is filled with the insulator 16b and the dielectric 16c in FIG. 14, a void may be provided in the trench isolation 16. For example, the dielectric 16c may be disposed between the void and the trench isolation 16 in a cross-sectional view.

[0098] According to the photodetector of this embodiment, as in the above-mentioned embodiments, it is possible to suppress the deterioration of the time resolution of signal readout compared to the photodetector of the comparative embodiment. In addition, the second conductive type layer 80 can be formed by the dielectric 16c without supplying a potential to the trench isolation portion 16. In addition, since it is not necessary to supply a potential to the trench isolation portion 16, the number of contact plugs can be reduced.

[0099] A modified example of this embodiment is shown in Fig. 15. In this modified example, a dielectric 17 (second dielectric layer) having a negative fixed charge is disposed on the second surface 15b. In Fig. 15, the dielectric 17 is disposed in contact with the second surface 15b, but as explained above, an insulator may be disposed between the dielectric 17 and the second surface 15b.

[0100] The dielectric 17 may be made of the same material as the dielectric 16b, or may be made of a different material.

[0101] The same effect as described above can be obtained in the modified example. Furthermore, since the semiconductor region 46 is not formed in the modified example, the region in which the electric charge remains can be made smaller than in the above-mentioned embodiment. Therefore, the decrease in time resolution can be reduced compared to the case where the semiconductor region 46 is formed.

[0102] <Embodiment 6> 16 and 17 are schematic cross-sectional views of a SPAD pixel in embodiment 6. A plan view is omitted since it is similar to FIG. 7. The SPAD pixel in this embodiment differs from embodiment 2 in that the second surface 15b has a scattering structure 79. In the following, the same components as those in embodiment 2 are denoted by the same reference numerals, and the description thereof may be omitted.

[0103] Second surface 15b is provided with a plurality of recesses as scattering structures 79. This makes it possible to increase the optical path length to first surface 15a by scattering light incident from second surface 15b. When the incident light is IR light, it is necessary to increase the distance until photoelectric conversion and to reduce the light that escapes without being photoelectrically converted, so the effect is more pronounced in the case of IR light.

[0104] The number and shape of the recesses provided in the scattering structure 79 can be designed as appropriate. As shown in FIG. 16, the recesses may be triangular in cross section and provided over the entire second surface 15b in the pixel. The recesses may also be pyramidal. As shown in FIG. 17, the recesses may be provided in a part of the second surface 15b in the pixel. According to the configuration of FIG. 16, the scattering and diffraction angles can be made gentle with respect to the incident angle of light. Therefore, the infrared sensitivity can be improved while suppressing the leakage of light to adjacent pixels. According to the configuration of FIG. 17, the incident and diffraction angles of light can be made steep, and a greater effect of improving the infrared sensitivity can be obtained.

[0105] 16, the width of one recess is preferably, for example, 1 / 30 to 1 / 3 of the width of a pixel. From another perspective, the width of one recess can be, for example, 10 nm to 1 μm. Also, the depth of one recess can be, for example, 1 / 50 to 1 / 3 of the distance from the first surface 15a to the second surface 15b.

[0106] The shape of the recesses can be, for example, a triangle or a trapezoid. The apex of the square or trapezoid may be rounded. The recesses do not need to be formed continuously on the second surface 15b. For example, there may be an area between the recesses or between the recesses and the trench isolation portion 16 where no recesses are formed. The recesses can be formed by a known method such as dry etching.

[0107] An insulator is disposed in the recess of the scattering structure 79. The material of the insulator may be, for example, silicon oxide, silicon nitride, or the like.

[0108] According to the photodetector of this embodiment, as in the above-mentioned embodiments, the deterioration of the time resolution of the signal readout can be suppressed compared to the photodetector of the comparative embodiment. In particular, when the scattering structure 79 is provided, the probability of photocharges being excited near the trench increases compared to the case where the scattering structure is not provided, so that the effect of suppressing the deterioration of the time resolution according to the present invention is enhanced. In addition, the scattering structure 79 can scatter light to lengthen the optical path to the semi-avalanche multiplication region. Therefore, the infrared light can be efficiently photoelectrically converted.

[0109] <Embodiment 7> FIG. 18 is a schematic cross-sectional view of a SPAD pixel in the seventh embodiment. A plan view is omitted since it is similar to FIG. 7. FIG. 19(a) is a potential diagram of Y-Y' in FIG. 18, and FIG. 19(b) is a potential diagram of Z-Z' in FIG. 18. The SPAD pixel of this embodiment is different from the second embodiment in that a second conductivity type semiconductor region is formed on a part of the side wall of the trench isolation portion 16, and a second conductivity type layer 80 is formed on another part of the trench isolation portion 16 by applying a voltage to the conductor 16a. In the following, the same reference numerals are used for the same configuration as the second embodiment, and the description may be omitted.

[0110] In this embodiment, a semiconductor region of the second conductivity type is formed on the side wall of the trench isolation portion 16 by ion implantation. At this time, impurities are implanted at a first impurity concentration up to a predetermined depth of the trench isolation portion 16, and at a position deeper than the predetermined depth, impurities are implanted at a second impurity concentration lower than the first impurity concentration. A semiconductor region 78b is formed at a lower impurity concentration than the impurity concentration forming the semiconductor region 78a. In this way, by lowering the impurity concentration in the deep portion, it is possible to reduce the increase in the width of the semiconductor region 78b. On the other hand, if the impurity concentration is lowered, there is a possibility that the potential supplied from the contact plug to the semiconductor region 76 is not sufficiently transmitted.

[0111] Therefore, in this embodiment, in the semiconductor region 78b having a low impurity concentration, a potential is supplied to the conductor 16a of the trench isolation 16 to form a second conductivity type layer 80 on the side wall of the trench isolation 16. This makes it possible to transmit the potential by supplementing it with the semiconductor region 78b, even when the semiconductor region 78b alone is unable to transmit the potential sufficiently.

[0112] 19(a) and 19(b), in this embodiment as well, it is possible to reduce the area where the potential is flat when forming the second conductive type layer 80. Therefore, it is possible to read out charges efficiently.

[0113] 18, semiconductor region 78 is disposed continuously from semiconductor region 74 to semiconductor region 76 on the sidewall of trench isolation 16. However, the present invention is not limited to this, and semiconductor region 78 may be disposed on a portion of the sidewall of trench isolation 16 and not on the other portion. For example, a configuration may be adopted in which semiconductor region 78 is not provided in a deep portion close to substrate 15b. The potential of semiconductor region 78 may be transmitted to semiconductor region 76 via second conductivity type layer 80.

[0114] According to the photodetector of this embodiment, as in the above-described embodiments, it is possible to suppress dark charge generation from the interface while suppressing deterioration in the time resolution of signal readout compared to the comparative photodetector.

[0115] <Embodiment 8> FIG. 20 is a block diagram showing a configuration of a light detection system 1200 according to this embodiment. The light detection system 1200 of this embodiment includes a light detection device 1204. Here, any of the light detection devices described in the above embodiments can be applied to the light detection device 1204. The light detection system 1200 can be used as, for example, an imaging system. Specific examples of the imaging system include a digital still camera, a digital camcorder, and a surveillance camera. FIG. 20 shows an example of a digital still camera as the light detection system 1200.

[0116] 20 includes a photodetector 1204, a lens 1202 that forms an optical image of a subject on the photodetector 1204, an aperture 1203 that varies the amount of light passing through the lens 1202, and a barrier 1201 that protects the lens 1202. The lens 1202 and the aperture 1203 form an optical system that focuses light on the photodetector 1204.

[0117] The light detection system 1200 has a signal processing unit 1205 that processes an output signal output from the light detection device 1204. The signal processing unit 1205 performs signal processing operations such as performing various corrections and compression on an input signal as necessary and outputting the signal. The light detection system 1200 further has a buffer memory unit 1206 for temporarily storing image data, and an external interface unit (external I / F unit) 1209 for communicating with an external computer or the like. The light detection system 1200 further has a recording medium 1211 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1210 for recording or reading out the imaging data on the recording medium 1211. The recording medium 1211 may be built in the light detection system 1200 or may be removable. In addition, communication between the recording medium control I / F unit 1210 and the recording medium 1211 and communication from the external I / F unit 1209 may be performed wirelessly.

[0118] Furthermore, the light detection system 1200 has an overall control / calculation unit 1208 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1207 that outputs various timing signals to the light detection device 1204 and the signal processing unit 1205. Here, the timing signals and the like may be input from outside, and the light detection system 1200 only needs to have at least the light detection device 1204 and the signal processing unit 1205 that processes the output signal output from the light detection device 1204. As explained in the fourth embodiment, the timing generation unit 1207 may be mounted on the light detection device. The overall control / calculation unit 1208 and the timing generation unit 1207 may be configured to implement a part or all of the control functions of the light detection device 1204.

[0119] The photodetector 1204 outputs an image signal to the signal processor 1205. The signal processor 1205 performs a predetermined signal processing on the image signal output from the photodetector 1204 and outputs image data. The signal processor 1205 generates an image using the image signal. The signal processor 1205 may perform distance measurement calculation on the signal output from the photodetector 1204. The signal processor 1205 and the timing generator 1207 may be mounted on the photodetector. That is, the signal processor 1205 and the timing generator 1207 may be provided on a substrate on which pixels are arranged, or may be provided on a separate substrate. By configuring an imaging system using the photodetector of each of the above-mentioned embodiments, an imaging system capable of acquiring a better quality image can be realized.

[0120] <Embodiment 9> FIG. 21 is a block diagram showing an example of the configuration of a range image sensor, which is an electronic device that uses the light detection device described in the above-described embodiment.

[0121] 21, the distance image sensor 401 is configured to include an optical system 402, a photodetector 403, an image processing circuit 404, a monitor 405, and a memory 406. The distance image sensor 401 can obtain a distance image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected from a light source device 411 toward the subject and reflected by the surface of the subject.

[0122] The optical system 402 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photodetector 403 , forming an image on the light receiving surface (sensor portion) of the photodetector 403 .

[0123] The photodetector 403 is any of the photodetectors according to the above-described embodiments, and a distance signal indicating a distance determined from a light reception signal output from the photodetector 403 is supplied to an image processing circuit 404 .

[0124] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the light detection device 403. The distance image (image data) obtained by this image processing is then supplied to a monitor 405 for display, or supplied to a memory 406 for storage (recording).

[0125] In the range image sensor 401 configured in this way, by applying the above-mentioned photodetection device, it is possible to obtain, for example, a more accurate range image as the pixel characteristics improve.

[0126] <Embodiment 10> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0127] FIG. 22 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0128] 22 shows a state in which an operator (doctor) 1131 is performing surgery on a patient 1132 on a patient bed 1133 using an endoscopic surgery system 1003. As shown in the figure, the endoscopic surgery system 1003 is composed of an endoscope 1100, a surgical tool 1110, and a cart 1134 on which various devices for endoscopic surgery are mounted.

[0129] The endoscope 1100 is composed of a lens barrel 1101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 1132, and a camera head 1102 connected to the base end of the lens barrel 1101. In the illustrated example, the endoscope 1100 is configured as a so-called rigid lens barrel having a rigid lens barrel 1101, but the endoscope 1100 may be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0130] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 1101. A light source device 1203 is connected to the endoscope 1100, and light generated by the light source device 1203 is guided to the tip of the lens barrel 1101 by a light guide extending inside the lens barrel 1101, and is irradiated via the objective lens toward an observation target in a body cavity of a patient 1132. The endoscope 1100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0131] An optical system and a photodetector are provided inside the camera head 1102, and reflected light (observation light) from an observation target is collected by the optical system onto the photodetector. The observation light is photoelectrically converted by the photodetector to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The photodetector described in each of the above-mentioned embodiments can be used as the photodetector. The image signal is transmitted to a camera control unit (CCU) 1135 as RAW data.

[0132] The CCU 1135 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 1100 and the display device 1136. Furthermore, the CCU 1135 receives an image signal from the camera head 1102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0133] Under the control of the CCU 1135 , the display device 1136 displays an image based on an image signal that has been subjected to image processing by the CCU 1135 .

[0134] The light source device 1203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 1100 with irradiation light when photographing an operation site or the like.

[0135] The input device 1137 is an input interface for the endoscopic surgery system 1003. A user can input various information and instructions to the endoscopic surgery system 1003 via the input device 1137.

[0136] The treatment tool control device 1138 controls the driving of the energy treatment tool 1112 for cauterizing tissue, incising, sealing blood vessels, or the like.

[0137] The light source device 1203 that supplies irradiation light to the endoscope 1100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 1203. In this case, it is also possible to capture images corresponding to each of the RGB colors in a time-division manner by irradiating the observation target with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the image sensor of the camera head 1102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0138] Furthermore, the light source device 1203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 1102 in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner and synthesizing the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0139] The light source device 1203 may be configured to supply light in a predetermined wavelength band corresponding to the special light observation. In the special light observation, for example, the wavelength dependency of light absorption in body tissue is utilized. Specifically, a predetermined tissue such as blood vessels on the mucous membrane surface is photographed with high contrast by irradiating light in a narrower band than the irradiation light (i.e., white light) in normal observation. Alternatively, the special light observation may be a fluorescent observation in which an image is obtained by fluorescence generated by irradiating excitation light. In the fluorescent observation, it is possible to irradiate excitation light to the body tissue and observe the fluorescence from the body tissue, or to locally inject a reagent such as indocyanine green (ICG) into the body tissue and irradiate the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0140] <Embodiment 11> The light detection system and the moving body of this embodiment will be described with reference to Fig. 23 and Fig. 24. Fig. 23 is a schematic diagram showing a configuration example of the light detection system and the moving body according to this embodiment. Fig. 24 is a flow diagram showing the operation of the light detection system according to this embodiment. In this embodiment, an example of an in-vehicle camera is shown as the light detection system.

[0141] FIG. 23 shows an example of a vehicle system and a photodetection system mounted thereon for capturing images. The photodetection system 1301 includes a photodetector 1302, an image preprocessing unit 1315, an integrated circuit 1303, and an optical system 1314. The optical system 1314 forms an optical image of a subject on the photodetector 1302. The photodetector 1302 converts the optical image of the subject formed by the optical system 1314 into an electrical signal. The photodetector 1302 is any of the photodetectors according to the above-mentioned embodiments. The image preprocessing unit 1315 performs predetermined signal processing on a signal output from the photodetector 1302. The function of the image preprocessing unit 1315 may be incorporated in the photodetector 1302. The photodetection system 1301 includes at least two sets of the optical system 1314, the photodetector 1302, and the image preprocessing unit 1315, and the output from each set of the image preprocessing unit 1315 is input to the integrated circuit 1303.

[0142] The integrated circuit 1303 is an integrated circuit for use in an imaging system, and includes an image processing unit 1304 including a memory 1305, an optical distance measuring unit 1306, a distance measuring calculation unit 1307, an object recognition unit 1308, and an abnormality detection unit 1309. The image processing unit 1304 performs image processing such as development processing and defect correction on the output signal of the image pre-processing unit 1315. The memory 1305 temporarily stores the captured image and stores the defective positions of the captured pixels. The optical distance measuring unit 1306 focuses on the subject and measures the distance. The distance measuring calculation unit 1307 calculates distance information from multiple image data acquired by multiple photodetectors 1302. The object recognition unit 1308 recognizes subjects such as cars, roads, signs, and people. When the abnormality detection unit 1309 detects an abnormality in the photodetector 1302, it notifies the main control unit 1313 of the abnormality.

[0143] The integrated circuit 1303 may be realized by dedicated hardware, a software module, or a combination of these. It may also be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like, or a combination of these.

[0144] The main control unit 1313 supervises and controls the operations of the light detection system 1301, the vehicle sensor 1310, the control unit 1320, etc. It is also possible to adopt a method in which the main control unit 1313 is not provided, and the light detection system 1301, the vehicle sensor 1310, and the control unit 1320 each have their own communication interface and transmit and receive control signals via a communication network (for example, CAN standard).

[0145] The integrated circuit 1303 has a function of receiving a control signal from the main control unit 1313 or transmitting a control signal or a set value to the photodetector 1302 by its own control unit.

[0146] The optical detection system 1301 is connected to a vehicle sensor 1310, and can detect the vehicle's driving state, such as vehicle speed, yaw rate, and steering angle, as well as the state of the environment outside the vehicle, other vehicles, and obstacles. The vehicle sensor 1310 is also a distance information acquisition means for acquiring distance information to an object. The optical detection system 1301 is also connected to a driving assistance control unit 1311 that performs various driving assistance functions, such as automatic steering, automatic cruising, and collision prevention functions. In particular, the collision determination function determines whether or not a collision with another vehicle or obstacle has occurred based on the detection results of the optical detection system 1301 and the vehicle sensor 1310. This allows for avoidance control when a collision is estimated, and activation of a safety device when a collision occurs.

[0147] The light detection system 1301 is also connected to an alarm device 1312 that issues an alarm to the driver based on the result of the determination by the collision determination unit. For example, if the collision determination unit determines that there is a high possibility of a collision, the main control unit 1313 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 1312 warns the user by sounding an alarm, displaying alarm information on a display screen such as a car navigation system or a meter panel, vibrating a seat belt or steering wheel, etc.

[0148] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are photographed by the light detection system 1301. Fig. 23(b) shows an example of the arrangement of the light detection system 1301 when the light detection system 1301 photographs the area in front of the vehicle.

[0149] The two photodetectors 1302 are disposed in front of the vehicle 1300. Specifically, if the center line of the vehicle 1300 relative to its forward / backward direction or outer shape (e.g., vehicle width) is regarded as an axis of symmetry, and the two photodetectors 1302 are disposed symmetrically about the axis of symmetry, this is preferable for obtaining distance information between the vehicle 1300 and an object to be photographed and for determining the possibility of a collision. In addition, the photodetectors 1302 are preferably disposed so as not to obstruct the driver's field of vision when the driver visually checks the situation outside the vehicle 1300 from the driver's seat. The alarm device 1312 is preferably disposed so as to be easily within the driver's field of vision.

[0150] Next, the failure detection operation of the photodetector 1302 in the photodetection system 1301 will be described with reference to Fig. 24. The failure detection operation of the photodetector 1302 is performed in accordance with steps S1410 to S1480 shown in Fig. 24.

[0151] Step S1410 is a step for performing startup settings of the photodetector 1302. That is, settings for the operation of the photodetector 1302 are transmitted from outside the photodetector system 1301 (e.g., the main control unit 1313) or from inside the photodetector system 1301, and the photodetector 1302 starts imaging and fault detection operations.

[0152] Next, in step S1420, pixel signals are obtained from the effective pixels. In addition, in step S1430, output values ​​are obtained from failure detection pixels provided for failure detection. These failure detection pixels have a photoelectric conversion unit, just like the effective pixels. A predetermined voltage is written to this photoelectric conversion unit. The failure detection pixels output a signal corresponding to the voltage written to this photoelectric conversion unit. Note that steps S1420 and S1430 may be reversed.

[0153] Next, in step S1440, a judgment is made as to whether the output expected value of the fault detection pixel corresponds to the output value from the actual fault detection pixel. If the result of the judgment in step S1440 indicates that the output expected value and the actual output value correspond, the process proceeds to step S1450, it is judged that the imaging operation is performed normally, and the process proceeds to step S1460. In step S1460, the pixel signal of the scanning row is sent to the memory 1305 and temporarily stored. Thereafter, the process returns to step S1420, and the fault detection operation is continued. On the other hand, if the result of the judgment in step S1440 indicates that the output expected value and the actual output value do not correspond, the process proceeds to step S1470. In step S1470, it is judged that there is an abnormality in the imaging operation, and an alarm is issued to the main control unit 1313 or the alarm device 1312. The alarm device 1312 displays the detection of the abnormality on the display unit. Thereafter, in step S1480, the light detection device 1302 is stopped, and the operation of the light detection system 1301 is terminated.

[0154] In this embodiment, the flowchart is looped for each line, but the flowchart may be looped for each set of lines, or the fault detection operation may be performed for each frame. The issuance of the alarm in step S1470 may be notified to the outside of the vehicle via a wireless network.

[0155] In addition, in this embodiment, the control to prevent collision with other vehicles has been described, but the control can also be applied to automatic driving control to follow other vehicles, automatic driving control not to go out of the lane, etc. Furthermore, the light detection system 1301 is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the light detection system 1301 is not limited to moving bodies, but can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0156] The photodetector of the present invention may further be configured to be capable of acquiring various types of information such as distance information.

[0157] (Other embodiments) Although the embodiments have been described above, the present invention is not limited to these embodiments, and various changes and modifications are possible. In addition, the embodiments are mutually applicable. [Explanation of symbols]

[0158] 71 First semiconductor region 76 Second Semiconductor Region 16 Trench isolation 80 Second conductive layer

Claims

1. a pixel array section in which a plurality of photoelectric conversion elements are arranged in a two-dimensional array in a plan view on a substrate; a trench isolation portion provided on the substrate and disposed between the plurality of photoelectric conversion elements; each of the plurality of photoelectric conversion elements includes an avalanche diode; the avalanche diode includes: a first semiconductor region of a first conductivity type, the first semiconductor region being disposed at a first depth from a first surface of the substrate, the first semiconductor region having charges of the same conductivity type as a signal charge as majority carriers; a second semiconductor region of a second conductivity type, the second semiconductor region being disposed at a second depth, the second depth being longer from the first surface of the substrate than the first depth and having a distance to a second surface opposed to the first surface shorter than the distance to the first surface; and a third semiconductor region being disposed at a third depth, the third depth being deeper than the first depth and shallower than the second depth, the third semiconductor region having an impurity concentration lower than impurity concentrations of the first semiconductor region and the second semiconductor region; the trench isolation portion includes a conductor and an insulator disposed between the conductor and the avalanche diode; A photodetection device characterized in that a second conductivity type layer in which charges of the second conductivity type possessed by the third semiconductor region are accumulated is formed on a side wall of the trench isolation portion, and the second conductivity type layer is configured to be in contact with the second semiconductor region.

2. 2. The photodetector according to claim 1, wherein the second conductive type layer is formed when a predetermined potential is applied to the conductor.

3. a pixel array section in which a plurality of photoelectric conversion elements are arranged in a two-dimensional array in a plan view on a substrate; a trench isolation portion provided on the substrate and disposed between the plurality of photoelectric conversion elements; each of the plurality of photoelectric conversion elements includes an avalanche diode; the avalanche diode includes: a first semiconductor region of a first conductivity type, disposed at a first depth from a first surface of the substrate, and having charges of the same conductivity type as a signal charge as majority carriers; a second semiconductor region of a second conductivity type, disposed at a second depth, the distance from the first surface of the substrate being longer than the first depth and the distance to a second surface opposing the first surface being shorter than the distance to the first surface; and a third semiconductor region of the first conductivity type, disposed at a third depth deeper than the first depth and shallower than the second depth, and having an impurity concentration lower than the impurity concentration of the first semiconductor region; the trench isolation portion includes a conductor and an insulator disposed between the conductor and the avalanche diode; a trench isolation portion and a third semiconductor region in contact with each other;

4. a pixel array section in which a plurality of photoelectric conversion elements are arranged in a two-dimensional array in a plan view on a substrate; a trench isolation portion provided on the substrate and disposed between the plurality of photoelectric conversion elements; each of the plurality of photoelectric conversion elements includes an avalanche diode; the avalanche diode includes: a first semiconductor region of a first conductivity type, disposed at a first depth from a first surface of the substrate, and having charges of the same conductivity type as a signal charge as majority carriers; and a second semiconductor region of a second conductivity type, disposed at a second depth, the distance from the first surface of the substrate being longer than the first depth and the distance to a second surface opposite the first surface being shorter than the distance to the first surface; a dielectric layer formed of at least one of a hafnium oxide layer, an aluminum oxide layer, a zirconium oxide layer, a titanium oxide layer, a tantalum oxide layer, and a ruthenium oxide layer, disposed in the trench isolation portion;

5. a pixel array section in which a plurality of photoelectric conversion elements are arranged in a two-dimensional array in a plan view on a substrate; a trench isolation portion provided on the substrate and disposed between the plurality of photoelectric conversion elements; each of the plurality of photoelectric conversion elements includes an avalanche diode; the avalanche diode includes: a first semiconductor region of a first conductivity type, disposed at a first depth from a first surface of the substrate, and having charges of the same conductivity type as a signal charge as majority carriers; and a second semiconductor region of a second conductivity type, disposed at a second depth, the distance from the first surface of the substrate being longer than the first depth and the distance to a second surface opposite the first surface being shorter than the distance to the first surface; A photodetector device, comprising: a dielectric material having a negative fixed charge disposed in the trench isolation portion.

6. 6. The photodetector according to claim 1, wherein the trench isolation portion is disposed so as to be in contact with the second semiconductor region.

7. a pixel array section in which a plurality of photoelectric conversion elements are arranged in a two-dimensional array in a plan view on a substrate; a trench isolation portion provided on the substrate and disposed between the plurality of photoelectric conversion elements; each of the plurality of photoelectric conversion elements includes an avalanche diode; a first dielectric layer made of at least one of a hafnium oxide layer, an aluminum oxide layer, a zirconium oxide layer, a titanium oxide layer, a tantalum oxide layer, and a ruthenium oxide layer is disposed in the trench isolation portion; the substrate has a first surface and a second surface opposite to the first surface; A photodetector device, characterized in that a second dielectric layer consisting of at least one of a hafnium oxide layer, an aluminum oxide layer, a zirconium oxide layer, a titanium oxide layer, a tantalum oxide layer, and a ruthenium oxide layer is disposed on the second surface of the substrate.

8. a pixel array section in which a plurality of photoelectric conversion elements are arranged in a two-dimensional array in a plan view on a substrate; a trench isolation portion provided on the substrate and disposed between the plurality of photoelectric conversion elements; each of the plurality of photoelectric conversion elements includes an avalanche diode; a first dielectric having a negative fixed charge is disposed in the trench isolation; the substrate has a first surface and a second surface opposite to the first surface; A photodetector device comprising a second dielectric material having a negative fixed charge disposed on a second surface of the substrate.

9. 9. The photodetector according to claim 7, wherein a second conductivity type layer in which charges of a second conductivity type are accumulated is formed on a side wall of the trench isolation portion and on the second surface of the substrate.

10. 10. The photodetection device according to claim 7, wherein the avalanche diode is disposed at a first depth from the first surface of the substrate and has a first semiconductor region of a first conductivity type having a majority carrier of charge of the same conductivity type as the signal charge.

11. the avalanche diode has a fourth semiconductor region of a second conductivity type disposed at a fourth depth that is a distance from the first surface of the substrate that is greater than the first depth; 11. The photodetector according to claim 1, wherein the first semiconductor region and the fourth semiconductor region form an avalanche multiplication region.

12. The photodetector according to claim 11 , wherein the fourth semiconductor region is disposed so as to be in contact with the trench isolation portion.

13. a second conductive type layer having second conductive type charges accumulated on a sidewall of the trench isolation portion; 13. The photodetector according to claim 11, wherein the second conductive type layer is in contact with the fourth semiconductor region.

14. 14. The photodetector according to claim 10, wherein, in a cross-sectional view, a width of the first semiconductor region is equal to or greater than 1 / 30 and equal to or less than 1 / 3 of a width of the photoelectric conversion element.

15. 15. A light detection device according to any preceding claim, wherein the second surface is a scattering structure.

16. 16. The light detection device according to claim 1, wherein the second surface is pyramidal.

17. 17. The light detection device according to claim 16, wherein a depth of the recess constituting the pyramid of the pyramid is in the range of 1 / 30 to 1 / 3 of a width of the photoelectric conversion element in a cross-sectional view.

18. 18. The light detection device according to claim 1, wherein the photoelectric conversion element converts infrared light into an electric signal.

19. 19. The light detection device according to claim 1, wherein the aperture ratio of the photoelectric conversion element is 50% or more and 100% or less.

20. The concentration of the second conductive type impurity at the sidewall of the trench isolation portion is the lowest at 5×10 １７ cm －３ 20. The light detection device according to claim 1, wherein:

21. A light detection device according to any one of claims 1 to 20, and a signal processing unit that processes a signal output from the photodetector.

22. A light detection device according to any one of claims 1 to 20, a distance information acquisition means for acquiring distance information to an object from distance measurement information based on a signal from the light detection device, A moving body further comprising a control means for controlling the moving body based on the distance information.

Images