Semiconductor device

Abstract

To suppress breakage near a wiring region passing an inside of an active region when IGBT is turned off.SOLUTION: A semiconductor device 1 has a wiring region 4 passing an inside of an active region 2 having an IGBT. The wiring region 4 has: a drift layer 11 of a first conductivity type; a collector layer 16 of a second conductivity type provided on a rear surface side of the drift layer 11; a well layer 17 of a second conductivity type provided on a surface side of the drift layer 11; a gate runner 5 provided on the surface side of the well layer 17 and supplying the gate electrode 21 with gate potential; an emitter electrode 22 provided on the surface side of the gate runner 5; and a contact region (a third contact region 30) electrically connecting the well layer 17 and the emitter electrode 22. The gate runner 5 is composed of a single layer (a first gate runner 5A) and has an opening 5C larger than the contact region at a position corresponding to the contact region.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art As one type of semiconductor device, an IGBT (Insulated Gate Bipolar Transistor) is known.

[0003] Fig. 8 is a top view of a conventional semiconductor device. Fig. 9 is an enlarged view of a portion D in Fig. 8. Fig. 10 is a cross-sectional view taken along the line CC' in Fig. 9. Note that in Figs. 8 and 9, some components are omitted for ease of viewing.

[0004] 8, the conventional semiconductor device 1 has an active region 2 having an IGBT, a termination region 3 surrounding the periphery of the active region 2, a wiring region 4 passing through the inside of the active region 2, a gate runner 5, and a gate pad 6. Also, as shown in FIGS. 9 and 10, the conventional semiconductor device 1 has a drift layer 11, a body layer 12, an emitter layer 13, a contact layer 14, a buffer layer 15, a collector layer 16, a well layer 17, a gate electrode 21, an emitter electrode 22, a collector electrode 23, a gate insulating film (not shown), a trench (not shown), an interlayer insulating film 26, an insulating film 27, a first contact region 28, and a second contact region 29.

[0005] 8, a gate runner 5 that supplies a gate potential to a gate electrode 21 of the IGBT is provided between the active region 2 and the termination region 3, and in the wiring region 4. The gate runner 5 is connected to a gate pad 6 that is connected to the outside.

[0006] 9 and 10, the gate runner 5 in the wiring region 4 is composed of two layers, a first gate runner 5A composed of polysilicon and a second gate runner 5B composed of metal. The first gate runner 5A and the second gate runner 5B are connected by a second contact region 29 that penetrates the interlayer insulating film 26. Since metal has a lower wiring resistance than polysilicon, by forming the gate runner 5 in two layers, the wiring resistance of the gate runner 5 can be reduced.

[0007] Conventional techniques in which the gate runner 5 in the wiring region 4 is configured in two layers include, for example, FIG. 26 of Patent Document 1 and FIG. 20 of Patent Document 2. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2019-12840 A [Patent Document 2] JP 2018-200950 A Summary of the Invention [Problem to be solved by the invention]

[0009] 10, in the wiring region 4, holes 31 injected from the collector layer 16 at a position overlapping the gate runner 5 at the time of turning off the IGBT enter the well layer 17, pass through the first contact region 28 that connects the body layer 12 and the emitter electrode 22 outside the wiring region 4 via the contact layer 14, and are pulled out along a path to the emitter electrode 22, so that the holes 31 are concentrated at the end of the first contact region 28, and destruction may occur at a position indicated by a destruction point 32 near the wiring region 4. This destruction causes a problem that the destruction tolerance of the IGBT in the reverse bias safe operating area (RBSOA) is limited.

[0010] An object of the present invention is to provide a semiconductor device that suppresses the occurrence of breakdown in the vicinity of a wiring region that passes through the inside of an active region when an IGBT is turned off. [Means for solving the problem]

[0011] In order to solve the above problems, a semiconductor device of the present invention has an active region having an IGBT, a termination region surrounding the periphery of the active region, and a wiring region passing through the inside of the active region, the IGBT has a gate electrode, an emitter electrode provided on a front side, and a collector electrode provided on a back side, the wiring region has a drift layer of a first conductivity type, a collector layer of a second conductivity type provided on the back side of the drift layer, a well layer of the second conductivity type provided on the front side of the drift layer, a gate runner provided on the front side of the well layer and supplying a gate potential to the gate electrode, the emitter electrode provided on the front side of the gate runner, and a contact region electrically connecting the well layer and the emitter electrode, the gate runner being composed of a single layer and having an opening larger than the contact region at a position corresponding to the contact region. Effect of the Invention

[0012] According to the present invention, it is possible to suppress the occurrence of breakdown in the vicinity of a wiring region passing through the inside of an active region when an IGBT is turned off. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a top view of the semiconductor device according to the embodiment. [Diagram 2] Enlarged view of part D in Figure 1. [Diagram 3] A cross-sectional view taken along the line A-A' in Figure 2. [Figure 4] Cross-sectional view taken along the line B-B' in Figure 2. [Diagram 5] C-C' cross-sectional view of Figure 2. [Figure 6]FIG. 13 is a top view of a semiconductor device according to a comparative example. [Figure 7] Enlarged view of part D in Figure 6. [Figure 8] FIG. 1 is a top view of a conventional semiconductor device. [Figure 9] Enlarged view of part D in Figure 8. [Figure 10] Cross-sectional view taken along the line CC' in Figure 9. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In each drawing, the same or similar components are designated by the same reference numerals, and duplicated explanations will be omitted.

[0015] Fig. 1 is a top view of a semiconductor device of an embodiment. Fig. 2 is an enlarged view of part D in Fig. 1. Fig. 3 is a cross-sectional view taken along line A-A' in Fig. 2. Fig. 4 is a cross-sectional view taken along line B-B' in Fig. 2. Fig. 5 is a cross-sectional view taken along line C-C' in Fig. 2. Note that in Figs. 1 and 2, some components are omitted from the illustration in order to make the drawings easier to see.

[0016] 1, a semiconductor device 1 of the embodiment has an active region 2 having an IGBT, a termination region 3 surrounding the periphery of the active region 2, and a wiring region 4 passing through the inside of the active region 2. The semiconductor device 1 also has, between the active region 2 and the termination region 3 and in the wiring region 4, a gate runner 5 which is a gate wiring that supplies a gate potential to a gate electrode 21 (see FIG. 2 etc.) of the IGBT, and a gate pad 6 which is connected to the outside and supplies a gate potential to the gate runner 5.

[0017] The gate runner 5 between the active region 2 and the termination region 3 is desirably composed of at least two layers, as in the conventional case. This allows the wiring resistance of the gate runner 5 to be reduced. In this embodiment, an example is described in which the gate runner 5 is composed of two layers, a first gate runner 5A composed of polysilicon, for example, and a second gate runner 5B composed of a metal such as Al. The first gate runner 5A arranged on the back side and the second gate runner 5B arranged on the front side are connected by a contact region (not shown) that penetrates the interlayer insulating film 26 (see FIGS. 3 to 6).

[0018] In contrast, in this embodiment, the gate runner 5 in the wiring region 4 is composed of a single layer of a first gate runner 5A made of, for example, polysilicon. As shown in Figures 2 and 5, the semiconductor device 1 of this embodiment has a third contact region 30 in the wiring region 4 that electrically connects the well layer 17 and the emitter electrode 22.

[0019] In this embodiment, in the wiring region 4, the well layer 17 and the emitter electrode 22 are electrically connected via the third contact region 30, so that in the wiring region 4, holes 31 injected from the collector layer 16 at a position overlapping with the gate runner 5 can enter the well layer 17 and pass directly to the emitter electrode 22 via the third contact region 30 when the IGBT is turned off. This makes it possible to suppress the concentration of holes 31 at the end of the first contact region 28 outside the wiring region 4, and to suppress the occurrence of breakdown in the vicinity of the wiring region 4. As a result, the RBSOA breakdown resistance of the IGBT is not limited by this breakdown, and the RBSOA breakdown resistance can be improved.

[0020] In the wiring region 4, the emitter electrode 22 is provided on the surface side of the first gate runner 5A. An interlayer insulating film 26 is provided between the emitter electrode 22 and the first gate runner 5A. An insulating film 27 is provided between the first gate runner 5A and the well layer 17. The first gate runner 5A has an opening 5C larger than the third contact region 30 at a position corresponding to the third contact region 30. Therefore, the third contact region 30 has a structure that penetrates the interlayer insulating film 26, the first gate runner 5A, and the insulating film 27. It is preferable that the well layer 17 and the third contact region 30 are connected via a contact layer 14 having a higher impurity concentration than the well layer 17. It is preferable that the emitter electrode 22 is provided at a position that covers the entire short side direction of the gate runner 5.

[0021] 2 and 3, the IGBT in the active region 2 has a gate electrode 21, an emitter electrode 22 provided on the front side, and a collector electrode 23 provided on the back side. In this embodiment, an example will be described in which the IGBT has a trench 25, and the gate electrode 21 and the gate insulating film 24 are provided inside the trench 25, but this is not limiting. The emitter electrode 22 and the collector electrode 23 are made of a metal such as Al, and the gate electrode 21 is made of polysilicon, for example.

[0022] The IGBT also includes a drift layer 11 formed of a semiconductor of a first conductivity type (an example of n-type is shown in FIG. 3), a body layer 12 formed of a semiconductor of a second conductivity type (an example of p-type is shown in FIG. 3) provided on the front side of the drift layer 11, an emitter layer 13 formed of a semiconductor of the first conductivity type provided on the front side of the body layer, an interlayer insulating film 26 provided between the emitter layer 13 and the gate electrode 21 and the emitter electrode 22, a buffer layer 15 formed of a semiconductor of the first conductivity type provided on the rear side of the drift layer 11 and having a higher impurity concentration than the drift layer 11, and a collector layer 16 formed of a semiconductor of the second conductivity type provided between the buffer layer 15 and the collector electrode 23. The emitter electrode 22 is connected to the emitter layer 13 at a first contact region 28, and is connected to the body layer 12 via the contact layer 14 formed of the semiconductor of the second conductivity type and the first contact region 28. The buffer layer 15 is not essential, but is preferably provided.

[0023] The trench 25 has a depth that penetrates the body layer 12 and reaches the drift layer 11. A gate insulating film 24 is provided inside the trench 25 so as to surround the gate electrode 21.

[0024] As shown in FIG. 2, FIG. 4, and FIG. 5, the wiring region 4 has a drift layer 11, a collector layer 16 provided on the back side of the drift layer 11, a well layer 17 of a second conductivity type provided on the front side of the drift layer 11, a gate runner 5 (first gate runner 5A) provided on the front side of the well layer 17 and supplying a gate potential to a gate electrode 21, an emitter electrode 22 provided on the front side of the gate runner 5, and a contact region (third contact region 30) electrically connecting the well layer 17 and the emitter electrode 22, and the gate runner 5 is composed of a single layer (first gate runner 5A) and has an opening 5C larger than the contact region (third contact region 30) at a position corresponding to the contact region (third contact region 30). The wiring region 4 also has an interlayer insulating film 26, an insulating film 27, a contact layer 14, and a buffer layer 15. The buffer layer 15 is not essential, but is preferably provided.

[0025] As shown in Fig. 4, the well layer 17 has a deeper diffusion depth of the impurities than the trench 25. The well layer 17 also extends to a part outside the wiring region 4, and as shown in Fig. 5, the well layer 17 becomes shallow midway and is connected to the body layer 12. As shown in Fig. 4, an insulating film 27 is formed between the well layer 17 and the first gate runner 5A, and the insulating film 27 is connected to the gate insulating film 24.

[0026] As shown in FIG. 4, the gate electrode 21 is extended to the outside of the trench 25 and connected to a first gate runner 5A.

[0027] Next, the effect of constructing the gate runner 5 in the wiring region 4 from a single layer of the first gate runner 5A as in this embodiment and electrically connecting the well layer 17 and the emitter electrode 22 by the third contact region 30 within the opening 5C of the first gate runner 5A will be described using the comparative examples in FIGS. 6 and 7.

[0028] Fig. 6 is a top view of a semiconductor device of a comparative example, and Fig. 7 is an enlarged view of a portion D in Fig. 6.

[0029] In the comparative example, the gate runner 5 in the wiring region 4 is composed of two layers, a first gate runner 5A and a second gate runner 5B, and they are connected to each other by a contact region (not shown) as in the conventional example shown in FIG. 10. Also, the emitter electrode 22 and the second gate runner 5B are formed of the same material at the same time as in the conventional example shown in FIG. 10, and are therefore in the same layer. Therefore, as shown in FIG. 7, if it is attempted to electrically connect the well layer 17 and the emitter electrode 22 by the third contact region 30 within the opening 5C of the first gate runner 5A, it is necessary to make the width (short-side dimension) of the first gate runner 5A larger than the width of the second gate runner 5B and to provide the third contact region 30 at a position that avoids the second gate runner 5B. As a result, the width of the wiring region 4 is increased, and the area of ​​the active region 2 is reduced.

[0030] 2, in this embodiment, the width of the wiring region 4 can be made smaller than in the comparative example, and the area of ​​the active region 2 can be secured. It is preferable that the opening 5C is provided at a position including the center of the gate runner 5 in the short side direction. It is more preferable that the opening 5C is provided at the center of the gate runner 5 in the short side direction.

[0031] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this and the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the carriers injected from the collector layer 16 become electrons instead of holes.

[0032] As an example of the impurity concentration, the drift layer 11 is shown as a low concentration n-, the emitter layer 13 as a high concentration n+, the contact layer 14 as a high concentration p+, the body layer 12, the collector layer 16, and the well layer 17 as p, and the buffer layer 15 as n. The impurity concentrations are not limited to these, and may be changed as appropriate within a range in which the intended operation of this embodiment is possible.

[0033] Although the embodiment of the present invention has been described above, the present invention is not limited to the configurations described in the embodiment, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in the embodiment may be combined and applied. [Explanation of symbols]

[0034] 1 Semiconductor device 2. Active Area 3 Termination area 4 Wiring area 5 Gate Runner 5A 1st Gate Runner (Polysilicon) 5B Second gate runner (metal) 5C opening 6 Gate Pad 11 Drift layer 12 Body Layer 13 Emitter layer 14 Contact layer 15 Buffer layer 16 Collector layer 17 Well Layer 21 Gate electrode 22 Emitter electrode 23 Collector electrode 24 Gate insulating film 25 Trench 26 Interlayer insulating film 27 Insulating Film 28 First contact area (inside IGBT) 29 Second Contact Area (between gate runners) 30 Third contact region (wiring region well layer) 31 holes 32 Destruction area

Claims

1. an active region having an IGBT, a termination region surrounding the periphery of the active region, and a wiring region passing through the inside of the active region; The IGBT has a gate electrode, an emitter electrode provided on a front surface side, and a collector electrode provided on a back surface side, the wiring region includes: a drift layer of a first conductivity type; a collector layer of a second conductivity type provided on a back surface side of the drift layer; a well layer of the second conductivity type provided on a front surface side of the drift layer; a gate runner provided on the front surface side of the well layer and supplying a gate potential to the gate electrode; the emitter electrode provided on the front surface side of the gate runner; and a contact region electrically connecting the well layer and the emitter electrode; The gate runner is formed of a single layer, and has an opening larger than the contact region at a position corresponding to the contact region.

2. In claim 1, The semiconductor device is characterized in that the opening is provided at a position including a center of the gate runner in a lateral direction.

3. In claim 1, The semiconductor device according to claim 1, wherein the emitter electrode is disposed at a position that covers the entire gate runner in a lateral direction.

4. In claim 1, The semiconductor device is characterized in that the gate runner is made of polysilicon.

5. In claim 1, The IGBT has a trench, The semiconductor device according to claim 1, wherein the gate electrode is provided inside the trench.

6. In claim 1, a gate runner, which is formed of at least two layers and supplies a gate potential to the gate electrode, between the active region and the termination region;

7. In claim 6, the gate runner provided in the wiring region is made of polysilicon; A semiconductor device characterized in that the gate runner, which is composed of at least two layers and is provided between the active area and the termination area, has a back side composed of polysilicon and a front side composed of metal.

Images