Semiconductor device

Abstract

To provide a semiconductor device that can be suppressed in temperature rise.SOLUTION: A semiconductor device according to one embodiment includes: a base substrate; a case provided on the upper surface of the base substrate; a first laminate provided inside the case on the upper surface of the base substrate; a second laminate provided apart from the first laminate on the upper surface of the base substrate; and a flat plate-like first conductor having a first portion in contact with the first laminate and a second portion in contact with the second laminate. The first laminate includes a first insulator, a second conductor that is provided on the upper surface of the first insulator and that is in contact with the first portion of the first conductor, and a first semiconductor element electrically connected to the second conductor. The second laminate includes a second insulator and a third conductor that is provided on the upper surface of the second insulator and that is in contact with the second portion of the first conductor, and does not include a semiconductor element.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Power modules are known as semiconductor devices that achieve high output. A power module is configured as a single package in which multiple power semiconductors are integrated. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2016 / 056532 [Patent Document 2] JP 2016-76563 A [Patent Document 3] JP 2010-35346 A Summary of the Invention [Problem to be solved by the invention]

[0004] Suppresses temperature rise. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a base substrate, a case provided on an upper surface of the base substrate, a first stack provided on the upper surface of the base substrate inside the case, a second stack provided on the upper surface of the base substrate away from the first stack, and a flat first conductor having a first portion in contact with the first stack and a second portion in contact with the second stack. The first stack includes a first insulator, a second conductor provided on the upper surface of the first insulator and in contact with the first portion of the first conductor, and a first semiconductor element electrically connected to the second conductor. The second stack includes a second insulator and a third conductor provided on the upper surface of the second insulator and in contact with the second portion of the first conductor, but does not include a semiconductor element. [Brief description of the drawings]

[0006] [Figure 1] 1 is a perspective view showing an external structure of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view showing a first example of a cross-sectional structure of a semiconductor device according to a first embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 11 is a cross-sectional view showing a first example of a cross-sectional structure of a semiconductor device according to a second embodiment. [Figure 6] FIG. 11 is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the second embodiment. [Figure 7] FIG. 11 is a cross-sectional view showing a first example of a cross-sectional structure of a semiconductor device according to a third embodiment. [Figure 8] FIG. 13 is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the third embodiment. [Figure 9] FIG. 13 is a cross-sectional view showing a first example of a cross-sectional structure of a semiconductor device according to a fourth embodiment. [Figure 10] FIG. 13 is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the fourth embodiment. [Figure 11] FIG. 13 is a cross-sectional view showing a first example of a cross-sectional structure of a semiconductor device according to a fifth embodiment. [Figure 12] FIG. 13 is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the fifth embodiment. [Figure 13] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a first modified example. [Figure 14] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a second modification. [Figure 15] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a third modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and ratios of the drawings are not necessarily the same as those in reality.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from each other, different letters or numbers may be added to the end of the same reference numerals.

[0009] 1. First embodiment The semiconductor device according to the first embodiment will be described.

[0010] The semiconductor device according to the first embodiment is a power module, and is applied to, for example, a power conversion device for a railway vehicle or a power unit for industrial equipment.

[0011] The configuration of the semiconductor device according to the first embodiment will be described.

[0012] First, the external structure of the semiconductor device according to the first embodiment will be described.

[0013] 1 is a perspective view showing an example of the external structure of a semiconductor device according to a first embodiment. The semiconductor device 1 includes a base substrate BS, a case CS, and a lid CV as its external structure. The base substrate BS, the case CS, and the lid CV form a container for the semiconductor device 1. A circuit configuration (not shown) including a semiconductor element is housed inside the container for the semiconductor device 1.

[0014] The base substrate BS is a support corresponding to the lower part of the container of the semiconductor device 1. The base substrate BS has a flat plate shape. The base substrate BS is fixed to an external device (not shown) of the semiconductor device 1, for example, via screw holes formed in the four corners.

[0015] A case CS is provided on the upper surface of the base substrate BS. The case CS is an insulating body having a rectangular cylindrical shape. The case CS corresponds to a side portion of the container of the semiconductor device 1. The case CS is fixed to the base substrate BS.

[0016] A lid CV is provided on the top surface of the case CS. The lid CV is an insulating material having a flat plate shape. The lid CV corresponds to the upper part of the container of the semiconductor device 1. The lid CV is fixed to the case CS.

[0017] By assembling the base substrate BS, the case CS, and the cover CV as described above, a space for arranging a circuit configuration is formed inside the container.

[0018] Moreover, the semiconductor device 1 further includes a plurality of terminals T (T_P, T_N, T_AC, and T_S).

[0019] The terminals T_P, T_N, T_AC, and T_S are ends of bus bars (not shown) that electrically connect between an external device and an internal circuit configuration of the semiconductor device 1. In the example of Fig. 1, two terminals T_P, two terminals T_N, three terminals T_AC, and eight terminals T_S are shown. Note that the number of each of the terminals T_P, T_N, T_AC, and T_S is not limited to the example of Fig. 1, and can be designed to be any number.

[0020] The two terminals T_P are input terminals. The two terminals T_P have P (Positive) polarity. The two terminals T_P are electrically connected to each other. The two terminals T_P are disposed on one of two opposing short sides of the semiconductor device 1.

[0021] The two terminals T_N are input terminals. The two terminals T_N have N (negative) polarity. The two terminals T_N are electrically connected to each other. The two terminals T_N are arranged on one of two opposing short sides of the semiconductor device 1, side by side with the two terminals T_P.

[0022] The three terminals T_AC are output terminals. The three terminals T_AC are also called AC (Alternating Current) terminals. The three terminals T_AC are electrically connected to each other. The three terminals T_AC are disposed on the other of the two opposing short sides of the semiconductor device 1.

[0023] The eight terminals T_S are control terminals and monitor terminals. The control terminals are, for example, terminals for controlling whether or not to drive a semiconductor element included in the circuit configuration of the semiconductor device 1. The monitor terminals are, for example, terminals for monitoring electrical characteristics of the circuit configuration of the semiconductor device 1. The eight terminals T_S are arranged on two opposing long sides of the semiconductor device 1, four on each side.

[0024] Next, the circuit configuration of the semiconductor device according to the first embodiment will be described.

[0025] Fig. 2 is a circuit diagram showing an example of a circuit configuration of the semiconductor device according to the first embodiment. As shown in Fig. 2, the multiple terminals T_S include terminals T_S1, T_S2, T_S3, and T_S4. In addition, in the example of Fig. 2, the semiconductor device 1 includes transistors TR_up and TR_low as electrical elements included in the internal circuit configuration.

[0026] The transistors TR_up and TR_low are, for example, insulated gate bipolar transistors (IGBTs) or metal-oxide-silicon field-effect transistors (MOSFETs) using silicon carbide (SiC). The transistors TR_up and TR_low are connected in series. Note that, although one each of the transistors TR_up and TR_low is shown in the example of FIG. 2, this is not limiting. For example, each of the transistors TR_up and TR_low may be composed of a plurality of transistors connected in parallel with each other.

[0027] Specifically, the transistor TR_up has a drain terminal connected to the terminal T_P, a source terminal connected to the drain terminal of the transistor TR_low, and a gate terminal connected to the terminal T_S1. The transistor TR_low has a drain terminal connected to the source terminal of the transistor TR_up, a source terminal connected to the terminal T_N, and a gate terminal connected to the terminal T_S2. The source terminal of the transistor TR_up and the drain terminal of the transistor TR_low are commonly connected to the terminals T_AC, T_S3, and T_S4.

[0028] The terminals T_S1 and T_S2 correspond to two different control terminals of the terminal T_S. The terminals T_S3 and T_S4 correspond to two different monitor terminals of the terminal T_S. The terminal T_S3 is located closer to the transistor TR_up than the terminal T_AC. The terminal T_S4 is located closer to the transistor TR_low than the terminal T_3.

[0029] With the above-described configuration, the semiconductor elements inside the semiconductor device 1 can be controlled by a voltage supplied from outside the semiconductor device 1.

[0030] Next, the cross-sectional structure of the semiconductor device according to the first embodiment will be described.

[0031] FIG. 3 is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the first embodiment. The first and second examples are cross-sectional views of the semiconductor device 1 taken along different cross sections. Specifically, the first example shows an example of the cross-sectional structure of the semiconductor device 1 in a portion where a bus bar functioning as a terminal T and a transistor TR are provided on the same conductor. The second example shows an example of the cross-sectional structure of the semiconductor device 1 in a portion where a bus bar functioning as a terminal T and a transistor TR are provided on different conductors.

[0032] The semiconductor device 1 includes conductors 10, 12, 13, 15, 17, 18, and 19, insulators 11, 14, and 20, and a semiconductor element 16. The conductor 12 includes conductors 12a, 12b, and 12c. The conductor 13 includes conductors 13a, 13b, and 13c. The insulator 14 includes insulators 14a, 14b, and 14c. The conductor 15a includes conductors 15a-1, 15a-2, 15b, and 15c. The conductor 17 includes conductors 17-1 and 17-2. The conductor 18 includes conductors 18-1 and 18-2.

[0033] The conductor 10 corresponds to the base substrate BS. The conductor 10 includes, for example, copper (Cu) or ceramics.

[0034] An insulator 11 corresponding to the case CS is provided on the upper surface of the conductor 10. The insulator 11 includes, for example, polyphenylene sulfide (PPC: Poly-Phenylene Sulfide).

[0035] On the upper surface of the conductor 10, in a region (inside) surrounded by the insulator 11, three laminated bodies LS1, LS2, and LS3 are provided spaced apart from one another.

[0036] As shown in FIG. 3 and FIG. 4, the laminate LS1 includes a conductor 12a, a conductor 13a, an insulator 14a, conductors 15a-1 and 15a-2, and a semiconductor element 16. The conductor 12a is provided on the upper surface of the conductor 10. The conductor 12a includes, for example, solder. The conductor 13a is provided on the upper surface of the conductor 12a. The conductor 13a includes, for example, copper (Cu). The insulator 14a is provided on the upper surface of the conductor 13a. The insulator 14a is an insulating substrate including insulating ceramics such as aluminum nitride (AlN) and silicon nitride (SiN). The conductors 15a-1 and 15a-2 are provided on the upper surface of the insulator 14a, spaced apart from each other. The conductors 15a-1 and 15a-2 include, for example, copper (Cu). A semiconductor element 16 is provided on the upper surface of the conductor 15a-1. That is, the insulator 14a is an insulating substrate on which the semiconductor element 16 is mounted. The semiconductor element 16 is a chip including a transistor TR (TR_up or TR_low). The upper surface of the semiconductor element 16 and the upper surface of the conductor 15a-2 are electrically connected by a conductor 19. The conductor 19 is, for example, a bonding wire.

[0037] As shown in FIG. 3, the laminate LS2 includes a conductor 12b, a conductor 13b, an insulator 14b, and a conductor 15b. The conductor 12b is provided on the upper surface of the conductor 10. The conductor 12b includes, for example, solder. The conductor 13b is provided on the upper surface of the conductor 12b. The conductor 13b includes, for example, copper (Cu). The insulator 14b is provided on the upper surface of the conductor 13b. The insulator 14b includes, for example, insulating ceramics such as aluminum nitride (AlN) and silicon nitride (SiN). The conductor 15b is provided on the upper surface of the insulator 14b. The conductor 15b includes, for example, copper (Cu). Note that the semiconductor element 16 is not provided above the insulator 14b. That is, all the semiconductor elements 16 included in the semiconductor device 1 are not included in the laminate LS2.

[0038] As shown in FIG. 4, the laminate LS3 includes a conductor 12c, a conductor 13c, an insulator 14c, and a conductor 15c. The conductor 12c is provided on the upper surface of the conductor 10. The conductor 12c includes, for example, solder. The conductor 13c is provided on the upper surface of the conductor 12c. The conductor 13c includes, for example, copper (Cu). The insulator 14c is provided on the upper surface of the conductor 13c. The insulator 14c is an insulating substrate including insulating ceramics such as aluminum nitride (AlN) and silicon nitride (SiN). The conductor 15c is provided on the upper surface of the insulator 14c. The conductor 15c includes, for example, copper (Cu). Note that the semiconductor element 16 is not provided above the insulator 14c. That is, all the semiconductor elements 16 included in the semiconductor device 1 are not included in the laminate LS3.

[0039] The laminates LS2 and LS3 are disposed between the laminate LS1 and the insulator 11. That is, the laminates LS2 and LS3 are disposed closer to the insulator 11 (outside) than the laminate LS1 when viewed in the up-down direction.

[0040] The conductors 17-1, 17-2, 18-1, and 18-2 are, for example, flat-plate shaped conductive materials containing copper (Cu). The conductors 17-1, 17-2, 18-1, and 18-2 are, for example, formed by bending a flat plate having a substantially uniform thickness. The thickness of the conductors 17-1, 17-2, 18-1, and 18-2 is designed to be, for example, in the range of 0.4 mm to 4.0 mm.

[0041] The conductor 17-1 has a first end joined onto the upper surface of the conductor 15a-1 and a second end joined onto the upper surface of the conductor 15b. The conductor 18-1 has a first end joined onto the upper surface of the first end of the conductor 17-1 and a second end disposed on the upper surface of the insulator 11 and functioning as a terminal T. The first end of the conductor 17-1 is electrically connected to the semiconductor element 16 via the conductor 15a-1 and is electrically connected to the terminal T via the conductor 18-1. The second end of the conductor 17-1 is connected to the insulator 14b via the conductor 15b. Thus, the conductor 17-1 functions as a heat dissipation path that dissipates heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the insulator 14b.

[0042] The conductor 17-2 has a first end joined onto the upper surface of the conductor 15a-2 and a second end joined onto the upper surface of the conductor 15c. The conductor 18-2 has a first end joined onto the upper surface of the first end of the conductor 17-2 and a second end disposed on the upper surface of the insulator 11 and functioning as a terminal T. The first end of the conductor 17-2 is electrically connected to the semiconductor element 16 via the conductors 15a-2 and 19, and is also electrically connected to the terminal T via the conductor 18-2. The second end of the conductor 17-2 is connected to the insulator 14c via the conductor 15c. Thus, the conductor 17-2 functions as a heat dissipation path that dissipates heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the insulator 14c.

[0043] The first end of the conductor 17-1 and the conductor 15a-1, the second end of the conductor 17-1 and the conductor 15b, the first end of the conductor 17-2 and the conductor 15a-2, and the second end of the conductor 17-2 and the conductor 15c are bonded, for example, by ultrasonic bonding. Similarly, the first end of the conductor 18-1 and the first end of the conductor 17-1, and the first end of the conductor 18-2 and the first end of the conductor 17-2 are bonded, for example, by ultrasonic bonding. In this case, indentations having fine irregularities like a knurled shape are formed on the upper surfaces of the first and second ends of the conductor 17-1, the first and second ends of the conductor 17-2, the first end of the conductor 18-1, and the first end of the conductor 18-2.

[0044] The second end of the conductor 18-1 and the second end of the conductor 18-2 are each connected to an external device via, for example, a screw hole (not shown). The type of the terminal T corresponding to the second end of the conductor 18-1 and the second end of the conductor 18-2 may be any of the terminals T_P, T_N, T_AC, and T_S. When the semiconductor element 16 is a transistor TR_up, the second end of the conductor 18-1 and the second end of the conductor 18-2 may be the terminal T_P, and the terminal T_AC, T_S1, or T_S3, respectively. When the semiconductor element 16 is a transistor TR_low, the second end of the conductor 18-1 and the second end of the conductor 18-2 may be the terminal T_AC or T_S4, and the terminal T_N or T_S2, respectively.

[0045] The width of the portion between the first and second ends of conductor 17-1 in the depth direction of the page is preferably designed to be longer than the width of the portion between the first and second ends of conductor 18-1 in the depth direction of the page, for example, by 0.5 mm or more. In this case, when the inside of semiconductor device 1 is looked down from above, a part of conductor 17-1 can be seen without being hidden by conductor 18-1.

[0046] Similarly, the width of the portion between the first and second ends of conductor 17-2 in the depth direction of the page is preferably designed to be longer than the width of the portion between the first and second ends of conductor 18-2 in the depth direction of the page, for example, by 0.5 mm or more. In this case, when the inside of semiconductor device 1 is looked down from above, a part of conductor 17-2 can be seen without being hidden by conductor 18-2.

[0047] The internal structure of the semiconductor device 1 configured as above is sealed by the insulator 20, except for the portions of the conductors 18-1 and 18-2 that function as terminals T. The insulator 20 has the function of physically and electrically protecting the internal structure of the semiconductor device 1 from the outside of the semiconductor device 1.

[0048] According to the first embodiment, it is possible to suppress an increase in temperature of the semiconductor device 1. This effect will be described below.

[0049] The insulators 14a, 14b, and 14c are provided on the upper surface of the conductor 10 at a distance from each other. The conductors 15a-1 and 15a-2 are provided on the upper surface of the insulator 14a. The conductors 15b and 15c are provided on the upper surfaces of the insulators 14b and 14c, respectively. The conductor 17-1 has a first end in contact with the conductor 15a-1 and a second end in contact with the conductor 15b. The conductor 17-2 has a first end in contact with the conductor 15a-2 and a second end in contact with the conductor 15c. The semiconductor element 16 is electrically connected to the conductors 17-1 and 17-2. As a result, the conductors 17-1 and 17-2 can form a heat dissipation path that dissipates heat generated in the semiconductor element 16 to the conductor 10 via the laminates LS2 and LS3, respectively. Therefore, the temperature rise of the stacked body LS1 including the semiconductor element 16 can be suppressed.

[0050] Moreover, the conductor 18-1 has a first end in contact with the first end of the conductor 17-1, and a second end located on the upper surface of the insulator 11 and functioning as a terminal T. The conductor 18-2 has a first end in contact with the first end of the conductor 17-2, and a second end located on the upper surface of the insulator 11 and functioning as a terminal T. This allows the conductors 17-1 and 17-2 to form heat dissipation paths that dissipate heat flowing into the terminal T to the conductor 10 via the laminates LS2 and LS3, respectively. This makes it possible to suppress a rise in temperature of the terminal T.

[0051] Supplementally, the external shape of the semiconductor device 1 is standardized for the purpose of improving user convenience. This requires that the current capacity of the semiconductor device 1 be increased to a certain extent within the range of the standard. The more the current capacity increases, the more heat flows into the laminate LS1 including the semiconductor element 16 and into the terminal T.

[0052] According to the first embodiment, the laminate LS1 and the terminal T are connected to the laminate LS2 and the laminate LS3, respectively, via the conductors 17-1 and 17-2. The laminates LS2 and LS3 do not include a semiconductor element 16. This allows the laminates LS2 and LS3 to function as a heat dissipation mechanism that suppresses a temperature rise in the laminate LS1 and the terminal T without becoming a heat source themselves.

[0053] The conductors 17-1, 17-2, 18-1, and 18-2 each contain copper (Cu) as an equivalent material. This prevents mismatching of the thermal expansion coefficients of the joints caused by temperature rise. The conductors 17-1, 17-2, 18-1, and 18-2 are ultrasonically bonded. This prevents deterioration of the strength of the joints caused by temperature rise, more than when they are connected via solder, for example.

[0054] 2. Second embodiment Next, a semiconductor device according to a second embodiment will be described.

[0055] The second embodiment differs from the first embodiment in that the bus bar forming the heat dissipation path is integrally formed with the bus bar functioning as the terminal T. The following mainly describes the configuration different from the first embodiment. Descriptions of the same configuration as the first embodiment will be omitted as appropriate.

[0056] Fig. 5 is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the second embodiment. Fig. 6 is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the second embodiment. Figs. 5 and 6 correspond to Figs. 3 and 4 in the first embodiment, respectively.

[0057] The semiconductor device 1A according to the second embodiment includes conductors 18A-1 and 18A-2 instead of the conductors 17-1 and 18-1, and the conductors 17-2 and 18-2, respectively. The configuration of the semiconductor device 1A, excluding the conductors 18A-1 and 18A-2, is equivalent to the corresponding configuration of the semiconductor device 1 according to the first embodiment.

[0058] The conductors 18A-1 and 18A-2 are, for example, flat-plate conductive materials containing copper (Cu). The conductors 18A-1 and 18A-2 are, for example, formed by bending a flat plate having a substantially uniform thickness. The thickness of the conductors 18A-1 and 18A-2 is designed to be, for example, in the range of 0.4 mm to 4.0 mm.

[0059] Conductor 18A-1 has a first end joined onto the upper surface of conductor 15a-1, a second end located on the upper surface of insulator 11 and functioning as terminal T, and a central portion located between the first and second ends and joined onto the upper surface of conductor 15b. Thus, conductor 18A-1 functions as a heat dissipation path that dissipates heat transferred from semiconductor element 16 to insulator 14a and terminal T to conductor 10 via insulator 14b.

[0060] Conductor 18A-2 has a first end joined onto the upper surface of conductor 15a-2, a second end located on the upper surface of insulator 11 and functioning as terminal T, and a central portion located between the first and second ends and joined onto the upper surface of conductor 15c. Thus, conductor 18A-2 functions as a heat dissipation path that dissipates heat transferred from semiconductor element 16 to insulator 14a and terminal T to conductor 10 via insulator 14c.

[0061] The first end of conductor 18A-1 and conductor 15a-1, and the central portion of conductor 18A-1 and conductor 15b are joined by, for example, ultrasonic bonding. Similarly, the first end of conductor 18A-2 and conductor 15a-2, and the central portion of conductor 18A-2 and conductor 15c are joined by, for example, ultrasonic bonding. In this case, indentations having fine irregularities like a knurled pattern are formed on the upper surfaces of the first end and central portion of conductor 18A-1 and the first end and central portion of conductor 18A-2.

[0062] The internal structure of the semiconductor device 1 configured as above is sealed with an insulator 20, except for the portions of the conductors 18A-1 and 18A-2 that function as terminals T.

[0063] According to the second embodiment, the conductor 18A-1 has a first end in contact with the conductor 15a-1, a second end located on the upper surface of the insulator 11 and functioning as the terminal T, and a central portion located between the first and second ends and in contact with the conductor 15b. The conductor 18A-2 has a first end in contact with the conductor 15a-2, a second end located on the upper surface of the insulator 11 and functioning as the terminal T, and a central portion located between the first and second ends and in contact with the conductor 15c. As a result, the conductors 18A-1 and 18A-2 function as a heat dissipation path that dissipates heat flowing into the terminal T and the laminate LS1 to the conductor 10 via the laminates LS2 and LS3, and can also function as a current path between the terminal T and the semiconductor element 16.

[0064] 3. Third embodiment Next, a semiconductor device according to a third embodiment will be described.

[0065] The third embodiment differs from the first and second embodiments in that a heat dissipation path is formed inside the case CS. The following mainly describes the configurations that differ from the first and second embodiments. Descriptions of the configurations that are the same as the first and second embodiments will be omitted as appropriate.

[0066] Fig. 7 is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the third embodiment. Fig. 8 is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the third embodiment. Figs. 7 and 8 correspond to Figs. 3 and 4 in the first embodiment, respectively.

[0067] The semiconductor device 1B according to the third embodiment includes conductors 17B-1 and 17B-2 instead of the conductors 17-1 and 18-1, and the conductors 17-2 and 18-2, respectively. The semiconductor device 1B according to the third embodiment also includes an insulator 11B, a stack LS4, and a stack LS5 instead of the insulator 11, the stack LS2, and the stack LS3, respectively. The configurations of the semiconductor device 1B, excluding the conductors 17B-1 and 17B-2, the insulator 11B, the stack LS4, and the stack LS5, are equivalent to the corresponding configurations of the semiconductor device 1 according to the first embodiment.

[0068] An insulator 11B corresponding to the case CS is provided on the upper surface of the conductor 10. The insulator 11B includes, for example, PPC. A plurality of spaces are formed in a part of the insulator 11B, penetrating from the lower end to the upper end.

[0069] The conductor 17B-1 has a first end joined onto the upper surface of the conductor 15a-1 and a second end located on the upper surface of the insulator 11B and functioning as a terminal T.

[0070] The conductor 17B-2 has a first end joined onto the upper surface of the conductor 15a-2 and a second end located on the upper surface of the insulator 11B and functioning as a terminal T.

[0071] The internal structure of the semiconductor device 1B configured as above is sealed with an insulator 20, except for the portions of the conductors 17B-1 and 17B-2 that function as terminals T.

[0072] 7, a laminate LS4 is provided in the internal space of the insulator 11B formed below the conductor 17B-1. The laminate LS4 includes an insulator 21b and a conductor 22b. The insulator 21b is, for example, a flat insulating sheet, and includes a material different from an insulating substrate such as the insulator 14a. The conductor 22b includes, for example, copper (Cu).

[0073] The upper surface of the conductor 22b contacts the lower surface of the second end of the conductor 17B-1 functioning as the terminal T. The lower surface of the conductor 22b contacts the upper surface of the insulator 21b. The lower surface of the insulator 21b contacts the upper surface of the conductor 10. The insulator 21b electrically insulates the conductor 10 from the conductor 22b. Thus, the conductor 17B-1 functions as a heat dissipation path that dissipates heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the conductor 22b and the insulator 21b.

[0074] As shown in Fig. 8, a laminate LS5 is provided in the internal space of the insulator 11B formed below the conductor 17B-2. The laminate LS5 includes an insulator 21c and a conductor 22c. The conductor 22c is provided away from the conductor 22b via the insulator 11B. This electrically insulates the conductors 22b and 22c. The insulator 21c is, for example, a flat insulating sheet, and includes a material different from an insulating substrate such as the insulator 14a. The conductor 22c includes, for example, copper (Cu).

[0075] The upper surface of the conductor 22c contacts the lower surface of the second end of the conductor 17B-2 functioning as the terminal T. The lower surface of the conductor 22c contacts the upper surface of the insulator 21c. The lower surface of the insulator 21c contacts the upper surface of the conductor 10. The insulator 21c electrically insulates the conductor 10 from the conductor 22c. Thus, the conductor 17B-2 functions as a heat dissipation path that dissipates heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the conductor 22c and the insulator 21c.

[0076] The first end of conductor 17B-1 and conductor 15a-1, the second end of conductor 17B-1 and conductor 22b, the first end of conductor 17B-2 and conductor 15a-2, and the second end of conductor 17B-2 and conductor 22c are bonded by ultrasonic bonding, for example. In this case, indentations having fine irregularities like a knurled pattern are formed on the upper surfaces of the first and second ends of conductor 17B-1 and the first and second ends of conductor 17B-2.

[0077] According to the third embodiment, the insulator 21b and the conductor 22b, as well as the insulator 21c and the conductor 22c, are provided in the space within the insulator 11B. The conductor 17B-1 has a first end in contact with the conductor 15a-1 and a second end in contact with the conductor 22b and located on the upper surface of the insulator 11B to function as the terminal T. The conductor 17B-2 has a first end in contact with the conductor 15a-2 and a second end in contact with the conductor 22c and located on the upper surface of the insulator 11B to function as the terminal T. As a result, the conductors 17B-1 and 17B-2 function as a heat dissipation path that dissipates heat flowing into the terminal T and the laminate LS1 to the conductor 10 via the conductors 22b and 22c, and can also function as a current path between the terminal T and the semiconductor element 16. Furthermore, since the heat dissipation path can be formed in the space within the insulator 11B, restrictions on the layout of the internal structure of the semiconductor device 1B can be alleviated compared to the case where the heat dissipation path is formed inside the insulator 11B.

[0078] 4. Fourth embodiment Next, a semiconductor device according to a fourth embodiment will be described.

[0079] The fourth embodiment differs from the third embodiment in that the conductor provided inside the case CS and the bus bar that electrically connects the semiconductor element 16 and the terminal T are integrally formed. The following mainly describes the configuration that differs from the third embodiment. Descriptions of the same configuration as the third embodiment will be omitted as appropriate.

[0080] Fig. 9 is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the fourth embodiment. Fig. 10 is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the fourth embodiment. Figs. 9 and 10 correspond to Figs. 7 and 8 in the third embodiment, respectively.

[0081] The semiconductor device 1C according to the fourth embodiment includes an insulator 11C, a conductor 23b, and a conductor 23c instead of the insulator 11B, the conductors 17B-1 and 22b, and the conductors 17B-2 and 22c, respectively. The configuration of the semiconductor device 1C, except for the insulator 11C, the conductor 23b, and the conductor 23c, is the same as the corresponding configuration of the semiconductor device 1B according to the third embodiment.

[0082] An insulator 11C corresponding to the case CS is provided on the upper surface of the conductor 10. The insulator 11C includes, for example, PPC. A part of the insulator 11C is formed with a plurality of spaces penetrating from the lower end to the upper end. Each space is connected to the internal space of the semiconductor device 1C via a hole formed on the inner side surface of the insulator 11C.

[0083] As shown in FIG. 9, the conductor 23b includes a busbar portion located in the internal space of the semiconductor device 1C, a heat dissipation portion located inside the insulator 11C, and a terminal portion located on the upper surface of the insulator 11C. The busbar portion of the conductor 23b has a first end joined to the upper surface of the conductor 15a-1 and a second end connected to the heat dissipation portion of the conductor 23b through a hole formed in the inner side surface of the insulator 11C. The heat dissipation portion of the conductor 23b has a lower surface in contact with the upper surface of the insulator 21b. The terminal portion of the conductor 23b is located above the heat dissipation portion of the conductor 23b and functions as a terminal T. Thus, the conductor 23b functions as a heat dissipation path that dissipates heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the insulator 21b.

[0084] As shown in FIG. 10, the conductor 23c includes a busbar portion located in the internal space of the semiconductor device 1C, a heat dissipation portion located inside the insulator 11C, and a terminal portion located on the upper surface of the insulator 11C. The busbar portion of the conductor 23c has a first end joined to the upper surface of the conductor 15a-2 and a second end connected to the heat dissipation portion of the conductor 23c through a hole formed in the inner side surface of the insulator 11C. The heat dissipation portion of the conductor 23c has a lower surface in contact with the upper surface of the insulator 21c. The terminal portion of the conductor 23c is located above the heat dissipation portion of the conductor 23c and functions as a terminal T. Thus, the conductor 23c functions as a heat dissipation path that dissipates heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the insulator 21c.

[0085] The first end of the busbar portion of conductor 23b is joined to conductor 15a-1, and the first end of the busbar portion of conductor 23c is joined to conductor 15a-2, for example, by ultrasonic bonding. In this case, indentations having fine irregularities like a knurled pattern are formed on the upper surface of each of the first ends of the busbar portion of conductor 23b and the first ends of the busbar portion of conductor 23c.

[0086] According to the fourth embodiment, each of the conductors 23b and 23c includes a heat dissipation portion, a busbar portion, and a terminal portion. The heat dissipation portion of the conductor 23b and the heat dissipation portion of the conductor 23c are provided in the space within the insulator 11C. The busbar portion of the conductor 23b has a first end that contacts the conductor 15a-1 and a second end that is connected to the heat dissipation portion of the conductor 23b. The busbar portion of the conductor 23c has a first end that contacts the conductor 15a-2 and a second end that is connected to the heat dissipation portion of the conductor 23c. The terminal portion of the conductor 23b and the terminal portion of the conductor 23c are located on the upper surface of the insulator 11C and function as a terminal T. As a result, the conductors 23b and 23c can function as a heat dissipation path that dissipates heat flowing into the terminal T and the laminate LS1 to the conductor 10 via the insulators 21b and 21c, and can also function as a current path between the terminal T and the semiconductor element 16.

[0087] 5. Fifth embodiment Next, a semiconductor device according to a fifth embodiment will be described.

[0088] The fifth embodiment differs from the fourth embodiment in that a laminate including an insulating substrate is formed inside the case CS. The following mainly describes the configuration different from the fourth embodiment. The description of the configuration equivalent to the fourth embodiment will be omitted as appropriate.

[0089] Fig. 11 is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the fifth embodiment. Fig. 12 is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the fifth embodiment. Figs. 11 and 12 correspond to Figs. 9 and 10 in the fourth embodiment, respectively.

[0090] The semiconductor device 1D according to the fifth embodiment includes an insulator 11D, a stack LS6, and a stack LS7 instead of the insulator 11C, the stack LS4, and the stack LS5, respectively. The configuration of the semiconductor device 1D except for the insulator 11D, the stack LS6, and the stack LS7 is the same as the corresponding configuration of the semiconductor device 1C according to the fourth embodiment.

[0091] An insulator 11D corresponding to the case CS is provided on the upper surface of the conductor 10. The insulator 11D includes, for example, PPC. A part of the insulator 11D is formed with a plurality of spaces penetrating from the lower end to the upper end. Each space is connected to the internal space of the semiconductor device 1D via a hole formed on the inner side surface of the insulator 11D.

[0092] As shown in FIG. 11, the laminate LS6 includes a conductor 12d, a conductor 13d, an insulator 14d, a conductor 15d, and a conductor 23d. The conductor 12d is provided inside the insulator 11D on the upper surface of the conductor 10. The conductor 12d includes, for example, solder. The conductor 13d is provided on the upper surface of the conductor 12d. The conductor 13d includes, for example, copper (Cu). The insulator 14d is provided on the upper surface of the conductor 13d. The insulator 14d is, for example, an insulating substrate including insulating ceramics such as aluminum nitride (AlN) and silicon nitride (SiN). The conductor 15d is provided on the upper surface of the insulator 14d. The conductor 15d includes, for example, copper (Cu).

[0093] The conductor 23d includes a busbar portion located in the internal space of the semiconductor device 1D, a heat dissipation portion located inside the insulator 11D, and a terminal portion located on the upper surface of the insulator 11D. The busbar portion of the conductor 23d has a first end joined to the upper surface of the conductor 15a-1 and a second end connected to the heat dissipation portion of the conductor 23d through a hole formed in the inner side surface of the insulator 11D. The heat dissipation portion of the conductor 23d has a lower surface in contact with the upper surface of the conductor 15d. The terminal portion of the conductor 23d is located above the heat dissipation portion of the conductor 23d and functions as a terminal T. Thus, the conductor 23d functions as a heat dissipation path that dissipates heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the laminate LS4.

[0094] As shown in FIG. 12, the laminate LS7 includes a conductor 12e, a conductor 13e, an insulator 14e, a conductor 15e, and a conductor 23e. The conductor 12e is provided inside the insulator 11D on the upper surface of the conductor 10. The conductor 12e includes, for example, solder. The conductor 13e is provided on the upper surface of the conductor 12e. The conductor 13e includes, for example, copper (Cu). The insulator 14e is provided on the upper surface of the conductor 13e. The insulator 14e is, for example, an insulating substrate including insulating ceramics such as aluminum nitride (AlN) and silicon nitride (SiN). The conductor 15e is provided on the upper surface of the insulator 14e. The conductor 15e includes, for example, copper (Cu).

[0095] The conductor 23e includes a busbar portion located in the internal space of the semiconductor device 1D, a heat dissipation portion located inside the insulator 11D, and a terminal portion located on the upper surface of the insulator 11D. The busbar portion of the conductor 23e has a first end joined to the upper surface of the conductor 15a-2 and a second end connected to the heat dissipation portion of the conductor 23e through a hole formed in the inner side surface of the insulator 11D. The heat dissipation portion of the conductor 23e has a lower surface in contact with the upper surface of the conductor 15e. The terminal portion of the conductor 23e is located above the heat dissipation portion of the conductor 23e and functions as a terminal T. Thus, the conductor 23e functions as a heat dissipation path that dissipates heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the laminate LS5.

[0096] According to the fifth embodiment, the conductor 12d includes solder and joins the laminate LS6 including the insulator 14d to the conductor 10 in the space within the insulator 11D. The conductor 12e includes solder and joins the laminate LS7 including the insulator 14e to the conductor 10 inside the insulator 11D. This can improve the bonding strength between the laminates LS6 and LS7 and the conductor 10.

[0097] Each of the conductors 23d and 23e includes a heat dissipation portion, a busbar portion, and a terminal portion. The heat dissipation portion of the conductor 23d and the heat dissipation portion of the conductor 23e are provided in the space within the insulator 11D. The busbar portion of the conductor 23d has a first end that contacts the conductor 15a-1 and a second end that is connected to the heat dissipation portion of the conductor 23d. The busbar portion of the conductor 23e has a first end that contacts the conductor 15a-2 and a second end that is connected to the heat dissipation portion of the conductor 23e. The terminal portion of the conductor 23d and the terminal portion of the conductor 23e are located on the upper surface of the insulator 11D and function as a terminal T. As a result, the conductors 23d and 23e can function as a heat dissipation path that dissipates heat flowing into the terminal T and the laminate LS1 to the conductor 10 via the laminates LS6 and LS7, and can also function as a current path between the terminal T and the semiconductor element 16.

[0098] 6. Modifications The first, second, third, fourth and fifth embodiments are not limited to the above-mentioned examples, and various modifications may be applied.

[0099] For example, in the above-described first, fourth, and fifth embodiments, the heat dissipation path suppresses the temperature rise of both the laminate LS1 and the terminal T, but this is not limited to the above. The heat dissipation path that suppresses the temperature rise of the laminate LS1 may be provided separately from the heat dissipation path that suppresses the temperature rise of the terminal T.

[0100] Fig. 13 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to Modification 1. Fig. 13 corresponds to Fig. 3 in the first embodiment.

[0101] 13, in the semiconductor device 1' according to the first modification, the conductor 17-1 may be provided apart from the conductor 18-1. In this case, the conductor 17-1 and the stacked body LS2 connected to the conductor 17-1 mainly contribute to suppressing the temperature rise of the stacked body LS1.

[0102] Fig. 14 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to Modification 2. Fig. 14 corresponds to Fig. 9 in the fourth embodiment.

[0103] 14, in the semiconductor device 1C' according to the second modification, the conductor 23b' has a bus bar portion and a heat dissipation portion, but may not have a terminal portion. In this case, the conductor 23b' and the insulator 21b connected to the conductor 23b' mainly contribute to suppressing the temperature rise of the laminate LS1.

[0104] Fig. 15 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to Modification 3. Fig. 15 corresponds to Fig. 11 in the fifth embodiment.

[0105] 15, in a semiconductor device 1D' according to a third modification, a conductor 23d' has a bus bar portion and a heat dissipation portion, but may not have a terminal portion. In this case, the conductor 23d' and the multilayer body LS6 connected to the conductor 23d' mainly contribute to suppressing a temperature rise in the multilayer body LS1.

[0106] In addition, in the above-mentioned first, second, third, fourth and fifth embodiments, the bus bars are ultrasonically joined, but the present invention is not limited to this. For example, the bus bars may be joined using solder or a sintered material.

[0107] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0108] 1...Semiconductor device 10, 12, 13, 15, 17, 19, 22, 23...Conductors 11, 14, 20, 21...Insulators 16...Semiconductor element BS: Base board CS…Case CV…lid T…Terminal TR…Transistor LS…Laminate

Claims

1. A base substrate; a case provided on an upper surface of the base substrate; a first laminate provided on an upper surface of the base substrate and inside the case; a second stack provided on an upper surface of the base substrate and spaced apart from the first stack; a first conductor having a flat plate shape and including a first portion in contact with the first laminate and a second portion in contact with the second laminate; Equipped with the first stack includes a first insulator, a second conductor provided on an upper surface of the first insulator and in contact with the first portion of the first conductor, and a first semiconductor element electrically connected to the second conductor, the second stack includes a second insulator and a third conductor provided on an upper surface of the second insulator and in contact with the second portion of the first conductor, and does not include a semiconductor element. Semiconductor device.

2. The second stack is located between the first stack and the case. The semiconductor device according to claim 1.

3. a fourth conductor having a third portion in contact with the first portion of the first conductor and a fourth portion located on the upper surface of the case and functioning as a terminal; 3. The semiconductor device according to claim 2.

4. The first conductor further has a fifth portion located on the upper surface of the case and functioning as a terminal.

3. The semiconductor device according to claim 2.

5. The second laminate is located inside the case. The semiconductor device according to claim 1.

6. the second portion of the first conductor is located on a top surface of the case and functions as a terminal; 6. The semiconductor device according to claim 5.

7. the second portion of the first conductor passes through an inner surface of the case and comes into contact with the third conductor; The first conductor and the third conductor are one continuous member.

6. The semiconductor device according to claim 5.

8. the material of the second insulator is different from the material of the first insulator; 8. The semiconductor device according to claim 7.

9. The material of the second insulator is substantially equal to the material of the first insulator.

8. The semiconductor device according to claim 7.

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