Semiconductor device and manufacturing method for the same

Abstract

To improve the performance of a semiconductor device that includes a resistance element made of silicon, chromium, and carbon.SOLUTION: The semiconductor device has an insulating film IL1, a resistive element RS disposed on the insulating film IL1, and an insulating film IL2 disposed on the resistive element RS. The resistive element RS contains silicon, chromium, and carbon. The silicon concentration of the resistive element RS increases from the center of the resistive element RS towards the top surface of the resistive element RS and also increases from the center of the resistive element RS towards the bottom surface of the resistive element RS.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably used, for example, in a semiconductor device including a resistance element and a manufacturing method thereof. [Background technology]

[0002] Japanese Patent Application Publication No. 2023-56630 (Patent Document 1) and Japanese Patent Application Publication No. 2023-58091 (Patent Document 2) describe semiconductor devices including a resistance element containing silicon, chromium, and carbon. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-56630 A [Patent Document 2] JP 2023-58091 A Summary of the Invention [Problem to be solved by the invention]

[0004] It is desirable to improve the performance of semiconductor devices that include resistive elements that contain silicon, chromium, and carbon.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device includes a first insulating film, a resistive element disposed on the first insulating film, and a second insulating film disposed on the resistive element. The resistive element includes silicon, chromium, and carbon. The silicon concentration of the resistive element increases from a center portion of the resistive element toward a top surface of the resistive element, and increases from the center portion of the resistive element toward a bottom surface of the resistive element. Effect of the Invention

[0007] According to one embodiment, the performance of a semiconductor device can be improved. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view of a main part of the semiconductor device in the manufacturing process of the first embodiment. FIG. [Diagram 3] 3 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 2; [Figure 4] 4 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 3. [Diagram 5] 5 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 4. [Figure 6] 6 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 5. [Figure 7] 7 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 6. [Figure 8] 8 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 7. [Figure 9] 9 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 8. [Figure 10] 10 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. [Figure 11] 11 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 10. [Figure 12] 12 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 11. [Figure 13] 13 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 12. [Figure 14] 1 is a graph showing the resistivity and temperature coefficient of resistance of a Si—Cr—C resistor element. [Figure 15] 1 is a graph showing the relationship between annealing temperature, resistivity, and temperature coefficient of resistance. [Figure 16] FIG. 2 is a partially enlarged cross-sectional view of the semiconductor device of the study example. [Figure 17] FIG. 2 is a partially enlarged cross-sectional view of the semiconductor device of the study example. [Figure 18] FIG. 2 is a partially enlarged cross-sectional view of FIG. [Figure 19] 19 is a graph showing the concentration distributions of silicon, chromium, and carbon in the layered structure shown in FIG. 18. [Figure 20] 11 is a graph showing the results of analyzing the concentration distribution of silicon, chromium, and carbon in the case where crystallization annealing treatment was not performed. [Figure 21] 1 is a graph showing the correlation between annealing temperature and temperature coefficient of resistance. [Figure 22] FIG. 2 is a plan view of a resistance element. [Diagram 23] FIG. 2 is a cross-sectional view of a resistance element. [Figure 24] 1 is a graph showing the correlation between the width and resistance value of a resistive element. [Diagram 25] 1 is a graph showing the correlation between the width of a resistor element and the temperature coefficient of resistance. [Figure 26] FIG. 13 is a plan view of a resistance element according to a modified example. [Figure 27] FIG. 11 is a cross-sectional view of a resistance element according to a modified example. [Figure 28] FIG. 11 is a cross-sectional view of a resistance element according to a modified example. [Figure 29] 11 is a cross-sectional view of a main part of a semiconductor device in a manufacturing process according to a second embodiment. FIG. [Diagram 30] 29 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process, continued from FIG. 29. [Diagram 31] 31 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 30. [Diagram 32] 32 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 31. [Diagram 33] 33 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 32. [Diagram 34] FIG. 2 is a cross-sectional view of a resistance element. [Diagram 35] 1 is a graph showing the carbon content and temperature coefficient of resistance of a resistor element. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. In addition, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, except when specifically specified or when it is clearly limited to a specific number in principle, and it may be more than or less than the specific number. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, except when specifically specified or when it is clearly considered to be essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of the components, etc. are mentioned, it includes those that are substantially similar to or similar to the shape, etc., except when specifically specified or when it is clearly considered not to be essential in principle. This also applies to the above numerical values ​​and ranges.

[0010] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations will be omitted. In the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0011] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views in order to make the drawings easier to understand, and hatching may be added even in plan views in order to make the drawings easier to understand.

[0012] (Embodiment 1) <About the structure of semiconductor device> The semiconductor device of the present embodiment will be described with reference to the drawings, in which: Fig. 1 is a cross-sectional view of a main part of the semiconductor device of the present embodiment;

[0013] As shown in FIG. 1, the semiconductor device of this embodiment has a semiconductor substrate SB, insulating films IL1, IL2, and IL3, a plurality of wirings M1, a plurality of wirings M2, a plurality of plugs V1, a plurality of plugs V2, and a resistive element RS.

[0014] The insulating film IL1 is formed on the main surface of the semiconductor substrate SB. The multiple wirings M1 are formed on the insulating film IL1 so as to be in contact with the upper surface of the insulating film IL1. The insulating film IL2 is formed on the insulating film IL1 so as to cover the multiple wirings M1. The resistor element RS is formed on the insulating film IL2 so as to be in contact with the upper surface of the insulating film IL2. The insulating film IL3 is formed on the insulating film IL2 so as to cover the resistor element RS. The upper surface and side surfaces of the resistor element RS are in contact with the insulating film IL3. The lower surface of the resistor element RS is in contact with the insulating film IL2.

[0015] The multiple wirings M2 are formed on the insulating film IL3 so as to be in contact with an upper surface of the insulating film IL3. The multiple plugs V1 are each conductive. The multiple plugs V2 are each conductive. The multiple plugs V1 are each disposed in the insulating film IL2. Specifically, the multiple plugs V1 are each embedded in an opening penetrating the insulating film IL2. The multiple plugs V2 are each embedded in an opening penetrating the insulating films IL2 and IL3.

[0016] Each of the insulating films IL1, IL2, and IL3 is a single-layer insulating film or a multi-layer insulating film in which a plurality of insulating films are stacked.

[0017] The resistor element RS contains silicon (Si), chromium (Cr), and carbon (C) as constituent elements. Specifically, the resistor element RS is made of a material layer (resistance layer) MT containing silicon (Si), chromium (Cr), and carbon (C) as constituent elements. The planar shape of the material layer MT is, for example, rectangular. The thickness of the material layer MT is preferably 10 nm or less, and more preferably 2 nm or more and 10 nm or less.

[0018] The multiple plugs V1 include plugs V1a and V1b. The multiple plugs V2 include plugs V2a and V2b. The multiple wirings M1 include wirings M1a and M1b. The multiple wirings M2 include wirings M2a and M2b. The wirings M1a and M1b are spaced apart from each other. The wirings M2a and M2b are spaced apart from each other.

[0019] The wirings M1a and M1b are disposed on the insulating film IL1 so as to be covered with the insulating film IL2. The plug V1a is disposed in the insulating film IL2 and is connected to the wiring M1a. The plug V1b is disposed in the insulating film IL2 and is connected to the wiring M1b. The resistor element RS connects the plug V1a and the plug V1b.

[0020] Specifically, in the vicinity of one end of the material layer MT, the upper surface of the plug V1a is covered with the material layer MT and is in contact with the lower surface of the material layer MT. The plug V1a is electrically connected to the material layer MT. The plug V1a is disposed on the wiring M1a, and the lower surface of the plug V1a is in contact with the upper surface of the wiring M1a. The plug V1a is electrically connected to the wiring M1a.

[0021] The plug V2a is disposed on the wiring M1a, and the lower surface of the plug V2a is in contact with the upper surface of the wiring M1a. The plug V2a is electrically connected to the wiring M1a. The upper surface of the plug V2a is covered with the wiring M2a and in contact with the lower surface of the wiring M2a. The plug V2a is electrically connected to the wiring M2a.

[0022] In the vicinity of the other end of the material layer MT, the upper surface of the plug V1b is covered with the material layer MT and is in contact with the lower surface of the material layer MT. The plug V1b is electrically connected to the material layer MT. The plug V1b is disposed on the wiring M1b, and the lower surface of the plug V1b is in contact with the upper surface of the wiring M1b. The plug V1b is electrically connected to the wiring M1b.

[0023] The plug V2b is disposed on the wiring M1b, and the lower surface of the plug V2b is in contact with the upper surface of the wiring M1b. The plug V2b is electrically connected to the wiring M1b. The upper surface of the plug V2b is covered with the wiring M2b and in contact with the lower surface of the wiring M2b. The plug V2b is electrically connected to the wiring M2b.

[0024] Therefore, a plug V1a is connected to one end of the resistor RS, and a plug V1b is connected to the other end of the resistor RS. The wiring M2a is electrically connected to one end of the resistor RS via the plug V2a, the wiring M1a, and the plug V1a. The wiring M2b is electrically connected to the other end of the resistor RS via the plug V2b, the wiring M1b, and the plug V1b.

[0025] The illustration and description of the structure above the insulating film IL3 and the wiring M2 will be omitted.

[0026] <About the manufacturing process of semiconductor devices> The manufacturing process of the semiconductor device of this embodiment will be described with reference to the drawings. Figures 2 to 13 are cross-sectional views of the main part of the semiconductor device during the manufacturing process of this embodiment.

[0027] First, a semiconductor substrate SB is prepared as shown in Fig. 2. The semiconductor substrate SB is made of single crystal silicon or the like doped with p-type or n-type impurities.

[0028] Next, if necessary, a semiconductor element (not shown) such as a metal insulator semiconductor field effect transistor (MISFET) or a diode is formed on the semiconductor substrate SB.

[0029] 3, an insulating film IL1 is formed on the main surface of the semiconductor substrate SB. The insulating film IL1 is an interlayer insulating film. The insulating film IL1 is made of, for example, a silicon oxide film, and can be formed by using a CVD (Chemical Vapor Deposition) method or the like. After the insulating film IL1 is formed, the upper surface of the insulating film IL1 can be planarized by a CMP (Chemical Mechanical Polishing) method or the like.

[0030] Next, as shown in FIG. 3, a plurality of wirings M1 are formed on the insulating film IL1. For example, a conductive film is formed on the insulating film IL1. Then, the conductive film is patterned using photolithography and etching techniques to form a plurality of wirings M1 made of the conductive film. The plurality of wirings M1 are, for example, aluminum wirings, but wirings using other metal materials can also be applied. The plurality of wirings M1 include wirings M1a and wirings M1b.

[0031] 4, an insulating film IL2 is formed on the insulating film IL1 so as to cover the multiple wirings M1. The insulating film IL2 is an interlayer insulating film. The insulating film IL2 is made of, for example, a silicon oxide film. After the insulating film IL2 is formed, the upper surface of the insulating film IL2 can be planarized by using a CMP method or the like.

[0032] Next, as shown in FIG. 5, the insulating film IL2 is etched using a photoresist pattern (not shown) formed on the insulating film IL2 as an etching mask, thereby forming a plurality of openings OP1 penetrating the insulating film IL2.

[0033] Next, as shown in FIG. 6, a conductive film CD1 is formed on the insulating film IL2 so as to fill the multiple openings OP1 of the insulating film IL2. The conductive film CD1 is, for example, a laminated film of a barrier conductor film and a main conductor film on the barrier conductor film. The main conductor film is, for example, a tungsten film. Thereafter, as shown in FIG. 7, the conductive film CD1 arranged outside the multiple openings OP1 of the insulating film IL2 is removed by a CMP method or the like. As a result, multiple plugs V1 are formed. The multiple plugs V1 are respectively embedded in the multiple openings OP1. The multiple plugs V1 include plugs V1a and plugs V1b.

[0034] 8, a material layer MTa is formed on the insulating film IL2 by sputtering or the like so as to cover the upper surface of each plug V1. The material layer MTa is formed on the entire upper surface of the insulating film IL2 and on the upper surfaces of the multiple plugs V1. The material layer MTa contains silicon (Si), chromium (Cr), and carbon (C) as constituent elements. The material layer MTa is an amorphous film.

[0035] 9, the material layer MTa is patterned using photolithography and etching techniques to form a material layer MT. The material layer MT is made of the patterned material layer MTa. The material layer MT constitutes a resistor element RS.

[0036] Next, as shown in FIG. 10, an insulating film IL3 is formed on the insulating film IL2 so as to cover the material layer MT. The insulating film IL3 is an interlayer insulating film. The insulating film IL3 is made of, for example, a silicon oxide film. The insulating film IL3 is formed so as to be in contact with the upper surface and side surfaces of the material layer MT. After the insulating film IL3 is formed, the upper surface of the insulating film IL3 can be planarized by using a CMP method or the like.

[0037] Next, a heat treatment (annealing treatment) is performed to crystallize the material layer MT. The material layer MT is heated by this heat treatment, and part or all of the material layer MT in an amorphous state is crystallized.

[0038] Next, as shown in FIG. 11, the insulating films IL3 and IL2 are etched using a photoresist pattern (not shown) formed on the insulating film IL3 as an etching mask, thereby forming a plurality of openings OP2 penetrating the insulating films IL3 and IL2.

[0039] Next, as shown in FIG. 12, a plurality of plugs V2 are formed. For example, a conductive film is formed on the insulating film IL3 so as to fill the openings OP2. This conductive film is, for example, a laminated film of a barrier conductor film and a main conductor film on the barrier conductor film. The main conductor film is, for example, a tungsten film. Thereafter, the conductive film disposed outside the openings OP2 is removed by a CMP method or the like. As a result, a plurality of plugs V2 are formed. The plurality of plugs V2 are embedded in the openings OP2, respectively. The plurality of plugs V2 include plugs V2a and plugs V2b.

[0040] Next, as shown in FIG. 13, a plurality of wirings M2 are formed on the insulating film IL3. For example, a conductive film is formed on the insulating film IL1. Then, the conductive film is patterned using photolithography and etching techniques to form a plurality of wirings M2 made of a conductive film. The plurality of wirings M2 are, for example, aluminum wirings, but wirings using other metal materials can also be applied. The plurality of wirings M2 include wirings M2a and wirings M2b.

[0041] Further, the process of forming the upper insulating film and wiring is omitted from the illustration and description.

[0042] <About the process of the review> The present inventors have studied a resistance element containing silicon (Si), chromium (Cr), and carbon (C) as constituent elements. In the following, a resistance element containing silicon (Si), chromium (Cr), and carbon (C) as constituent elements is referred to as a Si-Cr-C resistance element. The resistance element RS is also a Si-Cr-C resistance element. In addition, a film containing silicon (Si), chromium (Cr), and carbon (C) as constituent elements is referred to as a Si-Cr-C film. The material layer MTa is also a Si-Cr-C film.

[0043] In a Si-Cr-C resistor element, it is desirable that the resistivity is large and that the absolute value of the temperature coefficient of resistance (TCR) is small. If the resistivity of the resistor element is large, the resistance value can be increased while the planar dimensions of the resistor element are reduced, and therefore the semiconductor device including the resistor element can be miniaturized. If the absolute value of the temperature coefficient of resistance is small, the change in the resistance value of the resistor element caused by temperature change can be suppressed, and therefore the performance of the semiconductor device including the resistor element can be improved.

[0044] FIG. 14 is a graph showing the resistivity and temperature coefficient of resistance of a Si-Cr-C resistor element. The horizontal axis of FIG. 14 corresponds to the ratio of silicon to chromium in the Si-Cr-C resistor element based on the number of atoms. Hereinafter, the ratio of silicon to chromium in the Si-Cr-C resistor element is referred to as the Si / Cr ratio. The Si / Cr ratio is the content ratio based on the number of atoms. The vertical axis of FIG. 14 corresponds to the resistivity or temperature coefficient of resistance (TCR) of the Si-Cr-C resistor element. FIG. 14 shows the resistivity and temperature coefficient of resistance of the Si-Cr-C resistor element when the Si / Cr ratio is changed, and the carbon content in the Si-Cr-C resistor element is 15 to 25 atomic percent based on the number of atoms. The graph of FIG. 14 is based on measurement data of a Si-Cr-C resistor element that has not been subjected to crystallization annealing treatment.

[0045] From the graph of FIG. 14, it can be seen that in the Si-Cr-C resistance element, the resistivity increases as the Si / Cr ratio increases.

[0046] 14, it can be seen that the resistance temperature coefficient of the Si-Cr-C resistor element gradually decreases when the Si / Cr ratio exceeds 1.2, and the resistance temperature coefficient of the Si-Cr-C resistor element decreases further when the Si / Cr ratio exceeds 1.5. Furthermore, when the Si / Cr ratio exceeds 2.5, the absolute value of the resistance temperature coefficient of the Si-Cr-C resistor element increases to a level (200 ppm / degree or more) that is undesirable for a resistor material.

[0047] In the Si-Cr-C resistor element, there is a trade-off between resistivity and temperature coefficient of resistance. Therefore, increasing the resistivity increases the absolute value of the temperature coefficient of resistance. Therefore, it is difficult to simultaneously increase the resistivity and suppress the absolute value of the temperature coefficient of resistance by simply adjusting the composition ratio of the Si-Cr-C resistor element.

[0048] Fig. 15 is a graph showing the relationship between the annealing temperature and the resistivity and the temperature coefficient of resistance when a crystallization annealing process is performed on a Si-Cr-C resistor element. The horizontal axis of the graph in Fig. 15 corresponds to the annealing temperature. The vertical axis of the graph in Fig. 15 corresponds to the resistivity or the temperature coefficient of resistance (TCR) of the Si-Cr-C resistor element.

[0049] It can be seen from the graph in Fig. 15 that the resistivity and temperature coefficient of resistance of the Si-Cr-C resistor element change by performing crystallization annealing treatment. In the graph in Fig. 15, when the annealing temperature is in the range of 520 degrees Celsius to 530 degrees Celsius, the absolute value of the temperature coefficient of resistance becomes small.

[0050] However, annealing at a temperature higher than 500 degrees Celsius is not desirable because annealing at a temperature higher than 500 degrees Celsius may affect wiring or semiconductor elements formed on the semiconductor substrate. Therefore, in order to improve the reliability of the semiconductor device, it is desirable to perform the crystallization annealing treatment on the Si-Cr-C resistor element at a temperature of 500 degrees Celsius or less.

[0051] 16 and 17 are partially enlarged cross-sectional views of a semiconductor device as an example studied by the present inventors.

[0052] The semiconductor device of the study example shown in Fig. 16 and Fig. 17 has an insulating film IL2, a Si-Cr-C resistor element RS101 formed on the insulating film IL2, and an insulating film IL3 formed on the Si-Cr-C resistor element RS101. However, Fig. 16 shows a case where the thickness of the Si-Cr-C resistor element RS101 is large, and Fig. 17 shows a case where the thickness of the Si-Cr-C resistor element RS101 is small. For example, in Fig. 16, the thickness of the Si-Cr-C resistor element RS101 is about 300 nm. On the other hand, in Fig. 17, the thickness of the Si-Cr-C resistor element RS101 is 10 nm or less.

[0053] The upper and lower surfaces of the Si-Cr-C resistor element RS101 are not completely flat, but have unevenness reflecting the surface roughness. Therefore, each of the upper and lower surfaces of the Si-Cr-C resistor element RS101 has a plurality of convex portions (protrusions). This is because it is difficult to form a Si-Cr-C film having a completely flat upper and lower surface. The same is true for the upper and lower surfaces of the resistor element RS of this embodiment. The upper and lower surfaces of the resistor element RS are not completely flat, but have unevenness reflecting the surface roughness. Therefore, each of the upper and lower surfaces of the resistor element RS of this embodiment has a plurality of convex portions (protrusions).

[0054] When a current flows through the Si-Cr-C resistance element RS101, electrons are conducted through a path passing through the inside of the Si-Cr-C resistance element RS101. In each of Fig. 16 and Fig. 17, an arrow YG1 indicates a conduction path passing through the inside of the Si-Cr-C resistance element RS101. However, when a current flows through the Si-Cr-C resistance element RS101, electrons are also conducted through the insulating film IL2 or insulating film IL3 due to the unevenness of the upper and lower surfaces of the Si-Cr-C resistance element RS101.

[0055] 16 and 17, a current flows between the convex portions on the upper surface of the Si-Cr-C resistance element RS101 through a path shown typically by an arrow YG2. The arrow YG2 indicates a conduction path passing through the insulating film IL3. A current flows between the convex portions on the lower surface of the Si-Cr-C resistance element RS101 through a path shown typically by an arrow YG3. The arrow YG3 indicates a conduction path passing through the insulating film IL2. That is, in the vicinity of the upper surface of the Si-Cr-C resistance element RS101, a part of the insulating film IL3 also contributes as a conduction path for electrons, and in the vicinity of the lower surface of the Si-Cr-C resistance element RS101, a part of the insulating film IL2 also contributes as a conduction path for electrons.

[0056] 16, when the thickness of the Si-Cr-C resistor element RS101 is large, most of the current flows through the inside of the Si-Cr-C resistor element RS101, and the contribution of the conduction path indicated by the arrow YG2 or YG3 is small. Therefore, the resistance value of the conduction path passing through the insulating film IL2 or insulating film IL3 hardly contributes to the resistance value of the entire Si-Cr-C resistor element RS101.

[0057] However, when the thickness of the Si-Cr-C resistance element RS101 is small as shown in Fig. 17, the current passing through the inside of the Si-Cr-C resistance element RS101 is smaller than when the thickness of the Si-Cr-C resistance element RS101 is large as shown in Fig. 16, and the contribution of the conduction path indicated by the arrow YG2 or YG3 becomes larger. As a result, the proportion of the resistance value of the conduction path passing through the insulating film IL2 or insulating film IL3 to the resistance value of the entire Si-Cr-C resistance element RS101 increases.

[0058] In the conduction path (YG2) passing through the insulating film IL3 and the conduction path (YG3) passing through the insulating film IL2, the resistance value changes significantly due to temperature changes, the resistance temperature coefficient becomes negative, and the absolute value of the resistance temperature coefficient becomes large. Therefore, when the thickness of the Si-Cr-C resistor element RS101 is reduced, the influence of the conduction path passing through the insulating film IL2 or the insulating film IL3 becomes greater, and as a result, the absolute value of the resistance temperature coefficient becomes larger. It is desirable to suppress the absolute value of the resistance temperature coefficient even when the thickness of the Si-Cr-C resistor element is reduced.

[0059] <About resistor elements> FIG. 18 is a partially enlarged cross-sectional view of FIG. 1. FIG. 19 is a graph showing the concentration distribution of silicon (Si), chromium (Cr), and carbon (C) in the stacked structure shown in FIG. 18. The horizontal axis of the graph in FIG. 19 corresponds to the depth position. The vertical axis of the graph in FIG. 19 corresponds to the atomic fraction (concentration) of silicon (Si), chromium (Cr), or carbon (C). In the graph in FIG. 19, the concentration distribution of silicon (Si) is shown by a solid line, the concentration distribution of carbon (C) is shown by a dotted line, and the concentration distribution of chromium (Cr) is shown by a dashed line. The graph in FIG. 19 is based on the analysis results by EDX (energy dispersive X-ray spectroscopy).

[0060] In addition, in this embodiment, the material layer MT is subjected to a crystallization annealing treatment as described above during the manufacturing process of the semiconductor device. The graph in Fig. 19 is a graph showing the results of analyzing the concentration distribution of each element when the material layer MT is subjected to a crystallization annealing treatment as in this embodiment.

[0061] As can be seen from the graph in Fig. 19, in this embodiment, the composition ratio of silicon (Si), chromium (Cr) and carbon (C) in the resistor element RS is not distributed uniformly in the thickness direction, but has the following distribution. Note that the thickness direction is the direction from the lower surface to the upper surface of the resistor element RS, or the direction from the upper surface to the lower surface of the resistor element RS. The upper surface of the resistor element RS is the interface between the resistor element RS and the insulating film IL3. The lower surface of the resistor element RS is the interface between the resistor element RS and the insulating film IL2. Fig. 19 shows the concentration distribution in the thickness direction.

[0062] As shown in the graph of FIG. 19, within the resistor element RS, a silicon (Si) concentration peak P1 is formed at a position near the upper surface of the resistor element RS, and a silicon concentration peak P2 is formed at a position near the lower surface of the resistor element RS.

[0063] The silicon (Si) concentration in the resistor RS (material layer MT) increases from the center of the resistor RS toward the top surface of the resistor RS. Also, the silicon (Si) concentration in the resistor RS (material layer MT) increases from the center of the resistor RS toward the bottom surface of the resistor RS. That is, the silicon (Si) concentration in the resistor RS is lowest at the center of the resistor RS, increases from the center toward the top surface, and also increases from the center toward the bottom surface. Therefore, in the resistor RS, the silicon (Si) concentration in the vicinity of the top surface and the vicinity of the bottom surface of the resistor RS is higher than the silicon (Si) concentration in the center of the resistor RS. Note that the center of the resistor RS is the center in the thickness direction of the resistor RS.

[0064] As shown in the graph of FIG. 19, within the resistor element RS, a carbon (C) concentration peak P3 is formed at a position near the upper surface of the resistor element RS, and a carbon concentration peak P4 is formed at a position near the lower surface of the resistor element RS.

[0065] The carbon (C) concentration in the resistor RS (material layer MT) increases from the center of the resistor RS toward the top surface of the resistor RS. Also, the carbon (C) concentration in the resistor RS (material layer MT) increases from the center of the resistor RS toward the bottom surface of the resistor RS. That is, the carbon (C) concentration in the resistor RS is lowest at the center of the resistor RS, increases from the center toward the top surface, and also increases from the center toward the bottom surface. Therefore, in the resistor RS, the carbon (C) concentration near the top surface and near the bottom surface of the resistor RS is higher than the carbon (C) concentration in the center of the resistor RS.

[0066] As shown in the graph of FIG. 19, in the resistor element RS, a peak P5 of the chromium (Cr) concentration is formed in the center of the resistor element RS.

[0067] The chromium (Cr) concentration in the resistor RS (material layer MT) decreases from the center of the resistor RS toward the top surface of the resistor RS. Also, the chromium (Cr) concentration in the resistor RS (material layer MT) decreases from the center of the resistor RS toward the bottom surface of the resistor RS. That is, the chromium (Cr) concentration in the resistor RS is highest at the center of the resistor RS, decreases from the center toward the top surface, and also decreases from the center toward the bottom surface. Therefore, in the resistor RS, the chromium (Cr) concentration near the top surface and near the bottom surface of the resistor RS is smaller than the silicon (Si) concentration in the center of the resistor RS.

[0068] The silicon (Si) concentration, chromium (Cr) concentration, and carbon (C) concentration are all concentrations based on the number of atoms and are expressed in atomic percent.

[0069] Reflecting the concentration distribution of silicon (Si) and chromium (Cr) in the resistor element RS, the Si / Cr ratio in the resistor element RS exhibits the following distribution.

[0070] The Si / Cr ratio in the resistor element RS (material layer MT) increases from the center of the resistor element RS toward the upper surface of the resistor element RS. Also, the Si / Cr ratio in the resistor element RS (material layer MT) increases from the center of the resistor element RS toward the lower surface of the resistor element RS. That is, the Si / Cr ratio in the resistor element RS is lowest at the center of the resistor element RS, increases from the center toward the upper surface, and also increases from the center toward the lower surface. Therefore, in the resistor element RS, the Si / Cr ratio in the vicinity of the upper surface and the vicinity of the lower surface of the resistor element RS is higher than the Si / Cr ratio in the center of the resistor element RS.

[0071] 14, in a Si-Cr-C resistor element, the resistivity increases as the Si / Cr ratio increases. Therefore, reflecting the distribution of the Si / Cr ratio in the resistor element RS, the resistivity in the resistor element RS shows the following distribution:

[0072] The resistivity in the resistor RS (material layer MT) increases from the center of the resistor RS toward the top surface of the resistor RS. Also, the resistivity in the resistor RS (material layer MT) increases from the center of the resistor RS toward the bottom surface of the resistor RS. That is, the resistivity in the resistor RS is lowest at the center of the resistor RS, increases from the center toward the top surface, and also increases from the center toward the bottom surface. Therefore, in the resistor RS, the resistivity in the vicinity of the top surface and the vicinity of the bottom surface of the resistor RS is higher than the resistivity in the center of the resistor RS.

[0073] Fig. 20 is a graph showing the results of analyzing the concentration distribution of silicon (Si), chromium (Cr), and carbon (C) for the case where the crystallization annealing treatment was not performed on the material layer MT as an example of the study. The horizontal and vertical axes of Fig. 20 are the same as those of Fig. 19. As with Fig. 19, the graph of Fig. 20 is also based on the analysis results by EDX.

[0074] Unlike the present embodiment, when the crystallization annealing process is not performed on the material layer MT, as can be seen from the graph of FIG. 20, the concentration distribution of silicon (Si) in the material layer MT is almost uniform in the thickness direction. The concentration distribution of carbon (C) in the material layer MT is also almost uniform in the thickness direction. As can be seen by comparing the graphs of FIG. 19 and FIG. 20, the distribution curve of the chromium concentration in the graph of FIG. 20 is broader than the distribution curve of the chromium concentration in the graph of FIG. 19. Therefore, compared to the graph of FIG. 19, the concentration distribution of chromium (Cr) in the material layer MT in the graph of FIG. 20 is considered to be closer to uniform.

[0075] Therefore, it is considered that the composition ratio of chromium (Cr) and carbon (C) is closer to uniform in the thickness direction when the material layer MT is not subjected to crystallization annealing treatment, compared to when the material layer MT is subjected to crystallization annealing treatment.

[0076] In contrast, in the present embodiment, a crystallization annealing process is performed on the material layer MT during the manufacturing process of the semiconductor device. This crystallization annealing process is performed in a state where the material layer MT is sandwiched between the insulating films IL2 and IL3. That is, the crystallization annealing process is performed on the material layer MT in a state where the lower surface of the material layer MT is covered with the insulating film IL2 and the upper surface of the material layer MT is covered with the insulating film IL3. Therefore, during the crystallization annealing process, silicon (Si) and carbon (C) in the material layer MT diffuse toward the interface between the material layer MT and the insulating film IL3, segregate in the resistance element RS near the upper surface of the material layer MT, and diffuse toward the interface between the material layer MT and the insulating film IL2, and segregate in the resistance element RS near the lower surface of the material layer MT. It is considered that the concentration distribution shown in the graph of FIG. 19 is formed as a result.

[0077] Unlike this embodiment, when the crystallization annealing process is performed in a state where the upper surface of the material layer MT is not covered with an insulating film, the concentration distribution as shown in the graph of Fig. 19 is not formed. This is because, during the crystallization annealing process, silicon (Si) and carbon (C) in the material layer MT diffuse toward the interface between the material layer MT and the insulating film IL2, but hardly diffuse toward the upper surface of the material layer MT, and silicon (Si) and carbon (C) do not segregate near the upper surface of the material layer MT in the resistor element RS.

[0078] In this embodiment, the crystallization annealing is performed with the upper surface of the material layer MT covered with the insulating film IL3, so that during the crystallization annealing, silicon (Si) and carbon (C) in the material layer MT can diffuse toward the interface between the material layer MT and the insulating film IL3 and also toward the interface between the material layer MT and the insulating film IL2. As a result, silicon (Si) and carbon (C) are segregated in the material layer MT near the upper surface and near the lower surface of the material layer MT, respectively, and a concentration distribution as shown in the graph of FIG.

[0079] In this embodiment, as described above, the silicon (Si) concentration in the resistor RS (material layer MT) increases from the center of the resistor RS toward the upper surface of the resistor RS. Also, the silicon (Si) concentration in the resistor RS (material layer MT) increases from the center of the resistor RS toward the lower surface of the resistor RS. Reflecting this, the Si / Cr ratio is low in the center of the resistor RS, and the Si / Cr ratio is high in the vicinity of the upper surface and the vicinity of the lower surface of the resistor RS in the resistor RS compared to the center of the resistor RS. As a result, the absolute value of the resistance temperature coefficient of the resistor RS can be suppressed for the following two reasons.

[0080] The first reason will be described. In the resistor RS, the Si / Cr ratio in the vicinity of the upper surface of the resistor RS and the vicinity of the lower surface of the resistor RS becomes high, and the resistivity in the vicinity of the upper surface of the resistor RS and the vicinity of the lower surface of the resistor RS becomes high, and the current becomes difficult to flow in the vicinity of the upper surface of the resistor RS and the vicinity of the lower surface of the resistor RS. As a result, the current flowing in the conductive path (YG1) passing through the inside of the resistor RS increases, and the current flowing in the conductive path (YG2) passing through the insulating film IL3 and the conductive path (YG3) passing through the insulating film IL2 decreases. Therefore, the proportion of the resistance value of the insulating film IL2 or the conductive path (YG2, YG3) passing through the insulating film IL3 to the resistance value of the entire resistor RS can be reduced. As described above, in the conductive path (YG2) passing through the insulating film IL3 and the conductive path (YG3) passing through the insulating film IL2, the resistance temperature coefficient becomes negative and the absolute value of the resistance temperature coefficient becomes large. In this embodiment, the proportion of the resistance value of the conduction path (YG2, YG3) passing through the insulating film IL2 or the insulating film IL3 to the overall resistance value of the resistor element RS can be reduced, thereby suppressing the absolute value of the resistance temperature coefficient of the resistor element RS.

[0081] The second reason will be described. In the center of the resistor element RS, the resistivity decreases due to the lowering of the Si / Cr ratio, and therefore the current passing through the center of the resistor element RS increases. As can be seen from the graph of FIG. 14, the absolute value of the temperature coefficient of resistance of the Si-Cr-C resistor element tends to increase as the Si / Cr ratio increases. In this embodiment, the current flowing through the center of the resistor element RS is increased and the Si / Cr ratio in the center is lowered, thereby suppressing the absolute value of the temperature coefficient of resistance of the resistor element RS.

[0082] As explained with reference to Figures 16 and 17 above, when the thickness of the Si-Cr-C resistor element RS101 becomes smaller, the influence of the conduction path (YG2, YG3) passing through the insulating film IL2 or the insulating film IL3 becomes greater, and as a result, the absolute value of the temperature coefficient of resistance becomes larger.

[0083] In this embodiment, even if the thickness of the resistor element RS is reduced, the absolute value of the resistance temperature coefficient of the resistor element RS can be suppressed due to the above first and second reasons. Therefore, in this embodiment, the absolute value of the resistance temperature coefficient of the resistor element RS can be suppressed while reducing the thickness of the resistor element RS. By reducing the thickness of the resistor element RS, the resistance value of the resistor element RS can be increased while reducing the planar dimensions of the resistor element RS, and therefore the semiconductor device including the resistor element RS can be miniaturized. By suppressing the absolute value of the resistance temperature coefficient of the resistor element RS, the change in the resistance value of the resistor element RS caused by temperature change can be suppressed, and therefore the performance of the semiconductor device including the resistor element RS can be improved.

[0084] For this reason, this embodiment is highly effective when applied to the case where the thickness of the resistor element RS is made small. Specifically, this embodiment is highly effective when applied to the case where the thickness of the resistor element RS is 10 nm or less.

[0085] Fig. 21 is a graph showing the correlation between the crystallization annealing temperature and the temperature coefficient of resistance (TCR) of the resistor element RS. The horizontal axis of the graph in Fig. 21 corresponds to the crystallization annealing temperature of the resistor element RS (material layer MT). The vertical axis of the graph in Fig. 21 corresponds to the temperature coefficient of resistance (TCR) of the resistor element RS. The graph in Fig. 21 shows a case where the thickness of the resistor element RS is 300 nm and a case where the thickness of the resistor element RS is 5.5 nm.

[0086] From the graph in Fig. 21, it can be seen that the absolute value of the temperature coefficient of resistance (TCR) can be suppressed when the thickness of the resistor element RS is 5.5 nm, compared to when the thickness of the resistor element RS is 300 nm. Also, from the graph in Fig. 21, it can be seen that when the thickness of the resistor element RS is 5.5 nm, the absolute value of the temperature coefficient of resistance (TCR) of the resistor element RS can be sufficiently suppressed if the crystallization annealing temperature is 500 degrees Celsius or less.

[0087] For this reason, in this embodiment, it is preferable that the thickness of the resistor element RS is 10 nm or less, and the crystallization annealing temperature of the resistor element RS (material layer MT) is 500 degrees C or less, and it is more preferable that the crystallization annealing temperature is 300 degrees C or more and 500 degrees C or less, thereby making it possible to further suppress the absolute value of the resistance temperature coefficient of the resistor element RS.

[0088] Furthermore, by setting the crystallization annealing temperature to 500 degrees Celsius or less, it is possible to suppress or prevent the crystallization annealing from affecting the multiple wirings M1 or the semiconductor elements formed on the semiconductor substrate SB, thereby improving the reliability of the semiconductor device.

[0089] It is also preferable that the ratio of silicon (Si) to chromium (Cr) (Si / Cr ratio) in the resistor element RS is greater than 2, and the carbon (C) content of the resistor element RS is 15 atomic percent or more and 30 atomic percent or less. By satisfying these contents, a good balance can be obtained between the resistivity of the resistor element RS and the absolute value of the temperature coefficient of resistance of the resistor element RS when a crystallization annealing process is performed.

[0090] Fig. 22 is a plan view of the resistor element RS. Fig. 23 is a cross-sectional view of the resistor element RS. The cross-sectional view taken along line A1-A1 in Fig. 22 corresponds to Fig. 23. The X direction and Y direction shown in Fig. 22 are perpendicular to each other. The X direction and Y direction shown in Fig. 22 are approximately parallel to the main surface of the semiconductor substrate SB. The X direction is the long side direction of the resistor element RS, and the Y direction is the short side direction of the resistor element RS.

[0091] 22, the resistor element RS has a length L1 and a width W1. The length L1 is the dimension of the resistor element RS in the X direction. The width W1 is the dimension of the resistor element RS in the Y direction. In the resistor element RS, a current flows in the X direction.

[0092] 23, the resistor element RS has a low resistance region RG1 and a high resistance region RG2. The resistivity of the high resistance region RG2 is higher than the resistivity of the low resistance region RG1.

[0093] As shown in Fig. 23, in a cross-sectional view perpendicular to the X direction, the low resistance region RG1 is surrounded by the high resistance region RG2. In the resistor RS, the high resistance region RG2 is composed of a region adjacent to the upper surface of the resistor RS, a region adjacent to the lower surface of the resistor RS, and a region adjacent to the side surface of the resistor RS. In other words, in the resistor RS, the high resistance region RG2 is composed of a region near the upper surface of the resistor RS, a region near the lower surface of the resistor RS, and a region near the side surface of the resistor RS. The center of the resistor RS is included in the low resistance region RG1.

[0094] Compared to the low resistance region RG1, the high resistance region RG2 has a high silicon (Si) concentration, a high carbon (C) concentration, and a low chromium (Cr) concentration. That is, compared to the center of the resistor element RS, the resistor element RS has a high silicon (Si) concentration, a high carbon (C) concentration, and a low chromium (Cr) concentration in the region near the top surface of the resistor element RS, the region near the bottom surface of the resistor element RS, and the region near the side surface of the resistor element RS. This is because the resistor element RS has a concentration distribution as shown in FIG. 19. Reflecting this, the Si / Cr ratio in the high resistance region RG2 is higher than the Si / Cr ratio in the low resistance region RG1, and as a result, the resistivity of the high resistance region RG2 is higher than the resistivity of the low resistance region RG1.

[0095] In this embodiment, after the material layer MTa is patterned to form the material layer MT, an insulating film IL3 is formed to cover the material layer MT, and then a crystallization annealing process is performed. Therefore, the lower surface of the material layer MT is covered with the insulating film IL2, and the upper surface and side surface of the material layer MT are covered with the insulating film IL3, and the crystallization annealing process is performed on the material layer MT. Therefore, during the crystallization annealing process, silicon (Si) and carbon (C) in the material layer MT diffuse toward the upper surface of the material layer MT, forming a high resistance region RG2 in a region adjacent to the upper surface of the resistor element RS. Also, during the crystallization annealing process, silicon (Si) and carbon (C) in the material layer MT diffuse toward the lower surface of the material layer MT, forming a high resistance region RG2 in a region adjacent to the lower surface of the resistor element RS. During the crystallization annealing process, silicon (Si) and carbon (C) in the material layer MT diffuse toward the side surface of the material layer MT, forming a high resistance region RG2 in a region adjacent to the side surface of the resistor element RS. As a result, a cross-sectional structure as shown in FIG. 23 is formed.

[0096] By forming the low resistance region RG1 and the high resistance region RG2 in the resistor element RS, the absolute value of the resistance temperature coefficient of the resistor element RS can be suppressed for the above first and second reasons.

[0097] Not only the high resistance region RG2 adjacent to the upper surface of the resistor element RS and the high resistance region RG2 adjacent to the lower surface of the resistor element RS, but also the high resistance region RG2 adjacent to the side surface of the resistor element RS contribute to the effect of suppressing the absolute value of the resistance temperature coefficient of the resistor element RS. The effect of forming the low resistance region RG1 and the high resistance region RG2 in the resistor element RS increases as the width W1 of the resistor element RS becomes smaller. This is because even if the width W1 of the resistor element RS is reduced, the dimensions of the high resistance region RG2 adjacent to the side surface of the resistor element RS do not change.

[0098] Fig. 24 is a graph showing the correlation between the width W1 of the resistive element RS and the resistance value of the resistive element RS. Fig. 25 is a graph showing the correlation between the width W1 of the resistive element RS and the resistance temperature coefficient of the resistive element RS. The horizontal axis of each of the graphs in Fig. 24 and Fig. 25 corresponds to the width W1 of the resistive element RS. The vertical axis of the graph in Fig. 24 corresponds to the resistance value of the resistive element RS. The vertical axis of the graph in Fig. 25 corresponds to the resistance temperature coefficient of the resistive element RS. Each of the graphs in Fig. 24 and Fig. 25 is based on an analysis by simulation.

[0099] It can be seen from the graph of Fig. 24 that the resistance value of the resistor element RS increases as the width W1 of the resistor element RS is reduced, and it can be seen from the graph of Fig. 25 that the resistance temperature coefficient of the resistor element RS increases and the absolute value of the resistance temperature coefficient of the resistor element RS decreases as the width W1 of the resistor element RS is reduced.

[0100] Therefore, the smaller the width W1 of the resistor element RS, the greater the effect of this embodiment. Specifically, when the width W1 of the resistor element RS is 40 nm or less, the effect of this embodiment is large, and when the width W1 of the resistor element RS is 10 nm or less, the effect of this embodiment is even greater.

[0101] When the width W1 of the resistor element RS is greater than 10 nm and less than or equal to 40 nm, the change in the resistance value of the resistor element RS and the change in the resistance temperature coefficient of the resistor element RS when the width W1 of the resistor element RS is changed are small, making it easy to design the resistor element RS.

[0102] When the width W1 of the resistor element RS is 10 nm or less, the effect of increasing the resistance value of the resistor element RS and the effect of reducing the absolute value of the resistance temperature coefficient of the resistor element RS can be enhanced.

[0103] <Modification> Fig. 26 is a plan view of a modified resistance element RS. Fig. 27 is a cross-sectional view of the modified resistance element RS along the line A2-A2 in Fig. 26. Fig. 28 is a cross-sectional view of the modified resistance element RS along the line A3-A3 in Fig. 26.

[0104] The resistance element RS of the modified example shown in FIG. 26 differs from the resistance element RS shown in FIG. 22 in that the resistance element RS has a slit SL.

[0105] The number of slits SL formed in the resistor element RS is one or more, but is preferably more than one. In the case of Fig. 26, each slit SL extends in the X direction. As can be seen from Fig. 28, the slits SL of the resistor element RS are formed so as to penetrate from the upper surface to the lower surface of the resistor element RS. In other words, the slits SL of the resistor element RS are formed so as to expose the insulating film IL1. A through hole penetrating the resistor element RS can also be applied as the slit SL.

[0106] As shown in Fig. 27 and Fig. 28, in a cross-sectional view perpendicular to the X direction, the low resistance region RG1 is surrounded by the high resistance region RG2. In the resistor RS, the high resistance region RG2 is composed of a region adjacent to the upper surface of the resistor RS, a region adjacent to the lower surface of the resistor RS, a region adjacent to the side surface of the resistor RS, and a region adjacent to the inner wall of the slit SL. In other words, in the resistor RS, the high resistance region RG2 is composed of a region near the upper surface of the resistor RS, a region near the lower surface of the resistor RS, a region near the side surface of the resistor RS, and a region near the inner wall of the slit SL. Compared to the low resistance region RG1, the high resistance region RG2 has a high silicon (Si) concentration, a high carbon (C) concentration, and a low chromium (Cr) concentration.

[0107] The silicon concentration of the portion of the resistor RS in contact with the slit SL is higher than the silicon concentration of the portion of the resistor RS away from the slit SL, the upper surface of the resistor RS, the side surface of the resistor RS, and the lower surface of the resistor RS. Also, the carbon concentration of the portion of the resistor RS in contact with the slit SL is higher than the carbon concentration of the portion of the resistor RS away from the slit SL, the upper surface of the resistor RS, the side surface of the resistor RS, and the lower surface of the resistor RS. Also, the chromium concentration of the portion of the resistor RS in contact with the slit SL is lower than the chromium concentration of the portion of the resistor RS away from the slit SL, the upper surface of the resistor RS, the side surface of the resistor RS, and the lower surface of the resistor RS.

[0108] Not only the high resistance region RG2 adjacent to the upper surface of the resistor RS, the high resistance region RG2 adjacent to the lower surface of the resistor RS, and the high resistance region RG2 adjacent to the side surface of the resistor RS, but also the high resistance region RG2 adjacent to the inner wall of the slit SL contribute to the effect of suppressing the absolute value of the resistance temperature coefficient of the resistor RS. Therefore, the resistor RS of the modified examples shown in Figures 26, 27, and 28 can further increase the effect of suppressing the absolute value of the resistance temperature coefficient of the resistor RS compared to the resistor RS shown in Figures 22 and 23.

[0109] (Embodiment 2) The manufacturing process of the semiconductor device according to the second embodiment will be described with reference to the drawings. Figures 29 to 33 are cross-sectional views of the main part of the semiconductor device according to the second embodiment during the manufacturing process.

[0110] In the second embodiment, similarly to the first embodiment, the steps shown in Figs. 2 to 8 are carried out.

[0111] After forming a material layer MTa in the same manner as in the above-described first embodiment, in the second embodiment, as shown in FIG. 29, an insulating film HM is formed on the material layer MTa.

[0112] The insulating film HM functions as a hard mask. The insulating film HM is made of, for example, a silicon oxide film, and can be formed by using a CVD method or the like.

[0113] Next, as shown in FIG. 30, a photoresist pattern PR is formed on the insulating film HM by using a photolithography technique.

[0114] 31, the insulating film HM is etched using the photoresist pattern PR as an etching mask, thereby patterning the insulating film HM.

[0115] Next, as shown in FIG. 31, the material layer MTa is etched using the photoresist pattern PR and the insulating film HM as an etching mask. As a result, the material layer MTa is patterned to form a material layer MT. The material layer MT is made of the patterned material layer MTa. Thereafter, the photoresist pattern PR is removed by ashing or the like. An insulating film HM having the same planar shape as the material layer MT is disposed on the upper surface of the material layer MT. The upper surface of the material layer MT is in contact with the insulating film HM.

[0116] Alternatively, after the insulating film HM is etched using the photoresist pattern PR as an etching mask, the photoresist pattern PR is removed, and then the material layer MTa is etched using the insulating film HM as an etching mask.

[0117] 32, an insulating film IL3 is formed on the insulating film IL2 so as to cover the stacked film consisting of the material layer MT and the insulating film HM on the material layer MT. The insulating film IL3 is formed so as to contact the side surface of the material layer MT, the upper surface of the insulating film HM, and the side surface of the insulating film HM. After the insulating film IL3 is formed, the upper surface of the insulating film IL3 can be planarized by using a CMP method or the like.

[0118] Next, also in the present second embodiment, similarly to the above-described first embodiment, a plurality of openings OP2 penetrating the insulating film IL3 and the insulating film IL2 are formed as shown in Fig. 33. Next, similarly to the above-described first embodiment, a plurality of plugs V2 are formed as shown in Fig. 33. Next, similarly to the above-described first embodiment, a plurality of wirings M2 are formed as shown in Fig. 33.

[0119] Further, the process of forming the upper insulating film and wiring is omitted from the illustration and description.

[0120] In the above-described first embodiment, the crystallization annealing treatment for the material layer MT is performed after the insulating film IL3 is formed. As a result, the crystallization annealing treatment is performed in a state in which the insulating film IL3 is disposed on the material layer MT, and thus the concentration distribution as shown in the graph of FIG.

[0121] In the present second embodiment, the crystallization annealing process is performed after the insulating film HM is formed. As a result, the crystallization annealing process is performed in a state in which the insulating film HM is disposed on the material layer MTa or on the material layer MT, and thus the concentration distribution as shown in the graph of FIG.

[0122] In the second embodiment, the crystallization annealing treatment can be carried out at any of the following times.

[0123] In the second embodiment, the crystallization annealing process can be performed after the insulating film IL3 is formed. The crystallization annealing process crystallizes a part or the whole of the material layer MT in an amorphous state. Since the crystallization annealing process is performed in a state in which the upper surface of the material layer MT is covered with the insulating film HM and the side surface of the material layer MT is covered with the insulating film IL3, the concentration distribution shown in the graph of FIG. 19 is formed. In addition, the cross-sectional structure shown in FIG. 23 is obtained.

[0124] Alternatively, in the second embodiment, the crystallization annealing process can be performed after the material layer MTa is patterned to form the material layer MT and before the insulating film IL3 is formed. This crystallization annealing process crystallizes a part or the whole of the amorphous material layer MT. Since the crystallization annealing process is performed in a state where the upper surface of the material layer MT is covered with the insulating film HM, the concentration distribution as shown in the graph of FIG. 19 is formed. Also, the cross-sectional structure as shown in FIG. 23 is obtained.

[0125] Alternatively, in the second embodiment, the crystallization annealing process can be performed after the insulating film HM is formed and before the photoresist pattern PR is formed. This crystallization annealing process crystallizes a part or the whole of the material layer MTa in an amorphous state. Since the crystallization annealing process is performed in a state where the upper surface of the material layer MTa is covered with the insulating film HM, the concentration distribution as shown in the graph of FIG. 19 is formed. Also, a cross-sectional structure as shown in FIG. 34 is obtained.

[0126] Fig. 34 is a cross-sectional view of the resistor element RS, and shows a cross section corresponding to the above-mentioned Fig. 23. When the crystallization annealing process is performed before the material layer MTa is patterned, as shown in Fig. 34, the high resistance region RG2 is not formed in the region adjacent to the side surface of the resistor element RS (material layer MT).

[0127] When the high resistance region RG2 is formed in the region adjacent to the side surface of the resistor element RS, the effect of suppressing the absolute value of the resistance temperature coefficient of the resistor element RS is greater than when the high resistance region RG2 is not formed in the region adjacent to the side surface of the resistor element RS. That is, compared to the cross-sectional structure of FIG. 34, when the cross-sectional structure of FIG. 23 is formed, the effect of suppressing the absolute value of the resistance temperature coefficient of the resistor element RS is greater.

[0128] (Embodiment 3) According to the study by the present inventor, it was found that carbon (C) adheres to the upper surface of the insulating film IL2 before the material layer MTa is formed, and the carbon fluctuates the resistance temperature coefficient of the resistor element RS. The carbon adhered to the upper surface of the insulating film IL2 is considered to originate from organic matter present inside various manufacturing devices or transport devices. When the material layer MTa is formed on the insulating film IL2 with carbon (C) adhered to the upper surface of the insulating film IL2, the carbon (C) adhered to the upper surface of the insulating film IL2 diffuses into the material layer MTa or the material layer MT during crystallization annealing. The amount of carbon (C) adhered to the upper surface of the insulating film IL2 and the amount of carbon (C) diffused into the material layer MTa or the material layer MT during crystallization annealing vary, so the carbon (C) content of the resistor element RS varies. As a result, the resistance temperature coefficient of the resistor element RS is not stable and fluctuates.

[0129] Therefore, in the third embodiment, after the multiple plugs V1 are formed and before the material layer MTa is formed, a cleaning process is performed on the upper surface of the insulating film IL2. This cleaning process can remove carbon attached to the upper surface of the insulating film IL2. As a result, it is possible to suppress or prevent fluctuations in the carbon (C) content of the resistor element RS. This makes it possible to suppress fluctuations in the temperature coefficient of resistance of the resistor element RS. Therefore, it is possible to improve the reliability of the semiconductor device including the resistor element RS.

[0130] The cleaning process is preferably a plasma cleaning process. For example, a plasma process using argon (Ar) plasma is performed on the upper surface of the insulating film IL2, and then the material layer MTa is formed on the insulating film IL2.

[0131] It is preferable that the plasma cleaning process and the film formation process of the material layer MTa are performed consecutively without exposing the semiconductor substrate SB to the atmosphere. That is, the semiconductor substrate SB is carried into a chamber of a plasma device, and after the plasma cleaning process is performed on the upper surface of the insulating film IL2, the semiconductor substrate SB is carried out from the chamber of the plasma device. Then, the semiconductor substrate SB carried out from the chamber of the plasma device is carried into the chamber of a film formation device without being exposed to the atmosphere, and the material layer MTa is formed on the insulating film IL2. This makes it possible to prevent carbon (C) from re-adhering to the upper surface of the insulating film IL2 after the plasma cleaning process and before the film formation process of the material layer MTa.

[0132] FIG. 35 is a graph showing the carbon (C) content and resistance temperature coefficient of the resistor element RS. The horizontal axis of the graph in FIG. 35 corresponds to the carbon (C) content of the resistor element RS, and the vertical axis of the graph in FIG. 35 corresponds to the resistance temperature coefficient of the resistor element RS. The graph in FIG. 35 also plots the measurement results of the carbon (C) content and resistance temperature coefficient of the resistor element RS when the upper surface of the insulating film IL2 is subjected to a plasma cleaning process, and the measurement results of the carbon (C) content and resistance temperature coefficient of the resistor element RS when the upper surface of the insulating film IL2 is not subjected to a cleaning process. The number of samples when the upper surface of the insulating film IL2 is subjected to a plasma cleaning process is four. The number of samples when the upper surface of the insulating film IL2 is not subjected to a cleaning process is four.

[0133] 35, when the upper surface of the insulating film IL2 is not cleaned, the carbon (C) content and temperature coefficient of resistance of the resistor element RS fluctuate. It is believed that the carbon (C) content of the resistor element RS fluctuates due to the carbon (C) adhering to the upper surface of the insulating film IL2 diffusing into the material layer MTa or material layer MT during crystallization annealing, and as a result, the temperature coefficient of resistance of the resistor element RS fluctuates.

[0134] On the other hand, when the upper surface of the insulating film IL2 is subjected to a plasma cleaning process, as can be seen from the graph of FIG. 35, the fluctuations in the carbon (C) content and the temperature coefficient of resistance of the resistor element RS are suppressed.

[0135] As a cleaning process for the upper surface of the insulating film IL2, a wet cleaning process can be performed instead of the plasma cleaning process. In the wet cleaning process, a chemical effective for removing carbon attached to the upper surface of the insulating film IL2 is used. Specifically, a wet cleaning process using SPM (Sulfuric acid-hydrogen peroxide mixture), APM (Ammonia-hydrogen peroxide mixture) or ozone water can be used. By forming a material layer MTa on the insulating film IL2 after removing carbon (C) attached to the upper surface of the insulating film IL2 by a wet cleaning process, it is possible to suppress the variation of the carbon (C) content and the resistance temperature coefficient of the resistor element RS. In addition, by appropriately managing the time from the wet cleaning process to the formation of the material layer MTa, it is possible to suppress the carbon (C) from re-adhering to the upper surface of the insulating film IL2.

[0136] However, when a plasma cleaning process is used as the cleaning process for the upper surface of the insulating film IL2, the deposition process of the material layer MTa can be performed continuously after the plasma cleaning process without exposing the semiconductor substrate SB to the atmosphere. Therefore, it is possible to prevent carbon (C) from re-adhering to the upper surface of the insulating film IL2 after the cleaning process and before the deposition process of the material layer MTa.

[0137] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0138] CD1 Conductive Film HM insulating film IL1,IL2,IL3 Insulating film M1,M1a,M1b,M2,M2a,M2b wiring MT, MTa, MT101 material layer OP1,OP2 opening PR Photoresist pattern RG1 Low resistance region RG2 High resistance region RS Resistance element SB Semiconductor Substrate SL Slit V1, V1a, V1b, V2, V2a, V2b plugs

Claims

1. A first insulating film; a resistive element including silicon, chromium and carbon, disposed on the first insulating film; a second insulating film disposed on the resistor element so as to be in contact with the resistor element; having a silicon concentration of the resistor element increases from a center of the resistor element toward an upper surface of the resistor element, and increases from the center of the resistor element toward a lower surface of the resistor element.

2. 2. The semiconductor device according to claim 1, a chromium concentration of the resistor element decreases from the central portion of the resistor element toward the top surface of the resistor element, and decreases from the central portion of the resistor element toward the bottom surface of the resistor element.

3. 3. The semiconductor device according to claim 2, A semiconductor device, wherein a carbon concentration of the resistor element increases from the central portion of the resistor element toward the top surface of the resistor element and also increases from the central portion of the resistor element toward the bottom surface of the resistor element.

4. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the resistance element has a thickness of 10 nm or less.

5. 5. The semiconductor device according to claim 4, a ratio of silicon to chromium in said resistor element is greater than 2; The carbon content of the resistor element is 15 atomic percent or more and 30 atomic percent or less.

6. 5. The semiconductor device according to claim 4, The semiconductor device, wherein the width of the resistor element is not less than 10 nm and not more than 40 nm.

7. 5. The semiconductor device according to claim 4, The semiconductor device, wherein the width of the resistor element is 10 nm or less.

8. 8. The semiconductor device according to claim 7, The semiconductor device, wherein the upper surface and the lower surface of the resistor element each have a plurality of protrusions.

9. 2. The semiconductor device according to claim 1, A semiconductor device, wherein a silicon concentration in a region near a side surface of the resistor element is higher than a silicon concentration in the central portion of the resistor element.

10. 10. The semiconductor device according to claim 9, Within the resistor element, a chromium concentration in a region adjacent to the side surface of the resistor element is lower than a chromium concentration in the central portion of the resistor element; A semiconductor device, wherein a carbon concentration in a region near the side surface of the resistor element is higher than a carbon concentration in the central portion of the resistor element.

11. 2. The semiconductor device according to claim 1, a first wiring arranged so as to be covered with the first insulating film; A second wiring arranged so as to be covered with the first insulating film; a first plug disposed in the first insulating film and connected to the first wiring; a second plug disposed in the first insulating film and connected to the second wiring; Further comprising: The resistive element connects the first plug and the second plug.

12. (a) forming a first insulating film; (b) forming a resistor element containing silicon, chromium and carbon on the first insulating film; (c) forming a second insulating film on the first insulating film so as to cover the resistor element and to be in contact with the resistor element; (d) after the step (c), performing an annealing treatment on the resistance element with the second insulating film disposed on the resistance element; having a silicon concentration of the resistor element after the step (d) increases from a central portion of the resistor element toward an upper surface of the resistor element, and increases from the central portion of the resistor element toward a lower surface of the resistor element.

13. 13. The method of manufacturing a semiconductor device according to claim 12, The step (b) comprises: (b1) forming a first film containing silicon, chromium and carbon on the first insulating film; (b2) after the step (b1), forming the resistor element by patterning the first film; The method for manufacturing a semiconductor device comprising the steps of:

14. 13. The method of manufacturing a semiconductor device according to claim 12, A method for manufacturing a semiconductor device, wherein the annealing temperature is 300 degrees Celsius or more and 500 degrees Celsius or less.

15. 13. The method of manufacturing a semiconductor device according to claim 12, After the step (a) and before the step (b), (a1) subjecting an upper surface of the first insulating film to a plasma treatment; The method for manufacturing a semiconductor device further comprises:

16. 13. The method of manufacturing a semiconductor device according to claim 12, After the step (a) and before the step (b), (a1) cleaning the upper surface of the first insulating film with SPM, APM or ozone water; The method for manufacturing a semiconductor device further comprises:

17. 13. The method of manufacturing a semiconductor device according to claim 12, The method for manufacturing a semiconductor device, wherein the resistance element has a thickness of 10 nm or less.

18. 13. The method of manufacturing a semiconductor device according to claim 12, a chromium concentration of the resistor element after the step (d) decreases from the central portion of the resistor element toward the top surface of the resistor element, and decreases from the central portion of the resistor element toward the bottom surface of the resistor element.

19. 13. The method of manufacturing a semiconductor device according to claim 12, a carbon concentration of the resistor element after the step (d) increases from the central portion of the resistor element toward the top surface of the resistor element and also increases from the central portion of the resistor element toward the bottom surface of the resistor element.

20. (a) forming a first insulating film; (b) forming a first film containing silicon, chromium and carbon on the first insulating film; (c) forming a second insulating film on the first film so as to be in contact with the first film; (d) after the step (c), a step of patterning the second insulating film and the first film to form a resistor element made of the patterned first film; (e) after the step (c), performing an annealing treatment on the first film or the resistance element with the second insulating film disposed on the first film or the resistance element; having a silicon concentration of the resistor element after the step (c) increases from a central portion of the resistor element toward an upper surface of the resistor element, and also increases from the central portion of the resistor element toward a lower surface of the resistor element.

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