Semiconductor device, circuit board, and method for manufacturing circuit board

Abstract

To provide a semiconductor device that can be improved in handling ability, a circuit board including such a semiconductor device, and a method for manufacturing such a circuit board.SOLUTION: A semiconductor device has a first surface facing a first side and a second surface facing a second side opposite to the first side. The semiconductor device includes: a semiconductor device body; a lead frame to which the semiconductor device body is electrically connected; a conductive bump portion electrically connected to the semiconductor device body or the lead frame; and a resin portion that covers and holds at least a part of the semiconductor device body and at least a part of the lead frame. At least a part of the conductive bump portion is exposed to the outside of the resin portion.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device, a circuit board, and a method for manufacturing a circuit board. [Background technology]

[0002] There is a demand for thinner semiconductor devices. However, when a semiconductor device is made thinner, the handling properties of the semiconductor device are reduced. This can result in a reduction in the yield of products on which the semiconductor device is mounted, and restrictions on the mounting method for mounting the semiconductor device, resulting in a reduction in the productivity of products using the semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-25143 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device that can improve the handling properties, a circuit board including such a semiconductor device, and a method for manufacturing such a circuit board. [Means for solving the problem]

[0005] The semiconductor device of the embodiment has a first surface facing a first side and a second surface facing a second side opposite to the first side. The semiconductor device of the embodiment has a semiconductor device body, a lead frame to which the semiconductor device body is electrically connected, a conductive bump portion electrically connected to the semiconductor device body or the lead frame, and a resin portion that covers and holds at least a part of the semiconductor device body and at least a part of the lead frame. At least a part of the conductive bump portion is exposed to the outside of the resin portion. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2 is a cross-sectional view showing a portion of the circuit board according to the first embodiment. [Diagram 2] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Diagram 3] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 4] 3 is a cross-sectional view showing a stud bump for forming the conductive bump portion of the first embodiment. FIG. [Diagram 5] 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6A] 5A to 5C are cross-sectional views showing a first storage portion forming step in the first embodiment. [Figure 6B] 5A to 5C are cross-sectional views showing a chip fixing step according to the first embodiment. [Figure 6C] 5A to 5C are cross-sectional views showing a stud bump forming step according to the first embodiment. [Figure 6D] 4 is a cross-sectional view showing a state after a stud bump forming step according to the first embodiment is performed. FIG. [Figure 6E] FIG. 4 is a cross-sectional view showing a state after a molding step in the first embodiment. [Figure 6F] FIG. 4 is a cross-sectional view showing a state after a grinding step according to the first embodiment has been performed. [Figure 7] FIG. 2 is a plan view showing a base material of the lead frame according to the first embodiment. [Figure 8] 4 is a flowchart showing a method for manufacturing a circuit board according to the first embodiment. [Figure 9A] 4A to 4C are cross-sectional views showing a semiconductor device accommodation step according to the first embodiment. [Figure 9B] FIG. 4 is a cross-sectional view showing a state after a sealing step according to the first embodiment. [Figure 9C] 5A to 5C are cross-sectional views showing a laser processing step according to the first embodiment. [Figure 9D] FIG. 4 is a cross-sectional view showing a state after a laser processing step according to the first embodiment is performed. [Figure 10] FIG. 4 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 11]FIG. 11 is a plan view showing a semiconductor device according to a second embodiment. [Figure 12] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 13] FIG. 13 is a plan view showing a semiconductor device according to a third embodiment. [Figure 14] FIG. 13 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 15] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 16A] 13A to 13C are cross-sectional views showing a chip fixing step according to the fourth embodiment. [Figure 16B] 13A to 13C are cross-sectional views showing a stud bump forming step and a vertical wire forming step according to the fourth embodiment. [Figure 16C] FIG. 13 is a cross-sectional view showing a state after a stud bump forming step and a vertical wire forming step according to the fourth embodiment. [Figure 16D] FIG. 13 is a cross-sectional view showing a state after a molding step according to the fourth embodiment. [Figure 16E] FIG. 13 is a cross-sectional view showing a state after a grinding process according to the fourth embodiment. [Figure 17] FIG. 13 is a cross-sectional view showing a part of a circuit board according to a fifth embodiment. [Figure 18] FIG. 13 is a cross-sectional view showing a part of a circuit board according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, a semiconductor device, a circuit board, and a method for manufacturing a circuit board according to embodiments will be described with reference to the drawings.

[0008] In the drawings, the thickness direction of the circuit board of the embodiment is indicated as the Z-axis direction, one direction perpendicular to the thickness direction of the circuit board is indicated as the X-axis direction, and a direction perpendicular to both the Z-axis direction and the X-axis direction is indicated as the Y-axis direction. In the following description, the X-axis direction is called the "first direction X", the Y-axis direction is called the "second direction Y", and the Z-axis direction is called the "thickness direction Z". In addition, the side of the thickness direction Z toward which the Z-axis arrow points (+Z side) is called the "upper side", and the opposite side of the thickness direction Z to the side toward which the Z-axis arrow points (-Z side) is called the "lower side". In the following embodiments, the upper side corresponds to the "first side", and the lower side corresponds to the "second side" opposite to the first side.

[0009] (First embodiment) FIG. 1 is a cross-sectional view showing a part of a circuit board 100 of the first embodiment. As shown in FIG. 1, in the first embodiment, the circuit board 100 is a circuit board in which a semiconductor device 20 is built in. The circuit board 100 includes a board main body 10, a semiconductor device 20, and a wiring part 40. The board main body 10 is plate-shaped with a board surface facing the thickness direction Z. The semiconductor device 20 is mounted on the board main body 10. The board main body 10 includes a plate-shaped base part 11, a resin layer 12 laminated on an upper surface of the base part 11, a resin layer 13 laminated on a lower surface of the base part 11, and a sealing resin part 30.

[0010] The base material 11 is formed with a second housing portion 14 for housing the semiconductor device 20 therein. In the first embodiment, the second housing portion 14 is a hole penetrating the base material 11 in the thickness direction Z. An upper opening of the second housing portion 14 is blocked by a resin layer 12. A lower opening of the second housing portion 14 is blocked by a resin layer 13. A sealing resin portion 30 is filled in the inside of the second housing portion 14 except for the portion where the semiconductor device 20 is located.

[0011] FIG. 2 is a cross-sectional view showing the semiconductor device 20 of the first embodiment. FIG. 3 is a plan view showing the semiconductor device 20 of the first embodiment. In the first embodiment, the semiconductor device 20 is, for example, a vertical-structure field effect transistor (FET: Field Effect Transistor). The semiconductor device 20 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). As shown in FIGS. 2 and 3, the semiconductor device 20 is a thin plate in the thickness direction Z. As shown in FIG. 3, the semiconductor device 20 is substantially square-shaped with sides along the first direction X and the second direction Y when viewed in the thickness direction Z. As shown in FIG. 2, the semiconductor device 20 includes a semiconductor device body 50, a lead frame 60, a conductive bump portion 80, and a resin portion 70.

[0012] In the first embodiment, the semiconductor device body 50 is a semiconductor chip on which each electrode of a field effect transistor is formed. The semiconductor device body 50 is accommodated inside a first accommodation portion 63, which is included in a lead frame 60 and will be described later. The semiconductor device body 50 has a substrate portion 51, a first metal film 52a, a second metal film 52b, and a third metal film 52c. As shown in FIG. 2 and FIG. 3, the substrate portion 51 is plate-shaped with the plate surface facing the thickness direction Z. The substrate portion 51 is rectangular when viewed in the thickness direction Z. The material constituting the substrate portion 51 is a semiconductor material. The material constituting the substrate portion 51 is, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or the like.

[0013] The first metal film 52a and the second metal film 52b are formed on the upper surface of the substrate 51. The third metal film 52c is formed on the lower surface of the substrate 51. As shown in FIG. 3, the first metal film 52a is formed on one corner of the upper surface of the substrate 51. The first metal film 52a is substantially square-shaped when viewed in the thickness direction Z. The second metal film 52b is formed across the remaining three corners of the upper surface of the substrate 51. The second metal film 52b is substantially L-shaped when viewed in the thickness direction Z. The second metal film 52b has a portion adjacent to the first metal film 52a in the first direction X and a portion adjacent to the first metal film 52a in the second direction Y. As shown in FIG. 2, the third metal film 52c is formed on the entire lower surface of the substrate 51.

[0014] The first metal film 52a, the second metal film 52b, and the third metal film 52c are formed by, for example, sputtering. The material constituting the first metal film 52a and the material constituting the second metal film 52b are, for example, the same as each other. The material constituting the first metal film 52a and the material constituting the second metal film 52b are not particularly limited as long as they have conductivity, and are, for example, aluminum. The material constituting the third metal film 52c is not particularly limited as long as they have conductivity, and are, for example, materials containing one or more materials such as titanium (Ti), nickel (Ni), gold (Au), silver (Ag), and copper (Cu). The third metal film 52c is, for example, a Ti / Ni / Au laminated film, a Ti / Ni / Ag laminated film, or the like.

[0015] In the first embodiment, the first metal film 52a is a gate electrode. The second metal film 52b is a source electrode. The third metal film 52c is a drain electrode. Each metal film may be any electrode. The third metal film 52c does not have to be an electrode. In this case, three metal films may be formed on the upper surface of the substrate part 51, and the three metal films may correspond to the gate electrode, the source electrode, and the drain electrode, respectively.

[0016] The semiconductor device body 50 is electrically connected to the lead frame 60. The lead frame 60 is a conductive member made of metal. The material constituting the lead frame 60 is not particularly limited as long as it has conductivity, and is, for example, copper (Cu). Although not shown, a silver (Ag) coating is formed on the surface of the lead frame 60 to prevent oxidation. The coating does not have to be formed. The lead frame 60 has a support portion 61 that supports the semiconductor device body 50 from below, a frame portion 62 that protrudes upward from the support portion 61, and a protrusion portion 64 that protrudes from the support portion 61 in a direction perpendicular to the thickness direction Z.

[0017] The semiconductor device body 50 is joined to the upper surface of the support portion 61 via a joint portion 53. The joint portion 53 has electrical conductivity. The joint portion 53 is, for example, solder, a metal paste, or the like. In the first embodiment, the joint portion 53 electrically connects the upper surface of the support portion 61 and the third metal film 52c.

[0018] 3, in the first embodiment, the frame portion 62 has a rectangular frame shape. The frame portion 62 surrounds the semiconductor device body 50. As shown in FIG. 2, the upper surface of the frame portion 62 is disposed at the same position as the upper surface of the semiconductor device body 50 in the thickness direction Z. Note that the upper surface of the frame portion 62 may be located higher than the upper surface of the semiconductor device body 50, or may be located lower than the upper surface of the semiconductor device body 50.

[0019] The support portion 61 and the frame portion 62 form a first housing portion 63 that opens upward. In the first embodiment, the upper surface of the frame portion 62 is the periphery of the opening of the first housing portion 63 on the upper surface of the lead frame 60. The protrusion portion 64 is connected to the support portion 61. A plurality of protrusion portions 64 are provided. The multiple protrusion portions 64 include a protrusion portion 64 that protrudes from the support portion 61 in the first direction X and a protrusion portion 64 that protrudes from the support portion 61 in the second direction Y.

[0020] The conductive bump portion 80 is a bump having electrical conductivity. In this specification, the term "conductive bump portion" may refer to, for example, a portion in which a conductive material is formed as a lump having a certain thickness. The "certain thickness" is, for example, a thickness greater than the thickness of a film generally formed by sputtering and the thickness of a film generally formed by plating. In the first embodiment, the dimension of the conductive bump portion 80 in the thickness direction Z is greater than 4 μm. As an example, the dimension of the conductive bump portion 80 in the thickness direction Z is about 10 μm or more and 50 μm or less. The dimension of the conductive bump portion 80 in the thickness direction Z is not particularly limited.

[0021] In the first embodiment, the conductive bump portion 80 is formed by a stud bump. The stud bump is formed by performing ball bonding using a bonding wire and then cutting the bonding wire. FIG. 4 is a cross-sectional view showing a stud bump 180 for forming the conductive bump portion 80. The stud bump 180 is substantially conical in shape with an outer diameter that decreases toward the upper side. The stud bump 180 has a base portion 181 bonded to an object to which the stud bump 180 is connected, and a reduced diameter portion 182 protruding from the base portion 181. The outer diameter of the reduced diameter portion 182 decreases with increasing distance from the base portion 181.

[0022] The outer diameter D1 shown in FIG. 4 is the outer diameter of the bonding wire. For example, the outer diameter of a part of the upper part of the reduced diameter portion 182 is equal to the outer diameter D1 of the bonding wire. The outer diameter D1 of the bonding wire is not particularly limited, but is, for example, about 20 μm or more and 100 μm or less. The outer diameter D2 of the base portion 181 is, for example, about two times or more and three times or less than the outer diameter D1 of the bonding wire. The height H2 of the base portion 181 is, for example, about one-fifth of the outer diameter D2 of the base portion 181. The height H1 of the stud bump 180 can be arbitrarily large by overlapping ball bonding. The conductive bump portion 80 of the first embodiment is formed by cutting a part of the reduced diameter portion 182 of the stud bump 180. Specifically, for example, the conductive bump portion 80 is formed by cutting a part of the reduced diameter portion 182 of the stud bump 180 along the imaginary line CL shown in FIG. 4. 4, the imaginary line CL is located at a portion of the reduced diameter portion 182 whose outer diameter is larger than the outer diameter D1 of the bonding wire. Therefore, the outer diameter D3 at the upper end of the conductive bump portion 80 is smaller than the outer diameter D2 of the base portion 181 and larger than the outer diameter D1 of the bonding wire.

[0023] Since the conductive bump portion 80 is formed by cutting a part of the upper portion of the stud bump 180, the conductive bump portion 80 has a generally truncated cone shape with an outer diameter that decreases toward the upper side. The upper end face of the conductive bump portion 80 is a flat surface perpendicular to the thickness direction Z. The material constituting the conductive bump portion 80 is not particularly limited as long as it has conductivity, and may be, for example, gold (Au), silver (Ag), copper (Cu), or the like. From the viewpoint of ease of producing the stud bump 180, it is preferable to select, for example, gold (Au) as the material constituting the conductive bump portion 80. From the viewpoint of reducing the manufacturing cost, it is preferable to select, for example, copper (Cu) as the material constituting the conductive bump portion 80.

[0024] As shown in FIG. 2, the conductive bump portion 80 includes a first conductive bump portion 81 and a second conductive bump portion 82. The first conductive bump portion 81 is electrically connected to the semiconductor device body 50. More specifically, the first conductive bump portion 81 is connected to the upper surface of the semiconductor device body 50. A plurality of first conductive bump portions 81 are provided. The plurality of first conductive bump portions 81 include a first conductive bump portion 81 electrically connected to the first metal film 52a and a first conductive bump portion 81 electrically connected to the second metal film 52b. As shown in FIG. 3, for example, only one first conductive bump portion 81 electrically connected to the first metal film 52a is provided. Note that two or more first conductive bump portions 81 electrically connected to the first metal film 52a may be provided. A plurality of first conductive bump portions 81 electrically connected to the second metal film 52b are provided. A plurality of first conductive bump portions 81 electrically connected to the second metal film 52b are arranged side by side in the first direction X and the second direction Y, so as to be spread out on the substantially L-shaped second metal film 52b.

[0025] As shown in FIG. 2, the second conductive bump portion 82 is electrically connected to the lead frame 60. In the first embodiment, the second conductive bump portion 82 is electrically connected to the upper surface of the frame portion 62. In other words, the second conductive bump portion 82 is connected to the opening periphery of the first housing portion 63 on the upper surface of the lead frame 60. The second conductive bump portion 82 is electrically connected to the third metal film 52c via the lead frame 60 and the joint portion 53. A plurality of second conductive bump portions 82 are provided. As shown in FIG. 3, in the first embodiment, the plurality of second conductive bump portions 82 are arranged in a rectangular frame shape along the frame portion 62. The plurality of second conductive bump portions 82 are arranged to surround the first conductive bump portion 81 when viewed from above.

[0026] In the first embodiment, the material constituting first conductive bump portion 81 and the material constituting second conductive bump portion 82 are the same. In addition, in the first embodiment, the material constituting first conductive bump portion 81 and the material constituting second conductive bump portion 82 are different from the material constituting lead frame 60.

[0027] 2, the resin part 70 covers and holds at least a part of the semiconductor device body 50 and at least a part of the lead frame 60. In the first embodiment, the resin part 70 covers the entire semiconductor device body 50, the entire lead frame 60 except for the tip surface of the protruding part 64, and the entire conductive bump part 80 except for the upper end surface. In the first embodiment, the semiconductor device body 50, the lead frame 60, and the conductive bump part 80 are embedded and held in the resin part 70. In the first embodiment, the resin part 70 is formed by resin molding using a mold.

[0028] The upper surface of the resin portion 70 constitutes a part of the first surface 20a facing the upper side of the semiconductor device 20. The resin portion 70 covers the entire lower surface of the lead frame 60. The lower surface of the resin portion 70 is the second surface 20b facing the lower side of the semiconductor device 20. At least a part of the conductive bump portion 80 is exposed to the outside of the resin portion 70. In the first embodiment, the upper end faces of the multiple conductive bump portions 80 are exposed to the outside of the resin portion 70. More specifically, the upper end faces of the multiple conductive bump portions 80 are exposed to the first surface 20a of the semiconductor device 20. In the first embodiment, the first surface 20a is formed by the upper surface of the resin portion 70 and the upper end faces of the multiple conductive bump portions 80. The material constituting the resin portion 70 is not particularly limited as long as it is a resin having insulating properties. The material constituting the resin portion 70 may be a molded resin or an interlayer insulating material.

[0029] In the first embodiment, the upper end face of the first conductive bump portion 81 and the upper end face of the second conductive bump portion 82 are exposed on the first surface 20a. That is, the end face of the first conductive bump portion 81 and the end face of the second conductive bump portion 82 are exposed on the same surface of the semiconductor device 20. As shown in FIG. 3, in the first embodiment, the upper end face of the first conductive bump portion 81 and the upper end face of the second conductive bump portion 82 are circular. The first conductive bump portion 81 connected to the first metal film 52a functions as a gate electrode of the semiconductor device 20 by having the upper end face exposed to the outside of the resin portion 70. The first conductive bump portion 81 connected to the second metal film 52b functions as a source electrode of the semiconductor device 20 by having the upper end face exposed to the outside of the resin portion 70. The second conductive bump portion 82, electrically connected to the third metal film 52c via the lead frame 60 and the joint portion 53, functions as a drain electrode of the semiconductor device 20 by having its upper end face exposed to the outside of the resin portion 70.

[0030] 1, the semiconductor device 20 is accommodated in the second accommodation portion 14 of the substrate main body 10 and is built into the substrate main body 10. The second surface 20b of the semiconductor device 20 is in contact with the upper surface of the resin layer 13. The first surface 20a of the semiconductor device 20 is disposed downwardly and spaced apart from the lower surface of the resin layer 12. A part of the sealing resin portion 30 is interposed between the first surface 20a and the resin layer 12 in the thickness direction Z.

[0031] The wiring portion 40 is a portion forming at least a part of the circuit pattern formed on the circuit board 100. The wiring portion 40 has a first wiring pattern 41 formed on the upper surface of the substrate body portion 10 and a second wiring pattern 42 formed on the lower surface of the substrate body portion 10. The wiring portion 40 is electrically connected to a portion of the conductive bump portion 80 exposed to the outside of the resin portion 70 through a hole portion 15 formed in the substrate body portion 10. The hole portion 15 extends from the outer surface of the substrate body portion 10 to a portion of the conductive bump portion 80 exposed to the outside of the resin portion 70. In the first embodiment, the hole portion 15 is a hole recessed downward from the upper surface of the substrate body portion 10. The hole portion 15 penetrates the resin layer 12 and a portion of the sealing resin portion 30 located on the upper side of the semiconductor device 20 in the thickness direction Z. The inner diameter of the hole portion 15 is, for example, smaller toward the lower side. The hole portion 15 is formed by a drilling process using a laser beam. A plurality of holes 15 are formed. The plurality of holes 15 are located respectively above the plurality of conductive bump portions 80. At the lower end of each hole 15, the upper end face of each conductive bump portion 80 is exposed.

[0032] The wiring portion 40 has a connection wiring portion 43 formed inside the hole portion 15. The connection wiring portion 43 is provided for each of the plurality of holes 15. The connection wiring portion 43 is electrically connected to the conductive bump portion 80. More specifically, the lower end of each connection wiring portion 43 is electrically connected to the upper end face of each conductive bump portion 80 exposed in each hole portion 15. The upper end of each connection wiring portion 43 is connected to the first wiring pattern 41. In the first embodiment, the connection wiring portion 43 is filled in the hole portion 15. The connection wiring portion 43 may be a conductive film formed on the inner circumferential surface of the hole portion 15.

[0033] The wiring portion 40 has a connection wiring portion 44 that connects the first wiring pattern 41 and the second wiring pattern 42. The connection wiring portion 44 is formed in a through hole 16 that penetrates the substrate main body 10 in the thickness direction Z. In the first embodiment, the connection wiring portion 44 fills the through hole 16. Note that the connection wiring portion 44 may be a conductive film formed on the inner circumferential surface of the through hole 16.

[0034] FIG. 5 is a flowchart showing a method for manufacturing the semiconductor device 20 of the first embodiment. As shown in FIG. 5, the method for manufacturing the semiconductor device 20 includes a first housing portion forming step S11, a chip fixing step S12, a stud bump forming step S13, a molding step S14, a grinding step S15, and a singulation step S16. FIG. 6A is a cross-sectional view showing the first housing portion forming step S11. FIG. 6B is a cross-sectional view showing the chip fixing step S12. FIG. 6C is a cross-sectional view showing the stud bump forming step S13. FIG. 6D is a cross-sectional view showing a state after the stud bump forming step S13 has been performed. FIG. 6E is a cross-sectional view showing a state after the molding step S14 has been performed. FIG. 6F is a cross-sectional view showing a state after the grinding step S15 has been performed.

[0035] As shown in FIG. 6A, the first housing portion forming step S11 is a step of forming a first housing portion 63 in a base material 160 for forming a lead frame 60. FIG. 7 is a plan view showing the base material 160. The base material 160 has a plurality of frame main body portions 161. The plurality of frame main body portions 161 are arranged in a matrix. Adjacent frame main body portions 161 are connected to each other by two connecting portions 162. As shown in FIG. 6A, the dimension of the connecting portion 162 in the thickness direction Z is smaller than the dimension of the frame main body portion 161 in the thickness direction Z. The connecting portion 162 is connected to the lower end of the frame main body portion 161. In the first housing portion forming step S11 of the first embodiment, the first housing portion 63 recessed downward is formed in each frame main body portion 161 by etching. As shown in FIG. 6B, the support portion 61 and the frame portion 62 are formed in each frame main body portion 161 by forming the first housing portion 63.

[0036] The chip fixing step S12 is a step of fixing the semiconductor device body 50 in the first housing portion 63. As shown in Fig. 6B and Fig. 6C, in the chip fixing step S12, the semiconductor device body 50 is housed in the first housing portion 63 from above and fixed to the support portion 61 by the joint portion 53. In the chip fixing step S12, the semiconductor device bodies 50 are fixed one by one in each of the first housing portions 63 formed in each frame main body portion 161 of the base material 160.

[0037] As shown in Figures 6C and 6D, the stud bump forming step S13 is a step of forming a plurality of stud bumps 180 on the upper surface of the semiconductor device body 50 and the upper surface of the frame portion 62. As described above, the stud bumps 180 are formed by performing ball bonding using a bonding wire and then cutting the bonding wire. The stud bumps 180 formed on the upper surface of the semiconductor device body 50 are stud bumps 180 that form the first conductive bump portion 81. The stud bumps 180 formed on the upper surface of the frame portion 62 are stud bumps 180 that form the second conductive bump portion 82.

[0038] The molding process S14 is a process of performing insert molding using the base material 160, to which the semiconductor device body 50 is fixed and on which the stud bumps 180 are formed, as an insert member. As shown in Fig. 6E, the molding process S14 forms the base material 160, the semiconductor device body 50, and the resin part 170 in which the stud bumps 180 are embedded.

[0039] The grinding step S15 is a step of grinding the resin part 170 from above to reduce the dimension of the resin part 170 in the thickness direction Z. In the grinding step S15, the resin part 170 is ground until the dimension of the resin part 170 in the thickness direction Z becomes the dimension of the semiconductor device 20 in the thickness direction Z. As shown in FIG. 6F, the grinding step S15 grinds the resin part 170 from above, thereby exposing the stud bump 180 on the upper surface of the resin part 170. In the grinding step S15, the upper part of the stud bump 180 is also ground together with the resin part 170. In the grinding step S15, the upper part of the stud bump 180 is ground and removed, so that each stud bump 180 becomes each conductive bump part 80.

[0040] The singulation process S16 is a process in which the resin part 170 and the base material 160 are diced to separate each frame main body part 161. In the singulation process S16, each connection part 162 is cut and the base material 160 is separated into individual parts. In this way, a plurality of semiconductor devices 20 are manufactured.

[0041] Fig. 8 is a flowchart showing a method for manufacturing the circuit board 100 of the first embodiment. As shown in Fig. 8, the method for manufacturing the circuit board 100 includes a support substrate fixing step S21, a semiconductor device accommodating step S22, a sealing step S23, a support substrate removing step S24, a resin layer forming step S25, a laser processing step S26, and a wiring portion forming step S27. Fig. 9A is a cross-sectional view showing the semiconductor device accommodating step S22. Fig. 9B is a cross-sectional view showing a state after the sealing step S23 has been performed. Fig. 9C is a cross-sectional view showing the laser processing step S26. Fig. 9D is a cross-sectional view showing a state after the laser processing step S26 has been performed.

[0042] The support substrate fixing step S21 is a step of fixing the support substrate 90 to the base material part 11 in which the second housing part 14 is formed. The support substrate 90 is a plate-like plate with a plate surface facing the thickness direction Z. The support substrate 90 is made of, for example, stainless steel. The material constituting the support substrate 90 is not particularly limited. Although not shown, an adhesive layer is formed on the upper surface of the support substrate 90. In the support substrate fixing step S21, the support substrate 90 is fixed to the lower surface of the base material part 11 via the adhesive layer. As a result, as shown in FIG. 9A, the lower opening of the second housing part 14 is blocked by the support substrate 90.

[0043] The semiconductor device accommodating step S22 is a step of accommodating the semiconductor device 20 in the second accommodating section 14. As shown in Fig. 9A, in the semiconductor device accommodating step S22, the semiconductor device 20 is inserted into the second accommodating section 14 through an upper opening of the second accommodating section 14. As shown in Fig. 9B, the semiconductor device 20 inserted into the second accommodating section 14 is placed on the upper surface of a support substrate 90 and fixed onto the support substrate 90 via an adhesive layer formed on the support substrate 90.

[0044] The sealing step S23 is a step of sealing the second housing portion 14 with resin. In the sealing step S23, resin is poured into the second housing portion 14 with the semiconductor device 20 housed therein, to form the sealing resin portion 30. By forming the sealing resin portion 30, the semiconductor device 20 is embedded in the sealing resin portion 30 and is fixed to the base portion 11 via the sealing resin portion 30. The support substrate removal step S24 is a step of removing the support substrate 90 from the base portion 11. There is no particular limitation on the method of removing the support substrate 90 in the support substrate removal step S24.

[0045] The resin layer forming step S25 is a step of forming a pair of resin layers 12, 13. In the resin layer forming step S25, the pair of resin layers 12, 13 are formed, for example, simultaneously. Note that in the resin layer forming step S25, the pair of resin layers 12, 13 may be formed sequentially. By the resin layer forming step S25, as shown in FIG. 9C, the resin layer 12 is formed on the upper surface of the base material 11, and the resin layer 13 is formed on the lower surface of the base material 11.

[0046] The laser processing step S26 is a step of forming the hole 15 and the through hole 16 by irradiating the laser light LB. As shown in FIG. 9C, in the laser processing step S26, the laser light LB is irradiated from the upper side to the lower side of the resin layer 12. The laser light LB forming the hole 15 is irradiated toward the conductive bump portion 80. The laser light LB irradiated from the upper side of the resin layer 12 toward the conductive bump portion 80 penetrates the resin layer 12 and the portion of the sealing resin portion 30 located above the conductive bump portion 80, and is irradiated to the conductive bump portion 80. The laser light LB is blocked by the conductive bump portion 80. In the first embodiment, the conductive bump portion 80 functions as an absorption layer for the laser light LB. As a result, the hole 15 is formed, which reaches from the upper surface of the resin layer 12 to the conductive bump portion 80. The laser light LB forming the through hole 16 is irradiated to a position that does not overlap with the second housing portion 14 in the thickness direction Z. The laser light LB for forming the through holes 16 penetrates the resin layer 12, the base material 11, and the resin layer 13 in the thickness direction Z to form the through holes 16. By the laser processing step S26, a plurality of holes 15 and a plurality of through holes 16 are formed as shown in FIG. 9D. The through holes 16 may be formed using a drill instead of the laser light LB. In that case, the shape of the through holes 16 becomes a straight shape with a substantially uniform inner diameter.

[0047] The wiring portion forming process S27 is a process for forming the wiring portion 40. In the wiring portion forming process S27, for example, a metal layer is formed by plating on the upper surface of the resin layer 12, the lower surface of the resin layer 13, the inside of the hole portion 15, and the inside of the through hole 16, thereby forming the wiring portion 40. Through the above processes, the circuit board 100 of the first embodiment shown in FIG. 1 is manufactured.

[0048] According to the first embodiment, the semiconductor device 20 has a first surface 20a facing upward and a second surface 20b facing downward, and includes a semiconductor device body 50, a lead frame 60 to which the semiconductor device body 50 is electrically connected, a conductive bump portion 80 electrically connected to the semiconductor device body 50 or the lead frame 60, and a resin portion 70 that covers and holds at least a part of the semiconductor device body 50 and at least a part of the lead frame 60. At least a part of the conductive bump portion 80 is exposed to the outside of the resin portion 70. Therefore, even if the semiconductor device body 50 is covered with the resin portion 70, the semiconductor device body 50 can be electrically connected to other members through the conductive bump portion 80 exposed to the outside of the resin portion 70. As a result, the semiconductor device 20 can be a packaged semiconductor device in which the semiconductor device body 50 fixed to the lead frame 60 is covered with the resin portion 70. By packaging the semiconductor device 20 including not only the semiconductor device body 50 but also the lead frame 60 and the resin part 70, the semiconductor device 20 can be easily handled even when the semiconductor device body 50 is thinned. Therefore, the handleability of the semiconductor device 20 can be improved. This can improve the yield of products on which the semiconductor device 20 is mounted, and can improve the productivity of products on which the semiconductor device 20 is mounted. In the first embodiment, the yield when the circuit board 100 is manufactured by mounting the semiconductor device 20 on the board body part 10 can be improved, and the productivity of the circuit board 100 can be improved.

[0049] Moreover, by electrically connecting the lead frame 60 to the electrodes of the semiconductor device body 50, the position of the electrodes to which the external terminals are connected in the semiconductor device 20 can be freely designed. Specifically, for example, in the first embodiment, the lead frame 60 is connected to the third metal film 52c as a drain electrode provided on the lower surface of the semiconductor device body 50, and the second conductive bump portion 82 connected to the lead frame 60 is exposed on the upper first surface 20a, so that the drain electrode of the semiconductor device 20 can be arranged on the upper surface of the semiconductor device 20. This allows a gate electrode, a source electrode, and a drain electrode to be provided on the upper surface of the semiconductor device 20. Therefore, while the semiconductor device body 50 is a field effect transistor with a vertical structure, the semiconductor device 20 as a whole can be handled as a field effect transistor with a horizontal structure. In this way, by being able to improve the degree of freedom in the arrangement of the electrodes to which the external terminals are connected in the semiconductor device 20, it becomes easier to easily adopt a mounting method according to the product in which the semiconductor device 20 is mounted, and the productivity of the product in which the semiconductor device 20 is mounted can be further improved. In the first embodiment, the productivity of the circuit board 100 incorporating the semiconductor device 20 can be further improved.

[0050] Also, the heat of the semiconductor device body 50 can be easily released to the outside via the lead frame 60. Therefore, the heat dissipation of the semiconductor device 20 can be improved. Also, the conductive bump portion 80 has a larger dimension in the thickness direction Z and a larger heat capacity than a conductive film formed by, for example, plating. Therefore, by connecting the conductive bump portion 80 to the semiconductor device body 50, it is possible to easily transfer heat from the semiconductor device body 50 to the conductive bump portion 80, compared to a case where, for example, a conductive film formed by plating is provided on the semiconductor device body 50 instead of the conductive bump portion 80. This makes it possible to easily release heat from the semiconductor device body 50 to the outside, and further improves the heat dissipation of the semiconductor device 20.

[0051] Furthermore, when forming a conductive film by plating on the lower surface of the thin semiconductor device body 50, the use of plating not only complicates the process but is also technically difficult. In contrast, in the first embodiment, since the lead frame 60 can be fixed to the lower surface of the semiconductor device body 50, it is not necessary to form a conductive film by plating on the lower surface of the semiconductor device body 50.

[0052] Furthermore, according to the first embodiment, the conductive bump portion 80 includes a first conductive bump portion 81 electrically connected to the semiconductor device body 50, and a second conductive bump portion 82 electrically connected to the lead frame 60. This makes it easy to electrically connect other members to the semiconductor device body 50 and the lead frame 60 from outside the semiconductor device 20 via the first conductive bump portion 81 and the second conductive bump portion 82.

[0053] According to the first embodiment, the end face of the first conductive bump portion 81 and the end face of the second conductive bump portion 82 are exposed on the same surface of the semiconductor device 20. Therefore, compared with the case where the first conductive bump portion 81 and the second conductive bump portion 82 are exposed on different surfaces of the semiconductor device 20, the work of electrically connecting other members to each of the first conductive bump portion 81 and the second conductive bump portion 82 can be easily performed. This can further improve the productivity of the product on which the semiconductor device 20 is mounted. In addition, since the work of forming the first conductive bump portion 81 and the second conductive bump portion 82 can be performed from the same side, the number of steps in manufacturing the semiconductor device 20 can be reduced. This can improve the productivity of the semiconductor device 20.

[0054] According to the first embodiment, the first conductive bump 81 is connected to the upper surface of the semiconductor device body 50. The lead frame 60 has a first housing portion 63 that opens upward. The semiconductor device body 50 is housed inside the first housing portion 63. The second conductive bump 82 is connected to the opening periphery of the first housing portion 63 on the upper surface of the lead frame 60. The upper end face of the first conductive bump 81 and the upper end face of the second conductive bump 82 are exposed to the first surface 20a. Therefore, it is easy to align the positions in the thickness direction Z of the upper surface of the semiconductor device body 50 and the opening periphery of the first housing portion 63 on the upper surface of the lead frame 60, and the first conductive bump 81 and the second conductive bump 82 are easy to make by the same method. Specifically, in the first embodiment, the first conductive bump 81 and the second conductive bump 82 can be formed by forming a similar stud bump 180. This makes it easier to form first conductive bump portion 81 and second conductive bump portion 82.

[0055] Moreover, according to the first embodiment, the conductive bump portion 80 is formed by a stud bump. In other words, the first conductive bump portion 81 and the second conductive bump portion 82 are formed by a stud bump. Therefore, the first conductive bump portion 81 and the second conductive bump portion 82 can be easily formed by ball bonding using a bonding wire. This reduces the number of steps required to form a conductive portion electrically connected to the semiconductor device body 50 or the lead frame 60, compared to the case where a conductive film is formed by plating instead of the conductive bump portion 80. Therefore, the manufacturing cost of the semiconductor device 20 can be reduced.

[0056] Moreover, according to the first embodiment, a plurality of second conductive bump portions 82 are provided, and the plurality of second conductive bump portions 82 are arranged surrounding the first conductive bump portion 81 when viewed from above. This makes it easy to connect an external terminal or the like to the second conductive bump portion 82. This also makes it possible to dissipate heat from the third metal film 52c serving as the drain electrode efficiently over a large area to the side (upper side) on which the semiconductor device 20 is mounted.

[0057] According to the first embodiment, the material constituting the first conductive bump portion 81 and the material constituting the second conductive bump portion 82 are the same as each other and different from the material constituting the lead frame 60. For example, a configuration is also conceivable in which the conductive bump portion 80 is not connected to the lead frame 60, and the lead frame 60 itself is exposed to the outside of the resin portion 70 to serve as a terminal portion of the semiconductor device 20. In this case, in the above-mentioned grinding step S15, when grinding the resin portion 170, a part of the conductive bump portion 80 and a part of the lead frame 60 are ground together with the resin portion 170, so that a part of the conductive bump portion 80 and a part of the lead frame 60 are exposed to the outside of the resin portion 70. At this time, if the material constituting the conductive bump portion 80 and the material constituting the lead frame 60 are different from each other, it becomes necessary to grind three different materials including the resin portion 170, which may make it difficult to perform the grinding process. In contrast, in the first embodiment, by providing the second conductive bump portion 82 connected to the lead frame 60 and forming the second conductive bump portion 82 from the same material as the first conductive bump portion 81, the other material to be ground when grinding the resin portion 170 in the grinding step S15 can be reduced to one type. This makes it easier to perform the grinding process in the grinding step S15. In addition, by making the first conductive bump portion 81 and the second conductive bump portion 82 from the same material, it is easier to produce a plurality of conductive bump portions 80.

[0058] According to the first embodiment, the semiconductor device 20 is built into the substrate main body 10. Therefore, the length of the wiring connecting the electrodes of the semiconductor device 20 and the wiring pattern formed on the substrate main body 10 can be shortened compared to the case where the semiconductor device 20 is attached to the plate surface of the substrate main body 10 and the electrodes of the semiconductor device 20 are connected to the wiring pattern formed on the substrate main body 10 by wire bonding or the like. This makes it easier to reduce the resistance between the electrodes of the semiconductor device 20 and the wiring pattern formed on the substrate main body 10, and makes it easier to pass a current between the electrodes of the semiconductor device 20 and the wiring pattern formed on the substrate main body 10. Therefore, the circuit board 100 can be easily made into a circuit board that can also handle high-speed communication in which high-frequency electrical signals flow. Also, compared to the case where the semiconductor device 20 is attached to the plate surface of the substrate main body 10 and the electrodes of the semiconductor device 20 are connected to the wiring pattern formed on the substrate main body 10 by wire bonding or the like, the circuit board 100 can be made smaller. Also, it is possible to form other layers in the thickness direction Z and mount other devices on the part of the substrate main body 10 in which the semiconductor device 20 is built. This improves the degree of freedom in designing the circuit board 100.

[0059] According to the first embodiment, the substrate body 10 has a second housing portion 14 that houses the semiconductor device 20 therein. The substrate body 10 has a hole 15 that extends from the outer surface of the substrate body 10 to a portion of the conductive bump 80 that is exposed to the outside of the resin portion 70. Inside the hole 15, a connection wiring portion 43 that is electrically connected to the conductive bump 80 is formed. When forming such a hole 15, the substrate body 10 is processed using, for example, the above-mentioned laser processing to form the hole 15. At that time, in order to prevent the laser light LB from damaging the semiconductor device body 50, etc., it is necessary to provide an absorption layer that receives the laser light LB on the upper surface of the semiconductor device body 50, etc. If this absorption layer is a thin film formed by, for example, sputtering, there is a risk that the laser light LB will penetrate the thin film and damage the semiconductor device body 50, etc. In contrast, in the first embodiment, the conductive bump 80, which can have a certain size in the thickness direction Z, can be used as the absorption layer for the laser light LB. Therefore, when the hole 15 is formed by laser processing, the laser light LB can be appropriately received by the conductive bump portion 80, and damage to the semiconductor device body 50 and the like can be suppressed.

[0060] Also, for example, a conductive film having a certain large dimension in the thickness direction Z can be formed on the semiconductor device body 50 by plating or the like, and the conductive film can be used as an absorption layer for the laser light LB when processing the hole portion 15. However, the process of forming a conductive film by plating tends to require many steps, and the manufacturing cost of the semiconductor device 20 tends to increase. In addition, the conductive film formed by plating may not be thick enough to serve as an absorption layer. In contrast, in the first embodiment, instead of the conductive film formed by plating, a conductive bump portion 80 that is easy to form thicker than the conductive film is formed. The number of steps to form the conductive bump portion 80 tends to be less than the number of steps to form the conductive film by plating. Therefore, the increase in the manufacturing cost of the semiconductor device 20 can be suppressed. In addition, the conductive bump portion 80 tends to provide a sufficient thickness to serve as an absorption layer.

[0061] Furthermore, according to the first embodiment, the manufacturing method for manufacturing the circuit board 100 includes forming the hole 15 by irradiating the conductive bump portion 80 with the laser light LB. Therefore, as described above, the conductive bump portion 80 can be used as an absorption layer, and the laser light LB can be suitably prevented from penetrating the conductive bump portion 80. This can suitably prevent the semiconductor device body 50 and the like from being damaged by the laser light LB.

[0062] Second Embodiment The second embodiment is different from the first embodiment in the number of second conductive bump portions 82. In the following description, the same configurations as those in the above-described embodiments may be appropriately denoted by the same reference numerals and description thereof may be omitted.

[0063] FIG. 10 is a cross-sectional view showing the semiconductor device 220 of the second embodiment. FIG. 11 is a plan view showing the semiconductor device 220 of the second embodiment. As shown in FIG. 10 and FIG. 11, the semiconductor device 220 has a smaller number of second conductive bump portions 82 than the semiconductor device 20 of the first embodiment. Specifically, as shown in FIG. 11, the second conductive bump portions 82 are arranged in an L-shape along two sides of the rectangular frame portion 62. In other words, the second conductive bump portions 82 are not provided on the other two sides of the rectangular frame portion 62. In this way, by not arranging the second conductive bump portions 82 in a frame shape and not providing the second conductive bump portions 82 on one or more of the four sides of the frame portion 62, it is possible to prevent the second conductive bump portions 82 from interfering with the routing of wiring on the circuit board on which the semiconductor device 220 is mounted. Therefore, it is possible to improve the degree of freedom of routing of wiring on the circuit board on which the semiconductor device 220 is mounted. The other configurations of the semiconductor device 220 are similar to the other configurations of the semiconductor device 20 of the first embodiment.

[0064] (Third embodiment) The third embodiment differs from the first embodiment in that there is no second conductive bump portion 82. In the following description, the same components as those in the above-described embodiments may be appropriately denoted by the same reference numerals and description thereof may be omitted.

[0065] FIG. 12 is a cross-sectional view showing the semiconductor device 320 of the third embodiment. FIG. 13 is a plan view showing the semiconductor device 320 of the third embodiment. As shown in FIG. 12 and FIG. 13, unlike the semiconductor device 20 of the first embodiment, the semiconductor device 320 does not have a second conductive bump portion 82 connected to the lead frame 360. As shown in FIG. 12, the upper end face of the frame portion 362 in the lead frame 360 ​​is located above the upper surface of the semiconductor device body 50. The upper end face of the frame portion 362 is exposed on the first surface 320a on the upper side of the semiconductor device 320. In the third embodiment, the first surface 320a is composed of the upper surface of the resin portion 70, the upper end face of the first conductive bump portion 81, and the upper end face of the frame portion 362. In the third embodiment, the upper end face of the frame portion 362 can be used as an absorption layer when performing the laser processing step S26.

[0066] In the third embodiment, the material constituting the lead frame 360 ​​and the material constituting the first conductive bump portion 81 are the same. Therefore, when performing the grinding step S15, only one type of material other than the resin portion 70 is required to be ground, which makes it easier to perform the grinding process. When the material constituting the lead frame 360 ​​and the material constituting the first conductive bump portion 81 are the same, for example, from the viewpoint of manufacturing costs, the material is preferably copper (Cu). Note that in the third embodiment, the material constituting the lead frame 360 ​​and the material constituting the first conductive bump portion 81 may be different from each other. The other configurations of the semiconductor device 320 are the same as those of the semiconductor device 20 of the first embodiment.

[0067] (Fourth embodiment) The fourth embodiment is different from the first embodiment in the shape of second conductive bump portion 482. In the following description, the same components as those in the above-described embodiments are appropriately denoted by the same reference numerals and description thereof may be omitted.

[0068] Fig. 14 is a cross-sectional view showing a semiconductor device 420 of the fourth embodiment. As shown in Fig. 14, in the semiconductor device 420, the first accommodation portion 63 is not formed in the lead frame 460. The lead frame 460 is a flat plate whose plate surface faces the thickness direction Z.

[0069] In the fourth embodiment, the second conductive bump portion 482 is formed by a vertical wire 480a. The vertical wire 480a is formed by performing ball bonding using a bonding wire, extending the bonding wire vertically from a stud bump formed by ball bonding, and cutting the bonding wire at a certain length. The second conductive bump portion 482 is connected to the upper surface of the lead frame 460.

[0070] The second conductive bump portion 482 has a stud bump portion 482a connected to the lead frame 460 and a wire portion 482b extending upward from the stud bump portion 482a. The stud bump portion 482a is a portion formed by a stud bump. The stud bump portion 482a has the same shape as the stud bump 180 described in the first embodiment. The stud bump portion 482a is connected to the upper surface of the lead frame 460. In the fourth embodiment, the stud bump portion 482a and the semiconductor device body 50 are fixed to the same surface of the lead frame 460. In other words, the second conductive bump portion 482 and the semiconductor device body 50 are fixed to the same surface of the lead frame 460. The wire portion 482b is a portion formed by a bonding wire. The upper end surface of the wire portion 482b is exposed to the first surface 420a. The other configurations of the semiconductor device 420 are similar to the other configurations of the semiconductor device 20 of the first embodiment.

[0071] FIG. 15 is a flow chart showing a method for manufacturing the semiconductor device 420 of the fourth embodiment. As shown in FIG. 15, the method for manufacturing the semiconductor device 420 includes a chip fixing step S31, a stud bump forming step S32, a vertical wire forming step S33, a molding step S34, a grinding step S35, and a singulation step S36. FIG. 16A is a cross-sectional view showing the chip fixing step S31. FIG. 16B is a cross-sectional view showing the stud bump forming step S32 and the vertical wire forming step S33. FIG. 16C is a cross-sectional view showing a state after the stud bump forming step S32 and the vertical wire forming step S33 have been performed. FIG. 16D is a cross-sectional view showing a state after the molding step S34 has been performed. FIG. 16E is a cross-sectional view showing a state after the grinding step S35 has been performed.

[0072] As shown in FIG. 16A, the chip fixing step S31 is a step of fixing the semiconductor device body 50 to a base material 460a of a lead frame 460. The base material 460a is similar to the base material 160 of the first embodiment, except that the dimension in the thickness direction Z is the same throughout. The base material 460a may be the same base material as the base material 160 of the first embodiment. In the chip fixing step S31, the semiconductor device body 50 is fixed to the upper surface of the base material 460a by the joints 53. In the chip fixing step S31, the semiconductor device body 50 is fixed one by one to each of a plurality of frame body parts formed on the base material 460a.

[0073] The stud bump forming step S32 is similar to the stud bump forming step S13 in the first embodiment, except that only the first conductive bump portion 81 is formed. As shown in Fig. 16B and Fig. 16C, the vertical wire forming step S33 is a step of forming a vertical wire 480a on a base material 460a of a lead frame 460. As described above, the vertical wire 480a is formed by performing ball bonding using a bonding wire, extending the bonding wire in the vertical direction from the stud bump formed by ball bonding, and cutting the bonding wire at a certain length.

[0074] 16B shows the stud bump forming step S32 and the vertical wire forming step S33 being performed simultaneously, but this is not limited thereto. The vertical wire forming step S33 may be performed after the stud bump forming step S32 is completed, the stud bump forming step S32 may be performed after the vertical wire forming step S33 is completed, or the stud bump forming step S32 and the vertical wire forming step S33 may be performed simultaneously.

[0075] The molding process S34 is a process of performing insert molding using the base material 460a, to which the semiconductor device body 50 is fixed and on which the stud bumps 180 and vertical wires 480a are formed, as an insert member. As shown in Fig. 16D, the molding process S34 forms the resin part 170 in which the base material 460a, the semiconductor device body 50, the stud bumps 180, and the vertical wires 480a are embedded.

[0076] The grinding step S35 is a step of grinding the resin part 170 from above to reduce the dimension of the resin part 170 in the thickness direction Z. In the grinding step S35, the resin part 170 is ground until the dimension of the resin part 170 in the thickness direction Z becomes the dimension of the semiconductor device 420 in the thickness direction Z. As shown in FIG. 16E, the grinding step S35 grinds the resin part 170 from above, thereby exposing the stud bump 180 and the vertical wire 480a on the upper surface of the resin part 170. In the grinding step S35, the upper part of the stud bump 180 and the upper part of the wire part of the vertical wire 480a are also ground together with the resin part 170. In the grinding step S35, the upper part of the stud bump 180 is ground and removed, so that each stud bump 180 becomes each first conductive bump part 81. In the grinding step S35, the upper portion of the wire portion of the vertical wires 480a is ground and removed, so that each vertical wire 480a becomes each second conductive bump portion 482.

[0077] The singulation process S36 is the same as the singulation process S16 in the first embodiment. By the singulation process S36, a plurality of semiconductor devices 420 are formed. The other methods in the manufacturing method of the semiconductor device 420 are the same as the other methods in the manufacturing method of the semiconductor device 20 in the first embodiment.

[0078] According to the fourth embodiment, the second conductive bump portion 482 has a stud bump portion 482a connected to the lead frame 460 and a wire portion 482b extending upward from the stud bump portion 482a. The upper end face of the wire portion 482b is exposed to the first surface 420a. In this manner, by configuring the second conductive bump portion 482 to be formed by the vertical wire 480a, the position of the upper end portion of the second conductive bump portion 482 connected to the lead frame 460 can be made to be the same as the position of the upper end portion of the first conductive bump portion 81 without forming the first housing portion 63 in the lead frame 460. Therefore, the number of steps for processing the lead frame 460 can be reduced.

[0079] Fifth embodiment The fifth embodiment is different from the first embodiment in the shape of the wiring portion 540. In the following description, the same configurations as those in the above-mentioned embodiments are appropriately denoted by the same reference numerals, and the description may be omitted.

[0080] Fig. 17 is a cross-sectional view showing a part of a circuit board 500 of the fifth embodiment. As shown in Fig. 17, a through hole 16 is not formed in a board main body 510 of the circuit board 500. A wiring section 540 of the circuit board 500 does not have a second wiring pattern 42 and a connection wiring section 44 formed in the through hole 16. The other configurations of the wiring section 540 are similar to the other configurations of the wiring section 40 of the first embodiment. The other configurations of the circuit board 500 are similar to the other configurations of the circuit board 100 of the first embodiment.

[0081] Sixth embodiment The sixth embodiment differs from the first embodiment in that the circuit board 600 does not incorporate the semiconductor device 20. In the following description, the same components as those in the above-described embodiments may be appropriately denoted by the same reference numerals and description thereof may be omitted.

[0082] FIG. 18 is a cross-sectional view showing a part of a circuit board 600 of the sixth embodiment. As shown in FIG. 18, in the sixth embodiment, the semiconductor device 20 is attached to one plate surface of a substrate body 610. The semiconductor device 20 is mounted on the substrate body 610 by flip-chip mounting. The first conductive bump portion 81 and the second conductive bump portion 82 of the semiconductor device 20 are electrically connected to a wiring pattern (not shown) on the substrate body 610 via bumps 691 formed by solder or the like. An adhesive layer 692 is formed between the semiconductor device 20 and the substrate body 610 to bond the semiconductor device 20 to the substrate body 610. The bumps 691 are embedded in the adhesive layer 692.

[0083] According to the sixth embodiment, the semiconductor device 20 is attached to one surface of the substrate body 610. Therefore, the structure of the substrate body 610 can be simplified compared to the case where the semiconductor device 20 is built into the substrate body 610.

[0084] In addition, when the semiconductor device body 50 is made thinner, the handling of the semiconductor device body 50 is reduced, and thus, conventionally, there has been a problem that it is difficult to mount the semiconductor device body 50 on the substrate body 610 by flip-chip mounting. In addition, in order to perform flip-chip mounting, there are structural constraints, such as the need to make the semiconductor device body 50 a field effect transistor with a horizontal structure. In response to this, the semiconductor device body 50 and the lead frame 60 are covered with a resin part 70 to be packaged, and the handling of the semiconductor device 20 is improved, so that the semiconductor device 20 can be easily mounted on the substrate body 610 by flip-chip mounting. In addition, even if the semiconductor device body 50 is a field effect transistor with a vertical structure, the gate electrode, source electrode, and drain electrode of the semiconductor device 20 can be provided on the same surface via the lead frame 60, so that flip-chip mounting can be adopted as a mounting method for the semiconductor device 20 regardless of the structure of the semiconductor device body 50.

[0085] According to at least one of the embodiments described above, the semiconductor device has a first surface facing a first side and a second surface facing a second side opposite to the first side. The semiconductor device has a semiconductor device body, a lead frame to which the semiconductor device body is electrically connected, a conductive bump portion electrically connected to the semiconductor device body or the lead frame, and a resin portion that covers and holds at least a part of the semiconductor device body and at least a part of the lead frame. At least a part of the conductive bump portion is exposed to the outside of the resin portion. This can improve the handleability of the semiconductor device.

[0086] The conductive bump portion is not limited to the conductive bump portion formed by the stud bump and the conductive bump portion formed by the vertical wire described above. The method of forming the conductive bump portion is not particularly limited. The conductive bump portion may be formed by a metallic bump formed by screen printing, or may be formed by a metallic bump formed by an inkjet method. The conductive bump portion may be entirely exposed to the outside of the resin portion.

[0087] The conductive bump portion may be provided only with a first conductive bump portion or only with a second conductive bump portion. The number of conductive bump portions is not particularly limited as long as it is one or more. The surface of the semiconductor device on which the first conductive bump portion is exposed and the surface of the semiconductor device on which the second conductive bump portion is exposed may be different surfaces. When a plurality of first conductive bump portions are provided, the plurality of first conductive bump portions may include two or more first conductive bump portions exposed on different surfaces of the semiconductor device. When a plurality of second conductive bump portions are provided, the plurality of second conductive bump portions may include two or more second conductive bump portions exposed on different surfaces of the semiconductor device. The material constituting the first conductive bump portion and the material constituting the second conductive bump portion may be different from each other.

[0088] The configuration of the circuit board on which the semiconductor device is provided is not particularly limited. The circuit board may be a multi-layer board. The number of semiconductor devices provided on the circuit board is not particularly limited as long as it is one or more. The hole formed in the circuit board may be formed by a method other than laser processing. Even in this case, by forming a conductive bump portion having a certain thickness, damage to the semiconductor device body, etc. can be suppressed.

[0089] The semiconductor device, the circuit board, and the method for manufacturing the circuit board according to the embodiments include the following additional aspects. (Appendix 1) A semiconductor device having a first surface facing a first side and a second surface facing a second side opposite to the first side, A semiconductor device body; a lead frame to which the semiconductor device body is electrically connected; a conductive bump portion electrically connected to the semiconductor device body or the lead frame; a resin portion that covers and holds at least a portion of the semiconductor device body and at least a portion of the lead frame; Equipped with At least a portion of the conductive bump portion is exposed to the outside of the resin portion. (Appendix 2) The conductive bump portion is a first conductive bump portion electrically connected to the semiconductor device body; a second conductive bump portion electrically connected to the lead frame; 2. The semiconductor device of claim 1, (Appendix 3 3. The semiconductor device according to claim 2, wherein an end face of the first conductive bump portion and an end face of the second conductive bump portion are exposed on the same surface of the semiconductor device. (Appendix 4) the first conductive bump portion is connected to the first surface of the semiconductor device body, the lead frame has a first housing portion that opens to the first side, the semiconductor device body is accommodated inside the first accommodation portion, the second conductive bump portion is connected to an opening peripheral portion of the first housing portion on the first side surface of the lead frame, The semiconductor device according to claim 3, wherein an end face on the first side of the first conductive bump portion and an end face on the first side of the second conductive bump portion are exposed on the first surface. (Appendix 5) 5. The semiconductor device according to claim 4, wherein the first conductive bump portion and the second conductive bump portion are formed by stud bumps. (Appendix 6) the first conductive bump portion is connected to the first surface of the semiconductor device body, the second conductive bump portion is connected to the first surface of the lead frame; the first conductive bump portion is formed by a stud bump, The second conductive bump portion is a stud bump portion connected to the lead frame; a wire portion extending from the stud bump portion to the first side; having 4. The semiconductor device according to claim 3, wherein an end face on the first side of the first conductive bump portion and an end face on the first side of the wire portion are exposed on the first surface. (Appendix 7) 4. The semiconductor device according to claim 1, wherein the conductive bump portion is formed by a stud bump. (Appendix 8) The second conductive bump portion is provided in plurality, 7. The semiconductor device according to claim 4, wherein the second conductive bump portions are arranged to surround the first conductive bump portion when viewed from the first side. (Appendix 9) 7. The semiconductor device according to claim 2, wherein a material constituting the first conductive bump portion and a material constituting the second conductive bump portion are the same as each other and different from a material constituting the lead frame. (Appendix 10) A semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9; a substrate body portion on which the semiconductor device is mounted; A circuit board comprising: (Appendix 11) 11. The circuit board according to claim 10, wherein the semiconductor device is built into the board body portion. (Appendix 12) the substrate body has a second housing portion that houses the semiconductor device therein, a hole portion is formed in the substrate body portion, the hole portion extending from an outer surface of the substrate body portion to a portion of the conductive bump portion exposed to the outside of the resin portion; 12. The circuit board according to claim 11, wherein a connection wiring portion electrically connected to the conductive bump portion is formed inside the hole portion. (Appendix 13) 11. The circuit board according to claim 10, wherein the semiconductor device is attached to one of the plate surfaces of the substrate body. (Appendix 14) A method for producing the circuit board according to claim 12, comprising the steps of: forming the hole by irradiating the conductive bump with laser light.

[0090] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0091] 10,510,610...substrate main body portion, 14...second housing portion, 15...hole portion, 20,220,320,420...semiconductor device, 20a,320a,420a...first surface, 20b...second surface, 40,540...wiring portion, 43...connection wiring portion, 50...semiconductor device main body, 60,360,460...lead frame, 63...first housing portion, 70...resin portion, 80...conductive bump portion, 81...first conductive bump portion, 82,482...second conductive bump portion, 100,500,600...circuit board, 180...stud bump, 482a...stud bump portion, 482b...wire portion, LB...laser light

Claims

1. A semiconductor device having a first surface facing a first side and a second surface facing a second side opposite to the first side, A semiconductor device body; a lead frame to which the semiconductor device body is electrically connected; a conductive bump portion electrically connected to the semiconductor device body or the lead frame; a resin portion that covers and holds at least a portion of the semiconductor device body and at least a portion of the lead frame; Equipped with At least a portion of the conductive bump portion is exposed to the outside of the resin portion.

2. The conductive bump portion is a first conductive bump portion electrically connected to the semiconductor device body; a second conductive bump portion electrically connected to the lead frame; The semiconductor device according to claim 1 ,

3. 3. The semiconductor device according to claim 2, wherein an end face of said first conductive bump portion and an end face of said second conductive bump portion are exposed on the same surface of said semiconductor device.

4. the first conductive bump portion is connected to the first surface of the semiconductor device body, the lead frame has a first housing portion that opens to the first side, the semiconductor device body is accommodated inside the first accommodation portion, the second conductive bump portion is connected to an opening peripheral portion of the first housing portion on the first side surface of the lead frame, The semiconductor device according to claim 3 , wherein an end face on the first side of the first conductive bump portion and an end face on the first side of the second conductive bump portion are exposed on the first surface.

5. 5. The semiconductor device according to claim 4, wherein the first conductive bump portion and the second conductive bump portion are formed by stud bumps.

6. the first conductive bump portion is connected to the first surface of the semiconductor device body, the second conductive bump portion is connected to the first surface of the lead frame; the first conductive bump portion is formed by a stud bump, The second conductive bump portion is a stud bump portion connected to the lead frame; a wire portion extending from the stud bump portion to the first side; having The semiconductor device according to claim 3 , wherein an end face on the first side of the first conductive bump portion and an end face on the first side of the wire portion are exposed on the first surface.

7. 2. The semiconductor device according to claim 1, wherein said conductive bump portion is formed by a stud bump.

8. The second conductive bump portion is provided in plurality, The semiconductor device according to claim 4 , wherein the second conductive bump portions are arranged to surround the first conductive bump portion when viewed from the first side.

9. 3. The semiconductor device according to claim 2, wherein a material constituting said first conductive bump portion and a material constituting said second conductive bump portion are the same as each other and different from a material constituting said lead frame.

10. A semiconductor device according to any one of claims 1 to 9, a substrate body portion on which the semiconductor device is mounted; A circuit board comprising:

11. The circuit board according to claim 10 , wherein the semiconductor device is built into the board body.

12. the substrate body portion has a second housing portion that houses the semiconductor device therein, a hole portion is formed in the substrate body portion, the hole portion extending from an outer surface of the substrate body portion to a portion of the conductive bump portion exposed to the outside of the resin portion; The circuit board according to claim 11 , wherein a connection wiring portion electrically connected to the conductive bump portion is formed inside the hole portion.

13. The circuit board according to claim 10 , wherein the semiconductor device is attached to one of the plate surfaces of the board body portion.

14. A method for manufacturing the circuit board according to claim 12, comprising the steps of: forming the hole by irradiating the conductive bump with laser light.

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